2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
31 #include <video/display_timing.h>
32 #include <video/of_display_timing.h>
33 #include <video/videomode.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_device.h>
37 #include <drm/drm_mipi_dsi.h>
38 #include <drm/drm_panel.h>
41 * @modes: Pointer to array of fixed modes appropriate for this panel. If
42 * only one mode then this can just be the address of this the mode.
43 * NOTE: cannot be used with "timings" and also if this is specified
44 * then you cannot override the mode in the device tree.
45 * @num_modes: Number of elements in modes array.
46 * @timings: Pointer to array of display timings. NOTE: cannot be used with
47 * "modes" and also these will be used to validate a device tree
48 * override if one is present.
49 * @num_timings: Number of elements in timings array.
50 * @bpc: Bits per color.
51 * @size: Structure containing the physical size of this panel.
52 * @delay: Structure containing various delay values for this panel.
53 * @bus_format: See MEDIA_BUS_FMT_... defines.
54 * @bus_flags: See DRM_BUS_FLAG_... defines.
57 const struct drm_display_mode *modes;
58 unsigned int num_modes;
59 const struct display_timing *timings;
60 unsigned int num_timings;
65 * @width: width (in millimeters) of the panel's active display area
66 * @height: height (in millimeters) of the panel's active display area
74 * @prepare: the time (in milliseconds) that it takes for the panel to
75 * become ready and start receiving video data
76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
77 * Plug Detect isn't used.
78 * @enable: the time (in milliseconds) that it takes for the panel to
79 * display the first valid frame after starting to receive
81 * @disable: the time (in milliseconds) that it takes for the panel to
82 * turn the display off (no content is visible)
83 * @unprepare: the time (in milliseconds) that it takes for the panel
84 * to power itself down completely
88 unsigned int hpd_absent_delay;
91 unsigned int unprepare;
100 struct drm_panel base;
105 const struct panel_desc *desc;
107 struct regulator *supply;
108 struct i2c_adapter *ddc;
110 struct gpio_desc *enable_gpio;
112 struct drm_display_mode override_mode;
115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117 return container_of(panel, struct panel_simple, base);
120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
121 struct drm_connector *connector)
123 struct drm_display_mode *mode;
124 unsigned int i, num = 0;
126 for (i = 0; i < panel->desc->num_timings; i++) {
127 const struct display_timing *dt = &panel->desc->timings[i];
130 videomode_from_timing(dt, &vm);
131 mode = drm_mode_create(connector->dev);
133 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
134 dt->hactive.typ, dt->vactive.typ);
138 drm_display_mode_from_videomode(&vm, mode);
140 mode->type |= DRM_MODE_TYPE_DRIVER;
142 if (panel->desc->num_timings == 1)
143 mode->type |= DRM_MODE_TYPE_PREFERRED;
145 drm_mode_probed_add(connector, mode);
152 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
153 struct drm_connector *connector)
155 struct drm_display_mode *mode;
156 unsigned int i, num = 0;
158 for (i = 0; i < panel->desc->num_modes; i++) {
159 const struct drm_display_mode *m = &panel->desc->modes[i];
161 mode = drm_mode_duplicate(connector->dev, m);
163 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
164 m->hdisplay, m->vdisplay, m->vrefresh);
168 mode->type |= DRM_MODE_TYPE_DRIVER;
170 if (panel->desc->num_modes == 1)
171 mode->type |= DRM_MODE_TYPE_PREFERRED;
173 drm_mode_set_name(mode);
175 drm_mode_probed_add(connector, mode);
182 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
183 struct drm_connector *connector)
185 struct drm_display_mode *mode;
186 bool has_override = panel->override_mode.type;
187 unsigned int num = 0;
193 mode = drm_mode_duplicate(connector->dev,
194 &panel->override_mode);
196 drm_mode_probed_add(connector, mode);
199 dev_err(panel->base.dev, "failed to add override mode\n");
203 /* Only add timings if override was not there or failed to validate */
204 if (num == 0 && panel->desc->num_timings)
205 num = panel_simple_get_timings_modes(panel, connector);
208 * Only add fixed modes if timings/override added no mode.
210 * We should only ever have either the display timings specified
211 * or a fixed mode. Anything else is rather bogus.
213 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
215 num = panel_simple_get_display_modes(panel, connector);
217 connector->display_info.bpc = panel->desc->bpc;
218 connector->display_info.width_mm = panel->desc->size.width;
219 connector->display_info.height_mm = panel->desc->size.height;
220 if (panel->desc->bus_format)
221 drm_display_info_set_bus_formats(&connector->display_info,
222 &panel->desc->bus_format, 1);
223 connector->display_info.bus_flags = panel->desc->bus_flags;
228 static int panel_simple_disable(struct drm_panel *panel)
230 struct panel_simple *p = to_panel_simple(panel);
235 if (p->desc->delay.disable)
236 msleep(p->desc->delay.disable);
243 static int panel_simple_unprepare(struct drm_panel *panel)
245 struct panel_simple *p = to_panel_simple(panel);
250 gpiod_set_value_cansleep(p->enable_gpio, 0);
252 regulator_disable(p->supply);
254 if (p->desc->delay.unprepare)
255 msleep(p->desc->delay.unprepare);
262 static int panel_simple_prepare(struct drm_panel *panel)
264 struct panel_simple *p = to_panel_simple(panel);
271 err = regulator_enable(p->supply);
273 dev_err(panel->dev, "failed to enable supply: %d\n", err);
277 gpiod_set_value_cansleep(p->enable_gpio, 1);
279 delay = p->desc->delay.prepare;
281 delay += p->desc->delay.hpd_absent_delay;
290 static int panel_simple_enable(struct drm_panel *panel)
292 struct panel_simple *p = to_panel_simple(panel);
297 if (p->desc->delay.enable)
298 msleep(p->desc->delay.enable);
305 static int panel_simple_get_modes(struct drm_panel *panel,
306 struct drm_connector *connector)
308 struct panel_simple *p = to_panel_simple(panel);
311 /* probe EDID if a DDC bus is available */
313 struct edid *edid = drm_get_edid(connector, p->ddc);
315 drm_connector_update_edid_property(connector, edid);
317 num += drm_add_edid_modes(connector, edid);
322 /* add hard-coded panel modes */
323 num += panel_simple_get_non_edid_modes(p, connector);
328 static int panel_simple_get_timings(struct drm_panel *panel,
329 unsigned int num_timings,
330 struct display_timing *timings)
332 struct panel_simple *p = to_panel_simple(panel);
335 if (p->desc->num_timings < num_timings)
336 num_timings = p->desc->num_timings;
339 for (i = 0; i < num_timings; i++)
340 timings[i] = p->desc->timings[i];
342 return p->desc->num_timings;
345 static const struct drm_panel_funcs panel_simple_funcs = {
346 .disable = panel_simple_disable,
347 .unprepare = panel_simple_unprepare,
348 .prepare = panel_simple_prepare,
349 .enable = panel_simple_enable,
350 .get_modes = panel_simple_get_modes,
351 .get_timings = panel_simple_get_timings,
354 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
355 (to_check->field.typ >= bounds->field.min && \
356 to_check->field.typ <= bounds->field.max)
357 static void panel_simple_parse_panel_timing_node(struct device *dev,
358 struct panel_simple *panel,
359 const struct display_timing *ot)
361 const struct panel_desc *desc = panel->desc;
365 if (WARN_ON(desc->num_modes)) {
366 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
369 if (WARN_ON(!desc->num_timings)) {
370 dev_err(dev, "Reject override mode: no timings specified\n");
374 for (i = 0; i < panel->desc->num_timings; i++) {
375 const struct display_timing *dt = &panel->desc->timings[i];
377 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
378 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
379 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
387 if (ot->flags != dt->flags)
390 videomode_from_timing(ot, &vm);
391 drm_display_mode_from_videomode(&vm, &panel->override_mode);
392 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
393 DRM_MODE_TYPE_PREFERRED;
397 if (WARN_ON(!panel->override_mode.type))
398 dev_err(dev, "Reject override mode: No display_timing found\n");
401 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
403 struct panel_simple *panel;
404 struct display_timing dt;
405 struct device_node *ddc;
408 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
412 panel->enabled = false;
413 panel->prepared = false;
416 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
418 panel->supply = devm_regulator_get(dev, "power");
419 if (IS_ERR(panel->supply))
420 return PTR_ERR(panel->supply);
422 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
424 if (IS_ERR(panel->enable_gpio)) {
425 err = PTR_ERR(panel->enable_gpio);
426 if (err != -EPROBE_DEFER)
427 dev_err(dev, "failed to request GPIO: %d\n", err);
431 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
433 panel->ddc = of_find_i2c_adapter_by_node(ddc);
437 return -EPROBE_DEFER;
440 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
441 panel_simple_parse_panel_timing_node(dev, panel, &dt);
443 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
444 desc->connector_type);
446 err = drm_panel_of_backlight(&panel->base);
450 err = drm_panel_add(&panel->base);
454 dev_set_drvdata(dev, panel);
460 put_device(&panel->ddc->dev);
465 static int panel_simple_remove(struct device *dev)
467 struct panel_simple *panel = dev_get_drvdata(dev);
469 drm_panel_remove(&panel->base);
470 drm_panel_disable(&panel->base);
471 drm_panel_unprepare(&panel->base);
474 put_device(&panel->ddc->dev);
479 static void panel_simple_shutdown(struct device *dev)
481 struct panel_simple *panel = dev_get_drvdata(dev);
483 drm_panel_disable(&panel->base);
484 drm_panel_unprepare(&panel->base);
487 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
490 .hsync_start = 480 + 2,
491 .hsync_end = 480 + 2 + 41,
492 .htotal = 480 + 2 + 41 + 2,
494 .vsync_start = 272 + 2,
495 .vsync_end = 272 + 2 + 10,
496 .vtotal = 272 + 2 + 10 + 2,
498 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
501 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
502 .modes = &ire_am_480272h3tmqw_t01h_mode,
509 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
512 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
515 .hsync_start = 800 + 0,
516 .hsync_end = 800 + 0 + 255,
517 .htotal = 800 + 0 + 255 + 0,
519 .vsync_start = 480 + 2,
520 .vsync_end = 480 + 2 + 45,
521 .vtotal = 480 + 2 + 45 + 0,
523 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
526 static const struct panel_desc ampire_am800480r3tmqwa1h = {
527 .modes = &ire_am800480r3tmqwa1h_mode,
534 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
537 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
538 .pixelclock = { 26400000, 33300000, 46800000 },
539 .hactive = { 800, 800, 800 },
540 .hfront_porch = { 16, 210, 354 },
541 .hback_porch = { 45, 36, 6 },
542 .hsync_len = { 1, 10, 40 },
543 .vactive = { 480, 480, 480 },
544 .vfront_porch = { 7, 22, 147 },
545 .vback_porch = { 22, 13, 3 },
546 .vsync_len = { 1, 10, 20 },
547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
548 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
551 static const struct panel_desc armadeus_st0700_adapt = {
552 .timings = &santek_st0700i5y_rbslw_f_timing,
559 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
560 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
563 static const struct drm_display_mode auo_b101aw03_mode = {
566 .hsync_start = 1024 + 156,
567 .hsync_end = 1024 + 156 + 8,
568 .htotal = 1024 + 156 + 8 + 156,
570 .vsync_start = 600 + 16,
571 .vsync_end = 600 + 16 + 6,
572 .vtotal = 600 + 16 + 6 + 16,
576 static const struct panel_desc auo_b101aw03 = {
577 .modes = &auo_b101aw03_mode,
586 static const struct display_timing auo_b101ean01_timing = {
587 .pixelclock = { 65300000, 72500000, 75000000 },
588 .hactive = { 1280, 1280, 1280 },
589 .hfront_porch = { 18, 119, 119 },
590 .hback_porch = { 21, 21, 21 },
591 .hsync_len = { 32, 32, 32 },
592 .vactive = { 800, 800, 800 },
593 .vfront_porch = { 4, 4, 4 },
594 .vback_porch = { 8, 8, 8 },
595 .vsync_len = { 18, 20, 20 },
598 static const struct panel_desc auo_b101ean01 = {
599 .timings = &auo_b101ean01_timing,
608 static const struct drm_display_mode auo_b101xtn01_mode = {
611 .hsync_start = 1366 + 20,
612 .hsync_end = 1366 + 20 + 70,
613 .htotal = 1366 + 20 + 70,
615 .vsync_start = 768 + 14,
616 .vsync_end = 768 + 14 + 42,
617 .vtotal = 768 + 14 + 42,
619 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
622 static const struct panel_desc auo_b101xtn01 = {
623 .modes = &auo_b101xtn01_mode,
632 static const struct drm_display_mode auo_b116xw03_mode = {
635 .hsync_start = 1366 + 40,
636 .hsync_end = 1366 + 40 + 40,
637 .htotal = 1366 + 40 + 40 + 32,
639 .vsync_start = 768 + 10,
640 .vsync_end = 768 + 10 + 12,
641 .vtotal = 768 + 10 + 12 + 6,
645 static const struct panel_desc auo_b116xw03 = {
646 .modes = &auo_b116xw03_mode,
655 static const struct drm_display_mode auo_b133xtn01_mode = {
658 .hsync_start = 1366 + 48,
659 .hsync_end = 1366 + 48 + 32,
660 .htotal = 1366 + 48 + 32 + 20,
662 .vsync_start = 768 + 3,
663 .vsync_end = 768 + 3 + 6,
664 .vtotal = 768 + 3 + 6 + 13,
668 static const struct panel_desc auo_b133xtn01 = {
669 .modes = &auo_b133xtn01_mode,
678 static const struct drm_display_mode auo_b133htn01_mode = {
681 .hsync_start = 1920 + 172,
682 .hsync_end = 1920 + 172 + 80,
683 .htotal = 1920 + 172 + 80 + 60,
685 .vsync_start = 1080 + 25,
686 .vsync_end = 1080 + 25 + 10,
687 .vtotal = 1080 + 25 + 10 + 10,
691 static const struct panel_desc auo_b133htn01 = {
692 .modes = &auo_b133htn01_mode,
706 static const struct display_timing auo_g070vvn01_timings = {
707 .pixelclock = { 33300000, 34209000, 45000000 },
708 .hactive = { 800, 800, 800 },
709 .hfront_porch = { 20, 40, 200 },
710 .hback_porch = { 87, 40, 1 },
711 .hsync_len = { 1, 48, 87 },
712 .vactive = { 480, 480, 480 },
713 .vfront_porch = { 5, 13, 200 },
714 .vback_porch = { 31, 31, 29 },
715 .vsync_len = { 1, 1, 3 },
718 static const struct panel_desc auo_g070vvn01 = {
719 .timings = &auo_g070vvn01_timings,
734 static const struct drm_display_mode auo_g101evn010_mode = {
737 .hsync_start = 1280 + 82,
738 .hsync_end = 1280 + 82 + 2,
739 .htotal = 1280 + 82 + 2 + 84,
741 .vsync_start = 800 + 8,
742 .vsync_end = 800 + 8 + 2,
743 .vtotal = 800 + 8 + 2 + 6,
747 static const struct panel_desc auo_g101evn010 = {
748 .modes = &auo_g101evn010_mode,
755 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
758 static const struct drm_display_mode auo_g104sn02_mode = {
761 .hsync_start = 800 + 40,
762 .hsync_end = 800 + 40 + 216,
763 .htotal = 800 + 40 + 216 + 128,
765 .vsync_start = 600 + 10,
766 .vsync_end = 600 + 10 + 35,
767 .vtotal = 600 + 10 + 35 + 2,
771 static const struct panel_desc auo_g104sn02 = {
772 .modes = &auo_g104sn02_mode,
781 static const struct display_timing auo_g133han01_timings = {
782 .pixelclock = { 134000000, 141200000, 149000000 },
783 .hactive = { 1920, 1920, 1920 },
784 .hfront_porch = { 39, 58, 77 },
785 .hback_porch = { 59, 88, 117 },
786 .hsync_len = { 28, 42, 56 },
787 .vactive = { 1080, 1080, 1080 },
788 .vfront_porch = { 3, 8, 11 },
789 .vback_porch = { 5, 14, 19 },
790 .vsync_len = { 4, 14, 19 },
793 static const struct panel_desc auo_g133han01 = {
794 .timings = &auo_g133han01_timings,
807 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
808 .connector_type = DRM_MODE_CONNECTOR_LVDS,
811 static const struct display_timing auo_g185han01_timings = {
812 .pixelclock = { 120000000, 144000000, 175000000 },
813 .hactive = { 1920, 1920, 1920 },
814 .hfront_porch = { 36, 120, 148 },
815 .hback_porch = { 24, 88, 108 },
816 .hsync_len = { 20, 48, 64 },
817 .vactive = { 1080, 1080, 1080 },
818 .vfront_porch = { 6, 10, 40 },
819 .vback_porch = { 2, 5, 20 },
820 .vsync_len = { 2, 5, 20 },
823 static const struct panel_desc auo_g185han01 = {
824 .timings = &auo_g185han01_timings,
837 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
838 .connector_type = DRM_MODE_CONNECTOR_LVDS,
841 static const struct display_timing auo_p320hvn03_timings = {
842 .pixelclock = { 106000000, 148500000, 164000000 },
843 .hactive = { 1920, 1920, 1920 },
844 .hfront_porch = { 25, 50, 130 },
845 .hback_porch = { 25, 50, 130 },
846 .hsync_len = { 20, 40, 105 },
847 .vactive = { 1080, 1080, 1080 },
848 .vfront_porch = { 8, 17, 150 },
849 .vback_porch = { 8, 17, 150 },
850 .vsync_len = { 4, 11, 100 },
853 static const struct panel_desc auo_p320hvn03 = {
854 .timings = &auo_p320hvn03_timings,
866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
870 static const struct drm_display_mode auo_t215hvn01_mode = {
873 .hsync_start = 1920 + 88,
874 .hsync_end = 1920 + 88 + 44,
875 .htotal = 1920 + 88 + 44 + 148,
877 .vsync_start = 1080 + 4,
878 .vsync_end = 1080 + 4 + 5,
879 .vtotal = 1080 + 4 + 5 + 36,
883 static const struct panel_desc auo_t215hvn01 = {
884 .modes = &auo_t215hvn01_mode,
897 static const struct drm_display_mode avic_tm070ddh03_mode = {
900 .hsync_start = 1024 + 160,
901 .hsync_end = 1024 + 160 + 4,
902 .htotal = 1024 + 160 + 4 + 156,
904 .vsync_start = 600 + 17,
905 .vsync_end = 600 + 17 + 1,
906 .vtotal = 600 + 17 + 1 + 17,
910 static const struct panel_desc avic_tm070ddh03 = {
911 .modes = &avic_tm070ddh03_mode,
925 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
928 .hsync_start = 800 + 40,
929 .hsync_end = 800 + 40 + 48,
930 .htotal = 800 + 40 + 48 + 40,
932 .vsync_start = 480 + 13,
933 .vsync_end = 480 + 13 + 3,
934 .vtotal = 480 + 13 + 3 + 29,
937 static const struct panel_desc bananapi_s070wv20_ct16 = {
938 .modes = &bananapi_s070wv20_ct16_mode,
947 static const struct drm_display_mode boe_hv070wsa_mode = {
950 .hsync_start = 1024 + 30,
951 .hsync_end = 1024 + 30 + 30,
952 .htotal = 1024 + 30 + 30 + 30,
954 .vsync_start = 600 + 10,
955 .vsync_end = 600 + 10 + 10,
956 .vtotal = 600 + 10 + 10 + 10,
960 static const struct panel_desc boe_hv070wsa = {
961 .modes = &boe_hv070wsa_mode,
969 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
973 .hsync_start = 1280 + 48,
974 .hsync_end = 1280 + 48 + 32,
975 .htotal = 1280 + 48 + 32 + 80,
977 .vsync_start = 800 + 3,
978 .vsync_end = 800 + 3 + 5,
979 .vtotal = 800 + 3 + 5 + 24,
985 .hsync_start = 1280 + 48,
986 .hsync_end = 1280 + 48 + 32,
987 .htotal = 1280 + 48 + 32 + 80,
989 .vsync_start = 800 + 3,
990 .vsync_end = 800 + 3 + 5,
991 .vtotal = 800 + 3 + 5 + 24,
996 static const struct panel_desc boe_nv101wxmn51 = {
997 .modes = boe_nv101wxmn51_modes,
998 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1011 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1014 .hsync_start = 480 + 5,
1015 .hsync_end = 480 + 5 + 5,
1016 .htotal = 480 + 5 + 5 + 40,
1018 .vsync_start = 272 + 8,
1019 .vsync_end = 272 + 8 + 8,
1020 .vtotal = 272 + 8 + 8 + 8,
1022 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1025 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1026 .modes = &cdtech_s043wq26h_ct7_mode,
1033 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1036 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1039 .hsync_start = 800 + 40,
1040 .hsync_end = 800 + 40 + 40,
1041 .htotal = 800 + 40 + 40 + 48,
1043 .vsync_start = 480 + 29,
1044 .vsync_end = 480 + 29 + 13,
1045 .vtotal = 480 + 29 + 13 + 3,
1047 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1050 static const struct panel_desc cdtech_s070wv95_ct16 = {
1051 .modes = &cdtech_s070wv95_ct16_mode,
1060 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1063 .hsync_start = 800 + 49,
1064 .hsync_end = 800 + 49 + 33,
1065 .htotal = 800 + 49 + 33 + 17,
1067 .vsync_start = 1280 + 1,
1068 .vsync_end = 1280 + 1 + 7,
1069 .vtotal = 1280 + 1 + 7 + 15,
1071 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1074 static const struct panel_desc chunghwa_claa070wp03xg = {
1075 .modes = &chunghwa_claa070wp03xg_mode,
1084 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1087 .hsync_start = 1366 + 58,
1088 .hsync_end = 1366 + 58 + 58,
1089 .htotal = 1366 + 58 + 58 + 58,
1091 .vsync_start = 768 + 4,
1092 .vsync_end = 768 + 4 + 4,
1093 .vtotal = 768 + 4 + 4 + 4,
1097 static const struct panel_desc chunghwa_claa101wa01a = {
1098 .modes = &chunghwa_claa101wa01a_mode,
1107 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1110 .hsync_start = 1366 + 48,
1111 .hsync_end = 1366 + 48 + 32,
1112 .htotal = 1366 + 48 + 32 + 20,
1114 .vsync_start = 768 + 16,
1115 .vsync_end = 768 + 16 + 8,
1116 .vtotal = 768 + 16 + 8 + 16,
1120 static const struct panel_desc chunghwa_claa101wb01 = {
1121 .modes = &chunghwa_claa101wb01_mode,
1130 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1133 .hsync_start = 800 + 40,
1134 .hsync_end = 800 + 40 + 128,
1135 .htotal = 800 + 40 + 128 + 88,
1137 .vsync_start = 480 + 10,
1138 .vsync_end = 480 + 10 + 2,
1139 .vtotal = 480 + 10 + 2 + 33,
1141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1144 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1145 .modes = &dataimage_scf0700c48ggu18_mode,
1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1153 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1156 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1157 .pixelclock = { 45000000, 51200000, 57000000 },
1158 .hactive = { 1024, 1024, 1024 },
1159 .hfront_porch = { 100, 106, 113 },
1160 .hback_porch = { 100, 106, 113 },
1161 .hsync_len = { 100, 108, 114 },
1162 .vactive = { 600, 600, 600 },
1163 .vfront_porch = { 8, 11, 15 },
1164 .vback_porch = { 8, 11, 15 },
1165 .vsync_len = { 9, 13, 15 },
1166 .flags = DISPLAY_FLAGS_DE_HIGH,
1169 static const struct panel_desc dlc_dlc0700yzg_1 = {
1170 .timings = &dlc_dlc0700yzg_1_timing,
1182 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1183 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1186 static const struct display_timing dlc_dlc1010gig_timing = {
1187 .pixelclock = { 68900000, 71100000, 73400000 },
1188 .hactive = { 1280, 1280, 1280 },
1189 .hfront_porch = { 43, 53, 63 },
1190 .hback_porch = { 43, 53, 63 },
1191 .hsync_len = { 44, 54, 64 },
1192 .vactive = { 800, 800, 800 },
1193 .vfront_porch = { 5, 8, 11 },
1194 .vback_porch = { 5, 8, 11 },
1195 .vsync_len = { 5, 7, 11 },
1196 .flags = DISPLAY_FLAGS_DE_HIGH,
1199 static const struct panel_desc dlc_dlc1010gig = {
1200 .timings = &dlc_dlc1010gig_timing,
1213 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1214 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1217 static const struct drm_display_mode edt_et035012dm6_mode = {
1220 .hsync_start = 320 + 20,
1221 .hsync_end = 320 + 20 + 30,
1222 .htotal = 320 + 20 + 68,
1224 .vsync_start = 240 + 4,
1225 .vsync_end = 240 + 4 + 4,
1226 .vtotal = 240 + 4 + 4 + 14,
1228 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1231 static const struct panel_desc edt_et035012dm6 = {
1232 .modes = &edt_et035012dm6_mode,
1239 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1240 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1243 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1246 .hsync_start = 480 + 2,
1247 .hsync_end = 480 + 2 + 41,
1248 .htotal = 480 + 2 + 41 + 2,
1250 .vsync_start = 272 + 2,
1251 .vsync_end = 272 + 2 + 10,
1252 .vtotal = 272 + 2 + 10 + 2,
1254 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1257 static const struct panel_desc edt_etm0430g0dh6 = {
1258 .modes = &edt_etm0430g0dh6_mode,
1267 static const struct drm_display_mode edt_et057090dhu_mode = {
1270 .hsync_start = 640 + 16,
1271 .hsync_end = 640 + 16 + 30,
1272 .htotal = 640 + 16 + 30 + 114,
1274 .vsync_start = 480 + 10,
1275 .vsync_end = 480 + 10 + 3,
1276 .vtotal = 480 + 10 + 3 + 32,
1278 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1281 static const struct panel_desc edt_et057090dhu = {
1282 .modes = &edt_et057090dhu_mode,
1289 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1293 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1296 .hsync_start = 800 + 40,
1297 .hsync_end = 800 + 40 + 128,
1298 .htotal = 800 + 40 + 128 + 88,
1300 .vsync_start = 480 + 10,
1301 .vsync_end = 480 + 10 + 2,
1302 .vtotal = 480 + 10 + 2 + 33,
1304 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1307 static const struct panel_desc edt_etm0700g0dh6 = {
1308 .modes = &edt_etm0700g0dh6_mode,
1315 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1316 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1319 static const struct panel_desc edt_etm0700g0bdh6 = {
1320 .modes = &edt_etm0700g0dh6_mode,
1327 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1328 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1331 static const struct display_timing evervision_vgg804821_timing = {
1332 .pixelclock = { 27600000, 33300000, 50000000 },
1333 .hactive = { 800, 800, 800 },
1334 .hfront_porch = { 40, 66, 70 },
1335 .hback_porch = { 40, 67, 70 },
1336 .hsync_len = { 40, 67, 70 },
1337 .vactive = { 480, 480, 480 },
1338 .vfront_porch = { 6, 10, 10 },
1339 .vback_porch = { 7, 11, 11 },
1340 .vsync_len = { 7, 11, 11 },
1341 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1342 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1343 DISPLAY_FLAGS_SYNC_NEGEDGE,
1346 static const struct panel_desc evervision_vgg804821 = {
1347 .timings = &evervision_vgg804821_timing,
1354 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1355 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1358 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1361 .hsync_start = 800 + 168,
1362 .hsync_end = 800 + 168 + 64,
1363 .htotal = 800 + 168 + 64 + 88,
1365 .vsync_start = 480 + 37,
1366 .vsync_end = 480 + 37 + 2,
1367 .vtotal = 480 + 37 + 2 + 8,
1371 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1372 .modes = &foxlink_fl500wvr00_a0t_mode,
1379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1382 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1385 .hsync_start = 800 + 20,
1386 .hsync_end = 800 + 20 + 24,
1387 .htotal = 800 + 20 + 24 + 20,
1389 .vsync_start = 1280 + 4,
1390 .vsync_end = 1280 + 4 + 8,
1391 .vtotal = 1280 + 4 + 8 + 4,
1393 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1396 static const struct panel_desc friendlyarm_hd702e = {
1397 .modes = &friendlyarm_hd702e_mode,
1405 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1408 .hsync_start = 480 + 5,
1409 .hsync_end = 480 + 5 + 1,
1410 .htotal = 480 + 5 + 1 + 40,
1412 .vsync_start = 272 + 8,
1413 .vsync_end = 272 + 8 + 1,
1414 .vtotal = 272 + 8 + 1 + 8,
1418 static const struct panel_desc giantplus_gpg482739qs5 = {
1419 .modes = &giantplus_gpg482739qs5_mode,
1426 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1429 static const struct display_timing giantplus_gpm940b0_timing = {
1430 .pixelclock = { 13500000, 27000000, 27500000 },
1431 .hactive = { 320, 320, 320 },
1432 .hfront_porch = { 14, 686, 718 },
1433 .hback_porch = { 50, 70, 255 },
1434 .hsync_len = { 1, 1, 1 },
1435 .vactive = { 240, 240, 240 },
1436 .vfront_porch = { 1, 1, 179 },
1437 .vback_porch = { 1, 21, 31 },
1438 .vsync_len = { 1, 1, 6 },
1439 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1442 static const struct panel_desc giantplus_gpm940b0 = {
1443 .timings = &giantplus_gpm940b0_timing,
1450 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1451 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1454 static const struct display_timing hannstar_hsd070pww1_timing = {
1455 .pixelclock = { 64300000, 71100000, 82000000 },
1456 .hactive = { 1280, 1280, 1280 },
1457 .hfront_porch = { 1, 1, 10 },
1458 .hback_porch = { 1, 1, 10 },
1460 * According to the data sheet, the minimum horizontal blanking interval
1461 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1462 * minimum working horizontal blanking interval to be 60 clocks.
1464 .hsync_len = { 58, 158, 661 },
1465 .vactive = { 800, 800, 800 },
1466 .vfront_porch = { 1, 1, 10 },
1467 .vback_porch = { 1, 1, 10 },
1468 .vsync_len = { 1, 21, 203 },
1469 .flags = DISPLAY_FLAGS_DE_HIGH,
1472 static const struct panel_desc hannstar_hsd070pww1 = {
1473 .timings = &hannstar_hsd070pww1_timing,
1480 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1481 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1484 static const struct display_timing hannstar_hsd100pxn1_timing = {
1485 .pixelclock = { 55000000, 65000000, 75000000 },
1486 .hactive = { 1024, 1024, 1024 },
1487 .hfront_porch = { 40, 40, 40 },
1488 .hback_porch = { 220, 220, 220 },
1489 .hsync_len = { 20, 60, 100 },
1490 .vactive = { 768, 768, 768 },
1491 .vfront_porch = { 7, 7, 7 },
1492 .vback_porch = { 21, 21, 21 },
1493 .vsync_len = { 10, 10, 10 },
1494 .flags = DISPLAY_FLAGS_DE_HIGH,
1497 static const struct panel_desc hannstar_hsd100pxn1 = {
1498 .timings = &hannstar_hsd100pxn1_timing,
1505 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1506 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1509 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1512 .hsync_start = 800 + 85,
1513 .hsync_end = 800 + 85 + 86,
1514 .htotal = 800 + 85 + 86 + 85,
1516 .vsync_start = 480 + 16,
1517 .vsync_end = 480 + 16 + 13,
1518 .vtotal = 480 + 16 + 13 + 16,
1522 static const struct panel_desc hitachi_tx23d38vm0caa = {
1523 .modes = &hitachi_tx23d38vm0caa_mode,
1536 static const struct drm_display_mode innolux_at043tn24_mode = {
1539 .hsync_start = 480 + 2,
1540 .hsync_end = 480 + 2 + 41,
1541 .htotal = 480 + 2 + 41 + 2,
1543 .vsync_start = 272 + 2,
1544 .vsync_end = 272 + 2 + 10,
1545 .vtotal = 272 + 2 + 10 + 2,
1547 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1550 static const struct panel_desc innolux_at043tn24 = {
1551 .modes = &innolux_at043tn24_mode,
1558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1559 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1562 static const struct drm_display_mode innolux_at070tn92_mode = {
1565 .hsync_start = 800 + 210,
1566 .hsync_end = 800 + 210 + 20,
1567 .htotal = 800 + 210 + 20 + 46,
1569 .vsync_start = 480 + 22,
1570 .vsync_end = 480 + 22 + 10,
1571 .vtotal = 480 + 22 + 23 + 10,
1575 static const struct panel_desc innolux_at070tn92 = {
1576 .modes = &innolux_at070tn92_mode,
1582 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1585 static const struct display_timing innolux_g070y2_l01_timing = {
1586 .pixelclock = { 28000000, 29500000, 32000000 },
1587 .hactive = { 800, 800, 800 },
1588 .hfront_porch = { 61, 91, 141 },
1589 .hback_porch = { 60, 90, 140 },
1590 .hsync_len = { 12, 12, 12 },
1591 .vactive = { 480, 480, 480 },
1592 .vfront_porch = { 4, 9, 30 },
1593 .vback_porch = { 4, 8, 28 },
1594 .vsync_len = { 2, 2, 2 },
1595 .flags = DISPLAY_FLAGS_DE_HIGH,
1598 static const struct panel_desc innolux_g070y2_l01 = {
1599 .timings = &innolux_g070y2_l01_timing,
1612 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1613 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1616 static const struct display_timing innolux_g101ice_l01_timing = {
1617 .pixelclock = { 60400000, 71100000, 74700000 },
1618 .hactive = { 1280, 1280, 1280 },
1619 .hfront_porch = { 41, 80, 100 },
1620 .hback_porch = { 40, 79, 99 },
1621 .hsync_len = { 1, 1, 1 },
1622 .vactive = { 800, 800, 800 },
1623 .vfront_porch = { 5, 11, 14 },
1624 .vback_porch = { 4, 11, 14 },
1625 .vsync_len = { 1, 1, 1 },
1626 .flags = DISPLAY_FLAGS_DE_HIGH,
1629 static const struct panel_desc innolux_g101ice_l01 = {
1630 .timings = &innolux_g101ice_l01_timing,
1641 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1642 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1645 static const struct display_timing innolux_g121i1_l01_timing = {
1646 .pixelclock = { 67450000, 71000000, 74550000 },
1647 .hactive = { 1280, 1280, 1280 },
1648 .hfront_porch = { 40, 80, 160 },
1649 .hback_porch = { 39, 79, 159 },
1650 .hsync_len = { 1, 1, 1 },
1651 .vactive = { 800, 800, 800 },
1652 .vfront_porch = { 5, 11, 100 },
1653 .vback_porch = { 4, 11, 99 },
1654 .vsync_len = { 1, 1, 1 },
1657 static const struct panel_desc innolux_g121i1_l01 = {
1658 .timings = &innolux_g121i1_l01_timing,
1669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1670 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1673 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1676 .hsync_start = 1024 + 0,
1677 .hsync_end = 1024 + 1,
1678 .htotal = 1024 + 0 + 1 + 320,
1680 .vsync_start = 768 + 38,
1681 .vsync_end = 768 + 38 + 1,
1682 .vtotal = 768 + 38 + 1 + 0,
1684 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1687 static const struct panel_desc innolux_g121x1_l03 = {
1688 .modes = &innolux_g121x1_l03_mode,
1703 * Datasheet specifies that at 60 Hz refresh rate:
1704 * - total horizontal time: { 1506, 1592, 1716 }
1705 * - total vertical time: { 788, 800, 868 }
1707 * ...but doesn't go into exactly how that should be split into a front
1708 * porch, back porch, or sync length. For now we'll leave a single setting
1709 * here which allows a bit of tweaking of the pixel clock at the expense of
1712 static const struct display_timing innolux_n116bge_timing = {
1713 .pixelclock = { 72600000, 76420000, 80240000 },
1714 .hactive = { 1366, 1366, 1366 },
1715 .hfront_porch = { 136, 136, 136 },
1716 .hback_porch = { 60, 60, 60 },
1717 .hsync_len = { 30, 30, 30 },
1718 .vactive = { 768, 768, 768 },
1719 .vfront_porch = { 8, 8, 8 },
1720 .vback_porch = { 12, 12, 12 },
1721 .vsync_len = { 12, 12, 12 },
1722 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1725 static const struct panel_desc innolux_n116bge = {
1726 .timings = &innolux_n116bge_timing,
1735 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1738 .hsync_start = 1366 + 16,
1739 .hsync_end = 1366 + 16 + 34,
1740 .htotal = 1366 + 16 + 34 + 50,
1742 .vsync_start = 768 + 2,
1743 .vsync_end = 768 + 2 + 6,
1744 .vtotal = 768 + 2 + 6 + 12,
1748 static const struct panel_desc innolux_n156bge_l21 = {
1749 .modes = &innolux_n156bge_l21_mode,
1758 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1761 .hsync_start = 2160 + 48,
1762 .hsync_end = 2160 + 48 + 32,
1763 .htotal = 2160 + 48 + 32 + 80,
1765 .vsync_start = 1440 + 3,
1766 .vsync_end = 1440 + 3 + 10,
1767 .vtotal = 1440 + 3 + 10 + 27,
1769 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1772 static const struct panel_desc innolux_p120zdg_bf1 = {
1773 .modes = &innolux_p120zdg_bf1_mode,
1781 .hpd_absent_delay = 200,
1786 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1789 .hsync_start = 1024 + 128,
1790 .hsync_end = 1024 + 128 + 64,
1791 .htotal = 1024 + 128 + 64 + 128,
1793 .vsync_start = 600 + 16,
1794 .vsync_end = 600 + 16 + 4,
1795 .vtotal = 600 + 16 + 4 + 16,
1799 static const struct panel_desc innolux_zj070na_01p = {
1800 .modes = &innolux_zj070na_01p_mode,
1809 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1810 .pixelclock = { 5580000, 5850000, 6200000 },
1811 .hactive = { 320, 320, 320 },
1812 .hfront_porch = { 30, 30, 30 },
1813 .hback_porch = { 30, 30, 30 },
1814 .hsync_len = { 1, 5, 17 },
1815 .vactive = { 240, 240, 240 },
1816 .vfront_porch = { 6, 6, 6 },
1817 .vback_porch = { 5, 5, 5 },
1818 .vsync_len = { 1, 2, 11 },
1819 .flags = DISPLAY_FLAGS_DE_HIGH,
1822 static const struct panel_desc koe_tx14d24vm1bpa = {
1823 .timings = &koe_tx14d24vm1bpa_timing,
1832 static const struct display_timing koe_tx31d200vm0baa_timing = {
1833 .pixelclock = { 39600000, 43200000, 48000000 },
1834 .hactive = { 1280, 1280, 1280 },
1835 .hfront_porch = { 16, 36, 56 },
1836 .hback_porch = { 16, 36, 56 },
1837 .hsync_len = { 8, 8, 8 },
1838 .vactive = { 480, 480, 480 },
1839 .vfront_porch = { 6, 21, 33 },
1840 .vback_porch = { 6, 21, 33 },
1841 .vsync_len = { 8, 8, 8 },
1842 .flags = DISPLAY_FLAGS_DE_HIGH,
1845 static const struct panel_desc koe_tx31d200vm0baa = {
1846 .timings = &koe_tx31d200vm0baa_timing,
1853 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1854 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1857 static const struct display_timing kyo_tcg121xglp_timing = {
1858 .pixelclock = { 52000000, 65000000, 71000000 },
1859 .hactive = { 1024, 1024, 1024 },
1860 .hfront_porch = { 2, 2, 2 },
1861 .hback_porch = { 2, 2, 2 },
1862 .hsync_len = { 86, 124, 244 },
1863 .vactive = { 768, 768, 768 },
1864 .vfront_porch = { 2, 2, 2 },
1865 .vback_porch = { 2, 2, 2 },
1866 .vsync_len = { 6, 34, 73 },
1867 .flags = DISPLAY_FLAGS_DE_HIGH,
1870 static const struct panel_desc kyo_tcg121xglp = {
1871 .timings = &kyo_tcg121xglp_timing,
1878 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1879 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1882 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1885 .hsync_start = 320 + 20,
1886 .hsync_end = 320 + 20 + 30,
1887 .htotal = 320 + 20 + 30 + 38,
1889 .vsync_start = 240 + 4,
1890 .vsync_end = 240 + 4 + 3,
1891 .vtotal = 240 + 4 + 3 + 15,
1895 static const struct panel_desc lemaker_bl035_rgb_002 = {
1896 .modes = &lemaker_bl035_rgb_002_mode,
1902 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1903 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1906 static const struct drm_display_mode lg_lb070wv8_mode = {
1909 .hsync_start = 800 + 88,
1910 .hsync_end = 800 + 88 + 80,
1911 .htotal = 800 + 88 + 80 + 88,
1913 .vsync_start = 480 + 10,
1914 .vsync_end = 480 + 10 + 25,
1915 .vtotal = 480 + 10 + 25 + 10,
1919 static const struct panel_desc lg_lb070wv8 = {
1920 .modes = &lg_lb070wv8_mode,
1927 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1928 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1931 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1934 .hsync_start = 1536 + 12,
1935 .hsync_end = 1536 + 12 + 16,
1936 .htotal = 1536 + 12 + 16 + 48,
1938 .vsync_start = 2048 + 8,
1939 .vsync_end = 2048 + 8 + 4,
1940 .vtotal = 2048 + 8 + 4 + 8,
1942 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1945 static const struct panel_desc lg_lp079qx1_sp0v = {
1946 .modes = &lg_lp079qx1_sp0v_mode,
1954 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1957 .hsync_start = 2048 + 150,
1958 .hsync_end = 2048 + 150 + 5,
1959 .htotal = 2048 + 150 + 5 + 5,
1961 .vsync_start = 1536 + 3,
1962 .vsync_end = 1536 + 3 + 1,
1963 .vtotal = 1536 + 3 + 1 + 9,
1967 static const struct panel_desc lg_lp097qx1_spa1 = {
1968 .modes = &lg_lp097qx1_spa1_mode,
1976 static const struct drm_display_mode lg_lp120up1_mode = {
1979 .hsync_start = 1920 + 40,
1980 .hsync_end = 1920 + 40 + 40,
1981 .htotal = 1920 + 40 + 40+ 80,
1983 .vsync_start = 1280 + 4,
1984 .vsync_end = 1280 + 4 + 4,
1985 .vtotal = 1280 + 4 + 4 + 12,
1989 static const struct panel_desc lg_lp120up1 = {
1990 .modes = &lg_lp120up1_mode,
1999 static const struct drm_display_mode lg_lp129qe_mode = {
2002 .hsync_start = 2560 + 48,
2003 .hsync_end = 2560 + 48 + 32,
2004 .htotal = 2560 + 48 + 32 + 80,
2006 .vsync_start = 1700 + 3,
2007 .vsync_end = 1700 + 3 + 10,
2008 .vtotal = 1700 + 3 + 10 + 36,
2012 static const struct panel_desc lg_lp129qe = {
2013 .modes = &lg_lp129qe_mode,
2022 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2025 .hsync_start = 800 + 0,
2026 .hsync_end = 800 + 1,
2027 .htotal = 800 + 0 + 1 + 160,
2029 .vsync_start = 480 + 0,
2030 .vsync_end = 480 + 48 + 1,
2031 .vtotal = 480 + 48 + 1 + 0,
2033 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2036 static const struct drm_display_mode logicpd_type_28_mode = {
2039 .hsync_start = 480 + 3,
2040 .hsync_end = 480 + 3 + 42,
2041 .htotal = 480 + 3 + 42 + 2,
2044 .vsync_start = 272 + 2,
2045 .vsync_end = 272 + 2 + 11,
2046 .vtotal = 272 + 2 + 11 + 3,
2048 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2051 static const struct panel_desc logicpd_type_28 = {
2052 .modes = &logicpd_type_28_mode,
2065 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2066 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2067 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2070 static const struct panel_desc mitsubishi_aa070mc01 = {
2071 .modes = &mitsubishi_aa070mc01_mode,
2084 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2085 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2086 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2089 static const struct display_timing nec_nl12880bc20_05_timing = {
2090 .pixelclock = { 67000000, 71000000, 75000000 },
2091 .hactive = { 1280, 1280, 1280 },
2092 .hfront_porch = { 2, 30, 30 },
2093 .hback_porch = { 6, 100, 100 },
2094 .hsync_len = { 2, 30, 30 },
2095 .vactive = { 800, 800, 800 },
2096 .vfront_porch = { 5, 5, 5 },
2097 .vback_porch = { 11, 11, 11 },
2098 .vsync_len = { 7, 7, 7 },
2101 static const struct panel_desc nec_nl12880bc20_05 = {
2102 .timings = &nec_nl12880bc20_05_timing,
2113 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2114 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2117 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2120 .hsync_start = 480 + 2,
2121 .hsync_end = 480 + 2 + 41,
2122 .htotal = 480 + 2 + 41 + 2,
2124 .vsync_start = 272 + 2,
2125 .vsync_end = 272 + 2 + 4,
2126 .vtotal = 272 + 2 + 4 + 2,
2128 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2131 static const struct panel_desc nec_nl4827hc19_05b = {
2132 .modes = &nec_nl4827hc19_05b_mode,
2139 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2140 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2143 static const struct drm_display_mode netron_dy_e231732_mode = {
2146 .hsync_start = 1024 + 160,
2147 .hsync_end = 1024 + 160 + 70,
2148 .htotal = 1024 + 160 + 70 + 90,
2150 .vsync_start = 600 + 127,
2151 .vsync_end = 600 + 127 + 20,
2152 .vtotal = 600 + 127 + 20 + 3,
2156 static const struct panel_desc netron_dy_e231732 = {
2157 .modes = &netron_dy_e231732_mode,
2163 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2166 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2169 .hsync_start = 480 + 2,
2170 .hsync_end = 480 + 2 + 41,
2171 .htotal = 480 + 2 + 41 + 2,
2173 .vsync_start = 272 + 2,
2174 .vsync_end = 272 + 2 + 10,
2175 .vtotal = 272 + 2 + 10 + 2,
2177 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2180 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2181 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2188 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2189 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2190 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2193 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2194 .pixelclock = { 130000000, 148350000, 163000000 },
2195 .hactive = { 1920, 1920, 1920 },
2196 .hfront_porch = { 80, 100, 100 },
2197 .hback_porch = { 100, 120, 120 },
2198 .hsync_len = { 50, 60, 60 },
2199 .vactive = { 1080, 1080, 1080 },
2200 .vfront_porch = { 12, 30, 30 },
2201 .vback_porch = { 4, 10, 10 },
2202 .vsync_len = { 4, 5, 5 },
2205 static const struct panel_desc nlt_nl192108ac18_02d = {
2206 .timings = &nlt_nl192108ac18_02d_timing,
2216 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2217 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2220 static const struct drm_display_mode nvd_9128_mode = {
2223 .hsync_start = 800 + 130,
2224 .hsync_end = 800 + 130 + 98,
2225 .htotal = 800 + 0 + 130 + 98,
2227 .vsync_start = 480 + 10,
2228 .vsync_end = 480 + 10 + 50,
2229 .vtotal = 480 + 0 + 10 + 50,
2232 static const struct panel_desc nvd_9128 = {
2233 .modes = &nvd_9128_mode,
2240 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2241 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2244 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2245 .pixelclock = { 30000000, 30000000, 40000000 },
2246 .hactive = { 800, 800, 800 },
2247 .hfront_porch = { 40, 40, 40 },
2248 .hback_porch = { 40, 40, 40 },
2249 .hsync_len = { 1, 48, 48 },
2250 .vactive = { 480, 480, 480 },
2251 .vfront_porch = { 13, 13, 13 },
2252 .vback_porch = { 29, 29, 29 },
2253 .vsync_len = { 3, 3, 3 },
2254 .flags = DISPLAY_FLAGS_DE_HIGH,
2257 static const struct panel_desc okaya_rs800480t_7x0gp = {
2258 .timings = &okaya_rs800480t_7x0gp_timing,
2271 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2274 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2277 .hsync_start = 480 + 5,
2278 .hsync_end = 480 + 5 + 30,
2279 .htotal = 480 + 5 + 30 + 10,
2281 .vsync_start = 272 + 8,
2282 .vsync_end = 272 + 8 + 5,
2283 .vtotal = 272 + 8 + 5 + 3,
2287 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2288 .modes = &olimex_lcd_olinuxino_43ts_mode,
2294 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2298 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2299 * pixel clocks, but this is the timing that was being used in the Adafruit
2300 * installation instructions.
2302 static const struct drm_display_mode ontat_yx700wv03_mode = {
2313 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2318 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2320 static const struct panel_desc ontat_yx700wv03 = {
2321 .modes = &ontat_yx700wv03_mode,
2328 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2331 static const struct drm_display_mode ortustech_com37h3m_mode = {
2334 .hsync_start = 480 + 8,
2335 .hsync_end = 480 + 8 + 10,
2336 .htotal = 480 + 8 + 10 + 10,
2338 .vsync_start = 640 + 4,
2339 .vsync_end = 640 + 4 + 3,
2340 .vtotal = 640 + 4 + 3 + 4,
2342 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2345 static const struct panel_desc ortustech_com37h3m = {
2346 .modes = &ortustech_com37h3m_mode,
2350 .width = 56, /* 56.16mm */
2351 .height = 75, /* 74.88mm */
2353 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2354 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2355 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2358 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2361 .hsync_start = 480 + 10,
2362 .hsync_end = 480 + 10 + 10,
2363 .htotal = 480 + 10 + 10 + 15,
2365 .vsync_start = 800 + 3,
2366 .vsync_end = 800 + 3 + 3,
2367 .vtotal = 800 + 3 + 3 + 3,
2371 static const struct panel_desc ortustech_com43h4m85ulc = {
2372 .modes = &ortustech_com43h4m85ulc_mode,
2379 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2380 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2383 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2386 .hsync_start = 800 + 210,
2387 .hsync_end = 800 + 210 + 30,
2388 .htotal = 800 + 210 + 30 + 16,
2390 .vsync_start = 480 + 22,
2391 .vsync_end = 480 + 22 + 13,
2392 .vtotal = 480 + 22 + 13 + 10,
2394 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2397 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2398 .modes = &osddisplays_osd070t1718_19ts_mode,
2405 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2406 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2407 .connector_type = DRM_MODE_CONNECTOR_DPI,
2410 static const struct drm_display_mode pda_91_00156_a0_mode = {
2413 .hsync_start = 800 + 1,
2414 .hsync_end = 800 + 1 + 64,
2415 .htotal = 800 + 1 + 64 + 64,
2417 .vsync_start = 480 + 1,
2418 .vsync_end = 480 + 1 + 23,
2419 .vtotal = 480 + 1 + 23 + 22,
2423 static const struct panel_desc pda_91_00156_a0 = {
2424 .modes = &pda_91_00156_a0_mode,
2430 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2434 static const struct drm_display_mode qd43003c0_40_mode = {
2437 .hsync_start = 480 + 8,
2438 .hsync_end = 480 + 8 + 4,
2439 .htotal = 480 + 8 + 4 + 39,
2441 .vsync_start = 272 + 4,
2442 .vsync_end = 272 + 4 + 10,
2443 .vtotal = 272 + 4 + 10 + 2,
2447 static const struct panel_desc qd43003c0_40 = {
2448 .modes = &qd43003c0_40_mode,
2455 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2458 static const struct display_timing rocktech_rk070er9427_timing = {
2459 .pixelclock = { 26400000, 33300000, 46800000 },
2460 .hactive = { 800, 800, 800 },
2461 .hfront_porch = { 16, 210, 354 },
2462 .hback_porch = { 46, 46, 46 },
2463 .hsync_len = { 1, 1, 1 },
2464 .vactive = { 480, 480, 480 },
2465 .vfront_porch = { 7, 22, 147 },
2466 .vback_porch = { 23, 23, 23 },
2467 .vsync_len = { 1, 1, 1 },
2468 .flags = DISPLAY_FLAGS_DE_HIGH,
2471 static const struct panel_desc rocktech_rk070er9427 = {
2472 .timings = &rocktech_rk070er9427_timing,
2485 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2488 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2491 .hsync_start = 2560 + 48,
2492 .hsync_end = 2560 + 48 + 32,
2493 .htotal = 2560 + 48 + 32 + 80,
2495 .vsync_start = 1600 + 2,
2496 .vsync_end = 1600 + 2 + 5,
2497 .vtotal = 1600 + 2 + 5 + 57,
2501 static const struct panel_desc samsung_lsn122dl01_c01 = {
2502 .modes = &samsung_lsn122dl01_c01_mode,
2510 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2513 .hsync_start = 1024 + 24,
2514 .hsync_end = 1024 + 24 + 136,
2515 .htotal = 1024 + 24 + 136 + 160,
2517 .vsync_start = 600 + 3,
2518 .vsync_end = 600 + 3 + 6,
2519 .vtotal = 600 + 3 + 6 + 61,
2523 static const struct panel_desc samsung_ltn101nt05 = {
2524 .modes = &samsung_ltn101nt05_mode,
2533 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2536 .hsync_start = 1366 + 64,
2537 .hsync_end = 1366 + 64 + 48,
2538 .htotal = 1366 + 64 + 48 + 128,
2540 .vsync_start = 768 + 2,
2541 .vsync_end = 768 + 2 + 5,
2542 .vtotal = 768 + 2 + 5 + 17,
2546 static const struct panel_desc samsung_ltn140at29_301 = {
2547 .modes = &samsung_ltn140at29_301_mode,
2556 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2559 .hsync_start = 1920 + 48,
2560 .hsync_end = 1920 + 48 + 32,
2561 .htotal = 1920 + 48 + 32 + 80,
2563 .vsync_start = 1280 + 3,
2564 .vsync_end = 1280 + 3 + 10,
2565 .vtotal = 1280 + 3 + 10 + 57,
2567 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2570 static const struct panel_desc sharp_ld_d5116z01b = {
2571 .modes = &sharp_ld_d5116z01b_mode,
2578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2579 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2582 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2585 .hsync_start = 800 + 64,
2586 .hsync_end = 800 + 64 + 128,
2587 .htotal = 800 + 64 + 128 + 64,
2589 .vsync_start = 480 + 8,
2590 .vsync_end = 480 + 8 + 2,
2591 .vtotal = 480 + 8 + 2 + 35,
2593 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2596 static const struct panel_desc sharp_lq070y3dg3b = {
2597 .modes = &sharp_lq070y3dg3b_mode,
2601 .width = 152, /* 152.4mm */
2602 .height = 91, /* 91.4mm */
2604 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2605 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2606 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2609 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2612 .hsync_start = 240 + 16,
2613 .hsync_end = 240 + 16 + 7,
2614 .htotal = 240 + 16 + 7 + 5,
2616 .vsync_start = 320 + 9,
2617 .vsync_end = 320 + 9 + 1,
2618 .vtotal = 320 + 9 + 1 + 7,
2622 static const struct panel_desc sharp_lq035q7db03 = {
2623 .modes = &sharp_lq035q7db03_mode,
2630 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2633 static const struct display_timing sharp_lq101k1ly04_timing = {
2634 .pixelclock = { 60000000, 65000000, 80000000 },
2635 .hactive = { 1280, 1280, 1280 },
2636 .hfront_porch = { 20, 20, 20 },
2637 .hback_porch = { 20, 20, 20 },
2638 .hsync_len = { 10, 10, 10 },
2639 .vactive = { 800, 800, 800 },
2640 .vfront_porch = { 4, 4, 4 },
2641 .vback_porch = { 4, 4, 4 },
2642 .vsync_len = { 4, 4, 4 },
2643 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2646 static const struct panel_desc sharp_lq101k1ly04 = {
2647 .timings = &sharp_lq101k1ly04_timing,
2654 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2655 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2658 static const struct display_timing sharp_lq123p1jx31_timing = {
2659 .pixelclock = { 252750000, 252750000, 266604720 },
2660 .hactive = { 2400, 2400, 2400 },
2661 .hfront_porch = { 48, 48, 48 },
2662 .hback_porch = { 80, 80, 84 },
2663 .hsync_len = { 32, 32, 32 },
2664 .vactive = { 1600, 1600, 1600 },
2665 .vfront_porch = { 3, 3, 3 },
2666 .vback_porch = { 33, 33, 120 },
2667 .vsync_len = { 10, 10, 10 },
2668 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2671 static const struct panel_desc sharp_lq123p1jx31 = {
2672 .timings = &sharp_lq123p1jx31_timing,
2686 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2689 .hsync_start = 1024 + 168,
2690 .hsync_end = 1024 + 168 + 64,
2691 .htotal = 1024 + 168 + 64 + 88,
2693 .vsync_start = 768 + 37,
2694 .vsync_end = 768 + 37 + 2,
2695 .vtotal = 768 + 37 + 2 + 8,
2699 static const struct panel_desc sharp_lq150x1lg11 = {
2700 .modes = &sharp_lq150x1lg11_mode,
2707 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2710 static const struct display_timing sharp_ls020b1dd01d_timing = {
2711 .pixelclock = { 2000000, 4200000, 5000000 },
2712 .hactive = { 240, 240, 240 },
2713 .hfront_porch = { 66, 66, 66 },
2714 .hback_porch = { 1, 1, 1 },
2715 .hsync_len = { 1, 1, 1 },
2716 .vactive = { 160, 160, 160 },
2717 .vfront_porch = { 52, 52, 52 },
2718 .vback_porch = { 6, 6, 6 },
2719 .vsync_len = { 10, 10, 10 },
2720 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2723 static const struct panel_desc sharp_ls020b1dd01d = {
2724 .timings = &sharp_ls020b1dd01d_timing,
2731 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2732 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2733 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2734 | DRM_BUS_FLAG_SHARP_SIGNALS,
2737 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2740 .hsync_start = 800 + 1,
2741 .hsync_end = 800 + 1 + 64,
2742 .htotal = 800 + 1 + 64 + 64,
2744 .vsync_start = 480 + 1,
2745 .vsync_end = 480 + 1 + 23,
2746 .vtotal = 480 + 1 + 23 + 22,
2750 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2751 .modes = &shelly_sca07010_bfn_lnn_mode,
2757 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2760 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2763 .hsync_start = 1920 + 16,
2764 .hsync_end = 1920 + 16 + 16,
2765 .htotal = 1920 + 16 + 16 + 32,
2767 .vsync_start = 1200 + 15,
2768 .vsync_end = 1200 + 15 + 2,
2769 .vtotal = 1200 + 15 + 2 + 18,
2771 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2774 static const struct panel_desc starry_kr122ea0sra = {
2775 .modes = &starry_kr122ea0sra_mode,
2782 .prepare = 10 + 200,
2784 .unprepare = 10 + 500,
2788 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2791 .hsync_start = 800 + 39,
2792 .hsync_end = 800 + 39 + 47,
2793 .htotal = 800 + 39 + 47 + 39,
2795 .vsync_start = 480 + 13,
2796 .vsync_end = 480 + 13 + 2,
2797 .vtotal = 480 + 13 + 2 + 29,
2801 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2802 .modes = &tfc_s9700rtwv43tr_01b_mode,
2809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2810 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2813 static const struct display_timing tianma_tm070jdhg30_timing = {
2814 .pixelclock = { 62600000, 68200000, 78100000 },
2815 .hactive = { 1280, 1280, 1280 },
2816 .hfront_porch = { 15, 64, 159 },
2817 .hback_porch = { 5, 5, 5 },
2818 .hsync_len = { 1, 1, 256 },
2819 .vactive = { 800, 800, 800 },
2820 .vfront_porch = { 3, 40, 99 },
2821 .vback_porch = { 2, 2, 2 },
2822 .vsync_len = { 1, 1, 128 },
2823 .flags = DISPLAY_FLAGS_DE_HIGH,
2826 static const struct panel_desc tianma_tm070jdhg30 = {
2827 .timings = &tianma_tm070jdhg30_timing,
2834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2835 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2838 static const struct display_timing tianma_tm070rvhg71_timing = {
2839 .pixelclock = { 27700000, 29200000, 39600000 },
2840 .hactive = { 800, 800, 800 },
2841 .hfront_porch = { 12, 40, 212 },
2842 .hback_porch = { 88, 88, 88 },
2843 .hsync_len = { 1, 1, 40 },
2844 .vactive = { 480, 480, 480 },
2845 .vfront_porch = { 1, 13, 88 },
2846 .vback_porch = { 32, 32, 32 },
2847 .vsync_len = { 1, 1, 3 },
2848 .flags = DISPLAY_FLAGS_DE_HIGH,
2851 static const struct panel_desc tianma_tm070rvhg71 = {
2852 .timings = &tianma_tm070rvhg71_timing,
2859 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2860 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2863 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2867 .hsync_start = 320 + 50,
2868 .hsync_end = 320 + 50 + 6,
2869 .htotal = 320 + 50 + 6 + 38,
2871 .vsync_start = 240 + 3,
2872 .vsync_end = 240 + 3 + 1,
2873 .vtotal = 240 + 3 + 1 + 17,
2875 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2879 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2880 .modes = ti_nspire_cx_lcd_mode,
2887 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2888 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2891 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2895 .hsync_start = 320 + 6,
2896 .hsync_end = 320 + 6 + 6,
2897 .htotal = 320 + 6 + 6 + 6,
2899 .vsync_start = 240 + 0,
2900 .vsync_end = 240 + 0 + 1,
2901 .vtotal = 240 + 0 + 1 + 0,
2903 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2907 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2908 .modes = ti_nspire_classic_lcd_mode,
2910 /* The grayscale panel has 8 bit for the color .. Y (black) */
2916 /* This is the grayscale bus format */
2917 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2918 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2921 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2924 .hsync_start = 1280 + 192,
2925 .hsync_end = 1280 + 192 + 128,
2926 .htotal = 1280 + 192 + 128 + 64,
2928 .vsync_start = 768 + 20,
2929 .vsync_end = 768 + 20 + 7,
2930 .vtotal = 768 + 20 + 7 + 3,
2934 static const struct panel_desc toshiba_lt089ac29000 = {
2935 .modes = &toshiba_lt089ac29000_mode,
2941 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2942 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2943 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2946 static const struct drm_display_mode tpk_f07a_0102_mode = {
2949 .hsync_start = 800 + 40,
2950 .hsync_end = 800 + 40 + 128,
2951 .htotal = 800 + 40 + 128 + 88,
2953 .vsync_start = 480 + 10,
2954 .vsync_end = 480 + 10 + 2,
2955 .vtotal = 480 + 10 + 2 + 33,
2959 static const struct panel_desc tpk_f07a_0102 = {
2960 .modes = &tpk_f07a_0102_mode,
2966 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2969 static const struct drm_display_mode tpk_f10a_0102_mode = {
2972 .hsync_start = 1024 + 176,
2973 .hsync_end = 1024 + 176 + 5,
2974 .htotal = 1024 + 176 + 5 + 88,
2976 .vsync_start = 600 + 20,
2977 .vsync_end = 600 + 20 + 5,
2978 .vtotal = 600 + 20 + 5 + 25,
2982 static const struct panel_desc tpk_f10a_0102 = {
2983 .modes = &tpk_f10a_0102_mode,
2991 static const struct display_timing urt_umsh_8596md_timing = {
2992 .pixelclock = { 33260000, 33260000, 33260000 },
2993 .hactive = { 800, 800, 800 },
2994 .hfront_porch = { 41, 41, 41 },
2995 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2996 .hsync_len = { 71, 128, 128 },
2997 .vactive = { 480, 480, 480 },
2998 .vfront_porch = { 10, 10, 10 },
2999 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3000 .vsync_len = { 2, 2, 2 },
3001 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3002 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3005 static const struct panel_desc urt_umsh_8596md_lvds = {
3006 .timings = &urt_umsh_8596md_timing,
3013 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3014 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3017 static const struct panel_desc urt_umsh_8596md_parallel = {
3018 .timings = &urt_umsh_8596md_timing,
3025 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3028 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3031 .hsync_start = 800 + 210,
3032 .hsync_end = 800 + 210 + 20,
3033 .htotal = 800 + 210 + 20 + 46,
3035 .vsync_start = 480 + 22,
3036 .vsync_end = 480 + 22 + 10,
3037 .vtotal = 480 + 22 + 10 + 23,
3039 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3042 static const struct panel_desc vl050_8048nt_c01 = {
3043 .modes = &vl050_8048nt_c01_mode,
3050 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3051 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3054 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3057 .hsync_start = 320 + 20,
3058 .hsync_end = 320 + 20 + 30,
3059 .htotal = 320 + 20 + 30 + 38,
3061 .vsync_start = 240 + 4,
3062 .vsync_end = 240 + 4 + 3,
3063 .vtotal = 240 + 4 + 3 + 15,
3065 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3068 static const struct panel_desc winstar_wf35ltiacd = {
3069 .modes = &winstar_wf35ltiacd_mode,
3076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3079 static const struct drm_display_mode arm_rtsm_mode[] = {
3083 .hsync_start = 1024 + 24,
3084 .hsync_end = 1024 + 24 + 136,
3085 .htotal = 1024 + 24 + 136 + 160,
3087 .vsync_start = 768 + 3,
3088 .vsync_end = 768 + 3 + 6,
3089 .vtotal = 768 + 3 + 6 + 29,
3091 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3095 static const struct panel_desc arm_rtsm = {
3096 .modes = arm_rtsm_mode,
3103 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3106 static const struct of_device_id platform_of_match[] = {
3108 .compatible = "ampire,am-480272h3tmqw-t01h",
3109 .data = &ire_am_480272h3tmqw_t01h,
3111 .compatible = "ampire,am800480r3tmqwa1h",
3112 .data = &ire_am800480r3tmqwa1h,
3114 .compatible = "arm,rtsm-display",
3117 .compatible = "armadeus,st0700-adapt",
3118 .data = &armadeus_st0700_adapt,
3120 .compatible = "auo,b101aw03",
3121 .data = &auo_b101aw03,
3123 .compatible = "auo,b101ean01",
3124 .data = &auo_b101ean01,
3126 .compatible = "auo,b101xtn01",
3127 .data = &auo_b101xtn01,
3129 .compatible = "auo,b116xw03",
3130 .data = &auo_b116xw03,
3132 .compatible = "auo,b133htn01",
3133 .data = &auo_b133htn01,
3135 .compatible = "auo,b133xtn01",
3136 .data = &auo_b133xtn01,
3138 .compatible = "auo,g070vvn01",
3139 .data = &auo_g070vvn01,
3141 .compatible = "auo,g101evn010",
3142 .data = &auo_g101evn010,
3144 .compatible = "auo,g104sn02",
3145 .data = &auo_g104sn02,
3147 .compatible = "auo,g133han01",
3148 .data = &auo_g133han01,
3150 .compatible = "auo,g185han01",
3151 .data = &auo_g185han01,
3153 .compatible = "auo,p320hvn03",
3154 .data = &auo_p320hvn03,
3156 .compatible = "auo,t215hvn01",
3157 .data = &auo_t215hvn01,
3159 .compatible = "avic,tm070ddh03",
3160 .data = &avic_tm070ddh03,
3162 .compatible = "bananapi,s070wv20-ct16",
3163 .data = &bananapi_s070wv20_ct16,
3165 .compatible = "boe,hv070wsa-100",
3166 .data = &boe_hv070wsa
3168 .compatible = "boe,nv101wxmn51",
3169 .data = &boe_nv101wxmn51,
3171 .compatible = "cdtech,s043wq26h-ct7",
3172 .data = &cdtech_s043wq26h_ct7,
3174 .compatible = "cdtech,s070wv95-ct16",
3175 .data = &cdtech_s070wv95_ct16,
3177 .compatible = "chunghwa,claa070wp03xg",
3178 .data = &chunghwa_claa070wp03xg,
3180 .compatible = "chunghwa,claa101wa01a",
3181 .data = &chunghwa_claa101wa01a
3183 .compatible = "chunghwa,claa101wb01",
3184 .data = &chunghwa_claa101wb01
3186 .compatible = "dataimage,scf0700c48ggu18",
3187 .data = &dataimage_scf0700c48ggu18,
3189 .compatible = "dlc,dlc0700yzg-1",
3190 .data = &dlc_dlc0700yzg_1,
3192 .compatible = "dlc,dlc1010gig",
3193 .data = &dlc_dlc1010gig,
3195 .compatible = "edt,et035012dm6",
3196 .data = &edt_et035012dm6,
3198 .compatible = "edt,etm0430g0dh6",
3199 .data = &edt_etm0430g0dh6,
3201 .compatible = "edt,et057090dhu",
3202 .data = &edt_et057090dhu,
3204 .compatible = "edt,et070080dh6",
3205 .data = &edt_etm0700g0dh6,
3207 .compatible = "edt,etm0700g0dh6",
3208 .data = &edt_etm0700g0dh6,
3210 .compatible = "edt,etm0700g0bdh6",
3211 .data = &edt_etm0700g0bdh6,
3213 .compatible = "edt,etm0700g0edh6",
3214 .data = &edt_etm0700g0bdh6,
3216 .compatible = "evervision,vgg804821",
3217 .data = &evervision_vgg804821,
3219 .compatible = "foxlink,fl500wvr00-a0t",
3220 .data = &foxlink_fl500wvr00_a0t,
3222 .compatible = "friendlyarm,hd702e",
3223 .data = &friendlyarm_hd702e,
3225 .compatible = "giantplus,gpg482739qs5",
3226 .data = &giantplus_gpg482739qs5
3228 .compatible = "giantplus,gpm940b0",
3229 .data = &giantplus_gpm940b0,
3231 .compatible = "hannstar,hsd070pww1",
3232 .data = &hannstar_hsd070pww1,
3234 .compatible = "hannstar,hsd100pxn1",
3235 .data = &hannstar_hsd100pxn1,
3237 .compatible = "hit,tx23d38vm0caa",
3238 .data = &hitachi_tx23d38vm0caa
3240 .compatible = "innolux,at043tn24",
3241 .data = &innolux_at043tn24,
3243 .compatible = "innolux,at070tn92",
3244 .data = &innolux_at070tn92,
3246 .compatible = "innolux,g070y2-l01",
3247 .data = &innolux_g070y2_l01,
3249 .compatible = "innolux,g101ice-l01",
3250 .data = &innolux_g101ice_l01
3252 .compatible = "innolux,g121i1-l01",
3253 .data = &innolux_g121i1_l01
3255 .compatible = "innolux,g121x1-l03",
3256 .data = &innolux_g121x1_l03,
3258 .compatible = "innolux,n116bge",
3259 .data = &innolux_n116bge,
3261 .compatible = "innolux,n156bge-l21",
3262 .data = &innolux_n156bge_l21,
3264 .compatible = "innolux,p120zdg-bf1",
3265 .data = &innolux_p120zdg_bf1,
3267 .compatible = "innolux,zj070na-01p",
3268 .data = &innolux_zj070na_01p,
3270 .compatible = "koe,tx14d24vm1bpa",
3271 .data = &koe_tx14d24vm1bpa,
3273 .compatible = "koe,tx31d200vm0baa",
3274 .data = &koe_tx31d200vm0baa,
3276 .compatible = "kyo,tcg121xglp",
3277 .data = &kyo_tcg121xglp,
3279 .compatible = "lemaker,bl035-rgb-002",
3280 .data = &lemaker_bl035_rgb_002,
3282 .compatible = "lg,lb070wv8",
3283 .data = &lg_lb070wv8,
3285 .compatible = "lg,lp079qx1-sp0v",
3286 .data = &lg_lp079qx1_sp0v,
3288 .compatible = "lg,lp097qx1-spa1",
3289 .data = &lg_lp097qx1_spa1,
3291 .compatible = "lg,lp120up1",
3292 .data = &lg_lp120up1,
3294 .compatible = "lg,lp129qe",
3295 .data = &lg_lp129qe,
3297 .compatible = "logicpd,type28",
3298 .data = &logicpd_type_28,
3300 .compatible = "mitsubishi,aa070mc01-ca1",
3301 .data = &mitsubishi_aa070mc01,
3303 .compatible = "nec,nl12880bc20-05",
3304 .data = &nec_nl12880bc20_05,
3306 .compatible = "nec,nl4827hc19-05b",
3307 .data = &nec_nl4827hc19_05b,
3309 .compatible = "netron-dy,e231732",
3310 .data = &netron_dy_e231732,
3312 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3313 .data = &newhaven_nhd_43_480272ef_atxl,
3315 .compatible = "nlt,nl192108ac18-02d",
3316 .data = &nlt_nl192108ac18_02d,
3318 .compatible = "nvd,9128",
3321 .compatible = "okaya,rs800480t-7x0gp",
3322 .data = &okaya_rs800480t_7x0gp,
3324 .compatible = "olimex,lcd-olinuxino-43-ts",
3325 .data = &olimex_lcd_olinuxino_43ts,
3327 .compatible = "ontat,yx700wv03",
3328 .data = &ontat_yx700wv03,
3330 .compatible = "ortustech,com37h3m05dtc",
3331 .data = &ortustech_com37h3m,
3333 .compatible = "ortustech,com37h3m99dtc",
3334 .data = &ortustech_com37h3m,
3336 .compatible = "ortustech,com43h4m85ulc",
3337 .data = &ortustech_com43h4m85ulc,
3339 .compatible = "osddisplays,osd070t1718-19ts",
3340 .data = &osddisplays_osd070t1718_19ts,
3342 .compatible = "pda,91-00156-a0",
3343 .data = &pda_91_00156_a0,
3345 .compatible = "qiaodian,qd43003c0-40",
3346 .data = &qd43003c0_40,
3348 .compatible = "rocktech,rk070er9427",
3349 .data = &rocktech_rk070er9427,
3351 .compatible = "samsung,lsn122dl01-c01",
3352 .data = &samsung_lsn122dl01_c01,
3354 .compatible = "samsung,ltn101nt05",
3355 .data = &samsung_ltn101nt05,
3357 .compatible = "samsung,ltn140at29-301",
3358 .data = &samsung_ltn140at29_301,
3360 .compatible = "sharp,ld-d5116z01b",
3361 .data = &sharp_ld_d5116z01b,
3363 .compatible = "sharp,lq035q7db03",
3364 .data = &sharp_lq035q7db03,
3366 .compatible = "sharp,lq070y3dg3b",
3367 .data = &sharp_lq070y3dg3b,
3369 .compatible = "sharp,lq101k1ly04",
3370 .data = &sharp_lq101k1ly04,
3372 .compatible = "sharp,lq123p1jx31",
3373 .data = &sharp_lq123p1jx31,
3375 .compatible = "sharp,lq150x1lg11",
3376 .data = &sharp_lq150x1lg11,
3378 .compatible = "sharp,ls020b1dd01d",
3379 .data = &sharp_ls020b1dd01d,
3381 .compatible = "shelly,sca07010-bfn-lnn",
3382 .data = &shelly_sca07010_bfn_lnn,
3384 .compatible = "starry,kr122ea0sra",
3385 .data = &starry_kr122ea0sra,
3387 .compatible = "tfc,s9700rtwv43tr-01b",
3388 .data = &tfc_s9700rtwv43tr_01b,
3390 .compatible = "tianma,tm070jdhg30",
3391 .data = &tianma_tm070jdhg30,
3393 .compatible = "tianma,tm070rvhg71",
3394 .data = &tianma_tm070rvhg71,
3396 .compatible = "ti,nspire-cx-lcd-panel",
3397 .data = &ti_nspire_cx_lcd_panel,
3399 .compatible = "ti,nspire-classic-lcd-panel",
3400 .data = &ti_nspire_classic_lcd_panel,
3402 .compatible = "toshiba,lt089ac29000",
3403 .data = &toshiba_lt089ac29000,
3405 .compatible = "tpk,f07a-0102",
3406 .data = &tpk_f07a_0102,
3408 .compatible = "tpk,f10a-0102",
3409 .data = &tpk_f10a_0102,
3411 .compatible = "urt,umsh-8596md-t",
3412 .data = &urt_umsh_8596md_parallel,
3414 .compatible = "urt,umsh-8596md-1t",
3415 .data = &urt_umsh_8596md_parallel,
3417 .compatible = "urt,umsh-8596md-7t",
3418 .data = &urt_umsh_8596md_parallel,
3420 .compatible = "urt,umsh-8596md-11t",
3421 .data = &urt_umsh_8596md_lvds,
3423 .compatible = "urt,umsh-8596md-19t",
3424 .data = &urt_umsh_8596md_lvds,
3426 .compatible = "urt,umsh-8596md-20t",
3427 .data = &urt_umsh_8596md_parallel,
3429 .compatible = "vxt,vl050-8048nt-c01",
3430 .data = &vl050_8048nt_c01,
3432 .compatible = "winstar,wf35ltiacd",
3433 .data = &winstar_wf35ltiacd,
3438 MODULE_DEVICE_TABLE(of, platform_of_match);
3440 static int panel_simple_platform_probe(struct platform_device *pdev)
3442 const struct of_device_id *id;
3444 id = of_match_node(platform_of_match, pdev->dev.of_node);
3448 return panel_simple_probe(&pdev->dev, id->data);
3451 static int panel_simple_platform_remove(struct platform_device *pdev)
3453 return panel_simple_remove(&pdev->dev);
3456 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3458 panel_simple_shutdown(&pdev->dev);
3461 static struct platform_driver panel_simple_platform_driver = {
3463 .name = "panel-simple",
3464 .of_match_table = platform_of_match,
3466 .probe = panel_simple_platform_probe,
3467 .remove = panel_simple_platform_remove,
3468 .shutdown = panel_simple_platform_shutdown,
3471 struct panel_desc_dsi {
3472 struct panel_desc desc;
3474 unsigned long flags;
3475 enum mipi_dsi_pixel_format format;
3479 static const struct drm_display_mode auo_b080uan01_mode = {
3482 .hsync_start = 1200 + 62,
3483 .hsync_end = 1200 + 62 + 4,
3484 .htotal = 1200 + 62 + 4 + 62,
3486 .vsync_start = 1920 + 9,
3487 .vsync_end = 1920 + 9 + 2,
3488 .vtotal = 1920 + 9 + 2 + 8,
3492 static const struct panel_desc_dsi auo_b080uan01 = {
3494 .modes = &auo_b080uan01_mode,
3502 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3503 .format = MIPI_DSI_FMT_RGB888,
3507 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3510 .hsync_start = 1200 + 120,
3511 .hsync_end = 1200 + 120 + 20,
3512 .htotal = 1200 + 120 + 20 + 21,
3514 .vsync_start = 1920 + 21,
3515 .vsync_end = 1920 + 21 + 3,
3516 .vtotal = 1920 + 21 + 3 + 18,
3518 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3521 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3523 .modes = &boe_tv080wum_nl0_mode,
3530 .flags = MIPI_DSI_MODE_VIDEO |
3531 MIPI_DSI_MODE_VIDEO_BURST |
3532 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3533 .format = MIPI_DSI_FMT_RGB888,
3537 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3540 .hsync_start = 800 + 32,
3541 .hsync_end = 800 + 32 + 1,
3542 .htotal = 800 + 32 + 1 + 57,
3544 .vsync_start = 1280 + 28,
3545 .vsync_end = 1280 + 28 + 1,
3546 .vtotal = 1280 + 28 + 1 + 14,
3550 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3552 .modes = &lg_ld070wx3_sl01_mode,
3560 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3561 .format = MIPI_DSI_FMT_RGB888,
3565 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3568 .hsync_start = 720 + 12,
3569 .hsync_end = 720 + 12 + 4,
3570 .htotal = 720 + 12 + 4 + 112,
3572 .vsync_start = 1280 + 8,
3573 .vsync_end = 1280 + 8 + 4,
3574 .vtotal = 1280 + 8 + 4 + 12,
3578 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3580 .modes = &lg_lh500wx1_sd03_mode,
3588 .flags = MIPI_DSI_MODE_VIDEO,
3589 .format = MIPI_DSI_FMT_RGB888,
3593 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3596 .hsync_start = 1920 + 154,
3597 .hsync_end = 1920 + 154 + 16,
3598 .htotal = 1920 + 154 + 16 + 32,
3600 .vsync_start = 1200 + 17,
3601 .vsync_end = 1200 + 17 + 2,
3602 .vtotal = 1200 + 17 + 2 + 16,
3606 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3608 .modes = &panasonic_vvx10f004b00_mode,
3616 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3617 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3618 .format = MIPI_DSI_FMT_RGB888,
3622 static const struct drm_display_mode lg_acx467akm_7_mode = {
3625 .hsync_start = 1080 + 2,
3626 .hsync_end = 1080 + 2 + 2,
3627 .htotal = 1080 + 2 + 2 + 2,
3629 .vsync_start = 1920 + 2,
3630 .vsync_end = 1920 + 2 + 2,
3631 .vtotal = 1920 + 2 + 2 + 2,
3635 static const struct panel_desc_dsi lg_acx467akm_7 = {
3637 .modes = &lg_acx467akm_7_mode,
3646 .format = MIPI_DSI_FMT_RGB888,
3650 static const struct drm_display_mode osd101t2045_53ts_mode = {
3653 .hsync_start = 1920 + 112,
3654 .hsync_end = 1920 + 112 + 16,
3655 .htotal = 1920 + 112 + 16 + 32,
3657 .vsync_start = 1200 + 16,
3658 .vsync_end = 1200 + 16 + 2,
3659 .vtotal = 1200 + 16 + 2 + 16,
3661 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3664 static const struct panel_desc_dsi osd101t2045_53ts = {
3666 .modes = &osd101t2045_53ts_mode,
3674 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3675 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3676 MIPI_DSI_MODE_EOT_PACKET,
3677 .format = MIPI_DSI_FMT_RGB888,
3681 static const struct of_device_id dsi_of_match[] = {
3683 .compatible = "auo,b080uan01",
3684 .data = &auo_b080uan01
3686 .compatible = "boe,tv080wum-nl0",
3687 .data = &boe_tv080wum_nl0
3689 .compatible = "lg,ld070wx3-sl01",
3690 .data = &lg_ld070wx3_sl01
3692 .compatible = "lg,lh500wx1-sd03",
3693 .data = &lg_lh500wx1_sd03
3695 .compatible = "panasonic,vvx10f004b00",
3696 .data = &panasonic_vvx10f004b00
3698 .compatible = "lg,acx467akm-7",
3699 .data = &lg_acx467akm_7
3701 .compatible = "osddisplays,osd101t2045-53ts",
3702 .data = &osd101t2045_53ts
3707 MODULE_DEVICE_TABLE(of, dsi_of_match);
3709 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3711 const struct panel_desc_dsi *desc;
3712 const struct of_device_id *id;
3715 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3721 err = panel_simple_probe(&dsi->dev, &desc->desc);
3725 dsi->mode_flags = desc->flags;
3726 dsi->format = desc->format;
3727 dsi->lanes = desc->lanes;
3729 err = mipi_dsi_attach(dsi);
3731 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3733 drm_panel_remove(&panel->base);
3739 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3743 err = mipi_dsi_detach(dsi);
3745 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3747 return panel_simple_remove(&dsi->dev);
3750 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3752 panel_simple_shutdown(&dsi->dev);
3755 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3757 .name = "panel-simple-dsi",
3758 .of_match_table = dsi_of_match,
3760 .probe = panel_simple_dsi_probe,
3761 .remove = panel_simple_dsi_remove,
3762 .shutdown = panel_simple_dsi_shutdown,
3765 static int __init panel_simple_init(void)
3769 err = platform_driver_register(&panel_simple_platform_driver);
3773 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3774 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3781 module_init(panel_simple_init);
3783 static void __exit panel_simple_exit(void)
3785 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3786 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3788 platform_driver_unregister(&panel_simple_platform_driver);
3790 module_exit(panel_simple_exit);
3792 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3793 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3794 MODULE_LICENSE("GPL and additional rights");