2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
31 #include <video/display_timing.h>
32 #include <video/of_display_timing.h>
33 #include <video/videomode.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_device.h>
37 #include <drm/drm_mipi_dsi.h>
38 #include <drm/drm_panel.h>
41 * @modes: Pointer to array of fixed modes appropriate for this panel. If
42 * only one mode then this can just be the address of this the mode.
43 * NOTE: cannot be used with "timings" and also if this is specified
44 * then you cannot override the mode in the device tree.
45 * @num_modes: Number of elements in modes array.
46 * @timings: Pointer to array of display timings. NOTE: cannot be used with
47 * "modes" and also these will be used to validate a device tree
48 * override if one is present.
49 * @num_timings: Number of elements in timings array.
50 * @bpc: Bits per color.
51 * @size: Structure containing the physical size of this panel.
52 * @delay: Structure containing various delay values for this panel.
53 * @bus_format: See MEDIA_BUS_FMT_... defines.
54 * @bus_flags: See DRM_BUS_FLAG_... defines.
57 const struct drm_display_mode *modes;
58 unsigned int num_modes;
59 const struct display_timing *timings;
60 unsigned int num_timings;
65 * @width: width (in millimeters) of the panel's active display area
66 * @height: height (in millimeters) of the panel's active display area
74 * @prepare: the time (in milliseconds) that it takes for the panel to
75 * become ready and start receiving video data
76 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
77 * Plug Detect isn't used.
78 * @enable: the time (in milliseconds) that it takes for the panel to
79 * display the first valid frame after starting to receive
81 * @disable: the time (in milliseconds) that it takes for the panel to
82 * turn the display off (no content is visible)
83 * @unprepare: the time (in milliseconds) that it takes for the panel
84 * to power itself down completely
88 unsigned int hpd_absent_delay;
91 unsigned int unprepare;
100 struct drm_panel base;
105 const struct panel_desc *desc;
107 struct regulator *supply;
108 struct i2c_adapter *ddc;
110 struct gpio_desc *enable_gpio;
112 struct drm_display_mode override_mode;
115 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
117 return container_of(panel, struct panel_simple, base);
120 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
121 struct drm_connector *connector)
123 struct drm_device *drm = panel->base.drm;
124 struct drm_display_mode *mode;
125 unsigned int i, num = 0;
127 for (i = 0; i < panel->desc->num_timings; i++) {
128 const struct display_timing *dt = &panel->desc->timings[i];
131 videomode_from_timing(dt, &vm);
132 mode = drm_mode_create(drm);
134 dev_err(drm->dev, "failed to add mode %ux%u\n",
135 dt->hactive.typ, dt->vactive.typ);
139 drm_display_mode_from_videomode(&vm, mode);
141 mode->type |= DRM_MODE_TYPE_DRIVER;
143 if (panel->desc->num_timings == 1)
144 mode->type |= DRM_MODE_TYPE_PREFERRED;
146 drm_mode_probed_add(connector, mode);
153 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
154 struct drm_connector *connector)
156 struct drm_device *drm = panel->base.drm;
157 struct drm_display_mode *mode;
158 unsigned int i, num = 0;
160 for (i = 0; i < panel->desc->num_modes; i++) {
161 const struct drm_display_mode *m = &panel->desc->modes[i];
163 mode = drm_mode_duplicate(drm, m);
165 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
166 m->hdisplay, m->vdisplay, m->vrefresh);
170 mode->type |= DRM_MODE_TYPE_DRIVER;
172 if (panel->desc->num_modes == 1)
173 mode->type |= DRM_MODE_TYPE_PREFERRED;
175 drm_mode_set_name(mode);
177 drm_mode_probed_add(connector, mode);
184 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
185 struct drm_connector *connector)
187 struct drm_device *drm = panel->base.drm;
188 struct drm_display_mode *mode;
189 bool has_override = panel->override_mode.type;
190 unsigned int num = 0;
196 mode = drm_mode_duplicate(drm, &panel->override_mode);
198 drm_mode_probed_add(connector, mode);
201 dev_err(drm->dev, "failed to add override mode\n");
205 /* Only add timings if override was not there or failed to validate */
206 if (num == 0 && panel->desc->num_timings)
207 num = panel_simple_get_timings_modes(panel, connector);
210 * Only add fixed modes if timings/override added no mode.
212 * We should only ever have either the display timings specified
213 * or a fixed mode. Anything else is rather bogus.
215 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
217 num = panel_simple_get_display_modes(panel, connector);
219 connector->display_info.bpc = panel->desc->bpc;
220 connector->display_info.width_mm = panel->desc->size.width;
221 connector->display_info.height_mm = panel->desc->size.height;
222 if (panel->desc->bus_format)
223 drm_display_info_set_bus_formats(&connector->display_info,
224 &panel->desc->bus_format, 1);
225 connector->display_info.bus_flags = panel->desc->bus_flags;
230 static int panel_simple_disable(struct drm_panel *panel)
232 struct panel_simple *p = to_panel_simple(panel);
237 if (p->desc->delay.disable)
238 msleep(p->desc->delay.disable);
245 static int panel_simple_unprepare(struct drm_panel *panel)
247 struct panel_simple *p = to_panel_simple(panel);
252 gpiod_set_value_cansleep(p->enable_gpio, 0);
254 regulator_disable(p->supply);
256 if (p->desc->delay.unprepare)
257 msleep(p->desc->delay.unprepare);
264 static int panel_simple_prepare(struct drm_panel *panel)
266 struct panel_simple *p = to_panel_simple(panel);
273 err = regulator_enable(p->supply);
275 dev_err(panel->dev, "failed to enable supply: %d\n", err);
279 gpiod_set_value_cansleep(p->enable_gpio, 1);
281 delay = p->desc->delay.prepare;
283 delay += p->desc->delay.hpd_absent_delay;
292 static int panel_simple_enable(struct drm_panel *panel)
294 struct panel_simple *p = to_panel_simple(panel);
299 if (p->desc->delay.enable)
300 msleep(p->desc->delay.enable);
307 static int panel_simple_get_modes(struct drm_panel *panel,
308 struct drm_connector *connector)
310 struct panel_simple *p = to_panel_simple(panel);
313 /* probe EDID if a DDC bus is available */
315 struct edid *edid = drm_get_edid(connector, p->ddc);
317 drm_connector_update_edid_property(connector, edid);
319 num += drm_add_edid_modes(connector, edid);
324 /* add hard-coded panel modes */
325 num += panel_simple_get_non_edid_modes(p, connector);
330 static int panel_simple_get_timings(struct drm_panel *panel,
331 unsigned int num_timings,
332 struct display_timing *timings)
334 struct panel_simple *p = to_panel_simple(panel);
337 if (p->desc->num_timings < num_timings)
338 num_timings = p->desc->num_timings;
341 for (i = 0; i < num_timings; i++)
342 timings[i] = p->desc->timings[i];
344 return p->desc->num_timings;
347 static const struct drm_panel_funcs panel_simple_funcs = {
348 .disable = panel_simple_disable,
349 .unprepare = panel_simple_unprepare,
350 .prepare = panel_simple_prepare,
351 .enable = panel_simple_enable,
352 .get_modes = panel_simple_get_modes,
353 .get_timings = panel_simple_get_timings,
356 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
357 (to_check->field.typ >= bounds->field.min && \
358 to_check->field.typ <= bounds->field.max)
359 static void panel_simple_parse_panel_timing_node(struct device *dev,
360 struct panel_simple *panel,
361 const struct display_timing *ot)
363 const struct panel_desc *desc = panel->desc;
367 if (WARN_ON(desc->num_modes)) {
368 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
371 if (WARN_ON(!desc->num_timings)) {
372 dev_err(dev, "Reject override mode: no timings specified\n");
376 for (i = 0; i < panel->desc->num_timings; i++) {
377 const struct display_timing *dt = &panel->desc->timings[i];
379 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
380 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
381 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
382 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
383 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
384 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
385 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
386 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
389 if (ot->flags != dt->flags)
392 videomode_from_timing(ot, &vm);
393 drm_display_mode_from_videomode(&vm, &panel->override_mode);
394 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
395 DRM_MODE_TYPE_PREFERRED;
399 if (WARN_ON(!panel->override_mode.type))
400 dev_err(dev, "Reject override mode: No display_timing found\n");
403 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
405 struct panel_simple *panel;
406 struct display_timing dt;
407 struct device_node *ddc;
410 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
414 panel->enabled = false;
415 panel->prepared = false;
418 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
420 panel->supply = devm_regulator_get(dev, "power");
421 if (IS_ERR(panel->supply))
422 return PTR_ERR(panel->supply);
424 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
426 if (IS_ERR(panel->enable_gpio)) {
427 err = PTR_ERR(panel->enable_gpio);
428 if (err != -EPROBE_DEFER)
429 dev_err(dev, "failed to request GPIO: %d\n", err);
433 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
435 panel->ddc = of_find_i2c_adapter_by_node(ddc);
439 return -EPROBE_DEFER;
442 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
443 panel_simple_parse_panel_timing_node(dev, panel, &dt);
445 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
446 desc->connector_type);
448 err = drm_panel_of_backlight(&panel->base);
452 err = drm_panel_add(&panel->base);
456 dev_set_drvdata(dev, panel);
462 put_device(&panel->ddc->dev);
467 static int panel_simple_remove(struct device *dev)
469 struct panel_simple *panel = dev_get_drvdata(dev);
471 drm_panel_remove(&panel->base);
472 drm_panel_disable(&panel->base);
473 drm_panel_unprepare(&panel->base);
476 put_device(&panel->ddc->dev);
481 static void panel_simple_shutdown(struct device *dev)
483 struct panel_simple *panel = dev_get_drvdata(dev);
485 drm_panel_disable(&panel->base);
486 drm_panel_unprepare(&panel->base);
489 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
492 .hsync_start = 480 + 2,
493 .hsync_end = 480 + 2 + 41,
494 .htotal = 480 + 2 + 41 + 2,
496 .vsync_start = 272 + 2,
497 .vsync_end = 272 + 2 + 10,
498 .vtotal = 272 + 2 + 10 + 2,
500 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
503 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
504 .modes = &ire_am_480272h3tmqw_t01h_mode,
511 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
514 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
517 .hsync_start = 800 + 0,
518 .hsync_end = 800 + 0 + 255,
519 .htotal = 800 + 0 + 255 + 0,
521 .vsync_start = 480 + 2,
522 .vsync_end = 480 + 2 + 45,
523 .vtotal = 480 + 2 + 45 + 0,
525 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
528 static const struct panel_desc ampire_am800480r3tmqwa1h = {
529 .modes = &ire_am800480r3tmqwa1h_mode,
536 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
539 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
540 .pixelclock = { 26400000, 33300000, 46800000 },
541 .hactive = { 800, 800, 800 },
542 .hfront_porch = { 16, 210, 354 },
543 .hback_porch = { 45, 36, 6 },
544 .hsync_len = { 1, 10, 40 },
545 .vactive = { 480, 480, 480 },
546 .vfront_porch = { 7, 22, 147 },
547 .vback_porch = { 22, 13, 3 },
548 .vsync_len = { 1, 10, 20 },
549 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
550 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
553 static const struct panel_desc armadeus_st0700_adapt = {
554 .timings = &santek_st0700i5y_rbslw_f_timing,
561 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
562 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
565 static const struct drm_display_mode auo_b101aw03_mode = {
568 .hsync_start = 1024 + 156,
569 .hsync_end = 1024 + 156 + 8,
570 .htotal = 1024 + 156 + 8 + 156,
572 .vsync_start = 600 + 16,
573 .vsync_end = 600 + 16 + 6,
574 .vtotal = 600 + 16 + 6 + 16,
578 static const struct panel_desc auo_b101aw03 = {
579 .modes = &auo_b101aw03_mode,
588 static const struct display_timing auo_b101ean01_timing = {
589 .pixelclock = { 65300000, 72500000, 75000000 },
590 .hactive = { 1280, 1280, 1280 },
591 .hfront_porch = { 18, 119, 119 },
592 .hback_porch = { 21, 21, 21 },
593 .hsync_len = { 32, 32, 32 },
594 .vactive = { 800, 800, 800 },
595 .vfront_porch = { 4, 4, 4 },
596 .vback_porch = { 8, 8, 8 },
597 .vsync_len = { 18, 20, 20 },
600 static const struct panel_desc auo_b101ean01 = {
601 .timings = &auo_b101ean01_timing,
610 static const struct drm_display_mode auo_b101xtn01_mode = {
613 .hsync_start = 1366 + 20,
614 .hsync_end = 1366 + 20 + 70,
615 .htotal = 1366 + 20 + 70,
617 .vsync_start = 768 + 14,
618 .vsync_end = 768 + 14 + 42,
619 .vtotal = 768 + 14 + 42,
621 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
624 static const struct panel_desc auo_b101xtn01 = {
625 .modes = &auo_b101xtn01_mode,
634 static const struct drm_display_mode auo_b116xw03_mode = {
637 .hsync_start = 1366 + 40,
638 .hsync_end = 1366 + 40 + 40,
639 .htotal = 1366 + 40 + 40 + 32,
641 .vsync_start = 768 + 10,
642 .vsync_end = 768 + 10 + 12,
643 .vtotal = 768 + 10 + 12 + 6,
647 static const struct panel_desc auo_b116xw03 = {
648 .modes = &auo_b116xw03_mode,
657 static const struct drm_display_mode auo_b133xtn01_mode = {
660 .hsync_start = 1366 + 48,
661 .hsync_end = 1366 + 48 + 32,
662 .htotal = 1366 + 48 + 32 + 20,
664 .vsync_start = 768 + 3,
665 .vsync_end = 768 + 3 + 6,
666 .vtotal = 768 + 3 + 6 + 13,
670 static const struct panel_desc auo_b133xtn01 = {
671 .modes = &auo_b133xtn01_mode,
680 static const struct drm_display_mode auo_b133htn01_mode = {
683 .hsync_start = 1920 + 172,
684 .hsync_end = 1920 + 172 + 80,
685 .htotal = 1920 + 172 + 80 + 60,
687 .vsync_start = 1080 + 25,
688 .vsync_end = 1080 + 25 + 10,
689 .vtotal = 1080 + 25 + 10 + 10,
693 static const struct panel_desc auo_b133htn01 = {
694 .modes = &auo_b133htn01_mode,
708 static const struct display_timing auo_g070vvn01_timings = {
709 .pixelclock = { 33300000, 34209000, 45000000 },
710 .hactive = { 800, 800, 800 },
711 .hfront_porch = { 20, 40, 200 },
712 .hback_porch = { 87, 40, 1 },
713 .hsync_len = { 1, 48, 87 },
714 .vactive = { 480, 480, 480 },
715 .vfront_porch = { 5, 13, 200 },
716 .vback_porch = { 31, 31, 29 },
717 .vsync_len = { 1, 1, 3 },
720 static const struct panel_desc auo_g070vvn01 = {
721 .timings = &auo_g070vvn01_timings,
736 static const struct drm_display_mode auo_g101evn010_mode = {
739 .hsync_start = 1280 + 82,
740 .hsync_end = 1280 + 82 + 2,
741 .htotal = 1280 + 82 + 2 + 84,
743 .vsync_start = 800 + 8,
744 .vsync_end = 800 + 8 + 2,
745 .vtotal = 800 + 8 + 2 + 6,
749 static const struct panel_desc auo_g101evn010 = {
750 .modes = &auo_g101evn010_mode,
757 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
760 static const struct drm_display_mode auo_g104sn02_mode = {
763 .hsync_start = 800 + 40,
764 .hsync_end = 800 + 40 + 216,
765 .htotal = 800 + 40 + 216 + 128,
767 .vsync_start = 600 + 10,
768 .vsync_end = 600 + 10 + 35,
769 .vtotal = 600 + 10 + 35 + 2,
773 static const struct panel_desc auo_g104sn02 = {
774 .modes = &auo_g104sn02_mode,
783 static const struct display_timing auo_g133han01_timings = {
784 .pixelclock = { 134000000, 141200000, 149000000 },
785 .hactive = { 1920, 1920, 1920 },
786 .hfront_porch = { 39, 58, 77 },
787 .hback_porch = { 59, 88, 117 },
788 .hsync_len = { 28, 42, 56 },
789 .vactive = { 1080, 1080, 1080 },
790 .vfront_porch = { 3, 8, 11 },
791 .vback_porch = { 5, 14, 19 },
792 .vsync_len = { 4, 14, 19 },
795 static const struct panel_desc auo_g133han01 = {
796 .timings = &auo_g133han01_timings,
809 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
810 .connector_type = DRM_MODE_CONNECTOR_LVDS,
813 static const struct display_timing auo_g185han01_timings = {
814 .pixelclock = { 120000000, 144000000, 175000000 },
815 .hactive = { 1920, 1920, 1920 },
816 .hfront_porch = { 36, 120, 148 },
817 .hback_porch = { 24, 88, 108 },
818 .hsync_len = { 20, 48, 64 },
819 .vactive = { 1080, 1080, 1080 },
820 .vfront_porch = { 6, 10, 40 },
821 .vback_porch = { 2, 5, 20 },
822 .vsync_len = { 2, 5, 20 },
825 static const struct panel_desc auo_g185han01 = {
826 .timings = &auo_g185han01_timings,
839 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
840 .connector_type = DRM_MODE_CONNECTOR_LVDS,
843 static const struct display_timing auo_p320hvn03_timings = {
844 .pixelclock = { 106000000, 148500000, 164000000 },
845 .hactive = { 1920, 1920, 1920 },
846 .hfront_porch = { 25, 50, 130 },
847 .hback_porch = { 25, 50, 130 },
848 .hsync_len = { 20, 40, 105 },
849 .vactive = { 1080, 1080, 1080 },
850 .vfront_porch = { 8, 17, 150 },
851 .vback_porch = { 8, 17, 150 },
852 .vsync_len = { 4, 11, 100 },
855 static const struct panel_desc auo_p320hvn03 = {
856 .timings = &auo_p320hvn03_timings,
868 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
869 .connector_type = DRM_MODE_CONNECTOR_LVDS,
872 static const struct drm_display_mode auo_t215hvn01_mode = {
875 .hsync_start = 1920 + 88,
876 .hsync_end = 1920 + 88 + 44,
877 .htotal = 1920 + 88 + 44 + 148,
879 .vsync_start = 1080 + 4,
880 .vsync_end = 1080 + 4 + 5,
881 .vtotal = 1080 + 4 + 5 + 36,
885 static const struct panel_desc auo_t215hvn01 = {
886 .modes = &auo_t215hvn01_mode,
899 static const struct drm_display_mode avic_tm070ddh03_mode = {
902 .hsync_start = 1024 + 160,
903 .hsync_end = 1024 + 160 + 4,
904 .htotal = 1024 + 160 + 4 + 156,
906 .vsync_start = 600 + 17,
907 .vsync_end = 600 + 17 + 1,
908 .vtotal = 600 + 17 + 1 + 17,
912 static const struct panel_desc avic_tm070ddh03 = {
913 .modes = &avic_tm070ddh03_mode,
927 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
930 .hsync_start = 800 + 40,
931 .hsync_end = 800 + 40 + 48,
932 .htotal = 800 + 40 + 48 + 40,
934 .vsync_start = 480 + 13,
935 .vsync_end = 480 + 13 + 3,
936 .vtotal = 480 + 13 + 3 + 29,
939 static const struct panel_desc bananapi_s070wv20_ct16 = {
940 .modes = &bananapi_s070wv20_ct16_mode,
949 static const struct drm_display_mode boe_hv070wsa_mode = {
952 .hsync_start = 1024 + 30,
953 .hsync_end = 1024 + 30 + 30,
954 .htotal = 1024 + 30 + 30 + 30,
956 .vsync_start = 600 + 10,
957 .vsync_end = 600 + 10 + 10,
958 .vtotal = 600 + 10 + 10 + 10,
962 static const struct panel_desc boe_hv070wsa = {
963 .modes = &boe_hv070wsa_mode,
971 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
975 .hsync_start = 1280 + 48,
976 .hsync_end = 1280 + 48 + 32,
977 .htotal = 1280 + 48 + 32 + 80,
979 .vsync_start = 800 + 3,
980 .vsync_end = 800 + 3 + 5,
981 .vtotal = 800 + 3 + 5 + 24,
987 .hsync_start = 1280 + 48,
988 .hsync_end = 1280 + 48 + 32,
989 .htotal = 1280 + 48 + 32 + 80,
991 .vsync_start = 800 + 3,
992 .vsync_end = 800 + 3 + 5,
993 .vtotal = 800 + 3 + 5 + 24,
998 static const struct panel_desc boe_nv101wxmn51 = {
999 .modes = boe_nv101wxmn51_modes,
1000 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1013 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1016 .hsync_start = 480 + 5,
1017 .hsync_end = 480 + 5 + 5,
1018 .htotal = 480 + 5 + 5 + 40,
1020 .vsync_start = 272 + 8,
1021 .vsync_end = 272 + 8 + 8,
1022 .vtotal = 272 + 8 + 8 + 8,
1024 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1027 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1028 .modes = &cdtech_s043wq26h_ct7_mode,
1035 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1038 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1041 .hsync_start = 800 + 40,
1042 .hsync_end = 800 + 40 + 40,
1043 .htotal = 800 + 40 + 40 + 48,
1045 .vsync_start = 480 + 29,
1046 .vsync_end = 480 + 29 + 13,
1047 .vtotal = 480 + 29 + 13 + 3,
1049 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1052 static const struct panel_desc cdtech_s070wv95_ct16 = {
1053 .modes = &cdtech_s070wv95_ct16_mode,
1062 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1065 .hsync_start = 800 + 49,
1066 .hsync_end = 800 + 49 + 33,
1067 .htotal = 800 + 49 + 33 + 17,
1069 .vsync_start = 1280 + 1,
1070 .vsync_end = 1280 + 1 + 7,
1071 .vtotal = 1280 + 1 + 7 + 15,
1073 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1076 static const struct panel_desc chunghwa_claa070wp03xg = {
1077 .modes = &chunghwa_claa070wp03xg_mode,
1086 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1089 .hsync_start = 1366 + 58,
1090 .hsync_end = 1366 + 58 + 58,
1091 .htotal = 1366 + 58 + 58 + 58,
1093 .vsync_start = 768 + 4,
1094 .vsync_end = 768 + 4 + 4,
1095 .vtotal = 768 + 4 + 4 + 4,
1099 static const struct panel_desc chunghwa_claa101wa01a = {
1100 .modes = &chunghwa_claa101wa01a_mode,
1109 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1112 .hsync_start = 1366 + 48,
1113 .hsync_end = 1366 + 48 + 32,
1114 .htotal = 1366 + 48 + 32 + 20,
1116 .vsync_start = 768 + 16,
1117 .vsync_end = 768 + 16 + 8,
1118 .vtotal = 768 + 16 + 8 + 16,
1122 static const struct panel_desc chunghwa_claa101wb01 = {
1123 .modes = &chunghwa_claa101wb01_mode,
1132 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1135 .hsync_start = 800 + 40,
1136 .hsync_end = 800 + 40 + 128,
1137 .htotal = 800 + 40 + 128 + 88,
1139 .vsync_start = 480 + 10,
1140 .vsync_end = 480 + 10 + 2,
1141 .vtotal = 480 + 10 + 2 + 33,
1143 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1146 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1147 .modes = &dataimage_scf0700c48ggu18_mode,
1154 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1155 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1158 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1159 .pixelclock = { 45000000, 51200000, 57000000 },
1160 .hactive = { 1024, 1024, 1024 },
1161 .hfront_porch = { 100, 106, 113 },
1162 .hback_porch = { 100, 106, 113 },
1163 .hsync_len = { 100, 108, 114 },
1164 .vactive = { 600, 600, 600 },
1165 .vfront_porch = { 8, 11, 15 },
1166 .vback_porch = { 8, 11, 15 },
1167 .vsync_len = { 9, 13, 15 },
1168 .flags = DISPLAY_FLAGS_DE_HIGH,
1171 static const struct panel_desc dlc_dlc0700yzg_1 = {
1172 .timings = &dlc_dlc0700yzg_1_timing,
1184 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1185 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1188 static const struct display_timing dlc_dlc1010gig_timing = {
1189 .pixelclock = { 68900000, 71100000, 73400000 },
1190 .hactive = { 1280, 1280, 1280 },
1191 .hfront_porch = { 43, 53, 63 },
1192 .hback_porch = { 43, 53, 63 },
1193 .hsync_len = { 44, 54, 64 },
1194 .vactive = { 800, 800, 800 },
1195 .vfront_porch = { 5, 8, 11 },
1196 .vback_porch = { 5, 8, 11 },
1197 .vsync_len = { 5, 7, 11 },
1198 .flags = DISPLAY_FLAGS_DE_HIGH,
1201 static const struct panel_desc dlc_dlc1010gig = {
1202 .timings = &dlc_dlc1010gig_timing,
1215 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1216 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1219 static const struct drm_display_mode edt_et035012dm6_mode = {
1222 .hsync_start = 320 + 20,
1223 .hsync_end = 320 + 20 + 30,
1224 .htotal = 320 + 20 + 68,
1226 .vsync_start = 240 + 4,
1227 .vsync_end = 240 + 4 + 4,
1228 .vtotal = 240 + 4 + 4 + 14,
1230 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1233 static const struct panel_desc edt_et035012dm6 = {
1234 .modes = &edt_et035012dm6_mode,
1241 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1242 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1245 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1248 .hsync_start = 480 + 2,
1249 .hsync_end = 480 + 2 + 41,
1250 .htotal = 480 + 2 + 41 + 2,
1252 .vsync_start = 272 + 2,
1253 .vsync_end = 272 + 2 + 10,
1254 .vtotal = 272 + 2 + 10 + 2,
1256 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1259 static const struct panel_desc edt_etm0430g0dh6 = {
1260 .modes = &edt_etm0430g0dh6_mode,
1269 static const struct drm_display_mode edt_et057090dhu_mode = {
1272 .hsync_start = 640 + 16,
1273 .hsync_end = 640 + 16 + 30,
1274 .htotal = 640 + 16 + 30 + 114,
1276 .vsync_start = 480 + 10,
1277 .vsync_end = 480 + 10 + 3,
1278 .vtotal = 480 + 10 + 3 + 32,
1280 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1283 static const struct panel_desc edt_et057090dhu = {
1284 .modes = &edt_et057090dhu_mode,
1291 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1292 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1295 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1298 .hsync_start = 800 + 40,
1299 .hsync_end = 800 + 40 + 128,
1300 .htotal = 800 + 40 + 128 + 88,
1302 .vsync_start = 480 + 10,
1303 .vsync_end = 480 + 10 + 2,
1304 .vtotal = 480 + 10 + 2 + 33,
1306 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1309 static const struct panel_desc edt_etm0700g0dh6 = {
1310 .modes = &edt_etm0700g0dh6_mode,
1317 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1321 static const struct panel_desc edt_etm0700g0bdh6 = {
1322 .modes = &edt_etm0700g0dh6_mode,
1329 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1330 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1333 static const struct display_timing evervision_vgg804821_timing = {
1334 .pixelclock = { 27600000, 33300000, 50000000 },
1335 .hactive = { 800, 800, 800 },
1336 .hfront_porch = { 40, 66, 70 },
1337 .hback_porch = { 40, 67, 70 },
1338 .hsync_len = { 40, 67, 70 },
1339 .vactive = { 480, 480, 480 },
1340 .vfront_porch = { 6, 10, 10 },
1341 .vback_porch = { 7, 11, 11 },
1342 .vsync_len = { 7, 11, 11 },
1343 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1344 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1345 DISPLAY_FLAGS_SYNC_NEGEDGE,
1348 static const struct panel_desc evervision_vgg804821 = {
1349 .timings = &evervision_vgg804821_timing,
1356 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1357 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1360 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1363 .hsync_start = 800 + 168,
1364 .hsync_end = 800 + 168 + 64,
1365 .htotal = 800 + 168 + 64 + 88,
1367 .vsync_start = 480 + 37,
1368 .vsync_end = 480 + 37 + 2,
1369 .vtotal = 480 + 37 + 2 + 8,
1373 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1374 .modes = &foxlink_fl500wvr00_a0t_mode,
1381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1384 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1387 .hsync_start = 800 + 20,
1388 .hsync_end = 800 + 20 + 24,
1389 .htotal = 800 + 20 + 24 + 20,
1391 .vsync_start = 1280 + 4,
1392 .vsync_end = 1280 + 4 + 8,
1393 .vtotal = 1280 + 4 + 8 + 4,
1395 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1398 static const struct panel_desc friendlyarm_hd702e = {
1399 .modes = &friendlyarm_hd702e_mode,
1407 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1410 .hsync_start = 480 + 5,
1411 .hsync_end = 480 + 5 + 1,
1412 .htotal = 480 + 5 + 1 + 40,
1414 .vsync_start = 272 + 8,
1415 .vsync_end = 272 + 8 + 1,
1416 .vtotal = 272 + 8 + 1 + 8,
1420 static const struct panel_desc giantplus_gpg482739qs5 = {
1421 .modes = &giantplus_gpg482739qs5_mode,
1428 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1431 static const struct display_timing giantplus_gpm940b0_timing = {
1432 .pixelclock = { 13500000, 27000000, 27500000 },
1433 .hactive = { 320, 320, 320 },
1434 .hfront_porch = { 14, 686, 718 },
1435 .hback_porch = { 50, 70, 255 },
1436 .hsync_len = { 1, 1, 1 },
1437 .vactive = { 240, 240, 240 },
1438 .vfront_porch = { 1, 1, 179 },
1439 .vback_porch = { 1, 21, 31 },
1440 .vsync_len = { 1, 1, 6 },
1441 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1444 static const struct panel_desc giantplus_gpm940b0 = {
1445 .timings = &giantplus_gpm940b0_timing,
1452 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1453 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1456 static const struct display_timing hannstar_hsd070pww1_timing = {
1457 .pixelclock = { 64300000, 71100000, 82000000 },
1458 .hactive = { 1280, 1280, 1280 },
1459 .hfront_porch = { 1, 1, 10 },
1460 .hback_porch = { 1, 1, 10 },
1462 * According to the data sheet, the minimum horizontal blanking interval
1463 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1464 * minimum working horizontal blanking interval to be 60 clocks.
1466 .hsync_len = { 58, 158, 661 },
1467 .vactive = { 800, 800, 800 },
1468 .vfront_porch = { 1, 1, 10 },
1469 .vback_porch = { 1, 1, 10 },
1470 .vsync_len = { 1, 21, 203 },
1471 .flags = DISPLAY_FLAGS_DE_HIGH,
1474 static const struct panel_desc hannstar_hsd070pww1 = {
1475 .timings = &hannstar_hsd070pww1_timing,
1482 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1483 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1486 static const struct display_timing hannstar_hsd100pxn1_timing = {
1487 .pixelclock = { 55000000, 65000000, 75000000 },
1488 .hactive = { 1024, 1024, 1024 },
1489 .hfront_porch = { 40, 40, 40 },
1490 .hback_porch = { 220, 220, 220 },
1491 .hsync_len = { 20, 60, 100 },
1492 .vactive = { 768, 768, 768 },
1493 .vfront_porch = { 7, 7, 7 },
1494 .vback_porch = { 21, 21, 21 },
1495 .vsync_len = { 10, 10, 10 },
1496 .flags = DISPLAY_FLAGS_DE_HIGH,
1499 static const struct panel_desc hannstar_hsd100pxn1 = {
1500 .timings = &hannstar_hsd100pxn1_timing,
1507 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1508 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1511 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1514 .hsync_start = 800 + 85,
1515 .hsync_end = 800 + 85 + 86,
1516 .htotal = 800 + 85 + 86 + 85,
1518 .vsync_start = 480 + 16,
1519 .vsync_end = 480 + 16 + 13,
1520 .vtotal = 480 + 16 + 13 + 16,
1524 static const struct panel_desc hitachi_tx23d38vm0caa = {
1525 .modes = &hitachi_tx23d38vm0caa_mode,
1538 static const struct drm_display_mode innolux_at043tn24_mode = {
1541 .hsync_start = 480 + 2,
1542 .hsync_end = 480 + 2 + 41,
1543 .htotal = 480 + 2 + 41 + 2,
1545 .vsync_start = 272 + 2,
1546 .vsync_end = 272 + 2 + 10,
1547 .vtotal = 272 + 2 + 10 + 2,
1549 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1552 static const struct panel_desc innolux_at043tn24 = {
1553 .modes = &innolux_at043tn24_mode,
1560 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1561 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1564 static const struct drm_display_mode innolux_at070tn92_mode = {
1567 .hsync_start = 800 + 210,
1568 .hsync_end = 800 + 210 + 20,
1569 .htotal = 800 + 210 + 20 + 46,
1571 .vsync_start = 480 + 22,
1572 .vsync_end = 480 + 22 + 10,
1573 .vtotal = 480 + 22 + 23 + 10,
1577 static const struct panel_desc innolux_at070tn92 = {
1578 .modes = &innolux_at070tn92_mode,
1584 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1587 static const struct display_timing innolux_g070y2_l01_timing = {
1588 .pixelclock = { 28000000, 29500000, 32000000 },
1589 .hactive = { 800, 800, 800 },
1590 .hfront_porch = { 61, 91, 141 },
1591 .hback_porch = { 60, 90, 140 },
1592 .hsync_len = { 12, 12, 12 },
1593 .vactive = { 480, 480, 480 },
1594 .vfront_porch = { 4, 9, 30 },
1595 .vback_porch = { 4, 8, 28 },
1596 .vsync_len = { 2, 2, 2 },
1597 .flags = DISPLAY_FLAGS_DE_HIGH,
1600 static const struct panel_desc innolux_g070y2_l01 = {
1601 .timings = &innolux_g070y2_l01_timing,
1614 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1615 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1618 static const struct display_timing innolux_g101ice_l01_timing = {
1619 .pixelclock = { 60400000, 71100000, 74700000 },
1620 .hactive = { 1280, 1280, 1280 },
1621 .hfront_porch = { 41, 80, 100 },
1622 .hback_porch = { 40, 79, 99 },
1623 .hsync_len = { 1, 1, 1 },
1624 .vactive = { 800, 800, 800 },
1625 .vfront_porch = { 5, 11, 14 },
1626 .vback_porch = { 4, 11, 14 },
1627 .vsync_len = { 1, 1, 1 },
1628 .flags = DISPLAY_FLAGS_DE_HIGH,
1631 static const struct panel_desc innolux_g101ice_l01 = {
1632 .timings = &innolux_g101ice_l01_timing,
1643 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1644 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1647 static const struct display_timing innolux_g121i1_l01_timing = {
1648 .pixelclock = { 67450000, 71000000, 74550000 },
1649 .hactive = { 1280, 1280, 1280 },
1650 .hfront_porch = { 40, 80, 160 },
1651 .hback_porch = { 39, 79, 159 },
1652 .hsync_len = { 1, 1, 1 },
1653 .vactive = { 800, 800, 800 },
1654 .vfront_porch = { 5, 11, 100 },
1655 .vback_porch = { 4, 11, 99 },
1656 .vsync_len = { 1, 1, 1 },
1659 static const struct panel_desc innolux_g121i1_l01 = {
1660 .timings = &innolux_g121i1_l01_timing,
1671 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1672 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1675 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1678 .hsync_start = 1024 + 0,
1679 .hsync_end = 1024 + 1,
1680 .htotal = 1024 + 0 + 1 + 320,
1682 .vsync_start = 768 + 38,
1683 .vsync_end = 768 + 38 + 1,
1684 .vtotal = 768 + 38 + 1 + 0,
1686 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1689 static const struct panel_desc innolux_g121x1_l03 = {
1690 .modes = &innolux_g121x1_l03_mode,
1705 * Datasheet specifies that at 60 Hz refresh rate:
1706 * - total horizontal time: { 1506, 1592, 1716 }
1707 * - total vertical time: { 788, 800, 868 }
1709 * ...but doesn't go into exactly how that should be split into a front
1710 * porch, back porch, or sync length. For now we'll leave a single setting
1711 * here which allows a bit of tweaking of the pixel clock at the expense of
1714 static const struct display_timing innolux_n116bge_timing = {
1715 .pixelclock = { 72600000, 76420000, 80240000 },
1716 .hactive = { 1366, 1366, 1366 },
1717 .hfront_porch = { 136, 136, 136 },
1718 .hback_porch = { 60, 60, 60 },
1719 .hsync_len = { 30, 30, 30 },
1720 .vactive = { 768, 768, 768 },
1721 .vfront_porch = { 8, 8, 8 },
1722 .vback_porch = { 12, 12, 12 },
1723 .vsync_len = { 12, 12, 12 },
1724 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1727 static const struct panel_desc innolux_n116bge = {
1728 .timings = &innolux_n116bge_timing,
1737 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1740 .hsync_start = 1366 + 16,
1741 .hsync_end = 1366 + 16 + 34,
1742 .htotal = 1366 + 16 + 34 + 50,
1744 .vsync_start = 768 + 2,
1745 .vsync_end = 768 + 2 + 6,
1746 .vtotal = 768 + 2 + 6 + 12,
1750 static const struct panel_desc innolux_n156bge_l21 = {
1751 .modes = &innolux_n156bge_l21_mode,
1760 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1763 .hsync_start = 2160 + 48,
1764 .hsync_end = 2160 + 48 + 32,
1765 .htotal = 2160 + 48 + 32 + 80,
1767 .vsync_start = 1440 + 3,
1768 .vsync_end = 1440 + 3 + 10,
1769 .vtotal = 1440 + 3 + 10 + 27,
1771 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1774 static const struct panel_desc innolux_p120zdg_bf1 = {
1775 .modes = &innolux_p120zdg_bf1_mode,
1783 .hpd_absent_delay = 200,
1788 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1791 .hsync_start = 1024 + 128,
1792 .hsync_end = 1024 + 128 + 64,
1793 .htotal = 1024 + 128 + 64 + 128,
1795 .vsync_start = 600 + 16,
1796 .vsync_end = 600 + 16 + 4,
1797 .vtotal = 600 + 16 + 4 + 16,
1801 static const struct panel_desc innolux_zj070na_01p = {
1802 .modes = &innolux_zj070na_01p_mode,
1811 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1812 .pixelclock = { 5580000, 5850000, 6200000 },
1813 .hactive = { 320, 320, 320 },
1814 .hfront_porch = { 30, 30, 30 },
1815 .hback_porch = { 30, 30, 30 },
1816 .hsync_len = { 1, 5, 17 },
1817 .vactive = { 240, 240, 240 },
1818 .vfront_porch = { 6, 6, 6 },
1819 .vback_porch = { 5, 5, 5 },
1820 .vsync_len = { 1, 2, 11 },
1821 .flags = DISPLAY_FLAGS_DE_HIGH,
1824 static const struct panel_desc koe_tx14d24vm1bpa = {
1825 .timings = &koe_tx14d24vm1bpa_timing,
1834 static const struct display_timing koe_tx31d200vm0baa_timing = {
1835 .pixelclock = { 39600000, 43200000, 48000000 },
1836 .hactive = { 1280, 1280, 1280 },
1837 .hfront_porch = { 16, 36, 56 },
1838 .hback_porch = { 16, 36, 56 },
1839 .hsync_len = { 8, 8, 8 },
1840 .vactive = { 480, 480, 480 },
1841 .vfront_porch = { 6, 21, 33 },
1842 .vback_porch = { 6, 21, 33 },
1843 .vsync_len = { 8, 8, 8 },
1844 .flags = DISPLAY_FLAGS_DE_HIGH,
1847 static const struct panel_desc koe_tx31d200vm0baa = {
1848 .timings = &koe_tx31d200vm0baa_timing,
1855 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1856 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1859 static const struct display_timing kyo_tcg121xglp_timing = {
1860 .pixelclock = { 52000000, 65000000, 71000000 },
1861 .hactive = { 1024, 1024, 1024 },
1862 .hfront_porch = { 2, 2, 2 },
1863 .hback_porch = { 2, 2, 2 },
1864 .hsync_len = { 86, 124, 244 },
1865 .vactive = { 768, 768, 768 },
1866 .vfront_porch = { 2, 2, 2 },
1867 .vback_porch = { 2, 2, 2 },
1868 .vsync_len = { 6, 34, 73 },
1869 .flags = DISPLAY_FLAGS_DE_HIGH,
1872 static const struct panel_desc kyo_tcg121xglp = {
1873 .timings = &kyo_tcg121xglp_timing,
1880 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1881 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1884 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1887 .hsync_start = 320 + 20,
1888 .hsync_end = 320 + 20 + 30,
1889 .htotal = 320 + 20 + 30 + 38,
1891 .vsync_start = 240 + 4,
1892 .vsync_end = 240 + 4 + 3,
1893 .vtotal = 240 + 4 + 3 + 15,
1897 static const struct panel_desc lemaker_bl035_rgb_002 = {
1898 .modes = &lemaker_bl035_rgb_002_mode,
1904 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1905 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1908 static const struct drm_display_mode lg_lb070wv8_mode = {
1911 .hsync_start = 800 + 88,
1912 .hsync_end = 800 + 88 + 80,
1913 .htotal = 800 + 88 + 80 + 88,
1915 .vsync_start = 480 + 10,
1916 .vsync_end = 480 + 10 + 25,
1917 .vtotal = 480 + 10 + 25 + 10,
1921 static const struct panel_desc lg_lb070wv8 = {
1922 .modes = &lg_lb070wv8_mode,
1929 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1930 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1933 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1936 .hsync_start = 1536 + 12,
1937 .hsync_end = 1536 + 12 + 16,
1938 .htotal = 1536 + 12 + 16 + 48,
1940 .vsync_start = 2048 + 8,
1941 .vsync_end = 2048 + 8 + 4,
1942 .vtotal = 2048 + 8 + 4 + 8,
1944 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1947 static const struct panel_desc lg_lp079qx1_sp0v = {
1948 .modes = &lg_lp079qx1_sp0v_mode,
1956 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1959 .hsync_start = 2048 + 150,
1960 .hsync_end = 2048 + 150 + 5,
1961 .htotal = 2048 + 150 + 5 + 5,
1963 .vsync_start = 1536 + 3,
1964 .vsync_end = 1536 + 3 + 1,
1965 .vtotal = 1536 + 3 + 1 + 9,
1969 static const struct panel_desc lg_lp097qx1_spa1 = {
1970 .modes = &lg_lp097qx1_spa1_mode,
1978 static const struct drm_display_mode lg_lp120up1_mode = {
1981 .hsync_start = 1920 + 40,
1982 .hsync_end = 1920 + 40 + 40,
1983 .htotal = 1920 + 40 + 40+ 80,
1985 .vsync_start = 1280 + 4,
1986 .vsync_end = 1280 + 4 + 4,
1987 .vtotal = 1280 + 4 + 4 + 12,
1991 static const struct panel_desc lg_lp120up1 = {
1992 .modes = &lg_lp120up1_mode,
2001 static const struct drm_display_mode lg_lp129qe_mode = {
2004 .hsync_start = 2560 + 48,
2005 .hsync_end = 2560 + 48 + 32,
2006 .htotal = 2560 + 48 + 32 + 80,
2008 .vsync_start = 1700 + 3,
2009 .vsync_end = 1700 + 3 + 10,
2010 .vtotal = 1700 + 3 + 10 + 36,
2014 static const struct panel_desc lg_lp129qe = {
2015 .modes = &lg_lp129qe_mode,
2024 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2027 .hsync_start = 800 + 0,
2028 .hsync_end = 800 + 1,
2029 .htotal = 800 + 0 + 1 + 160,
2031 .vsync_start = 480 + 0,
2032 .vsync_end = 480 + 48 + 1,
2033 .vtotal = 480 + 48 + 1 + 0,
2035 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2038 static const struct drm_display_mode logicpd_type_28_mode = {
2041 .hsync_start = 480 + 3,
2042 .hsync_end = 480 + 3 + 42,
2043 .htotal = 480 + 3 + 42 + 2,
2046 .vsync_start = 272 + 2,
2047 .vsync_end = 272 + 2 + 11,
2048 .vtotal = 272 + 2 + 11 + 3,
2050 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2053 static const struct panel_desc logicpd_type_28 = {
2054 .modes = &logicpd_type_28_mode,
2067 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2068 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2069 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2072 static const struct panel_desc mitsubishi_aa070mc01 = {
2073 .modes = &mitsubishi_aa070mc01_mode,
2086 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2087 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2088 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2091 static const struct display_timing nec_nl12880bc20_05_timing = {
2092 .pixelclock = { 67000000, 71000000, 75000000 },
2093 .hactive = { 1280, 1280, 1280 },
2094 .hfront_porch = { 2, 30, 30 },
2095 .hback_porch = { 6, 100, 100 },
2096 .hsync_len = { 2, 30, 30 },
2097 .vactive = { 800, 800, 800 },
2098 .vfront_porch = { 5, 5, 5 },
2099 .vback_porch = { 11, 11, 11 },
2100 .vsync_len = { 7, 7, 7 },
2103 static const struct panel_desc nec_nl12880bc20_05 = {
2104 .timings = &nec_nl12880bc20_05_timing,
2115 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2116 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2119 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2122 .hsync_start = 480 + 2,
2123 .hsync_end = 480 + 2 + 41,
2124 .htotal = 480 + 2 + 41 + 2,
2126 .vsync_start = 272 + 2,
2127 .vsync_end = 272 + 2 + 4,
2128 .vtotal = 272 + 2 + 4 + 2,
2130 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2133 static const struct panel_desc nec_nl4827hc19_05b = {
2134 .modes = &nec_nl4827hc19_05b_mode,
2141 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2142 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2145 static const struct drm_display_mode netron_dy_e231732_mode = {
2148 .hsync_start = 1024 + 160,
2149 .hsync_end = 1024 + 160 + 70,
2150 .htotal = 1024 + 160 + 70 + 90,
2152 .vsync_start = 600 + 127,
2153 .vsync_end = 600 + 127 + 20,
2154 .vtotal = 600 + 127 + 20 + 3,
2158 static const struct panel_desc netron_dy_e231732 = {
2159 .modes = &netron_dy_e231732_mode,
2165 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2168 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2171 .hsync_start = 480 + 2,
2172 .hsync_end = 480 + 2 + 41,
2173 .htotal = 480 + 2 + 41 + 2,
2175 .vsync_start = 272 + 2,
2176 .vsync_end = 272 + 2 + 10,
2177 .vtotal = 272 + 2 + 10 + 2,
2179 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2182 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2183 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2190 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2191 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2192 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2195 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2196 .pixelclock = { 130000000, 148350000, 163000000 },
2197 .hactive = { 1920, 1920, 1920 },
2198 .hfront_porch = { 80, 100, 100 },
2199 .hback_porch = { 100, 120, 120 },
2200 .hsync_len = { 50, 60, 60 },
2201 .vactive = { 1080, 1080, 1080 },
2202 .vfront_porch = { 12, 30, 30 },
2203 .vback_porch = { 4, 10, 10 },
2204 .vsync_len = { 4, 5, 5 },
2207 static const struct panel_desc nlt_nl192108ac18_02d = {
2208 .timings = &nlt_nl192108ac18_02d_timing,
2218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2219 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2222 static const struct drm_display_mode nvd_9128_mode = {
2225 .hsync_start = 800 + 130,
2226 .hsync_end = 800 + 130 + 98,
2227 .htotal = 800 + 0 + 130 + 98,
2229 .vsync_start = 480 + 10,
2230 .vsync_end = 480 + 10 + 50,
2231 .vtotal = 480 + 0 + 10 + 50,
2234 static const struct panel_desc nvd_9128 = {
2235 .modes = &nvd_9128_mode,
2242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2243 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2246 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2247 .pixelclock = { 30000000, 30000000, 40000000 },
2248 .hactive = { 800, 800, 800 },
2249 .hfront_porch = { 40, 40, 40 },
2250 .hback_porch = { 40, 40, 40 },
2251 .hsync_len = { 1, 48, 48 },
2252 .vactive = { 480, 480, 480 },
2253 .vfront_porch = { 13, 13, 13 },
2254 .vback_porch = { 29, 29, 29 },
2255 .vsync_len = { 3, 3, 3 },
2256 .flags = DISPLAY_FLAGS_DE_HIGH,
2259 static const struct panel_desc okaya_rs800480t_7x0gp = {
2260 .timings = &okaya_rs800480t_7x0gp_timing,
2273 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2276 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2279 .hsync_start = 480 + 5,
2280 .hsync_end = 480 + 5 + 30,
2281 .htotal = 480 + 5 + 30 + 10,
2283 .vsync_start = 272 + 8,
2284 .vsync_end = 272 + 8 + 5,
2285 .vtotal = 272 + 8 + 5 + 3,
2289 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2290 .modes = &olimex_lcd_olinuxino_43ts_mode,
2296 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2300 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2301 * pixel clocks, but this is the timing that was being used in the Adafruit
2302 * installation instructions.
2304 static const struct drm_display_mode ontat_yx700wv03_mode = {
2315 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2320 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2322 static const struct panel_desc ontat_yx700wv03 = {
2323 .modes = &ontat_yx700wv03_mode,
2330 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2333 static const struct drm_display_mode ortustech_com37h3m_mode = {
2336 .hsync_start = 480 + 8,
2337 .hsync_end = 480 + 8 + 10,
2338 .htotal = 480 + 8 + 10 + 10,
2340 .vsync_start = 640 + 4,
2341 .vsync_end = 640 + 4 + 3,
2342 .vtotal = 640 + 4 + 3 + 4,
2344 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2347 static const struct panel_desc ortustech_com37h3m = {
2348 .modes = &ortustech_com37h3m_mode,
2352 .width = 56, /* 56.16mm */
2353 .height = 75, /* 74.88mm */
2355 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2356 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2357 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2360 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2363 .hsync_start = 480 + 10,
2364 .hsync_end = 480 + 10 + 10,
2365 .htotal = 480 + 10 + 10 + 15,
2367 .vsync_start = 800 + 3,
2368 .vsync_end = 800 + 3 + 3,
2369 .vtotal = 800 + 3 + 3 + 3,
2373 static const struct panel_desc ortustech_com43h4m85ulc = {
2374 .modes = &ortustech_com43h4m85ulc_mode,
2381 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2382 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2385 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2388 .hsync_start = 800 + 210,
2389 .hsync_end = 800 + 210 + 30,
2390 .htotal = 800 + 210 + 30 + 16,
2392 .vsync_start = 480 + 22,
2393 .vsync_end = 480 + 22 + 13,
2394 .vtotal = 480 + 22 + 13 + 10,
2396 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2399 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2400 .modes = &osddisplays_osd070t1718_19ts_mode,
2407 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2408 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2409 .connector_type = DRM_MODE_CONNECTOR_DPI,
2412 static const struct drm_display_mode pda_91_00156_a0_mode = {
2415 .hsync_start = 800 + 1,
2416 .hsync_end = 800 + 1 + 64,
2417 .htotal = 800 + 1 + 64 + 64,
2419 .vsync_start = 480 + 1,
2420 .vsync_end = 480 + 1 + 23,
2421 .vtotal = 480 + 1 + 23 + 22,
2425 static const struct panel_desc pda_91_00156_a0 = {
2426 .modes = &pda_91_00156_a0_mode,
2432 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2436 static const struct drm_display_mode qd43003c0_40_mode = {
2439 .hsync_start = 480 + 8,
2440 .hsync_end = 480 + 8 + 4,
2441 .htotal = 480 + 8 + 4 + 39,
2443 .vsync_start = 272 + 4,
2444 .vsync_end = 272 + 4 + 10,
2445 .vtotal = 272 + 4 + 10 + 2,
2449 static const struct panel_desc qd43003c0_40 = {
2450 .modes = &qd43003c0_40_mode,
2457 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2460 static const struct display_timing rocktech_rk070er9427_timing = {
2461 .pixelclock = { 26400000, 33300000, 46800000 },
2462 .hactive = { 800, 800, 800 },
2463 .hfront_porch = { 16, 210, 354 },
2464 .hback_porch = { 46, 46, 46 },
2465 .hsync_len = { 1, 1, 1 },
2466 .vactive = { 480, 480, 480 },
2467 .vfront_porch = { 7, 22, 147 },
2468 .vback_porch = { 23, 23, 23 },
2469 .vsync_len = { 1, 1, 1 },
2470 .flags = DISPLAY_FLAGS_DE_HIGH,
2473 static const struct panel_desc rocktech_rk070er9427 = {
2474 .timings = &rocktech_rk070er9427_timing,
2487 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2490 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2493 .hsync_start = 2560 + 48,
2494 .hsync_end = 2560 + 48 + 32,
2495 .htotal = 2560 + 48 + 32 + 80,
2497 .vsync_start = 1600 + 2,
2498 .vsync_end = 1600 + 2 + 5,
2499 .vtotal = 1600 + 2 + 5 + 57,
2503 static const struct panel_desc samsung_lsn122dl01_c01 = {
2504 .modes = &samsung_lsn122dl01_c01_mode,
2512 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2515 .hsync_start = 1024 + 24,
2516 .hsync_end = 1024 + 24 + 136,
2517 .htotal = 1024 + 24 + 136 + 160,
2519 .vsync_start = 600 + 3,
2520 .vsync_end = 600 + 3 + 6,
2521 .vtotal = 600 + 3 + 6 + 61,
2525 static const struct panel_desc samsung_ltn101nt05 = {
2526 .modes = &samsung_ltn101nt05_mode,
2535 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2538 .hsync_start = 1366 + 64,
2539 .hsync_end = 1366 + 64 + 48,
2540 .htotal = 1366 + 64 + 48 + 128,
2542 .vsync_start = 768 + 2,
2543 .vsync_end = 768 + 2 + 5,
2544 .vtotal = 768 + 2 + 5 + 17,
2548 static const struct panel_desc samsung_ltn140at29_301 = {
2549 .modes = &samsung_ltn140at29_301_mode,
2558 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2561 .hsync_start = 1920 + 48,
2562 .hsync_end = 1920 + 48 + 32,
2563 .htotal = 1920 + 48 + 32 + 80,
2565 .vsync_start = 1280 + 3,
2566 .vsync_end = 1280 + 3 + 10,
2567 .vtotal = 1280 + 3 + 10 + 57,
2569 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2572 static const struct panel_desc sharp_ld_d5116z01b = {
2573 .modes = &sharp_ld_d5116z01b_mode,
2580 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2581 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2584 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2587 .hsync_start = 800 + 64,
2588 .hsync_end = 800 + 64 + 128,
2589 .htotal = 800 + 64 + 128 + 64,
2591 .vsync_start = 480 + 8,
2592 .vsync_end = 480 + 8 + 2,
2593 .vtotal = 480 + 8 + 2 + 35,
2595 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2598 static const struct panel_desc sharp_lq070y3dg3b = {
2599 .modes = &sharp_lq070y3dg3b_mode,
2603 .width = 152, /* 152.4mm */
2604 .height = 91, /* 91.4mm */
2606 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2607 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2608 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2611 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2614 .hsync_start = 240 + 16,
2615 .hsync_end = 240 + 16 + 7,
2616 .htotal = 240 + 16 + 7 + 5,
2618 .vsync_start = 320 + 9,
2619 .vsync_end = 320 + 9 + 1,
2620 .vtotal = 320 + 9 + 1 + 7,
2624 static const struct panel_desc sharp_lq035q7db03 = {
2625 .modes = &sharp_lq035q7db03_mode,
2632 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2635 static const struct display_timing sharp_lq101k1ly04_timing = {
2636 .pixelclock = { 60000000, 65000000, 80000000 },
2637 .hactive = { 1280, 1280, 1280 },
2638 .hfront_porch = { 20, 20, 20 },
2639 .hback_porch = { 20, 20, 20 },
2640 .hsync_len = { 10, 10, 10 },
2641 .vactive = { 800, 800, 800 },
2642 .vfront_porch = { 4, 4, 4 },
2643 .vback_porch = { 4, 4, 4 },
2644 .vsync_len = { 4, 4, 4 },
2645 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2648 static const struct panel_desc sharp_lq101k1ly04 = {
2649 .timings = &sharp_lq101k1ly04_timing,
2656 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2657 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2660 static const struct display_timing sharp_lq123p1jx31_timing = {
2661 .pixelclock = { 252750000, 252750000, 266604720 },
2662 .hactive = { 2400, 2400, 2400 },
2663 .hfront_porch = { 48, 48, 48 },
2664 .hback_porch = { 80, 80, 84 },
2665 .hsync_len = { 32, 32, 32 },
2666 .vactive = { 1600, 1600, 1600 },
2667 .vfront_porch = { 3, 3, 3 },
2668 .vback_porch = { 33, 33, 120 },
2669 .vsync_len = { 10, 10, 10 },
2670 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2673 static const struct panel_desc sharp_lq123p1jx31 = {
2674 .timings = &sharp_lq123p1jx31_timing,
2688 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2691 .hsync_start = 1024 + 168,
2692 .hsync_end = 1024 + 168 + 64,
2693 .htotal = 1024 + 168 + 64 + 88,
2695 .vsync_start = 768 + 37,
2696 .vsync_end = 768 + 37 + 2,
2697 .vtotal = 768 + 37 + 2 + 8,
2701 static const struct panel_desc sharp_lq150x1lg11 = {
2702 .modes = &sharp_lq150x1lg11_mode,
2709 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2712 static const struct display_timing sharp_ls020b1dd01d_timing = {
2713 .pixelclock = { 2000000, 4200000, 5000000 },
2714 .hactive = { 240, 240, 240 },
2715 .hfront_porch = { 66, 66, 66 },
2716 .hback_porch = { 1, 1, 1 },
2717 .hsync_len = { 1, 1, 1 },
2718 .vactive = { 160, 160, 160 },
2719 .vfront_porch = { 52, 52, 52 },
2720 .vback_porch = { 6, 6, 6 },
2721 .vsync_len = { 10, 10, 10 },
2722 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2725 static const struct panel_desc sharp_ls020b1dd01d = {
2726 .timings = &sharp_ls020b1dd01d_timing,
2733 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2734 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2735 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2736 | DRM_BUS_FLAG_SHARP_SIGNALS,
2739 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2742 .hsync_start = 800 + 1,
2743 .hsync_end = 800 + 1 + 64,
2744 .htotal = 800 + 1 + 64 + 64,
2746 .vsync_start = 480 + 1,
2747 .vsync_end = 480 + 1 + 23,
2748 .vtotal = 480 + 1 + 23 + 22,
2752 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2753 .modes = &shelly_sca07010_bfn_lnn_mode,
2759 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2762 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2765 .hsync_start = 1920 + 16,
2766 .hsync_end = 1920 + 16 + 16,
2767 .htotal = 1920 + 16 + 16 + 32,
2769 .vsync_start = 1200 + 15,
2770 .vsync_end = 1200 + 15 + 2,
2771 .vtotal = 1200 + 15 + 2 + 18,
2773 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2776 static const struct panel_desc starry_kr122ea0sra = {
2777 .modes = &starry_kr122ea0sra_mode,
2784 .prepare = 10 + 200,
2786 .unprepare = 10 + 500,
2790 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2793 .hsync_start = 800 + 39,
2794 .hsync_end = 800 + 39 + 47,
2795 .htotal = 800 + 39 + 47 + 39,
2797 .vsync_start = 480 + 13,
2798 .vsync_end = 480 + 13 + 2,
2799 .vtotal = 480 + 13 + 2 + 29,
2803 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2804 .modes = &tfc_s9700rtwv43tr_01b_mode,
2811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2812 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2815 static const struct display_timing tianma_tm070jdhg30_timing = {
2816 .pixelclock = { 62600000, 68200000, 78100000 },
2817 .hactive = { 1280, 1280, 1280 },
2818 .hfront_porch = { 15, 64, 159 },
2819 .hback_porch = { 5, 5, 5 },
2820 .hsync_len = { 1, 1, 256 },
2821 .vactive = { 800, 800, 800 },
2822 .vfront_porch = { 3, 40, 99 },
2823 .vback_porch = { 2, 2, 2 },
2824 .vsync_len = { 1, 1, 128 },
2825 .flags = DISPLAY_FLAGS_DE_HIGH,
2828 static const struct panel_desc tianma_tm070jdhg30 = {
2829 .timings = &tianma_tm070jdhg30_timing,
2836 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2837 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2840 static const struct display_timing tianma_tm070rvhg71_timing = {
2841 .pixelclock = { 27700000, 29200000, 39600000 },
2842 .hactive = { 800, 800, 800 },
2843 .hfront_porch = { 12, 40, 212 },
2844 .hback_porch = { 88, 88, 88 },
2845 .hsync_len = { 1, 1, 40 },
2846 .vactive = { 480, 480, 480 },
2847 .vfront_porch = { 1, 13, 88 },
2848 .vback_porch = { 32, 32, 32 },
2849 .vsync_len = { 1, 1, 3 },
2850 .flags = DISPLAY_FLAGS_DE_HIGH,
2853 static const struct panel_desc tianma_tm070rvhg71 = {
2854 .timings = &tianma_tm070rvhg71_timing,
2861 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2862 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2865 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2869 .hsync_start = 320 + 50,
2870 .hsync_end = 320 + 50 + 6,
2871 .htotal = 320 + 50 + 6 + 38,
2873 .vsync_start = 240 + 3,
2874 .vsync_end = 240 + 3 + 1,
2875 .vtotal = 240 + 3 + 1 + 17,
2877 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2881 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2882 .modes = ti_nspire_cx_lcd_mode,
2889 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2890 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2893 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2897 .hsync_start = 320 + 6,
2898 .hsync_end = 320 + 6 + 6,
2899 .htotal = 320 + 6 + 6 + 6,
2901 .vsync_start = 240 + 0,
2902 .vsync_end = 240 + 0 + 1,
2903 .vtotal = 240 + 0 + 1 + 0,
2905 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2909 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2910 .modes = ti_nspire_classic_lcd_mode,
2912 /* The grayscale panel has 8 bit for the color .. Y (black) */
2918 /* This is the grayscale bus format */
2919 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2920 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2923 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2926 .hsync_start = 1280 + 192,
2927 .hsync_end = 1280 + 192 + 128,
2928 .htotal = 1280 + 192 + 128 + 64,
2930 .vsync_start = 768 + 20,
2931 .vsync_end = 768 + 20 + 7,
2932 .vtotal = 768 + 20 + 7 + 3,
2936 static const struct panel_desc toshiba_lt089ac29000 = {
2937 .modes = &toshiba_lt089ac29000_mode,
2943 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2944 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2945 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2948 static const struct drm_display_mode tpk_f07a_0102_mode = {
2951 .hsync_start = 800 + 40,
2952 .hsync_end = 800 + 40 + 128,
2953 .htotal = 800 + 40 + 128 + 88,
2955 .vsync_start = 480 + 10,
2956 .vsync_end = 480 + 10 + 2,
2957 .vtotal = 480 + 10 + 2 + 33,
2961 static const struct panel_desc tpk_f07a_0102 = {
2962 .modes = &tpk_f07a_0102_mode,
2968 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2971 static const struct drm_display_mode tpk_f10a_0102_mode = {
2974 .hsync_start = 1024 + 176,
2975 .hsync_end = 1024 + 176 + 5,
2976 .htotal = 1024 + 176 + 5 + 88,
2978 .vsync_start = 600 + 20,
2979 .vsync_end = 600 + 20 + 5,
2980 .vtotal = 600 + 20 + 5 + 25,
2984 static const struct panel_desc tpk_f10a_0102 = {
2985 .modes = &tpk_f10a_0102_mode,
2993 static const struct display_timing urt_umsh_8596md_timing = {
2994 .pixelclock = { 33260000, 33260000, 33260000 },
2995 .hactive = { 800, 800, 800 },
2996 .hfront_porch = { 41, 41, 41 },
2997 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2998 .hsync_len = { 71, 128, 128 },
2999 .vactive = { 480, 480, 480 },
3000 .vfront_porch = { 10, 10, 10 },
3001 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
3002 .vsync_len = { 2, 2, 2 },
3003 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
3004 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3007 static const struct panel_desc urt_umsh_8596md_lvds = {
3008 .timings = &urt_umsh_8596md_timing,
3015 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3016 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3019 static const struct panel_desc urt_umsh_8596md_parallel = {
3020 .timings = &urt_umsh_8596md_timing,
3027 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3030 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3033 .hsync_start = 800 + 210,
3034 .hsync_end = 800 + 210 + 20,
3035 .htotal = 800 + 210 + 20 + 46,
3037 .vsync_start = 480 + 22,
3038 .vsync_end = 480 + 22 + 10,
3039 .vtotal = 480 + 22 + 10 + 23,
3041 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3044 static const struct panel_desc vl050_8048nt_c01 = {
3045 .modes = &vl050_8048nt_c01_mode,
3052 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3053 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3056 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3059 .hsync_start = 320 + 20,
3060 .hsync_end = 320 + 20 + 30,
3061 .htotal = 320 + 20 + 30 + 38,
3063 .vsync_start = 240 + 4,
3064 .vsync_end = 240 + 4 + 3,
3065 .vtotal = 240 + 4 + 3 + 15,
3067 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3070 static const struct panel_desc winstar_wf35ltiacd = {
3071 .modes = &winstar_wf35ltiacd_mode,
3078 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3081 static const struct drm_display_mode arm_rtsm_mode[] = {
3085 .hsync_start = 1024 + 24,
3086 .hsync_end = 1024 + 24 + 136,
3087 .htotal = 1024 + 24 + 136 + 160,
3089 .vsync_start = 768 + 3,
3090 .vsync_end = 768 + 3 + 6,
3091 .vtotal = 768 + 3 + 6 + 29,
3093 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3097 static const struct panel_desc arm_rtsm = {
3098 .modes = arm_rtsm_mode,
3105 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3108 static const struct of_device_id platform_of_match[] = {
3110 .compatible = "ampire,am-480272h3tmqw-t01h",
3111 .data = &ire_am_480272h3tmqw_t01h,
3113 .compatible = "ampire,am800480r3tmqwa1h",
3114 .data = &ire_am800480r3tmqwa1h,
3116 .compatible = "arm,rtsm-display",
3119 .compatible = "armadeus,st0700-adapt",
3120 .data = &armadeus_st0700_adapt,
3122 .compatible = "auo,b101aw03",
3123 .data = &auo_b101aw03,
3125 .compatible = "auo,b101ean01",
3126 .data = &auo_b101ean01,
3128 .compatible = "auo,b101xtn01",
3129 .data = &auo_b101xtn01,
3131 .compatible = "auo,b116xw03",
3132 .data = &auo_b116xw03,
3134 .compatible = "auo,b133htn01",
3135 .data = &auo_b133htn01,
3137 .compatible = "auo,b133xtn01",
3138 .data = &auo_b133xtn01,
3140 .compatible = "auo,g070vvn01",
3141 .data = &auo_g070vvn01,
3143 .compatible = "auo,g101evn010",
3144 .data = &auo_g101evn010,
3146 .compatible = "auo,g104sn02",
3147 .data = &auo_g104sn02,
3149 .compatible = "auo,g133han01",
3150 .data = &auo_g133han01,
3152 .compatible = "auo,g185han01",
3153 .data = &auo_g185han01,
3155 .compatible = "auo,p320hvn03",
3156 .data = &auo_p320hvn03,
3158 .compatible = "auo,t215hvn01",
3159 .data = &auo_t215hvn01,
3161 .compatible = "avic,tm070ddh03",
3162 .data = &avic_tm070ddh03,
3164 .compatible = "bananapi,s070wv20-ct16",
3165 .data = &bananapi_s070wv20_ct16,
3167 .compatible = "boe,hv070wsa-100",
3168 .data = &boe_hv070wsa
3170 .compatible = "boe,nv101wxmn51",
3171 .data = &boe_nv101wxmn51,
3173 .compatible = "cdtech,s043wq26h-ct7",
3174 .data = &cdtech_s043wq26h_ct7,
3176 .compatible = "cdtech,s070wv95-ct16",
3177 .data = &cdtech_s070wv95_ct16,
3179 .compatible = "chunghwa,claa070wp03xg",
3180 .data = &chunghwa_claa070wp03xg,
3182 .compatible = "chunghwa,claa101wa01a",
3183 .data = &chunghwa_claa101wa01a
3185 .compatible = "chunghwa,claa101wb01",
3186 .data = &chunghwa_claa101wb01
3188 .compatible = "dataimage,scf0700c48ggu18",
3189 .data = &dataimage_scf0700c48ggu18,
3191 .compatible = "dlc,dlc0700yzg-1",
3192 .data = &dlc_dlc0700yzg_1,
3194 .compatible = "dlc,dlc1010gig",
3195 .data = &dlc_dlc1010gig,
3197 .compatible = "edt,et035012dm6",
3198 .data = &edt_et035012dm6,
3200 .compatible = "edt,etm0430g0dh6",
3201 .data = &edt_etm0430g0dh6,
3203 .compatible = "edt,et057090dhu",
3204 .data = &edt_et057090dhu,
3206 .compatible = "edt,et070080dh6",
3207 .data = &edt_etm0700g0dh6,
3209 .compatible = "edt,etm0700g0dh6",
3210 .data = &edt_etm0700g0dh6,
3212 .compatible = "edt,etm0700g0bdh6",
3213 .data = &edt_etm0700g0bdh6,
3215 .compatible = "edt,etm0700g0edh6",
3216 .data = &edt_etm0700g0bdh6,
3218 .compatible = "evervision,vgg804821",
3219 .data = &evervision_vgg804821,
3221 .compatible = "foxlink,fl500wvr00-a0t",
3222 .data = &foxlink_fl500wvr00_a0t,
3224 .compatible = "friendlyarm,hd702e",
3225 .data = &friendlyarm_hd702e,
3227 .compatible = "giantplus,gpg482739qs5",
3228 .data = &giantplus_gpg482739qs5
3230 .compatible = "giantplus,gpm940b0",
3231 .data = &giantplus_gpm940b0,
3233 .compatible = "hannstar,hsd070pww1",
3234 .data = &hannstar_hsd070pww1,
3236 .compatible = "hannstar,hsd100pxn1",
3237 .data = &hannstar_hsd100pxn1,
3239 .compatible = "hit,tx23d38vm0caa",
3240 .data = &hitachi_tx23d38vm0caa
3242 .compatible = "innolux,at043tn24",
3243 .data = &innolux_at043tn24,
3245 .compatible = "innolux,at070tn92",
3246 .data = &innolux_at070tn92,
3248 .compatible = "innolux,g070y2-l01",
3249 .data = &innolux_g070y2_l01,
3251 .compatible = "innolux,g101ice-l01",
3252 .data = &innolux_g101ice_l01
3254 .compatible = "innolux,g121i1-l01",
3255 .data = &innolux_g121i1_l01
3257 .compatible = "innolux,g121x1-l03",
3258 .data = &innolux_g121x1_l03,
3260 .compatible = "innolux,n116bge",
3261 .data = &innolux_n116bge,
3263 .compatible = "innolux,n156bge-l21",
3264 .data = &innolux_n156bge_l21,
3266 .compatible = "innolux,p120zdg-bf1",
3267 .data = &innolux_p120zdg_bf1,
3269 .compatible = "innolux,zj070na-01p",
3270 .data = &innolux_zj070na_01p,
3272 .compatible = "koe,tx14d24vm1bpa",
3273 .data = &koe_tx14d24vm1bpa,
3275 .compatible = "koe,tx31d200vm0baa",
3276 .data = &koe_tx31d200vm0baa,
3278 .compatible = "kyo,tcg121xglp",
3279 .data = &kyo_tcg121xglp,
3281 .compatible = "lemaker,bl035-rgb-002",
3282 .data = &lemaker_bl035_rgb_002,
3284 .compatible = "lg,lb070wv8",
3285 .data = &lg_lb070wv8,
3287 .compatible = "lg,lp079qx1-sp0v",
3288 .data = &lg_lp079qx1_sp0v,
3290 .compatible = "lg,lp097qx1-spa1",
3291 .data = &lg_lp097qx1_spa1,
3293 .compatible = "lg,lp120up1",
3294 .data = &lg_lp120up1,
3296 .compatible = "lg,lp129qe",
3297 .data = &lg_lp129qe,
3299 .compatible = "logicpd,type28",
3300 .data = &logicpd_type_28,
3302 .compatible = "mitsubishi,aa070mc01-ca1",
3303 .data = &mitsubishi_aa070mc01,
3305 .compatible = "nec,nl12880bc20-05",
3306 .data = &nec_nl12880bc20_05,
3308 .compatible = "nec,nl4827hc19-05b",
3309 .data = &nec_nl4827hc19_05b,
3311 .compatible = "netron-dy,e231732",
3312 .data = &netron_dy_e231732,
3314 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3315 .data = &newhaven_nhd_43_480272ef_atxl,
3317 .compatible = "nlt,nl192108ac18-02d",
3318 .data = &nlt_nl192108ac18_02d,
3320 .compatible = "nvd,9128",
3323 .compatible = "okaya,rs800480t-7x0gp",
3324 .data = &okaya_rs800480t_7x0gp,
3326 .compatible = "olimex,lcd-olinuxino-43-ts",
3327 .data = &olimex_lcd_olinuxino_43ts,
3329 .compatible = "ontat,yx700wv03",
3330 .data = &ontat_yx700wv03,
3332 .compatible = "ortustech,com37h3m05dtc",
3333 .data = &ortustech_com37h3m,
3335 .compatible = "ortustech,com37h3m99dtc",
3336 .data = &ortustech_com37h3m,
3338 .compatible = "ortustech,com43h4m85ulc",
3339 .data = &ortustech_com43h4m85ulc,
3341 .compatible = "osddisplays,osd070t1718-19ts",
3342 .data = &osddisplays_osd070t1718_19ts,
3344 .compatible = "pda,91-00156-a0",
3345 .data = &pda_91_00156_a0,
3347 .compatible = "qiaodian,qd43003c0-40",
3348 .data = &qd43003c0_40,
3350 .compatible = "rocktech,rk070er9427",
3351 .data = &rocktech_rk070er9427,
3353 .compatible = "samsung,lsn122dl01-c01",
3354 .data = &samsung_lsn122dl01_c01,
3356 .compatible = "samsung,ltn101nt05",
3357 .data = &samsung_ltn101nt05,
3359 .compatible = "samsung,ltn140at29-301",
3360 .data = &samsung_ltn140at29_301,
3362 .compatible = "sharp,ld-d5116z01b",
3363 .data = &sharp_ld_d5116z01b,
3365 .compatible = "sharp,lq035q7db03",
3366 .data = &sharp_lq035q7db03,
3368 .compatible = "sharp,lq070y3dg3b",
3369 .data = &sharp_lq070y3dg3b,
3371 .compatible = "sharp,lq101k1ly04",
3372 .data = &sharp_lq101k1ly04,
3374 .compatible = "sharp,lq123p1jx31",
3375 .data = &sharp_lq123p1jx31,
3377 .compatible = "sharp,lq150x1lg11",
3378 .data = &sharp_lq150x1lg11,
3380 .compatible = "sharp,ls020b1dd01d",
3381 .data = &sharp_ls020b1dd01d,
3383 .compatible = "shelly,sca07010-bfn-lnn",
3384 .data = &shelly_sca07010_bfn_lnn,
3386 .compatible = "starry,kr122ea0sra",
3387 .data = &starry_kr122ea0sra,
3389 .compatible = "tfc,s9700rtwv43tr-01b",
3390 .data = &tfc_s9700rtwv43tr_01b,
3392 .compatible = "tianma,tm070jdhg30",
3393 .data = &tianma_tm070jdhg30,
3395 .compatible = "tianma,tm070rvhg71",
3396 .data = &tianma_tm070rvhg71,
3398 .compatible = "ti,nspire-cx-lcd-panel",
3399 .data = &ti_nspire_cx_lcd_panel,
3401 .compatible = "ti,nspire-classic-lcd-panel",
3402 .data = &ti_nspire_classic_lcd_panel,
3404 .compatible = "toshiba,lt089ac29000",
3405 .data = &toshiba_lt089ac29000,
3407 .compatible = "tpk,f07a-0102",
3408 .data = &tpk_f07a_0102,
3410 .compatible = "tpk,f10a-0102",
3411 .data = &tpk_f10a_0102,
3413 .compatible = "urt,umsh-8596md-t",
3414 .data = &urt_umsh_8596md_parallel,
3416 .compatible = "urt,umsh-8596md-1t",
3417 .data = &urt_umsh_8596md_parallel,
3419 .compatible = "urt,umsh-8596md-7t",
3420 .data = &urt_umsh_8596md_parallel,
3422 .compatible = "urt,umsh-8596md-11t",
3423 .data = &urt_umsh_8596md_lvds,
3425 .compatible = "urt,umsh-8596md-19t",
3426 .data = &urt_umsh_8596md_lvds,
3428 .compatible = "urt,umsh-8596md-20t",
3429 .data = &urt_umsh_8596md_parallel,
3431 .compatible = "vxt,vl050-8048nt-c01",
3432 .data = &vl050_8048nt_c01,
3434 .compatible = "winstar,wf35ltiacd",
3435 .data = &winstar_wf35ltiacd,
3440 MODULE_DEVICE_TABLE(of, platform_of_match);
3442 static int panel_simple_platform_probe(struct platform_device *pdev)
3444 const struct of_device_id *id;
3446 id = of_match_node(platform_of_match, pdev->dev.of_node);
3450 return panel_simple_probe(&pdev->dev, id->data);
3453 static int panel_simple_platform_remove(struct platform_device *pdev)
3455 return panel_simple_remove(&pdev->dev);
3458 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3460 panel_simple_shutdown(&pdev->dev);
3463 static struct platform_driver panel_simple_platform_driver = {
3465 .name = "panel-simple",
3466 .of_match_table = platform_of_match,
3468 .probe = panel_simple_platform_probe,
3469 .remove = panel_simple_platform_remove,
3470 .shutdown = panel_simple_platform_shutdown,
3473 struct panel_desc_dsi {
3474 struct panel_desc desc;
3476 unsigned long flags;
3477 enum mipi_dsi_pixel_format format;
3481 static const struct drm_display_mode auo_b080uan01_mode = {
3484 .hsync_start = 1200 + 62,
3485 .hsync_end = 1200 + 62 + 4,
3486 .htotal = 1200 + 62 + 4 + 62,
3488 .vsync_start = 1920 + 9,
3489 .vsync_end = 1920 + 9 + 2,
3490 .vtotal = 1920 + 9 + 2 + 8,
3494 static const struct panel_desc_dsi auo_b080uan01 = {
3496 .modes = &auo_b080uan01_mode,
3504 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3505 .format = MIPI_DSI_FMT_RGB888,
3509 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3512 .hsync_start = 1200 + 120,
3513 .hsync_end = 1200 + 120 + 20,
3514 .htotal = 1200 + 120 + 20 + 21,
3516 .vsync_start = 1920 + 21,
3517 .vsync_end = 1920 + 21 + 3,
3518 .vtotal = 1920 + 21 + 3 + 18,
3520 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3523 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3525 .modes = &boe_tv080wum_nl0_mode,
3532 .flags = MIPI_DSI_MODE_VIDEO |
3533 MIPI_DSI_MODE_VIDEO_BURST |
3534 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3535 .format = MIPI_DSI_FMT_RGB888,
3539 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3542 .hsync_start = 800 + 32,
3543 .hsync_end = 800 + 32 + 1,
3544 .htotal = 800 + 32 + 1 + 57,
3546 .vsync_start = 1280 + 28,
3547 .vsync_end = 1280 + 28 + 1,
3548 .vtotal = 1280 + 28 + 1 + 14,
3552 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3554 .modes = &lg_ld070wx3_sl01_mode,
3562 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3563 .format = MIPI_DSI_FMT_RGB888,
3567 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3570 .hsync_start = 720 + 12,
3571 .hsync_end = 720 + 12 + 4,
3572 .htotal = 720 + 12 + 4 + 112,
3574 .vsync_start = 1280 + 8,
3575 .vsync_end = 1280 + 8 + 4,
3576 .vtotal = 1280 + 8 + 4 + 12,
3580 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3582 .modes = &lg_lh500wx1_sd03_mode,
3590 .flags = MIPI_DSI_MODE_VIDEO,
3591 .format = MIPI_DSI_FMT_RGB888,
3595 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3598 .hsync_start = 1920 + 154,
3599 .hsync_end = 1920 + 154 + 16,
3600 .htotal = 1920 + 154 + 16 + 32,
3602 .vsync_start = 1200 + 17,
3603 .vsync_end = 1200 + 17 + 2,
3604 .vtotal = 1200 + 17 + 2 + 16,
3608 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3610 .modes = &panasonic_vvx10f004b00_mode,
3618 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3619 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3620 .format = MIPI_DSI_FMT_RGB888,
3624 static const struct drm_display_mode lg_acx467akm_7_mode = {
3627 .hsync_start = 1080 + 2,
3628 .hsync_end = 1080 + 2 + 2,
3629 .htotal = 1080 + 2 + 2 + 2,
3631 .vsync_start = 1920 + 2,
3632 .vsync_end = 1920 + 2 + 2,
3633 .vtotal = 1920 + 2 + 2 + 2,
3637 static const struct panel_desc_dsi lg_acx467akm_7 = {
3639 .modes = &lg_acx467akm_7_mode,
3648 .format = MIPI_DSI_FMT_RGB888,
3652 static const struct drm_display_mode osd101t2045_53ts_mode = {
3655 .hsync_start = 1920 + 112,
3656 .hsync_end = 1920 + 112 + 16,
3657 .htotal = 1920 + 112 + 16 + 32,
3659 .vsync_start = 1200 + 16,
3660 .vsync_end = 1200 + 16 + 2,
3661 .vtotal = 1200 + 16 + 2 + 16,
3663 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3666 static const struct panel_desc_dsi osd101t2045_53ts = {
3668 .modes = &osd101t2045_53ts_mode,
3676 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3677 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3678 MIPI_DSI_MODE_EOT_PACKET,
3679 .format = MIPI_DSI_FMT_RGB888,
3683 static const struct of_device_id dsi_of_match[] = {
3685 .compatible = "auo,b080uan01",
3686 .data = &auo_b080uan01
3688 .compatible = "boe,tv080wum-nl0",
3689 .data = &boe_tv080wum_nl0
3691 .compatible = "lg,ld070wx3-sl01",
3692 .data = &lg_ld070wx3_sl01
3694 .compatible = "lg,lh500wx1-sd03",
3695 .data = &lg_lh500wx1_sd03
3697 .compatible = "panasonic,vvx10f004b00",
3698 .data = &panasonic_vvx10f004b00
3700 .compatible = "lg,acx467akm-7",
3701 .data = &lg_acx467akm_7
3703 .compatible = "osddisplays,osd101t2045-53ts",
3704 .data = &osd101t2045_53ts
3709 MODULE_DEVICE_TABLE(of, dsi_of_match);
3711 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3713 const struct panel_desc_dsi *desc;
3714 const struct of_device_id *id;
3717 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3723 err = panel_simple_probe(&dsi->dev, &desc->desc);
3727 dsi->mode_flags = desc->flags;
3728 dsi->format = desc->format;
3729 dsi->lanes = desc->lanes;
3731 err = mipi_dsi_attach(dsi);
3733 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3735 drm_panel_remove(&panel->base);
3741 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3745 err = mipi_dsi_detach(dsi);
3747 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3749 return panel_simple_remove(&dsi->dev);
3752 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3754 panel_simple_shutdown(&dsi->dev);
3757 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3759 .name = "panel-simple-dsi",
3760 .of_match_table = dsi_of_match,
3762 .probe = panel_simple_dsi_probe,
3763 .remove = panel_simple_dsi_remove,
3764 .shutdown = panel_simple_dsi_shutdown,
3767 static int __init panel_simple_init(void)
3771 err = platform_driver_register(&panel_simple_platform_driver);
3775 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3776 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3783 module_init(panel_simple_init);
3785 static void __exit panel_simple_exit(void)
3787 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3788 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3790 platform_driver_unregister(&panel_simple_platform_driver);
3792 module_exit(panel_simple_exit);
3794 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3795 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3796 MODULE_LICENSE("GPL and additional rights");