2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/delay.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/module.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/regulator/consumer.h>
32 #include <video/display_timing.h>
33 #include <video/of_display_timing.h>
34 #include <video/videomode.h>
36 #include <drm/drm_crtc.h>
37 #include <drm/drm_device.h>
38 #include <drm/drm_mipi_dsi.h>
39 #include <drm/drm_panel.h>
42 * @modes: Pointer to array of fixed modes appropriate for this panel. If
43 * only one mode then this can just be the address of this the mode.
44 * NOTE: cannot be used with "timings" and also if this is specified
45 * then you cannot override the mode in the device tree.
46 * @num_modes: Number of elements in modes array.
47 * @timings: Pointer to array of display timings. NOTE: cannot be used with
48 * "modes" and also these will be used to validate a device tree
49 * override if one is present.
50 * @num_timings: Number of elements in timings array.
51 * @bpc: Bits per color.
52 * @size: Structure containing the physical size of this panel.
53 * @delay: Structure containing various delay values for this panel.
54 * @bus_format: See MEDIA_BUS_FMT_... defines.
55 * @bus_flags: See DRM_BUS_FLAG_... defines.
58 const struct drm_display_mode *modes;
59 unsigned int num_modes;
60 const struct display_timing *timings;
61 unsigned int num_timings;
66 * @width: width (in millimeters) of the panel's active display area
67 * @height: height (in millimeters) of the panel's active display area
75 * @prepare: the time (in milliseconds) that it takes for the panel to
76 * become ready and start receiving video data
77 * @hpd_absent_delay: Add this to the prepare delay if we know Hot
78 * Plug Detect isn't used.
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
89 unsigned int hpd_absent_delay;
92 unsigned int unprepare;
100 struct panel_simple {
101 struct drm_panel base;
106 const struct panel_desc *desc;
108 struct backlight_device *backlight;
109 struct regulator *supply;
110 struct i2c_adapter *ddc;
112 struct gpio_desc *enable_gpio;
114 struct drm_display_mode override_mode;
117 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
119 return container_of(panel, struct panel_simple, base);
122 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel)
124 struct drm_connector *connector = panel->base.connector;
125 struct drm_device *drm = panel->base.drm;
126 struct drm_display_mode *mode;
127 unsigned int i, num = 0;
129 for (i = 0; i < panel->desc->num_timings; i++) {
130 const struct display_timing *dt = &panel->desc->timings[i];
133 videomode_from_timing(dt, &vm);
134 mode = drm_mode_create(drm);
136 dev_err(drm->dev, "failed to add mode %ux%u\n",
137 dt->hactive.typ, dt->vactive.typ);
141 drm_display_mode_from_videomode(&vm, mode);
143 mode->type |= DRM_MODE_TYPE_DRIVER;
145 if (panel->desc->num_timings == 1)
146 mode->type |= DRM_MODE_TYPE_PREFERRED;
148 drm_mode_probed_add(connector, mode);
155 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel)
157 struct drm_connector *connector = panel->base.connector;
158 struct drm_device *drm = panel->base.drm;
159 struct drm_display_mode *mode;
160 unsigned int i, num = 0;
162 for (i = 0; i < panel->desc->num_modes; i++) {
163 const struct drm_display_mode *m = &panel->desc->modes[i];
165 mode = drm_mode_duplicate(drm, m);
167 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
168 m->hdisplay, m->vdisplay, m->vrefresh);
172 mode->type |= DRM_MODE_TYPE_DRIVER;
174 if (panel->desc->num_modes == 1)
175 mode->type |= DRM_MODE_TYPE_PREFERRED;
177 drm_mode_set_name(mode);
179 drm_mode_probed_add(connector, mode);
186 static int panel_simple_get_non_edid_modes(struct panel_simple *panel)
188 struct drm_connector *connector = panel->base.connector;
189 struct drm_device *drm = panel->base.drm;
190 struct drm_display_mode *mode;
191 bool has_override = panel->override_mode.type;
192 unsigned int num = 0;
198 mode = drm_mode_duplicate(drm, &panel->override_mode);
200 drm_mode_probed_add(connector, mode);
203 dev_err(drm->dev, "failed to add override mode\n");
207 /* Only add timings if override was not there or failed to validate */
208 if (num == 0 && panel->desc->num_timings)
209 num = panel_simple_get_timings_modes(panel);
212 * Only add fixed modes if timings/override added no mode.
214 * We should only ever have either the display timings specified
215 * or a fixed mode. Anything else is rather bogus.
217 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
219 num = panel_simple_get_display_modes(panel);
221 connector->display_info.bpc = panel->desc->bpc;
222 connector->display_info.width_mm = panel->desc->size.width;
223 connector->display_info.height_mm = panel->desc->size.height;
224 if (panel->desc->bus_format)
225 drm_display_info_set_bus_formats(&connector->display_info,
226 &panel->desc->bus_format, 1);
227 connector->display_info.bus_flags = panel->desc->bus_flags;
232 static int panel_simple_disable(struct drm_panel *panel)
234 struct panel_simple *p = to_panel_simple(panel);
240 p->backlight->props.power = FB_BLANK_POWERDOWN;
241 p->backlight->props.state |= BL_CORE_FBBLANK;
242 backlight_update_status(p->backlight);
245 if (p->desc->delay.disable)
246 msleep(p->desc->delay.disable);
253 static int panel_simple_unprepare(struct drm_panel *panel)
255 struct panel_simple *p = to_panel_simple(panel);
260 gpiod_set_value_cansleep(p->enable_gpio, 0);
262 regulator_disable(p->supply);
264 if (p->desc->delay.unprepare)
265 msleep(p->desc->delay.unprepare);
272 static int panel_simple_prepare(struct drm_panel *panel)
274 struct panel_simple *p = to_panel_simple(panel);
281 err = regulator_enable(p->supply);
283 dev_err(panel->dev, "failed to enable supply: %d\n", err);
287 gpiod_set_value_cansleep(p->enable_gpio, 1);
289 delay = p->desc->delay.prepare;
291 delay += p->desc->delay.hpd_absent_delay;
300 static int panel_simple_enable(struct drm_panel *panel)
302 struct panel_simple *p = to_panel_simple(panel);
307 if (p->desc->delay.enable)
308 msleep(p->desc->delay.enable);
311 p->backlight->props.state &= ~BL_CORE_FBBLANK;
312 p->backlight->props.power = FB_BLANK_UNBLANK;
313 backlight_update_status(p->backlight);
321 static int panel_simple_get_modes(struct drm_panel *panel)
323 struct panel_simple *p = to_panel_simple(panel);
326 /* probe EDID if a DDC bus is available */
328 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
329 drm_connector_update_edid_property(panel->connector, edid);
331 num += drm_add_edid_modes(panel->connector, edid);
336 /* add hard-coded panel modes */
337 num += panel_simple_get_non_edid_modes(p);
342 static int panel_simple_get_timings(struct drm_panel *panel,
343 unsigned int num_timings,
344 struct display_timing *timings)
346 struct panel_simple *p = to_panel_simple(panel);
349 if (p->desc->num_timings < num_timings)
350 num_timings = p->desc->num_timings;
353 for (i = 0; i < num_timings; i++)
354 timings[i] = p->desc->timings[i];
356 return p->desc->num_timings;
359 static const struct drm_panel_funcs panel_simple_funcs = {
360 .disable = panel_simple_disable,
361 .unprepare = panel_simple_unprepare,
362 .prepare = panel_simple_prepare,
363 .enable = panel_simple_enable,
364 .get_modes = panel_simple_get_modes,
365 .get_timings = panel_simple_get_timings,
368 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
369 (to_check->field.typ >= bounds->field.min && \
370 to_check->field.typ <= bounds->field.max)
371 static void panel_simple_parse_panel_timing_node(struct device *dev,
372 struct panel_simple *panel,
373 const struct display_timing *ot)
375 const struct panel_desc *desc = panel->desc;
379 if (WARN_ON(desc->num_modes)) {
380 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
383 if (WARN_ON(!desc->num_timings)) {
384 dev_err(dev, "Reject override mode: no timings specified\n");
388 for (i = 0; i < panel->desc->num_timings; i++) {
389 const struct display_timing *dt = &panel->desc->timings[i];
391 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
392 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
393 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
394 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
395 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
396 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
397 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
398 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
401 if (ot->flags != dt->flags)
404 videomode_from_timing(ot, &vm);
405 drm_display_mode_from_videomode(&vm, &panel->override_mode);
406 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
407 DRM_MODE_TYPE_PREFERRED;
411 if (WARN_ON(!panel->override_mode.type))
412 dev_err(dev, "Reject override mode: No display_timing found\n");
415 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
417 struct device_node *backlight, *ddc;
418 struct panel_simple *panel;
419 struct display_timing dt;
422 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
426 panel->enabled = false;
427 panel->prepared = false;
430 panel->no_hpd = of_property_read_bool(dev->of_node, "no-hpd");
432 panel->supply = devm_regulator_get(dev, "power");
433 if (IS_ERR(panel->supply))
434 return PTR_ERR(panel->supply);
436 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
438 if (IS_ERR(panel->enable_gpio)) {
439 err = PTR_ERR(panel->enable_gpio);
440 if (err != -EPROBE_DEFER)
441 dev_err(dev, "failed to request GPIO: %d\n", err);
445 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
447 panel->backlight = of_find_backlight_by_node(backlight);
448 of_node_put(backlight);
450 if (!panel->backlight)
451 return -EPROBE_DEFER;
454 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
456 panel->ddc = of_find_i2c_adapter_by_node(ddc);
465 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
466 panel_simple_parse_panel_timing_node(dev, panel, &dt);
468 drm_panel_init(&panel->base, dev, &panel_simple_funcs,
469 desc->connector_type);
471 err = drm_panel_add(&panel->base);
475 dev_set_drvdata(dev, panel);
481 put_device(&panel->ddc->dev);
483 if (panel->backlight)
484 put_device(&panel->backlight->dev);
489 static int panel_simple_remove(struct device *dev)
491 struct panel_simple *panel = dev_get_drvdata(dev);
493 drm_panel_remove(&panel->base);
495 panel_simple_disable(&panel->base);
496 panel_simple_unprepare(&panel->base);
499 put_device(&panel->ddc->dev);
501 if (panel->backlight)
502 put_device(&panel->backlight->dev);
507 static void panel_simple_shutdown(struct device *dev)
509 struct panel_simple *panel = dev_get_drvdata(dev);
511 panel_simple_disable(&panel->base);
512 panel_simple_unprepare(&panel->base);
515 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
518 .hsync_start = 480 + 2,
519 .hsync_end = 480 + 2 + 41,
520 .htotal = 480 + 2 + 41 + 2,
522 .vsync_start = 272 + 2,
523 .vsync_end = 272 + 2 + 10,
524 .vtotal = 272 + 2 + 10 + 2,
526 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
529 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
530 .modes = &ire_am_480272h3tmqw_t01h_mode,
537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
540 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
543 .hsync_start = 800 + 0,
544 .hsync_end = 800 + 0 + 255,
545 .htotal = 800 + 0 + 255 + 0,
547 .vsync_start = 480 + 2,
548 .vsync_end = 480 + 2 + 45,
549 .vtotal = 480 + 2 + 45 + 0,
551 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
554 static const struct panel_desc ampire_am800480r3tmqwa1h = {
555 .modes = &ire_am800480r3tmqwa1h_mode,
562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
565 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
566 .pixelclock = { 26400000, 33300000, 46800000 },
567 .hactive = { 800, 800, 800 },
568 .hfront_porch = { 16, 210, 354 },
569 .hback_porch = { 45, 36, 6 },
570 .hsync_len = { 1, 10, 40 },
571 .vactive = { 480, 480, 480 },
572 .vfront_porch = { 7, 22, 147 },
573 .vback_porch = { 22, 13, 3 },
574 .vsync_len = { 1, 10, 20 },
575 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
576 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
579 static const struct panel_desc armadeus_st0700_adapt = {
580 .timings = &santek_st0700i5y_rbslw_f_timing,
587 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
588 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
591 static const struct drm_display_mode auo_b101aw03_mode = {
594 .hsync_start = 1024 + 156,
595 .hsync_end = 1024 + 156 + 8,
596 .htotal = 1024 + 156 + 8 + 156,
598 .vsync_start = 600 + 16,
599 .vsync_end = 600 + 16 + 6,
600 .vtotal = 600 + 16 + 6 + 16,
604 static const struct panel_desc auo_b101aw03 = {
605 .modes = &auo_b101aw03_mode,
614 static const struct display_timing auo_b101ean01_timing = {
615 .pixelclock = { 65300000, 72500000, 75000000 },
616 .hactive = { 1280, 1280, 1280 },
617 .hfront_porch = { 18, 119, 119 },
618 .hback_porch = { 21, 21, 21 },
619 .hsync_len = { 32, 32, 32 },
620 .vactive = { 800, 800, 800 },
621 .vfront_porch = { 4, 4, 4 },
622 .vback_porch = { 8, 8, 8 },
623 .vsync_len = { 18, 20, 20 },
626 static const struct panel_desc auo_b101ean01 = {
627 .timings = &auo_b101ean01_timing,
636 static const struct drm_display_mode auo_b101xtn01_mode = {
639 .hsync_start = 1366 + 20,
640 .hsync_end = 1366 + 20 + 70,
641 .htotal = 1366 + 20 + 70,
643 .vsync_start = 768 + 14,
644 .vsync_end = 768 + 14 + 42,
645 .vtotal = 768 + 14 + 42,
647 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
650 static const struct panel_desc auo_b101xtn01 = {
651 .modes = &auo_b101xtn01_mode,
660 static const struct drm_display_mode auo_b116xw03_mode = {
663 .hsync_start = 1366 + 40,
664 .hsync_end = 1366 + 40 + 40,
665 .htotal = 1366 + 40 + 40 + 32,
667 .vsync_start = 768 + 10,
668 .vsync_end = 768 + 10 + 12,
669 .vtotal = 768 + 10 + 12 + 6,
673 static const struct panel_desc auo_b116xw03 = {
674 .modes = &auo_b116xw03_mode,
683 static const struct drm_display_mode auo_b133xtn01_mode = {
686 .hsync_start = 1366 + 48,
687 .hsync_end = 1366 + 48 + 32,
688 .htotal = 1366 + 48 + 32 + 20,
690 .vsync_start = 768 + 3,
691 .vsync_end = 768 + 3 + 6,
692 .vtotal = 768 + 3 + 6 + 13,
696 static const struct panel_desc auo_b133xtn01 = {
697 .modes = &auo_b133xtn01_mode,
706 static const struct drm_display_mode auo_b133htn01_mode = {
709 .hsync_start = 1920 + 172,
710 .hsync_end = 1920 + 172 + 80,
711 .htotal = 1920 + 172 + 80 + 60,
713 .vsync_start = 1080 + 25,
714 .vsync_end = 1080 + 25 + 10,
715 .vtotal = 1080 + 25 + 10 + 10,
719 static const struct panel_desc auo_b133htn01 = {
720 .modes = &auo_b133htn01_mode,
734 static const struct display_timing auo_g070vvn01_timings = {
735 .pixelclock = { 33300000, 34209000, 45000000 },
736 .hactive = { 800, 800, 800 },
737 .hfront_porch = { 20, 40, 200 },
738 .hback_porch = { 87, 40, 1 },
739 .hsync_len = { 1, 48, 87 },
740 .vactive = { 480, 480, 480 },
741 .vfront_porch = { 5, 13, 200 },
742 .vback_porch = { 31, 31, 29 },
743 .vsync_len = { 1, 1, 3 },
746 static const struct panel_desc auo_g070vvn01 = {
747 .timings = &auo_g070vvn01_timings,
762 static const struct drm_display_mode auo_g101evn010_mode = {
765 .hsync_start = 1280 + 82,
766 .hsync_end = 1280 + 82 + 2,
767 .htotal = 1280 + 82 + 2 + 84,
769 .vsync_start = 800 + 8,
770 .vsync_end = 800 + 8 + 2,
771 .vtotal = 800 + 8 + 2 + 6,
775 static const struct panel_desc auo_g101evn010 = {
776 .modes = &auo_g101evn010_mode,
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
786 static const struct drm_display_mode auo_g104sn02_mode = {
789 .hsync_start = 800 + 40,
790 .hsync_end = 800 + 40 + 216,
791 .htotal = 800 + 40 + 216 + 128,
793 .vsync_start = 600 + 10,
794 .vsync_end = 600 + 10 + 35,
795 .vtotal = 600 + 10 + 35 + 2,
799 static const struct panel_desc auo_g104sn02 = {
800 .modes = &auo_g104sn02_mode,
809 static const struct display_timing auo_g133han01_timings = {
810 .pixelclock = { 134000000, 141200000, 149000000 },
811 .hactive = { 1920, 1920, 1920 },
812 .hfront_porch = { 39, 58, 77 },
813 .hback_porch = { 59, 88, 117 },
814 .hsync_len = { 28, 42, 56 },
815 .vactive = { 1080, 1080, 1080 },
816 .vfront_porch = { 3, 8, 11 },
817 .vback_porch = { 5, 14, 19 },
818 .vsync_len = { 4, 14, 19 },
821 static const struct panel_desc auo_g133han01 = {
822 .timings = &auo_g133han01_timings,
835 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
836 .connector_type = DRM_MODE_CONNECTOR_LVDS,
839 static const struct display_timing auo_g185han01_timings = {
840 .pixelclock = { 120000000, 144000000, 175000000 },
841 .hactive = { 1920, 1920, 1920 },
842 .hfront_porch = { 36, 120, 148 },
843 .hback_porch = { 24, 88, 108 },
844 .hsync_len = { 20, 48, 64 },
845 .vactive = { 1080, 1080, 1080 },
846 .vfront_porch = { 6, 10, 40 },
847 .vback_porch = { 2, 5, 20 },
848 .vsync_len = { 2, 5, 20 },
851 static const struct panel_desc auo_g185han01 = {
852 .timings = &auo_g185han01_timings,
865 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
866 .connector_type = DRM_MODE_CONNECTOR_LVDS,
869 static const struct display_timing auo_p320hvn03_timings = {
870 .pixelclock = { 106000000, 148500000, 164000000 },
871 .hactive = { 1920, 1920, 1920 },
872 .hfront_porch = { 25, 50, 130 },
873 .hback_porch = { 25, 50, 130 },
874 .hsync_len = { 20, 40, 105 },
875 .vactive = { 1080, 1080, 1080 },
876 .vfront_porch = { 8, 17, 150 },
877 .vback_porch = { 8, 17, 150 },
878 .vsync_len = { 4, 11, 100 },
881 static const struct panel_desc auo_p320hvn03 = {
882 .timings = &auo_p320hvn03_timings,
894 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
895 .connector_type = DRM_MODE_CONNECTOR_LVDS,
898 static const struct drm_display_mode auo_t215hvn01_mode = {
901 .hsync_start = 1920 + 88,
902 .hsync_end = 1920 + 88 + 44,
903 .htotal = 1920 + 88 + 44 + 148,
905 .vsync_start = 1080 + 4,
906 .vsync_end = 1080 + 4 + 5,
907 .vtotal = 1080 + 4 + 5 + 36,
911 static const struct panel_desc auo_t215hvn01 = {
912 .modes = &auo_t215hvn01_mode,
925 static const struct drm_display_mode avic_tm070ddh03_mode = {
928 .hsync_start = 1024 + 160,
929 .hsync_end = 1024 + 160 + 4,
930 .htotal = 1024 + 160 + 4 + 156,
932 .vsync_start = 600 + 17,
933 .vsync_end = 600 + 17 + 1,
934 .vtotal = 600 + 17 + 1 + 17,
938 static const struct panel_desc avic_tm070ddh03 = {
939 .modes = &avic_tm070ddh03_mode,
953 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
956 .hsync_start = 800 + 40,
957 .hsync_end = 800 + 40 + 48,
958 .htotal = 800 + 40 + 48 + 40,
960 .vsync_start = 480 + 13,
961 .vsync_end = 480 + 13 + 3,
962 .vtotal = 480 + 13 + 3 + 29,
965 static const struct panel_desc bananapi_s070wv20_ct16 = {
966 .modes = &bananapi_s070wv20_ct16_mode,
975 static const struct drm_display_mode boe_hv070wsa_mode = {
978 .hsync_start = 1024 + 30,
979 .hsync_end = 1024 + 30 + 30,
980 .htotal = 1024 + 30 + 30 + 30,
982 .vsync_start = 600 + 10,
983 .vsync_end = 600 + 10 + 10,
984 .vtotal = 600 + 10 + 10 + 10,
988 static const struct panel_desc boe_hv070wsa = {
989 .modes = &boe_hv070wsa_mode,
997 static const struct drm_display_mode boe_nv101wxmn51_modes[] = {
1001 .hsync_start = 1280 + 48,
1002 .hsync_end = 1280 + 48 + 32,
1003 .htotal = 1280 + 48 + 32 + 80,
1005 .vsync_start = 800 + 3,
1006 .vsync_end = 800 + 3 + 5,
1007 .vtotal = 800 + 3 + 5 + 24,
1013 .hsync_start = 1280 + 48,
1014 .hsync_end = 1280 + 48 + 32,
1015 .htotal = 1280 + 48 + 32 + 80,
1017 .vsync_start = 800 + 3,
1018 .vsync_end = 800 + 3 + 5,
1019 .vtotal = 800 + 3 + 5 + 24,
1024 static const struct panel_desc boe_nv101wxmn51 = {
1025 .modes = boe_nv101wxmn51_modes,
1026 .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes),
1039 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1042 .hsync_start = 480 + 5,
1043 .hsync_end = 480 + 5 + 5,
1044 .htotal = 480 + 5 + 5 + 40,
1046 .vsync_start = 272 + 8,
1047 .vsync_end = 272 + 8 + 8,
1048 .vtotal = 272 + 8 + 8 + 8,
1050 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1053 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1054 .modes = &cdtech_s043wq26h_ct7_mode,
1061 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1064 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1067 .hsync_start = 800 + 40,
1068 .hsync_end = 800 + 40 + 40,
1069 .htotal = 800 + 40 + 40 + 48,
1071 .vsync_start = 480 + 29,
1072 .vsync_end = 480 + 29 + 13,
1073 .vtotal = 480 + 29 + 13 + 3,
1075 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1078 static const struct panel_desc cdtech_s070wv95_ct16 = {
1079 .modes = &cdtech_s070wv95_ct16_mode,
1088 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1091 .hsync_start = 800 + 49,
1092 .hsync_end = 800 + 49 + 33,
1093 .htotal = 800 + 49 + 33 + 17,
1095 .vsync_start = 1280 + 1,
1096 .vsync_end = 1280 + 1 + 7,
1097 .vtotal = 1280 + 1 + 7 + 15,
1099 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1102 static const struct panel_desc chunghwa_claa070wp03xg = {
1103 .modes = &chunghwa_claa070wp03xg_mode,
1112 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1115 .hsync_start = 1366 + 58,
1116 .hsync_end = 1366 + 58 + 58,
1117 .htotal = 1366 + 58 + 58 + 58,
1119 .vsync_start = 768 + 4,
1120 .vsync_end = 768 + 4 + 4,
1121 .vtotal = 768 + 4 + 4 + 4,
1125 static const struct panel_desc chunghwa_claa101wa01a = {
1126 .modes = &chunghwa_claa101wa01a_mode,
1135 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1138 .hsync_start = 1366 + 48,
1139 .hsync_end = 1366 + 48 + 32,
1140 .htotal = 1366 + 48 + 32 + 20,
1142 .vsync_start = 768 + 16,
1143 .vsync_end = 768 + 16 + 8,
1144 .vtotal = 768 + 16 + 8 + 16,
1148 static const struct panel_desc chunghwa_claa101wb01 = {
1149 .modes = &chunghwa_claa101wb01_mode,
1158 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1161 .hsync_start = 800 + 40,
1162 .hsync_end = 800 + 40 + 128,
1163 .htotal = 800 + 40 + 128 + 88,
1165 .vsync_start = 480 + 10,
1166 .vsync_end = 480 + 10 + 2,
1167 .vtotal = 480 + 10 + 2 + 33,
1169 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1172 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1173 .modes = &dataimage_scf0700c48ggu18_mode,
1180 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1181 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1184 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1185 .pixelclock = { 45000000, 51200000, 57000000 },
1186 .hactive = { 1024, 1024, 1024 },
1187 .hfront_porch = { 100, 106, 113 },
1188 .hback_porch = { 100, 106, 113 },
1189 .hsync_len = { 100, 108, 114 },
1190 .vactive = { 600, 600, 600 },
1191 .vfront_porch = { 8, 11, 15 },
1192 .vback_porch = { 8, 11, 15 },
1193 .vsync_len = { 9, 13, 15 },
1194 .flags = DISPLAY_FLAGS_DE_HIGH,
1197 static const struct panel_desc dlc_dlc0700yzg_1 = {
1198 .timings = &dlc_dlc0700yzg_1_timing,
1210 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1211 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1214 static const struct display_timing dlc_dlc1010gig_timing = {
1215 .pixelclock = { 68900000, 71100000, 73400000 },
1216 .hactive = { 1280, 1280, 1280 },
1217 .hfront_porch = { 43, 53, 63 },
1218 .hback_porch = { 43, 53, 63 },
1219 .hsync_len = { 44, 54, 64 },
1220 .vactive = { 800, 800, 800 },
1221 .vfront_porch = { 5, 8, 11 },
1222 .vback_porch = { 5, 8, 11 },
1223 .vsync_len = { 5, 7, 11 },
1224 .flags = DISPLAY_FLAGS_DE_HIGH,
1227 static const struct panel_desc dlc_dlc1010gig = {
1228 .timings = &dlc_dlc1010gig_timing,
1241 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1242 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1245 static const struct drm_display_mode edt_et035012dm6_mode = {
1248 .hsync_start = 320 + 20,
1249 .hsync_end = 320 + 20 + 30,
1250 .htotal = 320 + 20 + 68,
1252 .vsync_start = 240 + 4,
1253 .vsync_end = 240 + 4 + 4,
1254 .vtotal = 240 + 4 + 4 + 14,
1256 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1259 static const struct panel_desc edt_et035012dm6 = {
1260 .modes = &edt_et035012dm6_mode,
1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1268 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1271 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1274 .hsync_start = 480 + 2,
1275 .hsync_end = 480 + 2 + 41,
1276 .htotal = 480 + 2 + 41 + 2,
1278 .vsync_start = 272 + 2,
1279 .vsync_end = 272 + 2 + 10,
1280 .vtotal = 272 + 2 + 10 + 2,
1282 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1285 static const struct panel_desc edt_etm0430g0dh6 = {
1286 .modes = &edt_etm0430g0dh6_mode,
1295 static const struct drm_display_mode edt_et057090dhu_mode = {
1298 .hsync_start = 640 + 16,
1299 .hsync_end = 640 + 16 + 30,
1300 .htotal = 640 + 16 + 30 + 114,
1302 .vsync_start = 480 + 10,
1303 .vsync_end = 480 + 10 + 3,
1304 .vtotal = 480 + 10 + 3 + 32,
1306 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1309 static const struct panel_desc edt_et057090dhu = {
1310 .modes = &edt_et057090dhu_mode,
1317 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1318 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1321 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1324 .hsync_start = 800 + 40,
1325 .hsync_end = 800 + 40 + 128,
1326 .htotal = 800 + 40 + 128 + 88,
1328 .vsync_start = 480 + 10,
1329 .vsync_end = 480 + 10 + 2,
1330 .vtotal = 480 + 10 + 2 + 33,
1332 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1335 static const struct panel_desc edt_etm0700g0dh6 = {
1336 .modes = &edt_etm0700g0dh6_mode,
1343 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1344 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1347 static const struct panel_desc edt_etm0700g0bdh6 = {
1348 .modes = &edt_etm0700g0dh6_mode,
1355 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1356 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1359 static const struct display_timing evervision_vgg804821_timing = {
1360 .pixelclock = { 27600000, 33300000, 50000000 },
1361 .hactive = { 800, 800, 800 },
1362 .hfront_porch = { 40, 66, 70 },
1363 .hback_porch = { 40, 67, 70 },
1364 .hsync_len = { 40, 67, 70 },
1365 .vactive = { 480, 480, 480 },
1366 .vfront_porch = { 6, 10, 10 },
1367 .vback_porch = { 7, 11, 11 },
1368 .vsync_len = { 7, 11, 11 },
1369 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1370 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1371 DISPLAY_FLAGS_SYNC_NEGEDGE,
1374 static const struct panel_desc evervision_vgg804821 = {
1375 .timings = &evervision_vgg804821_timing,
1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1386 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1389 .hsync_start = 800 + 168,
1390 .hsync_end = 800 + 168 + 64,
1391 .htotal = 800 + 168 + 64 + 88,
1393 .vsync_start = 480 + 37,
1394 .vsync_end = 480 + 37 + 2,
1395 .vtotal = 480 + 37 + 2 + 8,
1399 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1400 .modes = &foxlink_fl500wvr00_a0t_mode,
1407 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1410 static const struct drm_display_mode friendlyarm_hd702e_mode = {
1413 .hsync_start = 800 + 20,
1414 .hsync_end = 800 + 20 + 24,
1415 .htotal = 800 + 20 + 24 + 20,
1417 .vsync_start = 1280 + 4,
1418 .vsync_end = 1280 + 4 + 8,
1419 .vtotal = 1280 + 4 + 8 + 4,
1421 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1424 static const struct panel_desc friendlyarm_hd702e = {
1425 .modes = &friendlyarm_hd702e_mode,
1433 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1436 .hsync_start = 480 + 5,
1437 .hsync_end = 480 + 5 + 1,
1438 .htotal = 480 + 5 + 1 + 40,
1440 .vsync_start = 272 + 8,
1441 .vsync_end = 272 + 8 + 1,
1442 .vtotal = 272 + 8 + 1 + 8,
1446 static const struct panel_desc giantplus_gpg482739qs5 = {
1447 .modes = &giantplus_gpg482739qs5_mode,
1454 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1457 static const struct display_timing giantplus_gpm940b0_timing = {
1458 .pixelclock = { 13500000, 27000000, 27500000 },
1459 .hactive = { 320, 320, 320 },
1460 .hfront_porch = { 14, 686, 718 },
1461 .hback_porch = { 50, 70, 255 },
1462 .hsync_len = { 1, 1, 1 },
1463 .vactive = { 240, 240, 240 },
1464 .vfront_porch = { 1, 1, 179 },
1465 .vback_porch = { 1, 21, 31 },
1466 .vsync_len = { 1, 1, 6 },
1467 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1470 static const struct panel_desc giantplus_gpm940b0 = {
1471 .timings = &giantplus_gpm940b0_timing,
1478 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
1479 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
1482 static const struct display_timing hannstar_hsd070pww1_timing = {
1483 .pixelclock = { 64300000, 71100000, 82000000 },
1484 .hactive = { 1280, 1280, 1280 },
1485 .hfront_porch = { 1, 1, 10 },
1486 .hback_porch = { 1, 1, 10 },
1488 * According to the data sheet, the minimum horizontal blanking interval
1489 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1490 * minimum working horizontal blanking interval to be 60 clocks.
1492 .hsync_len = { 58, 158, 661 },
1493 .vactive = { 800, 800, 800 },
1494 .vfront_porch = { 1, 1, 10 },
1495 .vback_porch = { 1, 1, 10 },
1496 .vsync_len = { 1, 21, 203 },
1497 .flags = DISPLAY_FLAGS_DE_HIGH,
1500 static const struct panel_desc hannstar_hsd070pww1 = {
1501 .timings = &hannstar_hsd070pww1_timing,
1508 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1509 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1512 static const struct display_timing hannstar_hsd100pxn1_timing = {
1513 .pixelclock = { 55000000, 65000000, 75000000 },
1514 .hactive = { 1024, 1024, 1024 },
1515 .hfront_porch = { 40, 40, 40 },
1516 .hback_porch = { 220, 220, 220 },
1517 .hsync_len = { 20, 60, 100 },
1518 .vactive = { 768, 768, 768 },
1519 .vfront_porch = { 7, 7, 7 },
1520 .vback_porch = { 21, 21, 21 },
1521 .vsync_len = { 10, 10, 10 },
1522 .flags = DISPLAY_FLAGS_DE_HIGH,
1525 static const struct panel_desc hannstar_hsd100pxn1 = {
1526 .timings = &hannstar_hsd100pxn1_timing,
1533 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1534 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1537 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1540 .hsync_start = 800 + 85,
1541 .hsync_end = 800 + 85 + 86,
1542 .htotal = 800 + 85 + 86 + 85,
1544 .vsync_start = 480 + 16,
1545 .vsync_end = 480 + 16 + 13,
1546 .vtotal = 480 + 16 + 13 + 16,
1550 static const struct panel_desc hitachi_tx23d38vm0caa = {
1551 .modes = &hitachi_tx23d38vm0caa_mode,
1564 static const struct drm_display_mode innolux_at043tn24_mode = {
1567 .hsync_start = 480 + 2,
1568 .hsync_end = 480 + 2 + 41,
1569 .htotal = 480 + 2 + 41 + 2,
1571 .vsync_start = 272 + 2,
1572 .vsync_end = 272 + 2 + 10,
1573 .vtotal = 272 + 2 + 10 + 2,
1575 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1578 static const struct panel_desc innolux_at043tn24 = {
1579 .modes = &innolux_at043tn24_mode,
1586 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1587 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1590 static const struct drm_display_mode innolux_at070tn92_mode = {
1593 .hsync_start = 800 + 210,
1594 .hsync_end = 800 + 210 + 20,
1595 .htotal = 800 + 210 + 20 + 46,
1597 .vsync_start = 480 + 22,
1598 .vsync_end = 480 + 22 + 10,
1599 .vtotal = 480 + 22 + 23 + 10,
1603 static const struct panel_desc innolux_at070tn92 = {
1604 .modes = &innolux_at070tn92_mode,
1610 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1613 static const struct display_timing innolux_g070y2_l01_timing = {
1614 .pixelclock = { 28000000, 29500000, 32000000 },
1615 .hactive = { 800, 800, 800 },
1616 .hfront_porch = { 61, 91, 141 },
1617 .hback_porch = { 60, 90, 140 },
1618 .hsync_len = { 12, 12, 12 },
1619 .vactive = { 480, 480, 480 },
1620 .vfront_porch = { 4, 9, 30 },
1621 .vback_porch = { 4, 8, 28 },
1622 .vsync_len = { 2, 2, 2 },
1623 .flags = DISPLAY_FLAGS_DE_HIGH,
1626 static const struct panel_desc innolux_g070y2_l01 = {
1627 .timings = &innolux_g070y2_l01_timing,
1640 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1641 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1644 static const struct display_timing innolux_g101ice_l01_timing = {
1645 .pixelclock = { 60400000, 71100000, 74700000 },
1646 .hactive = { 1280, 1280, 1280 },
1647 .hfront_porch = { 41, 80, 100 },
1648 .hback_porch = { 40, 79, 99 },
1649 .hsync_len = { 1, 1, 1 },
1650 .vactive = { 800, 800, 800 },
1651 .vfront_porch = { 5, 11, 14 },
1652 .vback_porch = { 4, 11, 14 },
1653 .vsync_len = { 1, 1, 1 },
1654 .flags = DISPLAY_FLAGS_DE_HIGH,
1657 static const struct panel_desc innolux_g101ice_l01 = {
1658 .timings = &innolux_g101ice_l01_timing,
1669 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1670 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1673 static const struct display_timing innolux_g121i1_l01_timing = {
1674 .pixelclock = { 67450000, 71000000, 74550000 },
1675 .hactive = { 1280, 1280, 1280 },
1676 .hfront_porch = { 40, 80, 160 },
1677 .hback_porch = { 39, 79, 159 },
1678 .hsync_len = { 1, 1, 1 },
1679 .vactive = { 800, 800, 800 },
1680 .vfront_porch = { 5, 11, 100 },
1681 .vback_porch = { 4, 11, 99 },
1682 .vsync_len = { 1, 1, 1 },
1685 static const struct panel_desc innolux_g121i1_l01 = {
1686 .timings = &innolux_g121i1_l01_timing,
1697 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1698 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1701 static const struct drm_display_mode innolux_g121x1_l03_mode = {
1704 .hsync_start = 1024 + 0,
1705 .hsync_end = 1024 + 1,
1706 .htotal = 1024 + 0 + 1 + 320,
1708 .vsync_start = 768 + 38,
1709 .vsync_end = 768 + 38 + 1,
1710 .vtotal = 768 + 38 + 1 + 0,
1712 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1715 static const struct panel_desc innolux_g121x1_l03 = {
1716 .modes = &innolux_g121x1_l03_mode,
1731 * Datasheet specifies that at 60 Hz refresh rate:
1732 * - total horizontal time: { 1506, 1592, 1716 }
1733 * - total vertical time: { 788, 800, 868 }
1735 * ...but doesn't go into exactly how that should be split into a front
1736 * porch, back porch, or sync length. For now we'll leave a single setting
1737 * here which allows a bit of tweaking of the pixel clock at the expense of
1740 static const struct display_timing innolux_n116bge_timing = {
1741 .pixelclock = { 72600000, 76420000, 80240000 },
1742 .hactive = { 1366, 1366, 1366 },
1743 .hfront_porch = { 136, 136, 136 },
1744 .hback_porch = { 60, 60, 60 },
1745 .hsync_len = { 30, 30, 30 },
1746 .vactive = { 768, 768, 768 },
1747 .vfront_porch = { 8, 8, 8 },
1748 .vback_porch = { 12, 12, 12 },
1749 .vsync_len = { 12, 12, 12 },
1750 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
1753 static const struct panel_desc innolux_n116bge = {
1754 .timings = &innolux_n116bge_timing,
1763 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1766 .hsync_start = 1366 + 16,
1767 .hsync_end = 1366 + 16 + 34,
1768 .htotal = 1366 + 16 + 34 + 50,
1770 .vsync_start = 768 + 2,
1771 .vsync_end = 768 + 2 + 6,
1772 .vtotal = 768 + 2 + 6 + 12,
1776 static const struct panel_desc innolux_n156bge_l21 = {
1777 .modes = &innolux_n156bge_l21_mode,
1786 static const struct drm_display_mode innolux_p120zdg_bf1_mode = {
1789 .hsync_start = 2160 + 48,
1790 .hsync_end = 2160 + 48 + 32,
1791 .htotal = 2160 + 48 + 32 + 80,
1793 .vsync_start = 1440 + 3,
1794 .vsync_end = 1440 + 3 + 10,
1795 .vtotal = 1440 + 3 + 10 + 27,
1797 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
1800 static const struct panel_desc innolux_p120zdg_bf1 = {
1801 .modes = &innolux_p120zdg_bf1_mode,
1809 .hpd_absent_delay = 200,
1814 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1817 .hsync_start = 1024 + 128,
1818 .hsync_end = 1024 + 128 + 64,
1819 .htotal = 1024 + 128 + 64 + 128,
1821 .vsync_start = 600 + 16,
1822 .vsync_end = 600 + 16 + 4,
1823 .vtotal = 600 + 16 + 4 + 16,
1827 static const struct panel_desc innolux_zj070na_01p = {
1828 .modes = &innolux_zj070na_01p_mode,
1837 static const struct display_timing koe_tx14d24vm1bpa_timing = {
1838 .pixelclock = { 5580000, 5850000, 6200000 },
1839 .hactive = { 320, 320, 320 },
1840 .hfront_porch = { 30, 30, 30 },
1841 .hback_porch = { 30, 30, 30 },
1842 .hsync_len = { 1, 5, 17 },
1843 .vactive = { 240, 240, 240 },
1844 .vfront_porch = { 6, 6, 6 },
1845 .vback_porch = { 5, 5, 5 },
1846 .vsync_len = { 1, 2, 11 },
1847 .flags = DISPLAY_FLAGS_DE_HIGH,
1850 static const struct panel_desc koe_tx14d24vm1bpa = {
1851 .timings = &koe_tx14d24vm1bpa_timing,
1860 static const struct display_timing koe_tx31d200vm0baa_timing = {
1861 .pixelclock = { 39600000, 43200000, 48000000 },
1862 .hactive = { 1280, 1280, 1280 },
1863 .hfront_porch = { 16, 36, 56 },
1864 .hback_porch = { 16, 36, 56 },
1865 .hsync_len = { 8, 8, 8 },
1866 .vactive = { 480, 480, 480 },
1867 .vfront_porch = { 6, 21, 33 },
1868 .vback_porch = { 6, 21, 33 },
1869 .vsync_len = { 8, 8, 8 },
1870 .flags = DISPLAY_FLAGS_DE_HIGH,
1873 static const struct panel_desc koe_tx31d200vm0baa = {
1874 .timings = &koe_tx31d200vm0baa_timing,
1881 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1882 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1885 static const struct display_timing kyo_tcg121xglp_timing = {
1886 .pixelclock = { 52000000, 65000000, 71000000 },
1887 .hactive = { 1024, 1024, 1024 },
1888 .hfront_porch = { 2, 2, 2 },
1889 .hback_porch = { 2, 2, 2 },
1890 .hsync_len = { 86, 124, 244 },
1891 .vactive = { 768, 768, 768 },
1892 .vfront_porch = { 2, 2, 2 },
1893 .vback_porch = { 2, 2, 2 },
1894 .vsync_len = { 6, 34, 73 },
1895 .flags = DISPLAY_FLAGS_DE_HIGH,
1898 static const struct panel_desc kyo_tcg121xglp = {
1899 .timings = &kyo_tcg121xglp_timing,
1906 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1907 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1910 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
1913 .hsync_start = 320 + 20,
1914 .hsync_end = 320 + 20 + 30,
1915 .htotal = 320 + 20 + 30 + 38,
1917 .vsync_start = 240 + 4,
1918 .vsync_end = 240 + 4 + 3,
1919 .vtotal = 240 + 4 + 3 + 15,
1923 static const struct panel_desc lemaker_bl035_rgb_002 = {
1924 .modes = &lemaker_bl035_rgb_002_mode,
1930 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1931 .bus_flags = DRM_BUS_FLAG_DE_LOW,
1934 static const struct drm_display_mode lg_lb070wv8_mode = {
1937 .hsync_start = 800 + 88,
1938 .hsync_end = 800 + 88 + 80,
1939 .htotal = 800 + 88 + 80 + 88,
1941 .vsync_start = 480 + 10,
1942 .vsync_end = 480 + 10 + 25,
1943 .vtotal = 480 + 10 + 25 + 10,
1947 static const struct panel_desc lg_lb070wv8 = {
1948 .modes = &lg_lb070wv8_mode,
1955 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1956 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1959 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1962 .hsync_start = 1536 + 12,
1963 .hsync_end = 1536 + 12 + 16,
1964 .htotal = 1536 + 12 + 16 + 48,
1966 .vsync_start = 2048 + 8,
1967 .vsync_end = 2048 + 8 + 4,
1968 .vtotal = 2048 + 8 + 4 + 8,
1970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1973 static const struct panel_desc lg_lp079qx1_sp0v = {
1974 .modes = &lg_lp079qx1_sp0v_mode,
1982 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1985 .hsync_start = 2048 + 150,
1986 .hsync_end = 2048 + 150 + 5,
1987 .htotal = 2048 + 150 + 5 + 5,
1989 .vsync_start = 1536 + 3,
1990 .vsync_end = 1536 + 3 + 1,
1991 .vtotal = 1536 + 3 + 1 + 9,
1995 static const struct panel_desc lg_lp097qx1_spa1 = {
1996 .modes = &lg_lp097qx1_spa1_mode,
2004 static const struct drm_display_mode lg_lp120up1_mode = {
2007 .hsync_start = 1920 + 40,
2008 .hsync_end = 1920 + 40 + 40,
2009 .htotal = 1920 + 40 + 40+ 80,
2011 .vsync_start = 1280 + 4,
2012 .vsync_end = 1280 + 4 + 4,
2013 .vtotal = 1280 + 4 + 4 + 12,
2017 static const struct panel_desc lg_lp120up1 = {
2018 .modes = &lg_lp120up1_mode,
2027 static const struct drm_display_mode lg_lp129qe_mode = {
2030 .hsync_start = 2560 + 48,
2031 .hsync_end = 2560 + 48 + 32,
2032 .htotal = 2560 + 48 + 32 + 80,
2034 .vsync_start = 1700 + 3,
2035 .vsync_end = 1700 + 3 + 10,
2036 .vtotal = 1700 + 3 + 10 + 36,
2040 static const struct panel_desc lg_lp129qe = {
2041 .modes = &lg_lp129qe_mode,
2050 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2053 .hsync_start = 800 + 0,
2054 .hsync_end = 800 + 1,
2055 .htotal = 800 + 0 + 1 + 160,
2057 .vsync_start = 480 + 0,
2058 .vsync_end = 480 + 48 + 1,
2059 .vtotal = 480 + 48 + 1 + 0,
2061 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2064 static const struct panel_desc mitsubishi_aa070mc01 = {
2065 .modes = &mitsubishi_aa070mc01_mode,
2078 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2079 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2080 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2083 static const struct display_timing nec_nl12880bc20_05_timing = {
2084 .pixelclock = { 67000000, 71000000, 75000000 },
2085 .hactive = { 1280, 1280, 1280 },
2086 .hfront_porch = { 2, 30, 30 },
2087 .hback_porch = { 6, 100, 100 },
2088 .hsync_len = { 2, 30, 30 },
2089 .vactive = { 800, 800, 800 },
2090 .vfront_porch = { 5, 5, 5 },
2091 .vback_porch = { 11, 11, 11 },
2092 .vsync_len = { 7, 7, 7 },
2095 static const struct panel_desc nec_nl12880bc20_05 = {
2096 .timings = &nec_nl12880bc20_05_timing,
2107 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2108 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2111 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2114 .hsync_start = 480 + 2,
2115 .hsync_end = 480 + 2 + 41,
2116 .htotal = 480 + 2 + 41 + 2,
2118 .vsync_start = 272 + 2,
2119 .vsync_end = 272 + 2 + 4,
2120 .vtotal = 272 + 2 + 4 + 2,
2122 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2125 static const struct panel_desc nec_nl4827hc19_05b = {
2126 .modes = &nec_nl4827hc19_05b_mode,
2133 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2134 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2137 static const struct drm_display_mode netron_dy_e231732_mode = {
2140 .hsync_start = 1024 + 160,
2141 .hsync_end = 1024 + 160 + 70,
2142 .htotal = 1024 + 160 + 70 + 90,
2144 .vsync_start = 600 + 127,
2145 .vsync_end = 600 + 127 + 20,
2146 .vtotal = 600 + 127 + 20 + 3,
2150 static const struct panel_desc netron_dy_e231732 = {
2151 .modes = &netron_dy_e231732_mode,
2157 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2160 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
2163 .hsync_start = 480 + 2,
2164 .hsync_end = 480 + 2 + 41,
2165 .htotal = 480 + 2 + 41 + 2,
2167 .vsync_start = 272 + 2,
2168 .vsync_end = 272 + 2 + 10,
2169 .vtotal = 272 + 2 + 10 + 2,
2171 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2174 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
2175 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
2182 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2183 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2184 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2187 static const struct display_timing nlt_nl192108ac18_02d_timing = {
2188 .pixelclock = { 130000000, 148350000, 163000000 },
2189 .hactive = { 1920, 1920, 1920 },
2190 .hfront_porch = { 80, 100, 100 },
2191 .hback_porch = { 100, 120, 120 },
2192 .hsync_len = { 50, 60, 60 },
2193 .vactive = { 1080, 1080, 1080 },
2194 .vfront_porch = { 12, 30, 30 },
2195 .vback_porch = { 4, 10, 10 },
2196 .vsync_len = { 4, 5, 5 },
2199 static const struct panel_desc nlt_nl192108ac18_02d = {
2200 .timings = &nlt_nl192108ac18_02d_timing,
2210 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2211 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2214 static const struct drm_display_mode nvd_9128_mode = {
2217 .hsync_start = 800 + 130,
2218 .hsync_end = 800 + 130 + 98,
2219 .htotal = 800 + 0 + 130 + 98,
2221 .vsync_start = 480 + 10,
2222 .vsync_end = 480 + 10 + 50,
2223 .vtotal = 480 + 0 + 10 + 50,
2226 static const struct panel_desc nvd_9128 = {
2227 .modes = &nvd_9128_mode,
2234 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2235 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2238 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
2239 .pixelclock = { 30000000, 30000000, 40000000 },
2240 .hactive = { 800, 800, 800 },
2241 .hfront_porch = { 40, 40, 40 },
2242 .hback_porch = { 40, 40, 40 },
2243 .hsync_len = { 1, 48, 48 },
2244 .vactive = { 480, 480, 480 },
2245 .vfront_porch = { 13, 13, 13 },
2246 .vback_porch = { 29, 29, 29 },
2247 .vsync_len = { 3, 3, 3 },
2248 .flags = DISPLAY_FLAGS_DE_HIGH,
2251 static const struct panel_desc okaya_rs800480t_7x0gp = {
2252 .timings = &okaya_rs800480t_7x0gp_timing,
2265 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2268 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
2271 .hsync_start = 480 + 5,
2272 .hsync_end = 480 + 5 + 30,
2273 .htotal = 480 + 5 + 30 + 10,
2275 .vsync_start = 272 + 8,
2276 .vsync_end = 272 + 8 + 5,
2277 .vtotal = 272 + 8 + 5 + 3,
2281 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
2282 .modes = &olimex_lcd_olinuxino_43ts_mode,
2288 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2292 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
2293 * pixel clocks, but this is the timing that was being used in the Adafruit
2294 * installation instructions.
2296 static const struct drm_display_mode ontat_yx700wv03_mode = {
2307 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2312 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
2314 static const struct panel_desc ontat_yx700wv03 = {
2315 .modes = &ontat_yx700wv03_mode,
2322 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2325 static const struct drm_display_mode ortustech_com37h3m_mode = {
2328 .hsync_start = 480 + 8,
2329 .hsync_end = 480 + 8 + 10,
2330 .htotal = 480 + 8 + 10 + 10,
2332 .vsync_start = 640 + 4,
2333 .vsync_end = 640 + 4 + 3,
2334 .vtotal = 640 + 4 + 3 + 4,
2336 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2339 static const struct panel_desc ortustech_com37h3m = {
2340 .modes = &ortustech_com37h3m_mode,
2344 .width = 56, /* 56.16mm */
2345 .height = 75, /* 74.88mm */
2347 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2348 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2349 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2352 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
2355 .hsync_start = 480 + 10,
2356 .hsync_end = 480 + 10 + 10,
2357 .htotal = 480 + 10 + 10 + 15,
2359 .vsync_start = 800 + 3,
2360 .vsync_end = 800 + 3 + 3,
2361 .vtotal = 800 + 3 + 3 + 3,
2365 static const struct panel_desc ortustech_com43h4m85ulc = {
2366 .modes = &ortustech_com43h4m85ulc_mode,
2373 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2374 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2377 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
2380 .hsync_start = 800 + 210,
2381 .hsync_end = 800 + 210 + 30,
2382 .htotal = 800 + 210 + 30 + 16,
2384 .vsync_start = 480 + 22,
2385 .vsync_end = 480 + 22 + 13,
2386 .vtotal = 480 + 22 + 13 + 10,
2388 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2391 static const struct panel_desc osddisplays_osd070t1718_19ts = {
2392 .modes = &osddisplays_osd070t1718_19ts_mode,
2399 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2400 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2401 .connector_type = DRM_MODE_CONNECTOR_DPI,
2404 static const struct drm_display_mode pda_91_00156_a0_mode = {
2407 .hsync_start = 800 + 1,
2408 .hsync_end = 800 + 1 + 64,
2409 .htotal = 800 + 1 + 64 + 64,
2411 .vsync_start = 480 + 1,
2412 .vsync_end = 480 + 1 + 23,
2413 .vtotal = 480 + 1 + 23 + 22,
2417 static const struct panel_desc pda_91_00156_a0 = {
2418 .modes = &pda_91_00156_a0_mode,
2424 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2428 static const struct drm_display_mode qd43003c0_40_mode = {
2431 .hsync_start = 480 + 8,
2432 .hsync_end = 480 + 8 + 4,
2433 .htotal = 480 + 8 + 4 + 39,
2435 .vsync_start = 272 + 4,
2436 .vsync_end = 272 + 4 + 10,
2437 .vtotal = 272 + 4 + 10 + 2,
2441 static const struct panel_desc qd43003c0_40 = {
2442 .modes = &qd43003c0_40_mode,
2449 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2452 static const struct display_timing rocktech_rk070er9427_timing = {
2453 .pixelclock = { 26400000, 33300000, 46800000 },
2454 .hactive = { 800, 800, 800 },
2455 .hfront_porch = { 16, 210, 354 },
2456 .hback_porch = { 46, 46, 46 },
2457 .hsync_len = { 1, 1, 1 },
2458 .vactive = { 480, 480, 480 },
2459 .vfront_porch = { 7, 22, 147 },
2460 .vback_porch = { 23, 23, 23 },
2461 .vsync_len = { 1, 1, 1 },
2462 .flags = DISPLAY_FLAGS_DE_HIGH,
2465 static const struct panel_desc rocktech_rk070er9427 = {
2466 .timings = &rocktech_rk070er9427_timing,
2479 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2482 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
2485 .hsync_start = 2560 + 48,
2486 .hsync_end = 2560 + 48 + 32,
2487 .htotal = 2560 + 48 + 32 + 80,
2489 .vsync_start = 1600 + 2,
2490 .vsync_end = 1600 + 2 + 5,
2491 .vtotal = 1600 + 2 + 5 + 57,
2495 static const struct panel_desc samsung_lsn122dl01_c01 = {
2496 .modes = &samsung_lsn122dl01_c01_mode,
2504 static const struct drm_display_mode samsung_ltn101nt05_mode = {
2507 .hsync_start = 1024 + 24,
2508 .hsync_end = 1024 + 24 + 136,
2509 .htotal = 1024 + 24 + 136 + 160,
2511 .vsync_start = 600 + 3,
2512 .vsync_end = 600 + 3 + 6,
2513 .vtotal = 600 + 3 + 6 + 61,
2517 static const struct panel_desc samsung_ltn101nt05 = {
2518 .modes = &samsung_ltn101nt05_mode,
2527 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
2530 .hsync_start = 1366 + 64,
2531 .hsync_end = 1366 + 64 + 48,
2532 .htotal = 1366 + 64 + 48 + 128,
2534 .vsync_start = 768 + 2,
2535 .vsync_end = 768 + 2 + 5,
2536 .vtotal = 768 + 2 + 5 + 17,
2540 static const struct panel_desc samsung_ltn140at29_301 = {
2541 .modes = &samsung_ltn140at29_301_mode,
2550 static const struct drm_display_mode sharp_ld_d5116z01b_mode = {
2553 .hsync_start = 1920 + 48,
2554 .hsync_end = 1920 + 48 + 32,
2555 .htotal = 1920 + 48 + 32 + 80,
2557 .vsync_start = 1280 + 3,
2558 .vsync_end = 1280 + 3 + 10,
2559 .vtotal = 1280 + 3 + 10 + 57,
2561 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2564 static const struct panel_desc sharp_ld_d5116z01b = {
2565 .modes = &sharp_ld_d5116z01b_mode,
2572 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2573 .bus_flags = DRM_BUS_FLAG_DATA_MSB_TO_LSB,
2576 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
2579 .hsync_start = 800 + 64,
2580 .hsync_end = 800 + 64 + 128,
2581 .htotal = 800 + 64 + 128 + 64,
2583 .vsync_start = 480 + 8,
2584 .vsync_end = 480 + 8 + 2,
2585 .vtotal = 480 + 8 + 2 + 35,
2587 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2590 static const struct panel_desc sharp_lq070y3dg3b = {
2591 .modes = &sharp_lq070y3dg3b_mode,
2595 .width = 152, /* 152.4mm */
2596 .height = 91, /* 91.4mm */
2598 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2599 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE |
2600 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
2603 static const struct drm_display_mode sharp_lq035q7db03_mode = {
2606 .hsync_start = 240 + 16,
2607 .hsync_end = 240 + 16 + 7,
2608 .htotal = 240 + 16 + 7 + 5,
2610 .vsync_start = 320 + 9,
2611 .vsync_end = 320 + 9 + 1,
2612 .vtotal = 320 + 9 + 1 + 7,
2616 static const struct panel_desc sharp_lq035q7db03 = {
2617 .modes = &sharp_lq035q7db03_mode,
2624 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2627 static const struct display_timing sharp_lq101k1ly04_timing = {
2628 .pixelclock = { 60000000, 65000000, 80000000 },
2629 .hactive = { 1280, 1280, 1280 },
2630 .hfront_porch = { 20, 20, 20 },
2631 .hback_porch = { 20, 20, 20 },
2632 .hsync_len = { 10, 10, 10 },
2633 .vactive = { 800, 800, 800 },
2634 .vfront_porch = { 4, 4, 4 },
2635 .vback_porch = { 4, 4, 4 },
2636 .vsync_len = { 4, 4, 4 },
2637 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
2640 static const struct panel_desc sharp_lq101k1ly04 = {
2641 .timings = &sharp_lq101k1ly04_timing,
2648 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
2649 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2652 static const struct display_timing sharp_lq123p1jx31_timing = {
2653 .pixelclock = { 252750000, 252750000, 266604720 },
2654 .hactive = { 2400, 2400, 2400 },
2655 .hfront_porch = { 48, 48, 48 },
2656 .hback_porch = { 80, 80, 84 },
2657 .hsync_len = { 32, 32, 32 },
2658 .vactive = { 1600, 1600, 1600 },
2659 .vfront_porch = { 3, 3, 3 },
2660 .vback_porch = { 33, 33, 120 },
2661 .vsync_len = { 10, 10, 10 },
2662 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
2665 static const struct panel_desc sharp_lq123p1jx31 = {
2666 .timings = &sharp_lq123p1jx31_timing,
2680 static const struct drm_display_mode sharp_lq150x1lg11_mode = {
2683 .hsync_start = 1024 + 168,
2684 .hsync_end = 1024 + 168 + 64,
2685 .htotal = 1024 + 168 + 64 + 88,
2687 .vsync_start = 768 + 37,
2688 .vsync_end = 768 + 37 + 2,
2689 .vtotal = 768 + 37 + 2 + 8,
2693 static const struct panel_desc sharp_lq150x1lg11 = {
2694 .modes = &sharp_lq150x1lg11_mode,
2701 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2704 static const struct display_timing sharp_ls020b1dd01d_timing = {
2705 .pixelclock = { 2000000, 4200000, 5000000 },
2706 .hactive = { 240, 240, 240 },
2707 .hfront_porch = { 66, 66, 66 },
2708 .hback_porch = { 1, 1, 1 },
2709 .hsync_len = { 1, 1, 1 },
2710 .vactive = { 160, 160, 160 },
2711 .vfront_porch = { 52, 52, 52 },
2712 .vback_porch = { 6, 6, 6 },
2713 .vsync_len = { 10, 10, 10 },
2714 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_LOW,
2717 static const struct panel_desc sharp_ls020b1dd01d = {
2718 .timings = &sharp_ls020b1dd01d_timing,
2725 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2726 .bus_flags = DRM_BUS_FLAG_DE_HIGH
2727 | DRM_BUS_FLAG_PIXDATA_NEGEDGE
2728 | DRM_BUS_FLAG_SHARP_SIGNALS,
2731 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
2734 .hsync_start = 800 + 1,
2735 .hsync_end = 800 + 1 + 64,
2736 .htotal = 800 + 1 + 64 + 64,
2738 .vsync_start = 480 + 1,
2739 .vsync_end = 480 + 1 + 23,
2740 .vtotal = 480 + 1 + 23 + 22,
2744 static const struct panel_desc shelly_sca07010_bfn_lnn = {
2745 .modes = &shelly_sca07010_bfn_lnn_mode,
2751 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2754 static const struct drm_display_mode starry_kr122ea0sra_mode = {
2757 .hsync_start = 1920 + 16,
2758 .hsync_end = 1920 + 16 + 16,
2759 .htotal = 1920 + 16 + 16 + 32,
2761 .vsync_start = 1200 + 15,
2762 .vsync_end = 1200 + 15 + 2,
2763 .vtotal = 1200 + 15 + 2 + 18,
2765 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2768 static const struct panel_desc starry_kr122ea0sra = {
2769 .modes = &starry_kr122ea0sra_mode,
2776 .prepare = 10 + 200,
2778 .unprepare = 10 + 500,
2782 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
2785 .hsync_start = 800 + 39,
2786 .hsync_end = 800 + 39 + 47,
2787 .htotal = 800 + 39 + 47 + 39,
2789 .vsync_start = 480 + 13,
2790 .vsync_end = 480 + 13 + 2,
2791 .vtotal = 480 + 13 + 2 + 29,
2795 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
2796 .modes = &tfc_s9700rtwv43tr_01b_mode,
2803 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
2807 static const struct display_timing tianma_tm070jdhg30_timing = {
2808 .pixelclock = { 62600000, 68200000, 78100000 },
2809 .hactive = { 1280, 1280, 1280 },
2810 .hfront_porch = { 15, 64, 159 },
2811 .hback_porch = { 5, 5, 5 },
2812 .hsync_len = { 1, 1, 256 },
2813 .vactive = { 800, 800, 800 },
2814 .vfront_porch = { 3, 40, 99 },
2815 .vback_porch = { 2, 2, 2 },
2816 .vsync_len = { 1, 1, 128 },
2817 .flags = DISPLAY_FLAGS_DE_HIGH,
2820 static const struct panel_desc tianma_tm070jdhg30 = {
2821 .timings = &tianma_tm070jdhg30_timing,
2828 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2829 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2832 static const struct display_timing tianma_tm070rvhg71_timing = {
2833 .pixelclock = { 27700000, 29200000, 39600000 },
2834 .hactive = { 800, 800, 800 },
2835 .hfront_porch = { 12, 40, 212 },
2836 .hback_porch = { 88, 88, 88 },
2837 .hsync_len = { 1, 1, 40 },
2838 .vactive = { 480, 480, 480 },
2839 .vfront_porch = { 1, 13, 88 },
2840 .vback_porch = { 32, 32, 32 },
2841 .vsync_len = { 1, 1, 3 },
2842 .flags = DISPLAY_FLAGS_DE_HIGH,
2845 static const struct panel_desc tianma_tm070rvhg71 = {
2846 .timings = &tianma_tm070rvhg71_timing,
2853 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2854 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2857 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
2861 .hsync_start = 320 + 50,
2862 .hsync_end = 320 + 50 + 6,
2863 .htotal = 320 + 50 + 6 + 38,
2865 .vsync_start = 240 + 3,
2866 .vsync_end = 240 + 3 + 1,
2867 .vtotal = 240 + 3 + 1 + 17,
2869 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2873 static const struct panel_desc ti_nspire_cx_lcd_panel = {
2874 .modes = ti_nspire_cx_lcd_mode,
2881 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2882 .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE,
2885 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
2889 .hsync_start = 320 + 6,
2890 .hsync_end = 320 + 6 + 6,
2891 .htotal = 320 + 6 + 6 + 6,
2893 .vsync_start = 240 + 0,
2894 .vsync_end = 240 + 0 + 1,
2895 .vtotal = 240 + 0 + 1 + 0,
2897 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2901 static const struct panel_desc ti_nspire_classic_lcd_panel = {
2902 .modes = ti_nspire_classic_lcd_mode,
2904 /* The grayscale panel has 8 bit for the color .. Y (black) */
2910 /* This is the grayscale bus format */
2911 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
2912 .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE,
2915 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
2918 .hsync_start = 1280 + 192,
2919 .hsync_end = 1280 + 192 + 128,
2920 .htotal = 1280 + 192 + 128 + 64,
2922 .vsync_start = 768 + 20,
2923 .vsync_end = 768 + 20 + 7,
2924 .vtotal = 768 + 20 + 7 + 3,
2928 static const struct panel_desc toshiba_lt089ac29000 = {
2929 .modes = &toshiba_lt089ac29000_mode,
2935 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2936 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2937 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2940 static const struct drm_display_mode tpk_f07a_0102_mode = {
2943 .hsync_start = 800 + 40,
2944 .hsync_end = 800 + 40 + 128,
2945 .htotal = 800 + 40 + 128 + 88,
2947 .vsync_start = 480 + 10,
2948 .vsync_end = 480 + 10 + 2,
2949 .vtotal = 480 + 10 + 2 + 33,
2953 static const struct panel_desc tpk_f07a_0102 = {
2954 .modes = &tpk_f07a_0102_mode,
2960 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2963 static const struct drm_display_mode tpk_f10a_0102_mode = {
2966 .hsync_start = 1024 + 176,
2967 .hsync_end = 1024 + 176 + 5,
2968 .htotal = 1024 + 176 + 5 + 88,
2970 .vsync_start = 600 + 20,
2971 .vsync_end = 600 + 20 + 5,
2972 .vtotal = 600 + 20 + 5 + 25,
2976 static const struct panel_desc tpk_f10a_0102 = {
2977 .modes = &tpk_f10a_0102_mode,
2985 static const struct display_timing urt_umsh_8596md_timing = {
2986 .pixelclock = { 33260000, 33260000, 33260000 },
2987 .hactive = { 800, 800, 800 },
2988 .hfront_porch = { 41, 41, 41 },
2989 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
2990 .hsync_len = { 71, 128, 128 },
2991 .vactive = { 480, 480, 480 },
2992 .vfront_porch = { 10, 10, 10 },
2993 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
2994 .vsync_len = { 2, 2, 2 },
2995 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
2996 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2999 static const struct panel_desc urt_umsh_8596md_lvds = {
3000 .timings = &urt_umsh_8596md_timing,
3007 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3008 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3011 static const struct panel_desc urt_umsh_8596md_parallel = {
3012 .timings = &urt_umsh_8596md_timing,
3019 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3022 static const struct drm_display_mode vl050_8048nt_c01_mode = {
3025 .hsync_start = 800 + 210,
3026 .hsync_end = 800 + 210 + 20,
3027 .htotal = 800 + 210 + 20 + 46,
3029 .vsync_start = 480 + 22,
3030 .vsync_end = 480 + 22 + 10,
3031 .vtotal = 480 + 22 + 10 + 23,
3033 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3036 static const struct panel_desc vl050_8048nt_c01 = {
3037 .modes = &vl050_8048nt_c01_mode,
3044 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3045 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE,
3048 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
3051 .hsync_start = 320 + 20,
3052 .hsync_end = 320 + 20 + 30,
3053 .htotal = 320 + 20 + 30 + 38,
3055 .vsync_start = 240 + 4,
3056 .vsync_end = 240 + 4 + 3,
3057 .vtotal = 240 + 4 + 3 + 15,
3059 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3062 static const struct panel_desc winstar_wf35ltiacd = {
3063 .modes = &winstar_wf35ltiacd_mode,
3070 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3073 static const struct drm_display_mode arm_rtsm_mode[] = {
3077 .hsync_start = 1024 + 24,
3078 .hsync_end = 1024 + 24 + 136,
3079 .htotal = 1024 + 24 + 136 + 160,
3081 .vsync_start = 768 + 3,
3082 .vsync_end = 768 + 3 + 6,
3083 .vtotal = 768 + 3 + 6 + 29,
3085 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3089 static const struct panel_desc arm_rtsm = {
3090 .modes = arm_rtsm_mode,
3097 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3100 static const struct of_device_id platform_of_match[] = {
3102 .compatible = "ampire,am-480272h3tmqw-t01h",
3103 .data = &ire_am_480272h3tmqw_t01h,
3105 .compatible = "ampire,am800480r3tmqwa1h",
3106 .data = &ire_am800480r3tmqwa1h,
3108 .compatible = "arm,rtsm-display",
3111 .compatible = "armadeus,st0700-adapt",
3112 .data = &armadeus_st0700_adapt,
3114 .compatible = "auo,b101aw03",
3115 .data = &auo_b101aw03,
3117 .compatible = "auo,b101ean01",
3118 .data = &auo_b101ean01,
3120 .compatible = "auo,b101xtn01",
3121 .data = &auo_b101xtn01,
3123 .compatible = "auo,b116xw03",
3124 .data = &auo_b116xw03,
3126 .compatible = "auo,b133htn01",
3127 .data = &auo_b133htn01,
3129 .compatible = "auo,b133xtn01",
3130 .data = &auo_b133xtn01,
3132 .compatible = "auo,g070vvn01",
3133 .data = &auo_g070vvn01,
3135 .compatible = "auo,g101evn010",
3136 .data = &auo_g101evn010,
3138 .compatible = "auo,g104sn02",
3139 .data = &auo_g104sn02,
3141 .compatible = "auo,g133han01",
3142 .data = &auo_g133han01,
3144 .compatible = "auo,g185han01",
3145 .data = &auo_g185han01,
3147 .compatible = "auo,p320hvn03",
3148 .data = &auo_p320hvn03,
3150 .compatible = "auo,t215hvn01",
3151 .data = &auo_t215hvn01,
3153 .compatible = "avic,tm070ddh03",
3154 .data = &avic_tm070ddh03,
3156 .compatible = "bananapi,s070wv20-ct16",
3157 .data = &bananapi_s070wv20_ct16,
3159 .compatible = "boe,hv070wsa-100",
3160 .data = &boe_hv070wsa
3162 .compatible = "boe,nv101wxmn51",
3163 .data = &boe_nv101wxmn51,
3165 .compatible = "cdtech,s043wq26h-ct7",
3166 .data = &cdtech_s043wq26h_ct7,
3168 .compatible = "cdtech,s070wv95-ct16",
3169 .data = &cdtech_s070wv95_ct16,
3171 .compatible = "chunghwa,claa070wp03xg",
3172 .data = &chunghwa_claa070wp03xg,
3174 .compatible = "chunghwa,claa101wa01a",
3175 .data = &chunghwa_claa101wa01a
3177 .compatible = "chunghwa,claa101wb01",
3178 .data = &chunghwa_claa101wb01
3180 .compatible = "dataimage,scf0700c48ggu18",
3181 .data = &dataimage_scf0700c48ggu18,
3183 .compatible = "dlc,dlc0700yzg-1",
3184 .data = &dlc_dlc0700yzg_1,
3186 .compatible = "dlc,dlc1010gig",
3187 .data = &dlc_dlc1010gig,
3189 .compatible = "edt,et035012dm6",
3190 .data = &edt_et035012dm6,
3192 .compatible = "edt,etm0430g0dh6",
3193 .data = &edt_etm0430g0dh6,
3195 .compatible = "edt,et057090dhu",
3196 .data = &edt_et057090dhu,
3198 .compatible = "edt,et070080dh6",
3199 .data = &edt_etm0700g0dh6,
3201 .compatible = "edt,etm0700g0dh6",
3202 .data = &edt_etm0700g0dh6,
3204 .compatible = "edt,etm0700g0bdh6",
3205 .data = &edt_etm0700g0bdh6,
3207 .compatible = "edt,etm0700g0edh6",
3208 .data = &edt_etm0700g0bdh6,
3210 .compatible = "evervision,vgg804821",
3211 .data = &evervision_vgg804821,
3213 .compatible = "foxlink,fl500wvr00-a0t",
3214 .data = &foxlink_fl500wvr00_a0t,
3216 .compatible = "friendlyarm,hd702e",
3217 .data = &friendlyarm_hd702e,
3219 .compatible = "giantplus,gpg482739qs5",
3220 .data = &giantplus_gpg482739qs5
3222 .compatible = "giantplus,gpm940b0",
3223 .data = &giantplus_gpm940b0,
3225 .compatible = "hannstar,hsd070pww1",
3226 .data = &hannstar_hsd070pww1,
3228 .compatible = "hannstar,hsd100pxn1",
3229 .data = &hannstar_hsd100pxn1,
3231 .compatible = "hit,tx23d38vm0caa",
3232 .data = &hitachi_tx23d38vm0caa
3234 .compatible = "innolux,at043tn24",
3235 .data = &innolux_at043tn24,
3237 .compatible = "innolux,at070tn92",
3238 .data = &innolux_at070tn92,
3240 .compatible = "innolux,g070y2-l01",
3241 .data = &innolux_g070y2_l01,
3243 .compatible = "innolux,g101ice-l01",
3244 .data = &innolux_g101ice_l01
3246 .compatible = "innolux,g121i1-l01",
3247 .data = &innolux_g121i1_l01
3249 .compatible = "innolux,g121x1-l03",
3250 .data = &innolux_g121x1_l03,
3252 .compatible = "innolux,n116bge",
3253 .data = &innolux_n116bge,
3255 .compatible = "innolux,n156bge-l21",
3256 .data = &innolux_n156bge_l21,
3258 .compatible = "innolux,p120zdg-bf1",
3259 .data = &innolux_p120zdg_bf1,
3261 .compatible = "innolux,zj070na-01p",
3262 .data = &innolux_zj070na_01p,
3264 .compatible = "koe,tx14d24vm1bpa",
3265 .data = &koe_tx14d24vm1bpa,
3267 .compatible = "koe,tx31d200vm0baa",
3268 .data = &koe_tx31d200vm0baa,
3270 .compatible = "kyo,tcg121xglp",
3271 .data = &kyo_tcg121xglp,
3273 .compatible = "lemaker,bl035-rgb-002",
3274 .data = &lemaker_bl035_rgb_002,
3276 .compatible = "lg,lb070wv8",
3277 .data = &lg_lb070wv8,
3279 .compatible = "lg,lp079qx1-sp0v",
3280 .data = &lg_lp079qx1_sp0v,
3282 .compatible = "lg,lp097qx1-spa1",
3283 .data = &lg_lp097qx1_spa1,
3285 .compatible = "lg,lp120up1",
3286 .data = &lg_lp120up1,
3288 .compatible = "lg,lp129qe",
3289 .data = &lg_lp129qe,
3291 .compatible = "mitsubishi,aa070mc01-ca1",
3292 .data = &mitsubishi_aa070mc01,
3294 .compatible = "nec,nl12880bc20-05",
3295 .data = &nec_nl12880bc20_05,
3297 .compatible = "nec,nl4827hc19-05b",
3298 .data = &nec_nl4827hc19_05b,
3300 .compatible = "netron-dy,e231732",
3301 .data = &netron_dy_e231732,
3303 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
3304 .data = &newhaven_nhd_43_480272ef_atxl,
3306 .compatible = "nlt,nl192108ac18-02d",
3307 .data = &nlt_nl192108ac18_02d,
3309 .compatible = "nvd,9128",
3312 .compatible = "okaya,rs800480t-7x0gp",
3313 .data = &okaya_rs800480t_7x0gp,
3315 .compatible = "olimex,lcd-olinuxino-43-ts",
3316 .data = &olimex_lcd_olinuxino_43ts,
3318 .compatible = "ontat,yx700wv03",
3319 .data = &ontat_yx700wv03,
3321 .compatible = "ortustech,com37h3m05dtc",
3322 .data = &ortustech_com37h3m,
3324 .compatible = "ortustech,com37h3m99dtc",
3325 .data = &ortustech_com37h3m,
3327 .compatible = "ortustech,com43h4m85ulc",
3328 .data = &ortustech_com43h4m85ulc,
3330 .compatible = "osddisplays,osd070t1718-19ts",
3331 .data = &osddisplays_osd070t1718_19ts,
3333 .compatible = "pda,91-00156-a0",
3334 .data = &pda_91_00156_a0,
3336 .compatible = "qiaodian,qd43003c0-40",
3337 .data = &qd43003c0_40,
3339 .compatible = "rocktech,rk070er9427",
3340 .data = &rocktech_rk070er9427,
3342 .compatible = "samsung,lsn122dl01-c01",
3343 .data = &samsung_lsn122dl01_c01,
3345 .compatible = "samsung,ltn101nt05",
3346 .data = &samsung_ltn101nt05,
3348 .compatible = "samsung,ltn140at29-301",
3349 .data = &samsung_ltn140at29_301,
3351 .compatible = "sharp,ld-d5116z01b",
3352 .data = &sharp_ld_d5116z01b,
3354 .compatible = "sharp,lq035q7db03",
3355 .data = &sharp_lq035q7db03,
3357 .compatible = "sharp,lq070y3dg3b",
3358 .data = &sharp_lq070y3dg3b,
3360 .compatible = "sharp,lq101k1ly04",
3361 .data = &sharp_lq101k1ly04,
3363 .compatible = "sharp,lq123p1jx31",
3364 .data = &sharp_lq123p1jx31,
3366 .compatible = "sharp,lq150x1lg11",
3367 .data = &sharp_lq150x1lg11,
3369 .compatible = "sharp,ls020b1dd01d",
3370 .data = &sharp_ls020b1dd01d,
3372 .compatible = "shelly,sca07010-bfn-lnn",
3373 .data = &shelly_sca07010_bfn_lnn,
3375 .compatible = "starry,kr122ea0sra",
3376 .data = &starry_kr122ea0sra,
3378 .compatible = "tfc,s9700rtwv43tr-01b",
3379 .data = &tfc_s9700rtwv43tr_01b,
3381 .compatible = "tianma,tm070jdhg30",
3382 .data = &tianma_tm070jdhg30,
3384 .compatible = "tianma,tm070rvhg71",
3385 .data = &tianma_tm070rvhg71,
3387 .compatible = "ti,nspire-cx-lcd-panel",
3388 .data = &ti_nspire_cx_lcd_panel,
3390 .compatible = "ti,nspire-classic-lcd-panel",
3391 .data = &ti_nspire_classic_lcd_panel,
3393 .compatible = "toshiba,lt089ac29000",
3394 .data = &toshiba_lt089ac29000,
3396 .compatible = "tpk,f07a-0102",
3397 .data = &tpk_f07a_0102,
3399 .compatible = "tpk,f10a-0102",
3400 .data = &tpk_f10a_0102,
3402 .compatible = "urt,umsh-8596md-t",
3403 .data = &urt_umsh_8596md_parallel,
3405 .compatible = "urt,umsh-8596md-1t",
3406 .data = &urt_umsh_8596md_parallel,
3408 .compatible = "urt,umsh-8596md-7t",
3409 .data = &urt_umsh_8596md_parallel,
3411 .compatible = "urt,umsh-8596md-11t",
3412 .data = &urt_umsh_8596md_lvds,
3414 .compatible = "urt,umsh-8596md-19t",
3415 .data = &urt_umsh_8596md_lvds,
3417 .compatible = "urt,umsh-8596md-20t",
3418 .data = &urt_umsh_8596md_parallel,
3420 .compatible = "vxt,vl050-8048nt-c01",
3421 .data = &vl050_8048nt_c01,
3423 .compatible = "winstar,wf35ltiacd",
3424 .data = &winstar_wf35ltiacd,
3429 MODULE_DEVICE_TABLE(of, platform_of_match);
3431 static int panel_simple_platform_probe(struct platform_device *pdev)
3433 const struct of_device_id *id;
3435 id = of_match_node(platform_of_match, pdev->dev.of_node);
3439 return panel_simple_probe(&pdev->dev, id->data);
3442 static int panel_simple_platform_remove(struct platform_device *pdev)
3444 return panel_simple_remove(&pdev->dev);
3447 static void panel_simple_platform_shutdown(struct platform_device *pdev)
3449 panel_simple_shutdown(&pdev->dev);
3452 static struct platform_driver panel_simple_platform_driver = {
3454 .name = "panel-simple",
3455 .of_match_table = platform_of_match,
3457 .probe = panel_simple_platform_probe,
3458 .remove = panel_simple_platform_remove,
3459 .shutdown = panel_simple_platform_shutdown,
3462 struct panel_desc_dsi {
3463 struct panel_desc desc;
3465 unsigned long flags;
3466 enum mipi_dsi_pixel_format format;
3470 static const struct drm_display_mode auo_b080uan01_mode = {
3473 .hsync_start = 1200 + 62,
3474 .hsync_end = 1200 + 62 + 4,
3475 .htotal = 1200 + 62 + 4 + 62,
3477 .vsync_start = 1920 + 9,
3478 .vsync_end = 1920 + 9 + 2,
3479 .vtotal = 1920 + 9 + 2 + 8,
3483 static const struct panel_desc_dsi auo_b080uan01 = {
3485 .modes = &auo_b080uan01_mode,
3493 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3494 .format = MIPI_DSI_FMT_RGB888,
3498 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
3501 .hsync_start = 1200 + 120,
3502 .hsync_end = 1200 + 120 + 20,
3503 .htotal = 1200 + 120 + 20 + 21,
3505 .vsync_start = 1920 + 21,
3506 .vsync_end = 1920 + 21 + 3,
3507 .vtotal = 1920 + 21 + 3 + 18,
3509 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3512 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
3514 .modes = &boe_tv080wum_nl0_mode,
3521 .flags = MIPI_DSI_MODE_VIDEO |
3522 MIPI_DSI_MODE_VIDEO_BURST |
3523 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
3524 .format = MIPI_DSI_FMT_RGB888,
3528 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
3531 .hsync_start = 800 + 32,
3532 .hsync_end = 800 + 32 + 1,
3533 .htotal = 800 + 32 + 1 + 57,
3535 .vsync_start = 1280 + 28,
3536 .vsync_end = 1280 + 28 + 1,
3537 .vtotal = 1280 + 28 + 1 + 14,
3541 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
3543 .modes = &lg_ld070wx3_sl01_mode,
3551 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
3552 .format = MIPI_DSI_FMT_RGB888,
3556 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
3559 .hsync_start = 720 + 12,
3560 .hsync_end = 720 + 12 + 4,
3561 .htotal = 720 + 12 + 4 + 112,
3563 .vsync_start = 1280 + 8,
3564 .vsync_end = 1280 + 8 + 4,
3565 .vtotal = 1280 + 8 + 4 + 12,
3569 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
3571 .modes = &lg_lh500wx1_sd03_mode,
3579 .flags = MIPI_DSI_MODE_VIDEO,
3580 .format = MIPI_DSI_FMT_RGB888,
3584 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
3587 .hsync_start = 1920 + 154,
3588 .hsync_end = 1920 + 154 + 16,
3589 .htotal = 1920 + 154 + 16 + 32,
3591 .vsync_start = 1200 + 17,
3592 .vsync_end = 1200 + 17 + 2,
3593 .vtotal = 1200 + 17 + 2 + 16,
3597 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
3599 .modes = &panasonic_vvx10f004b00_mode,
3607 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3608 MIPI_DSI_CLOCK_NON_CONTINUOUS,
3609 .format = MIPI_DSI_FMT_RGB888,
3613 static const struct drm_display_mode lg_acx467akm_7_mode = {
3616 .hsync_start = 1080 + 2,
3617 .hsync_end = 1080 + 2 + 2,
3618 .htotal = 1080 + 2 + 2 + 2,
3620 .vsync_start = 1920 + 2,
3621 .vsync_end = 1920 + 2 + 2,
3622 .vtotal = 1920 + 2 + 2 + 2,
3626 static const struct panel_desc_dsi lg_acx467akm_7 = {
3628 .modes = &lg_acx467akm_7_mode,
3637 .format = MIPI_DSI_FMT_RGB888,
3641 static const struct drm_display_mode osd101t2045_53ts_mode = {
3644 .hsync_start = 1920 + 112,
3645 .hsync_end = 1920 + 112 + 16,
3646 .htotal = 1920 + 112 + 16 + 32,
3648 .vsync_start = 1200 + 16,
3649 .vsync_end = 1200 + 16 + 2,
3650 .vtotal = 1200 + 16 + 2 + 16,
3652 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
3655 static const struct panel_desc_dsi osd101t2045_53ts = {
3657 .modes = &osd101t2045_53ts_mode,
3665 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
3666 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
3667 MIPI_DSI_MODE_EOT_PACKET,
3668 .format = MIPI_DSI_FMT_RGB888,
3672 static const struct of_device_id dsi_of_match[] = {
3674 .compatible = "auo,b080uan01",
3675 .data = &auo_b080uan01
3677 .compatible = "boe,tv080wum-nl0",
3678 .data = &boe_tv080wum_nl0
3680 .compatible = "lg,ld070wx3-sl01",
3681 .data = &lg_ld070wx3_sl01
3683 .compatible = "lg,lh500wx1-sd03",
3684 .data = &lg_lh500wx1_sd03
3686 .compatible = "panasonic,vvx10f004b00",
3687 .data = &panasonic_vvx10f004b00
3689 .compatible = "lg,acx467akm-7",
3690 .data = &lg_acx467akm_7
3692 .compatible = "osddisplays,osd101t2045-53ts",
3693 .data = &osd101t2045_53ts
3698 MODULE_DEVICE_TABLE(of, dsi_of_match);
3700 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
3702 const struct panel_desc_dsi *desc;
3703 const struct of_device_id *id;
3706 id = of_match_node(dsi_of_match, dsi->dev.of_node);
3712 err = panel_simple_probe(&dsi->dev, &desc->desc);
3716 dsi->mode_flags = desc->flags;
3717 dsi->format = desc->format;
3718 dsi->lanes = desc->lanes;
3720 err = mipi_dsi_attach(dsi);
3722 struct panel_simple *panel = dev_get_drvdata(&dsi->dev);
3724 drm_panel_remove(&panel->base);
3730 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
3734 err = mipi_dsi_detach(dsi);
3736 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
3738 return panel_simple_remove(&dsi->dev);
3741 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
3743 panel_simple_shutdown(&dsi->dev);
3746 static struct mipi_dsi_driver panel_simple_dsi_driver = {
3748 .name = "panel-simple-dsi",
3749 .of_match_table = dsi_of_match,
3751 .probe = panel_simple_dsi_probe,
3752 .remove = panel_simple_dsi_remove,
3753 .shutdown = panel_simple_dsi_shutdown,
3756 static int __init panel_simple_init(void)
3760 err = platform_driver_register(&panel_simple_platform_driver);
3764 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
3765 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
3772 module_init(panel_simple_init);
3774 static void __exit panel_simple_exit(void)
3776 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
3777 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
3779 platform_driver_unregister(&panel_simple_platform_driver);
3781 module_exit(panel_simple_exit);
3783 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
3784 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
3785 MODULE_LICENSE("GPL and additional rights");