drivers/gpu/drm/pl111/pl111_display.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved.
   4  *
   5  * Parts of this file were based on sources as follows:
   6  *
   7  * Copyright (c) 2006-2008 Intel Corporation
   8  * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
   9  * Copyright (C) 2011 Texas Instruments
  10  */
  11
  12 #include <linux/amba/clcd-regs.h>
  13 #include <linux/clk.h>
  14 #include <linux/delay.h>
  15 #include <linux/version.h>
  16 #include <linux/dma-buf.h>
  17 #include <linux/of_graph.h>
  18
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_fourcc.h>
  21 #include <drm/drm_gem_cma_helper.h>
  22 #include <drm/drm_gem_framebuffer_helper.h>
  23 #include <drm/drm_vblank.h>
  24
  25 #include "pl111_drm.h"
  26
  27 irqreturn_t pl111_irq(int irq, void *data)
  28 {
  29         struct pl111_drm_dev_private *priv = data;
  30         u32 irq_stat;
  31         irqreturn_t status = IRQ_NONE;
  32
  33         irq_stat = readl(priv->regs + CLCD_PL111_MIS);
  34
  35         if (!irq_stat)
  36                 return IRQ_NONE;
  37
  38         if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) {
  39                 drm_crtc_handle_vblank(&priv->pipe.crtc);
  40
  41                 status = IRQ_HANDLED;
  42         }
  43
  44         /* Clear the interrupt once done */
  45         writel(irq_stat, priv->regs + CLCD_PL111_ICR);
  46
  47         return status;
  48 }
  49
  50 static enum drm_mode_status
  51 pl111_mode_valid(struct drm_crtc *crtc,
  52                  const struct drm_display_mode *mode)
  53 {
  54         struct drm_device *drm = crtc->dev;
  55         struct pl111_drm_dev_private *priv = drm->dev_private;
  56         u32 cpp = priv->variant->fb_bpp / 8;
  57         u64 bw;
  58
  59         /*
  60          * We use the pixelclock to also account for interlaced modes, the
  61          * resulting bandwidth is in bytes per second.
  62          */
  63         bw = mode->clock * 1000ULL; /* In Hz */
  64         bw = bw * mode->hdisplay * mode->vdisplay * cpp;
  65         bw = div_u64(bw, mode->htotal * mode->vtotal);
  66
  67         /*
  68          * If no bandwidth constraints, anything goes, else
  69          * check if we are too fast.
  70          */
  71         if (priv->memory_bw && (bw > priv->memory_bw)) {
  72                 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n",
  73                               mode->hdisplay, mode->vdisplay,
  74                               mode->clock * 1000, cpp, bw);
  75
  76                 return MODE_BAD;
  77         }
  78         DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n",
  79                       mode->hdisplay, mode->vdisplay,
  80                       mode->clock * 1000, cpp, bw);
  81
  82         return MODE_OK;
  83 }
  84
  85 static int pl111_display_check(struct drm_simple_display_pipe *pipe,
  86                                struct drm_plane_state *pstate,
  87                                struct drm_crtc_state *cstate)
  88 {
  89         const struct drm_display_mode *mode = &cstate->mode;
  90         struct drm_framebuffer *old_fb = pipe->plane.state->fb;
  91         struct drm_framebuffer *fb = pstate->fb;
  92
  93         if (mode->hdisplay % 16)
  94                 return -EINVAL;
  95
  96         if (fb) {
  97                 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
  98
  99                 /* FB base address must be dword aligned. */
 100                 if (offset & 3)
 101                         return -EINVAL;
 102
 103                 /* There's no pitch register -- the mode's hdisplay
 104                  * controls it.
 105                  */
 106                 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0])
 107                         return -EINVAL;
 108
 109                 /* We can't change the FB format in a flicker-free
 110                  * manner (and only update it during CRTC enable).
 111                  */
 112                 if (old_fb && old_fb->format != fb->format)
 113                         cstate->mode_changed = true;
 114         }
 115
 116         return 0;
 117 }
 118
 119 static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
 120                                  struct drm_crtc_state *cstate,
 121                                  struct drm_plane_state *plane_state)
 122 {
 123         struct drm_crtc *crtc = &pipe->crtc;
 124         struct drm_plane *plane = &pipe->plane;
 125         struct drm_device *drm = crtc->dev;
 126         struct pl111_drm_dev_private *priv = drm->dev_private;
 127         const struct drm_display_mode *mode = &cstate->mode;
 128         struct drm_framebuffer *fb = plane->state->fb;
 129         struct drm_connector *connector = priv->connector;
 130         struct drm_bridge *bridge = priv->bridge;
 131         u32 cntl;
 132         u32 ppl, hsw, hfp, hbp;
 133         u32 lpp, vsw, vfp, vbp;
 134         u32 cpl, tim2;
 135         int ret;
 136
 137         ret = clk_set_rate(priv->clk, mode->clock * 1000);
 138         if (ret) {
 139                 dev_err(drm->dev,
 140                         "Failed to set pixel clock rate to %d: %d\n",
 141                         mode->clock * 1000, ret);
 142         }
 143
 144         clk_prepare_enable(priv->clk);
 145
 146         ppl = (mode->hdisplay / 16) - 1;
 147         hsw = mode->hsync_end - mode->hsync_start - 1;
 148         hfp = mode->hsync_start - mode->hdisplay - 1;
 149         hbp = mode->htotal - mode->hsync_end - 1;
 150
 151         lpp = mode->vdisplay - 1;
 152         vsw = mode->vsync_end - mode->vsync_start - 1;
 153         vfp = mode->vsync_start - mode->vdisplay;
 154         vbp = mode->vtotal - mode->vsync_end;
 155
 156         cpl = mode->hdisplay - 1;
 157
 158         writel((ppl << 2) |
 159                (hsw << 8) |
 160                (hfp << 16) |
 161                (hbp << 24),
 162                priv->regs + CLCD_TIM0);
 163         writel(lpp |
 164                (vsw << 10) |
 165                (vfp << 16) |
 166                (vbp << 24),
 167                priv->regs + CLCD_TIM1);
 168
 169         spin_lock(&priv->tim2_lock);
 170
 171         tim2 = readl(priv->regs + CLCD_TIM2);
 172         tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
 173
 174         if (priv->variant->broken_clockdivider)
 175                 tim2 |= TIM2_BCD;
 176
 177         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 178                 tim2 |= TIM2_IHS;
 179
 180         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 181                 tim2 |= TIM2_IVS;
 182
 183         if (connector) {
 184                 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
 185                         tim2 |= TIM2_IOE;
 186
 187                 if (connector->display_info.bus_flags &
 188                     DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 189                         tim2 |= TIM2_IPC;
 190         }
 191
 192         if (bridge) {
 193                 const struct drm_bridge_timings *btimings = bridge->timings;
 194
 195                 /*
 196                  * Here is when things get really fun. Sometimes the bridge
 197                  * timings are such that the signal out from PL11x is not
 198                  * stable before the receiving bridge (such as a dumb VGA DAC
 199                  * or similar) samples it. If that happens, we compensate by
 200                  * the only method we have: output the data on the opposite
 201                  * edge of the clock so it is for sure stable when it gets
 202                  * sampled.
 203                  *
 204                  * The PL111 manual does not contain proper timining diagrams
 205                  * or data for these details, but we know from experiments
 206                  * that the setup time is more than 3000 picoseconds (3 ns).
 207                  * If we have a bridge that requires the signal to be stable
 208                  * earlier than 3000 ps before the clock pulse, we have to
 209                  * output the data on the opposite edge to avoid flicker.
 210                  */
 211                 if (btimings && btimings->setup_time_ps >= 3000)
 212                         tim2 ^= TIM2_IPC;
 213         }
 214
 215         tim2 |= cpl << 16;
 216         writel(tim2, priv->regs + CLCD_TIM2);
 217         spin_unlock(&priv->tim2_lock);
 218
 219         writel(0, priv->regs + CLCD_TIM3);
 220
 221         /* Hard-code TFT panel */
 222         cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1);
 223         /* On the ST Micro variant, assume all 24 bits are connected */
 224         if (priv->variant->st_bitmux_control)
 225                 cntl |= CNTL_ST_CDWID_24;
 226
 227         /*
 228          * Note that the the ARM hardware's format reader takes 'r' from
 229          * the low bit, while DRM formats list channels from high bit
 230          * to low bit as you read left to right. The ST Micro version of
 231          * the PL110 (LCDC) however uses the standard DRM format.
 232          */
 233         switch (fb->format->format) {
 234         case DRM_FORMAT_BGR888:
 235                 /* Only supported on the ST Micro variant */
 236                 if (priv->variant->st_bitmux_control)
 237                         cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR;
 238                 break;
 239         case DRM_FORMAT_RGB888:
 240                 /* Only supported on the ST Micro variant */
 241                 if (priv->variant->st_bitmux_control)
 242                         cntl |= CNTL_ST_LCDBPP24_PACKED;
 243                 break;
 244         case DRM_FORMAT_ABGR8888:
 245         case DRM_FORMAT_XBGR8888:
 246                 if (priv->variant->st_bitmux_control)
 247                         cntl |= CNTL_LCDBPP24 | CNTL_BGR;
 248                 else
 249                         cntl |= CNTL_LCDBPP24;
 250                 break;
 251         case DRM_FORMAT_ARGB8888:
 252         case DRM_FORMAT_XRGB8888:
 253                 if (priv->variant->st_bitmux_control)
 254                         cntl |= CNTL_LCDBPP24;
 255                 else
 256                         cntl |= CNTL_LCDBPP24 | CNTL_BGR;
 257                 break;
 258         case DRM_FORMAT_BGR565:
 259                 if (priv->variant->is_pl110)
 260                         cntl |= CNTL_LCDBPP16;
 261                 else if (priv->variant->st_bitmux_control)
 262                         cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR;
 263                 else
 264                         cntl |= CNTL_LCDBPP16_565;
 265                 break;
 266         case DRM_FORMAT_RGB565:
 267                 if (priv->variant->is_pl110)
 268                         cntl |= CNTL_LCDBPP16 | CNTL_BGR;
 269                 else if (priv->variant->st_bitmux_control)
 270                         cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565;
 271                 else
 272                         cntl |= CNTL_LCDBPP16_565 | CNTL_BGR;
 273                 break;
 274         case DRM_FORMAT_ABGR1555:
 275         case DRM_FORMAT_XBGR1555:
 276                 cntl |= CNTL_LCDBPP16;
 277                 if (priv->variant->st_bitmux_control)
 278                         cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR;
 279                 break;
 280         case DRM_FORMAT_ARGB1555:
 281         case DRM_FORMAT_XRGB1555:
 282                 cntl |= CNTL_LCDBPP16;
 283                 if (priv->variant->st_bitmux_control)
 284                         cntl |= CNTL_ST_1XBPP_5551;
 285                 else
 286                         cntl |= CNTL_BGR;
 287                 break;
 288         case DRM_FORMAT_ABGR4444:
 289         case DRM_FORMAT_XBGR4444:
 290                 cntl |= CNTL_LCDBPP16_444;
 291                 if (priv->variant->st_bitmux_control)
 292                         cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR;
 293                 break;
 294         case DRM_FORMAT_ARGB4444:
 295         case DRM_FORMAT_XRGB4444:
 296                 cntl |= CNTL_LCDBPP16_444;
 297                 if (priv->variant->st_bitmux_control)
 298                         cntl |= CNTL_ST_1XBPP_444;
 299                 else
 300                         cntl |= CNTL_BGR;
 301                 break;
 302         default:
 303                 WARN_ONCE(true, "Unknown FB format 0x%08x\n",
 304                           fb->format->format);
 305                 break;
 306         }
 307
 308         /* The PL110 in Integrator/Versatile does the BGR routing externally */
 309         if (priv->variant->external_bgr)
 310                 cntl &= ~CNTL_BGR;
 311
 312         /* Power sequence: first enable and chill */
 313         writel(cntl, priv->regs + priv->ctrl);
 314
 315         /*
 316          * We expect this delay to stabilize the contrast
 317          * voltage Vee as stipulated by the manual
 318          */
 319         msleep(20);
 320
 321         if (priv->variant_display_enable)
 322                 priv->variant_display_enable(drm, fb->format->format);
 323
 324         /* Power Up */
 325         cntl |= CNTL_LCDPWR;
 326         writel(cntl, priv->regs + priv->ctrl);
 327
 328         if (!priv->variant->broken_vblank)
 329                 drm_crtc_vblank_on(crtc);
 330 }
 331
 332 void pl111_display_disable(struct drm_simple_display_pipe *pipe)
 333 {
 334         struct drm_crtc *crtc = &pipe->crtc;
 335         struct drm_device *drm = crtc->dev;
 336         struct pl111_drm_dev_private *priv = drm->dev_private;
 337         u32 cntl;
 338
 339         if (!priv->variant->broken_vblank)
 340                 drm_crtc_vblank_off(crtc);
 341
 342         /* Power Down */
 343         cntl = readl(priv->regs + priv->ctrl);
 344         if (cntl & CNTL_LCDPWR) {
 345                 cntl &= ~CNTL_LCDPWR;
 346                 writel(cntl, priv->regs + priv->ctrl);
 347         }
 348
 349         /*
 350          * We expect this delay to stabilize the contrast voltage Vee as
 351          * stipulated by the manual
 352          */
 353         msleep(20);
 354
 355         if (priv->variant_display_disable)
 356                 priv->variant_display_disable(drm);
 357
 358         /* Disable */
 359         writel(0, priv->regs + priv->ctrl);
 360
 361         clk_disable_unprepare(priv->clk);
 362 }
 363
 364 static void pl111_display_update(struct drm_simple_display_pipe *pipe,
 365                                  struct drm_plane_state *old_pstate)
 366 {
 367         struct drm_crtc *crtc = &pipe->crtc;
 368         struct drm_device *drm = crtc->dev;
 369         struct pl111_drm_dev_private *priv = drm->dev_private;
 370         struct drm_pending_vblank_event *event = crtc->state->event;
 371         struct drm_plane *plane = &pipe->plane;
 372         struct drm_plane_state *pstate = plane->state;
 373         struct drm_framebuffer *fb = pstate->fb;
 374
 375         if (fb) {
 376                 u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0);
 377
 378                 writel(addr, priv->regs + CLCD_UBAS);
 379         }
 380
 381         if (event) {
 382                 crtc->state->event = NULL;
 383
 384                 spin_lock_irq(&crtc->dev->event_lock);
 385                 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
 386                         drm_crtc_arm_vblank_event(crtc, event);
 387                 else
 388                         drm_crtc_send_vblank_event(crtc, event);
 389                 spin_unlock_irq(&crtc->dev->event_lock);
 390         }
 391 }
 392
 393 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe)
 394 {
 395         struct drm_crtc *crtc = &pipe->crtc;
 396         struct drm_device *drm = crtc->dev;
 397         struct pl111_drm_dev_private *priv = drm->dev_private;
 398
 399         writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb);
 400
 401         return 0;
 402 }
 403
 404 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe)
 405 {
 406         struct drm_crtc *crtc = &pipe->crtc;
 407         struct drm_device *drm = crtc->dev;
 408         struct pl111_drm_dev_private *priv = drm->dev_private;
 409
 410         writel(0, priv->regs + priv->ienb);
 411 }
 412
 413 static struct drm_simple_display_pipe_funcs pl111_display_funcs = {
 414         .mode_valid = pl111_mode_valid,
 415         .check = pl111_display_check,
 416         .enable = pl111_display_enable,
 417         .disable = pl111_display_disable,
 418         .update = pl111_display_update,
 419         .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
 420 };
 421
 422 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
 423                                     unsigned long *prate, bool set_parent)
 424 {
 425         int best_div = 1, div;
 426         struct clk_hw *parent = clk_hw_get_parent(hw);
 427         unsigned long best_prate = 0;
 428         unsigned long best_diff = ~0ul;
 429         int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1;
 430
 431         for (div = 1; div < max_div; div++) {
 432                 unsigned long this_prate, div_rate, diff;
 433
 434                 if (set_parent)
 435                         this_prate = clk_hw_round_rate(parent, rate * div);
 436                 else
 437                         this_prate = *prate;
 438                 div_rate = DIV_ROUND_UP_ULL(this_prate, div);
 439                 diff = abs(rate - div_rate);
 440
 441                 if (diff < best_diff) {
 442                         best_div = div;
 443                         best_diff = diff;
 444                         best_prate = this_prate;
 445                 }
 446         }
 447
 448         *prate = best_prate;
 449         return best_div;
 450 }
 451
 452 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
 453                                      unsigned long *prate)
 454 {
 455         int div = pl111_clk_div_choose_div(hw, rate, prate, true);
 456
 457         return DIV_ROUND_UP_ULL(*prate, div);
 458 }
 459
 460 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw,
 461                                                unsigned long prate)
 462 {
 463         struct pl111_drm_dev_private *priv =
 464                 container_of(hw, struct pl111_drm_dev_private, clk_div);
 465         u32 tim2 = readl(priv->regs + CLCD_TIM2);
 466         int div;
 467
 468         if (tim2 & TIM2_BCD)
 469                 return prate;
 470
 471         div = tim2 & TIM2_PCD_LO_MASK;
 472         div |= (tim2 & TIM2_PCD_HI_MASK) >>
 473                 (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS);
 474         div += 2;
 475
 476         return DIV_ROUND_UP_ULL(prate, div);
 477 }
 478
 479 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
 480                                   unsigned long prate)
 481 {
 482         struct pl111_drm_dev_private *priv =
 483                 container_of(hw, struct pl111_drm_dev_private, clk_div);
 484         int div = pl111_clk_div_choose_div(hw, rate, &prate, false);
 485         u32 tim2;
 486
 487         spin_lock(&priv->tim2_lock);
 488         tim2 = readl(priv->regs + CLCD_TIM2);
 489         tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
 490
 491         if (div == 1) {
 492                 tim2 |= TIM2_BCD;
 493         } else {
 494                 div -= 2;
 495                 tim2 |= div & TIM2_PCD_LO_MASK;
 496                 tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT;
 497         }
 498
 499         writel(tim2, priv->regs + CLCD_TIM2);
 500         spin_unlock(&priv->tim2_lock);
 501
 502         return 0;
 503 }
 504
 505 static const struct clk_ops pl111_clk_div_ops = {
 506         .recalc_rate = pl111_clk_div_recalc_rate,
 507         .round_rate = pl111_clk_div_round_rate,
 508         .set_rate = pl111_clk_div_set_rate,
 509 };
 510
 511 static int
 512 pl111_init_clock_divider(struct drm_device *drm)
 513 {
 514         struct pl111_drm_dev_private *priv = drm->dev_private;
 515         struct clk *parent = devm_clk_get(drm->dev, "clcdclk");
 516         struct clk_hw *div = &priv->clk_div;
 517         const char *parent_name;
 518         struct clk_init_data init = {
 519                 .name = "pl111_div",
 520                 .ops = &pl111_clk_div_ops,
 521                 .parent_names = &parent_name,
 522                 .num_parents = 1,
 523                 .flags = CLK_SET_RATE_PARENT,
 524         };
 525         int ret;
 526
 527         if (IS_ERR(parent)) {
 528                 dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
 529                 return PTR_ERR(parent);
 530         }
 531
 532         spin_lock_init(&priv->tim2_lock);
 533
 534         /* If the clock divider is broken, use the parent directly */
 535         if (priv->variant->broken_clockdivider) {
 536                 priv->clk = parent;
 537                 return 0;
 538         }
 539         parent_name = __clk_get_name(parent);
 540         div->init = &init;
 541
 542         ret = devm_clk_hw_register(drm->dev, div);
 543
 544         priv->clk = div->clk;
 545         return ret;
 546 }
 547
 548 int pl111_display_init(struct drm_device *drm)
 549 {
 550         struct pl111_drm_dev_private *priv = drm->dev_private;
 551         struct device *dev = drm->dev;
 552         struct device_node *endpoint;
 553         u32 tft_r0b0g0[3];
 554         int ret;
 555
 556         endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
 557         if (!endpoint)
 558                 return -ENODEV;
 559
 560         if (of_property_read_u32_array(endpoint,
 561                                        "arm,pl11x,tft-r0g0b0-pads",
 562                                        tft_r0b0g0,
 563                                        ARRAY_SIZE(tft_r0b0g0)) != 0) {
 564                 dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n");
 565                 of_node_put(endpoint);
 566                 return -ENOENT;
 567         }
 568         of_node_put(endpoint);
 569
 570         ret = pl111_init_clock_divider(drm);
 571         if (ret)
 572                 return ret;
 573
 574         if (!priv->variant->broken_vblank) {
 575                 pl111_display_funcs.enable_vblank = pl111_display_enable_vblank;
 576                 pl111_display_funcs.disable_vblank = pl111_display_disable_vblank;
 577         }
 578
 579         ret = drm_simple_display_pipe_init(drm, &priv->pipe,
 580                                            &pl111_display_funcs,
 581                                            priv->variant->formats,
 582                                            priv->variant->nformats,
 583                                            NULL,
 584                                            priv->connector);
 585         if (ret)
 586                 return ret;
 587
 588         return 0;
 589 }