2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/radeon_drm.h>
30 #include <drm/drm_fixed.h>
33 #include "atom-bits.h"
35 static void atombios_overscan_setup(struct drm_crtc *crtc,
36 struct drm_display_mode *mode,
37 struct drm_display_mode *adjusted_mode)
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
46 memset(&args, 0, sizeof(args));
48 args.ucCRTC = radeon_crtc->crtc_id;
50 switch (radeon_crtc->rmx_type) {
52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
80 static void atombios_scaler_setup(struct drm_crtc *crtc)
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
85 ENABLE_SCALER_PS_ALLOCATION args;
86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 struct radeon_encoder *radeon_encoder =
88 to_radeon_encoder(radeon_crtc->encoder);
89 /* fixme - fill in enc_priv for atom dac */
90 enum radeon_tv_std tv_std = TV_STD_NTSC;
91 bool is_tv = false, is_cv = false;
93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
98 tv_std = tv_dac->tv_std;
102 memset(&args, 0, sizeof(args));
104 args.ucScaler = radeon_crtc->crtc_id;
110 args.ucTVStandard = ATOM_TV_NTSC;
113 args.ucTVStandard = ATOM_TV_PAL;
116 args.ucTVStandard = ATOM_TV_PALM;
119 args.ucTVStandard = ATOM_TV_PAL60;
122 args.ucTVStandard = ATOM_TV_NTSCJ;
124 case TV_STD_SCART_PAL:
125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
128 args.ucTVStandard = ATOM_TV_SECAM;
131 args.ucTVStandard = ATOM_TV_PALCN;
134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
136 args.ucTVStandard = ATOM_TV_CV;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
139 switch (radeon_crtc->rmx_type) {
141 args.ucEnable = ATOM_SCALER_EXPANSION;
144 args.ucEnable = ATOM_SCALER_CENTER;
147 args.ucEnable = ATOM_SCALER_EXPANSION;
150 if (ASIC_IS_AVIVO(rdev))
151 args.ucEnable = ATOM_SCALER_DISABLE;
153 args.ucEnable = ATOM_SCALER_CENTER;
157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
160 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 struct drm_device *dev = crtc->dev;
168 struct radeon_device *rdev = dev->dev_private;
170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
171 ENABLE_CRTC_PS_ALLOCATION args;
173 memset(&args, 0, sizeof(args));
175 args.ucCRTC = radeon_crtc->crtc_id;
176 args.ucEnable = lock;
178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
184 struct drm_device *dev = crtc->dev;
185 struct radeon_device *rdev = dev->dev_private;
186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
187 ENABLE_CRTC_PS_ALLOCATION args;
189 memset(&args, 0, sizeof(args));
191 args.ucCRTC = radeon_crtc->crtc_id;
192 args.ucEnable = state;
194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
200 struct drm_device *dev = crtc->dev;
201 struct radeon_device *rdev = dev->dev_private;
202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
203 ENABLE_CRTC_PS_ALLOCATION args;
205 memset(&args, 0, sizeof(args));
207 args.ucCRTC = radeon_crtc->crtc_id;
208 args.ucEnable = state;
210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
213 static const u32 vga_control_regs[6] =
217 EVERGREEN_D3VGA_CONTROL,
218 EVERGREEN_D4VGA_CONTROL,
219 EVERGREEN_D5VGA_CONTROL,
220 EVERGREEN_D6VGA_CONTROL,
223 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
229 BLANK_CRTC_PS_ALLOCATION args;
232 memset(&args, 0, sizeof(args));
234 if (ASIC_IS_DCE8(rdev)) {
235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
239 args.ucCRTC = radeon_crtc->crtc_id;
240 args.ucBlanking = state;
242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
244 if (ASIC_IS_DCE8(rdev)) {
245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
249 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
257 memset(&args, 0, sizeof(args));
259 args.ucDispPipeId = radeon_crtc->crtc_id;
260 args.ucEnable = state;
262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
265 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
267 struct drm_device *dev = crtc->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 case DRM_MODE_DPMS_ON:
273 radeon_crtc->enabled = true;
274 atombios_enable_crtc(crtc, ATOM_ENABLE);
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_vblank_on(dev, radeon_crtc->crtc_id);
280 radeon_crtc_load_lut(crtc);
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_vblank_off(dev, radeon_crtc->crtc_id);
287 if (radeon_crtc->enabled)
288 atombios_blank_crtc(crtc, ATOM_ENABLE);
289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
291 atombios_enable_crtc(crtc, ATOM_DISABLE);
292 radeon_crtc->enabled = false;
295 /* adjust pm to dpms */
296 radeon_pm_compute_clocks(rdev);
300 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
301 struct drm_display_mode *mode)
303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
304 struct drm_device *dev = crtc->dev;
305 struct radeon_device *rdev = dev->dev_private;
306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
310 memset(&args, 0, sizeof(args));
311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
312 args.usH_Blanking_Time =
313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
315 args.usV_Blanking_Time =
316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
317 args.usH_SyncOffset =
318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
321 args.usV_SyncOffset =
322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
325 args.ucH_Border = radeon_crtc->h_border;
326 args.ucV_Border = radeon_crtc->v_border;
328 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
329 misc |= ATOM_VSYNC_POLARITY;
330 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
331 misc |= ATOM_HSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_CSYNC)
333 misc |= ATOM_COMPOSITESYNC;
334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
335 misc |= ATOM_INTERLACE;
336 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337 misc |= ATOM_DOUBLE_CLOCK_MODE;
338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
342 args.ucCRTC = radeon_crtc->crtc_id;
344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
347 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
348 struct drm_display_mode *mode)
350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
357 memset(&args, 0, sizeof(args));
358 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
369 args.ucOverscanRight = radeon_crtc->h_border;
370 args.ucOverscanLeft = radeon_crtc->h_border;
371 args.ucOverscanBottom = radeon_crtc->v_border;
372 args.ucOverscanTop = radeon_crtc->v_border;
374 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
375 misc |= ATOM_VSYNC_POLARITY;
376 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
377 misc |= ATOM_HSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_CSYNC)
379 misc |= ATOM_COMPOSITESYNC;
380 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
381 misc |= ATOM_INTERLACE;
382 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383 misc |= ATOM_DOUBLE_CLOCK_MODE;
384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
388 args.ucCRTC = radeon_crtc->crtc_id;
390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
393 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
397 if (ASIC_IS_DCE4(rdev)) {
400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
410 case ATOM_PPLL_INVALID:
413 } else if (ASIC_IS_AVIVO(rdev)) {
416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
426 case ATOM_PPLL_INVALID:
433 union atom_enable_ss {
434 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
441 static void atombios_crtc_program_ss(struct radeon_device *rdev,
445 struct radeon_atom_ss *ss)
448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
449 union atom_enable_ss args;
452 /* Don't mess with SS if percentage is 0 or external ss.
453 * SS is already disabled previously, and disabling it
454 * again can cause display problems if the pll is already
457 if (ss->percentage == 0)
459 if (ss->type & ATOM_EXTERNAL_SS_MASK)
462 for (i = 0; i < rdev->num_crtc; i++) {
463 if (rdev->mode_info.crtcs[i] &&
464 rdev->mode_info.crtcs[i]->enabled &&
466 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
467 /* one other crtc is using this pll don't turn
468 * off spread spectrum as it might turn off
469 * display on active crtc
476 memset(&args, 0, sizeof(args));
478 if (ASIC_IS_DCE5(rdev)) {
479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
491 case ATOM_PPLL_INVALID:
494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
496 args.v3.ucEnable = enable;
497 } else if (ASIC_IS_DCE4(rdev)) {
498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
510 case ATOM_PPLL_INVALID:
513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
515 args.v2.ucEnable = enable;
516 } else if (ASIC_IS_DCE3(rdev)) {
517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519 args.v1.ucSpreadSpectrumStep = ss->step;
520 args.v1.ucSpreadSpectrumDelay = ss->delay;
521 args.v1.ucSpreadSpectrumRange = ss->range;
522 args.v1.ucPpll = pll_id;
523 args.v1.ucEnable = enable;
524 } else if (ASIC_IS_AVIVO(rdev)) {
525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
527 atombios_disable_ss(rdev, pll_id);
530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
535 args.lvds_ss_2.ucEnable = enable;
537 if (enable == ATOM_DISABLE) {
538 atombios_disable_ss(rdev, pll_id);
541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
545 args.lvds_ss.ucEnable = enable;
547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
550 union adjust_pixel_clock {
551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
555 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
556 struct drm_display_mode *mode)
558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
559 struct drm_device *dev = crtc->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct drm_encoder *encoder = radeon_crtc->encoder;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
564 u32 adjusted_clock = mode->clock;
565 int encoder_mode = atombios_get_encoder_mode(encoder);
566 u32 dp_clock = mode->clock;
567 u32 clock = mode->clock;
568 int bpc = radeon_crtc->bpc;
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
571 /* reset the pll flags */
572 radeon_crtc->pll_flags = 0;
574 if (ASIC_IS_AVIVO(rdev)) {
575 if ((rdev->family == CHIP_RS600) ||
576 (rdev->family == CHIP_RS690) ||
577 (rdev->family == CHIP_RS740))
578 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
579 RADEON_PLL_PREFER_CLOSEST_LOWER);
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
586 if (rdev->family < CHIP_RV770)
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
588 /* use frac fb div on APUs */
589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
591 /* use frac fb div on RS780/RS880 */
592 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
594 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
595 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
599 if (mode->clock > 200000) /* range limits??? */
600 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
602 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
605 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
606 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
608 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
609 struct radeon_connector_atom_dig *dig_connector =
610 radeon_connector->con_priv;
612 dp_clock = dig_connector->dp_clock;
616 if (radeon_encoder->is_mst_encoder) {
617 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
618 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
620 dp_clock = dig_connector->dp_clock;
623 /* use recommended ref_div for ss */
624 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
625 if (radeon_crtc->ss_enabled) {
626 if (radeon_crtc->ss.refdiv) {
627 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
628 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
629 if (ASIC_IS_AVIVO(rdev))
630 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
635 if (ASIC_IS_AVIVO(rdev)) {
636 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
637 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
638 adjusted_clock = mode->clock * 2;
639 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
640 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
641 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
642 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
644 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
645 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
646 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
647 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
650 /* adjust pll for deep color modes */
651 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
657 clock = (clock * 5) / 4;
660 clock = (clock * 3) / 2;
668 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
669 * accordingly based on the encoder/transmitter to work around
670 * special hw requirements.
672 if (ASIC_IS_DCE3(rdev)) {
673 union adjust_pixel_clock args;
677 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
678 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
680 return adjusted_clock;
682 memset(&args, 0, sizeof(args));
689 args.v1.usPixelClock = cpu_to_le16(clock / 10);
690 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
691 args.v1.ucEncodeMode = encoder_mode;
692 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
694 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
696 atom_execute_table(rdev->mode_info.atom_context,
697 index, (uint32_t *)&args);
698 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
701 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
702 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
703 args.v3.sInput.ucEncodeMode = encoder_mode;
704 args.v3.sInput.ucDispPllConfig = 0;
705 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
706 args.v3.sInput.ucDispPllConfig |=
707 DISPPLL_CONFIG_SS_ENABLE;
708 if (ENCODER_MODE_IS_DP(encoder_mode)) {
709 args.v3.sInput.ucDispPllConfig |=
710 DISPPLL_CONFIG_COHERENT_MODE;
712 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
713 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
714 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
715 if (dig->coherent_mode)
716 args.v3.sInput.ucDispPllConfig |=
717 DISPPLL_CONFIG_COHERENT_MODE;
719 args.v3.sInput.ucDispPllConfig |=
720 DISPPLL_CONFIG_DUAL_LINK;
722 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
723 ENCODER_OBJECT_ID_NONE)
724 args.v3.sInput.ucExtTransmitterID =
725 radeon_encoder_get_dp_bridge_encoder_id(encoder);
727 args.v3.sInput.ucExtTransmitterID = 0;
729 atom_execute_table(rdev->mode_info.atom_context,
730 index, (uint32_t *)&args);
731 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
732 if (args.v3.sOutput.ucRefDiv) {
733 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
734 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
735 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
737 if (args.v3.sOutput.ucPostDiv) {
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
740 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
744 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
745 return adjusted_clock;
749 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
750 return adjusted_clock;
753 return adjusted_clock;
756 union set_pixel_clock {
757 SET_PIXEL_CLOCK_PS_ALLOCATION base;
758 PIXEL_CLOCK_PARAMETERS v1;
759 PIXEL_CLOCK_PARAMETERS_V2 v2;
760 PIXEL_CLOCK_PARAMETERS_V3 v3;
761 PIXEL_CLOCK_PARAMETERS_V5 v5;
762 PIXEL_CLOCK_PARAMETERS_V6 v6;
765 /* on DCE5, make sure the voltage is high enough to support the
768 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
773 union set_pixel_clock args;
775 memset(&args, 0, sizeof(args));
777 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
778 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
786 /* if the default dcpll clock is specified,
787 * SetPixelClock provides the dividers
789 args.v5.ucCRTC = ATOM_CRTC_INVALID;
790 args.v5.usPixelClock = cpu_to_le16(dispclk);
791 args.v5.ucPpll = ATOM_DCPLL;
794 /* if the default dcpll clock is specified,
795 * SetPixelClock provides the dividers
797 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
798 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
799 args.v6.ucPpll = ATOM_EXT_PLL1;
800 else if (ASIC_IS_DCE6(rdev))
801 args.v6.ucPpll = ATOM_PPLL0;
803 args.v6.ucPpll = ATOM_DCPLL;
806 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
811 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
814 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
817 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
829 struct radeon_atom_ss *ss)
831 struct drm_device *dev = crtc->dev;
832 struct radeon_device *rdev = dev->dev_private;
834 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
835 union set_pixel_clock args;
837 memset(&args, 0, sizeof(args));
839 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
847 if (clock == ATOM_DISABLE)
849 args.v1.usPixelClock = cpu_to_le16(clock / 10);
850 args.v1.usRefDiv = cpu_to_le16(ref_div);
851 args.v1.usFbDiv = cpu_to_le16(fb_div);
852 args.v1.ucFracFbDiv = frac_fb_div;
853 args.v1.ucPostDiv = post_div;
854 args.v1.ucPpll = pll_id;
855 args.v1.ucCRTC = crtc_id;
856 args.v1.ucRefDivSrc = 1;
859 args.v2.usPixelClock = cpu_to_le16(clock / 10);
860 args.v2.usRefDiv = cpu_to_le16(ref_div);
861 args.v2.usFbDiv = cpu_to_le16(fb_div);
862 args.v2.ucFracFbDiv = frac_fb_div;
863 args.v2.ucPostDiv = post_div;
864 args.v2.ucPpll = pll_id;
865 args.v2.ucCRTC = crtc_id;
866 args.v2.ucRefDivSrc = 1;
869 args.v3.usPixelClock = cpu_to_le16(clock / 10);
870 args.v3.usRefDiv = cpu_to_le16(ref_div);
871 args.v3.usFbDiv = cpu_to_le16(fb_div);
872 args.v3.ucFracFbDiv = frac_fb_div;
873 args.v3.ucPostDiv = post_div;
874 args.v3.ucPpll = pll_id;
875 if (crtc_id == ATOM_CRTC2)
876 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
878 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
879 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
880 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
881 args.v3.ucTransmitterId = encoder_id;
882 args.v3.ucEncoderMode = encoder_mode;
885 args.v5.ucCRTC = crtc_id;
886 args.v5.usPixelClock = cpu_to_le16(clock / 10);
887 args.v5.ucRefDiv = ref_div;
888 args.v5.usFbDiv = cpu_to_le16(fb_div);
889 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
890 args.v5.ucPostDiv = post_div;
891 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
892 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
893 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
894 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
898 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
901 /* yes this is correct, the atom define is wrong */
902 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
905 /* yes this is correct, the atom define is wrong */
906 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
910 args.v5.ucTransmitterID = encoder_id;
911 args.v5.ucEncoderMode = encoder_mode;
912 args.v5.ucPpll = pll_id;
915 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
916 args.v6.ucRefDiv = ref_div;
917 args.v6.usFbDiv = cpu_to_le16(fb_div);
918 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
919 args.v6.ucPostDiv = post_div;
920 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
921 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
922 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
923 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
927 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
930 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
936 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
940 args.v6.ucTransmitterID = encoder_id;
941 args.v6.ucEncoderMode = encoder_mode;
942 args.v6.ucPpll = pll_id;
945 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
950 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
957 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
959 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
960 struct drm_device *dev = crtc->dev;
961 struct radeon_device *rdev = dev->dev_private;
962 struct radeon_encoder *radeon_encoder =
963 to_radeon_encoder(radeon_crtc->encoder);
964 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
966 radeon_crtc->bpc = 8;
967 radeon_crtc->ss_enabled = false;
969 if (radeon_encoder->is_mst_encoder) {
970 radeon_dp_mst_prepare_pll(crtc, mode);
971 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
972 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
973 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
974 struct drm_connector *connector =
975 radeon_get_connector_for_encoder(radeon_crtc->encoder);
976 struct radeon_connector *radeon_connector =
977 to_radeon_connector(connector);
978 struct radeon_connector_atom_dig *dig_connector =
979 radeon_connector->con_priv;
982 /* Assign mode clock for hdmi deep color max clock limit check */
983 radeon_connector->pixelclock_for_modeset = mode->clock;
984 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
986 switch (encoder_mode) {
987 case ATOM_ENCODER_MODE_DP_MST:
988 case ATOM_ENCODER_MODE_DP:
990 dp_clock = dig_connector->dp_clock / 10;
991 if (ASIC_IS_DCE4(rdev))
992 radeon_crtc->ss_enabled =
993 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
994 ASIC_INTERNAL_SS_ON_DP,
997 if (dp_clock == 16200) {
998 radeon_crtc->ss_enabled =
999 radeon_atombios_get_ppll_ss_info(rdev,
1002 if (!radeon_crtc->ss_enabled)
1003 radeon_crtc->ss_enabled =
1004 radeon_atombios_get_ppll_ss_info(rdev,
1008 radeon_crtc->ss_enabled =
1009 radeon_atombios_get_ppll_ss_info(rdev,
1013 /* disable spread spectrum on DCE3 DP */
1014 radeon_crtc->ss_enabled = false;
1017 case ATOM_ENCODER_MODE_LVDS:
1018 if (ASIC_IS_DCE4(rdev))
1019 radeon_crtc->ss_enabled =
1020 radeon_atombios_get_asic_ss_info(rdev,
1025 radeon_crtc->ss_enabled =
1026 radeon_atombios_get_ppll_ss_info(rdev,
1030 case ATOM_ENCODER_MODE_DVI:
1031 if (ASIC_IS_DCE4(rdev))
1032 radeon_crtc->ss_enabled =
1033 radeon_atombios_get_asic_ss_info(rdev,
1035 ASIC_INTERNAL_SS_ON_TMDS,
1038 case ATOM_ENCODER_MODE_HDMI:
1039 if (ASIC_IS_DCE4(rdev))
1040 radeon_crtc->ss_enabled =
1041 radeon_atombios_get_asic_ss_info(rdev,
1043 ASIC_INTERNAL_SS_ON_HDMI,
1051 /* adjust pixel clock as needed */
1052 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1057 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1059 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1060 struct drm_device *dev = crtc->dev;
1061 struct radeon_device *rdev = dev->dev_private;
1062 struct radeon_encoder *radeon_encoder =
1063 to_radeon_encoder(radeon_crtc->encoder);
1064 u32 pll_clock = mode->clock;
1065 u32 clock = mode->clock;
1066 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1067 struct radeon_pll *pll;
1068 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1070 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1071 if (ASIC_IS_DCE5(rdev) &&
1072 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1073 (radeon_crtc->bpc > 8))
1074 clock = radeon_crtc->adjusted_clock;
1076 switch (radeon_crtc->pll_id) {
1078 pll = &rdev->clock.p1pll;
1081 pll = &rdev->clock.p2pll;
1084 case ATOM_PPLL_INVALID:
1086 pll = &rdev->clock.dcpll;
1090 /* update pll params */
1091 pll->flags = radeon_crtc->pll_flags;
1092 pll->reference_div = radeon_crtc->pll_reference_div;
1093 pll->post_div = radeon_crtc->pll_post_div;
1095 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1096 /* TV seems to prefer the legacy algo on some boards */
1097 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1098 &fb_div, &frac_fb_div, &ref_div, &post_div);
1099 else if (ASIC_IS_AVIVO(rdev))
1100 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101 &fb_div, &frac_fb_div, &ref_div, &post_div);
1103 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1104 &fb_div, &frac_fb_div, &ref_div, &post_div);
1106 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1107 radeon_crtc->crtc_id, &radeon_crtc->ss);
1109 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1110 encoder_mode, radeon_encoder->encoder_id, clock,
1111 ref_div, fb_div, frac_fb_div, post_div,
1112 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1114 if (radeon_crtc->ss_enabled) {
1115 /* calculate ss amount and step size */
1116 if (ASIC_IS_DCE4(rdev)) {
1118 u32 amount = (((fb_div * 10) + frac_fb_div) *
1119 (u32)radeon_crtc->ss.percentage) /
1120 (100 * (u32)radeon_crtc->ss.percentage_divider);
1121 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1122 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1123 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1124 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1125 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1126 (125 * 25 * pll->reference_freq / 100);
1128 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1129 (125 * 25 * pll->reference_freq / 100);
1130 radeon_crtc->ss.step = step_size;
1133 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1134 radeon_crtc->crtc_id, &radeon_crtc->ss);
1138 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1139 struct drm_framebuffer *fb,
1140 int x, int y, int atomic)
1142 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1143 struct drm_device *dev = crtc->dev;
1144 struct radeon_device *rdev = dev->dev_private;
1145 struct radeon_framebuffer *radeon_fb;
1146 struct drm_framebuffer *target_fb;
1147 struct drm_gem_object *obj;
1148 struct radeon_bo *rbo;
1149 uint64_t fb_location;
1150 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1151 unsigned bankw, bankh, mtaspect, tile_split;
1152 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1153 u32 tmp, viewport_w, viewport_h;
1155 bool bypass_lut = false;
1158 if (!atomic && !crtc->primary->fb) {
1159 DRM_DEBUG_KMS("No FB bound\n");
1164 radeon_fb = to_radeon_framebuffer(fb);
1168 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1169 target_fb = crtc->primary->fb;
1172 /* If atomic, assume fb object is pinned & idle & fenced and
1173 * just update base pointers
1175 obj = radeon_fb->obj;
1176 rbo = gem_to_radeon_bo(obj);
1177 r = radeon_bo_reserve(rbo, false);
1178 if (unlikely(r != 0))
1182 fb_location = radeon_bo_gpu_offset(rbo);
1184 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1185 if (unlikely(r != 0)) {
1186 radeon_bo_unreserve(rbo);
1191 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1192 radeon_bo_unreserve(rbo);
1194 switch (target_fb->pixel_format) {
1196 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1197 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1199 case DRM_FORMAT_XRGB4444:
1200 case DRM_FORMAT_ARGB4444:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1207 case DRM_FORMAT_XRGB1555:
1208 case DRM_FORMAT_ARGB1555:
1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1215 case DRM_FORMAT_BGRX5551:
1216 case DRM_FORMAT_BGRA5551:
1217 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1218 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1220 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1223 case DRM_FORMAT_RGB565:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1230 case DRM_FORMAT_XRGB8888:
1231 case DRM_FORMAT_ARGB8888:
1232 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1233 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1235 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1238 case DRM_FORMAT_XRGB2101010:
1239 case DRM_FORMAT_ARGB2101010:
1240 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1241 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1243 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1245 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1248 case DRM_FORMAT_BGRX1010102:
1249 case DRM_FORMAT_BGRA1010102:
1250 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1251 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1253 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1255 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1259 DRM_ERROR("Unsupported screen format %s\n",
1260 drm_get_format_name(target_fb->pixel_format));
1264 if (tiling_flags & RADEON_TILING_MACRO) {
1265 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1267 /* Set NUM_BANKS. */
1268 if (rdev->family >= CHIP_TAHITI) {
1269 unsigned index, num_banks;
1271 if (rdev->family >= CHIP_BONAIRE) {
1272 unsigned tileb, tile_split_bytes;
1274 /* Calculate the macrotile mode index. */
1275 tile_split_bytes = 64 << tile_split;
1276 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1277 tileb = min(tile_split_bytes, tileb);
1279 for (index = 0; tileb > 64; index++)
1283 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1284 target_fb->bits_per_pixel, tile_split);
1288 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1290 switch (target_fb->bits_per_pixel) {
1295 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1299 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1303 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1306 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1309 if (rdev->family >= CHIP_CAYMAN)
1310 tmp = rdev->config.cayman.tile_config;
1312 tmp = rdev->config.evergreen.tile_config;
1314 switch ((tmp & 0xf0) >> 4) {
1315 case 0: /* 4 banks */
1316 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1318 case 1: /* 8 banks */
1320 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1322 case 2: /* 16 banks */
1323 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1328 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1329 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1330 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1331 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1332 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1333 if (rdev->family >= CHIP_BONAIRE) {
1334 /* XXX need to know more about the surface tiling mode */
1335 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1337 } else if (tiling_flags & RADEON_TILING_MICRO)
1338 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1340 if (rdev->family >= CHIP_BONAIRE) {
1341 /* Read the pipe config from the 2D TILED SCANOUT mode.
1342 * It should be the same for the other modes too, but not all
1343 * modes set the pipe config field. */
1344 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1346 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1347 } else if ((rdev->family == CHIP_TAHITI) ||
1348 (rdev->family == CHIP_PITCAIRN))
1349 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1350 else if ((rdev->family == CHIP_VERDE) ||
1351 (rdev->family == CHIP_OLAND) ||
1352 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1353 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1355 switch (radeon_crtc->crtc_id) {
1357 WREG32(AVIVO_D1VGA_CONTROL, 0);
1360 WREG32(AVIVO_D2VGA_CONTROL, 0);
1363 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1366 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1369 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1372 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1378 /* Make sure surface address is updated at vertical blank rather than
1381 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1383 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1384 upper_32_bits(fb_location));
1385 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1386 upper_32_bits(fb_location));
1387 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1388 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1389 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1390 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1391 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1392 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1395 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1396 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1397 * retain the full precision throughout the pipeline.
1399 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1400 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1401 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1404 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1406 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1407 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1408 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1409 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1410 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1411 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1413 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1414 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1415 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1417 if (rdev->family >= CHIP_BONAIRE)
1418 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1421 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1425 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1427 viewport_w = crtc->mode.hdisplay;
1428 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1429 if ((rdev->family >= CHIP_BONAIRE) &&
1430 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1432 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1433 (viewport_w << 16) | viewport_h);
1435 /* set pageflip to happen only at start of vblank interval (front porch) */
1436 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1438 if (!atomic && fb && fb != crtc->primary->fb) {
1439 radeon_fb = to_radeon_framebuffer(fb);
1440 rbo = gem_to_radeon_bo(radeon_fb->obj);
1441 r = radeon_bo_reserve(rbo, false);
1442 if (unlikely(r != 0))
1444 radeon_bo_unpin(rbo);
1445 radeon_bo_unreserve(rbo);
1448 /* Bytes per pixel may have changed */
1449 radeon_bandwidth_update(rdev);
1454 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1455 struct drm_framebuffer *fb,
1456 int x, int y, int atomic)
1458 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1459 struct drm_device *dev = crtc->dev;
1460 struct radeon_device *rdev = dev->dev_private;
1461 struct radeon_framebuffer *radeon_fb;
1462 struct drm_gem_object *obj;
1463 struct radeon_bo *rbo;
1464 struct drm_framebuffer *target_fb;
1465 uint64_t fb_location;
1466 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1467 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1468 u32 viewport_w, viewport_h;
1470 bool bypass_lut = false;
1473 if (!atomic && !crtc->primary->fb) {
1474 DRM_DEBUG_KMS("No FB bound\n");
1479 radeon_fb = to_radeon_framebuffer(fb);
1483 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1484 target_fb = crtc->primary->fb;
1487 obj = radeon_fb->obj;
1488 rbo = gem_to_radeon_bo(obj);
1489 r = radeon_bo_reserve(rbo, false);
1490 if (unlikely(r != 0))
1493 /* If atomic, assume fb object is pinned & idle & fenced and
1494 * just update base pointers
1497 fb_location = radeon_bo_gpu_offset(rbo);
1499 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1500 if (unlikely(r != 0)) {
1501 radeon_bo_unreserve(rbo);
1505 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1506 radeon_bo_unreserve(rbo);
1508 switch (target_fb->pixel_format) {
1511 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1512 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1514 case DRM_FORMAT_XRGB4444:
1515 case DRM_FORMAT_ARGB4444:
1517 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1518 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1520 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1523 case DRM_FORMAT_XRGB1555:
1525 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1526 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1528 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1531 case DRM_FORMAT_RGB565:
1533 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1534 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1536 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1539 case DRM_FORMAT_XRGB8888:
1540 case DRM_FORMAT_ARGB8888:
1542 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1543 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1545 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1548 case DRM_FORMAT_XRGB2101010:
1549 case DRM_FORMAT_ARGB2101010:
1551 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1552 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1554 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1556 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1560 DRM_ERROR("Unsupported screen format %s\n",
1561 drm_get_format_name(target_fb->pixel_format));
1565 if (rdev->family >= CHIP_R600) {
1566 if (tiling_flags & RADEON_TILING_MACRO)
1567 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1568 else if (tiling_flags & RADEON_TILING_MICRO)
1569 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1571 if (tiling_flags & RADEON_TILING_MACRO)
1572 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1574 if (tiling_flags & RADEON_TILING_MICRO)
1575 fb_format |= AVIVO_D1GRPH_TILED;
1578 if (radeon_crtc->crtc_id == 0)
1579 WREG32(AVIVO_D1VGA_CONTROL, 0);
1581 WREG32(AVIVO_D2VGA_CONTROL, 0);
1583 /* Make sure surface address is update at vertical blank rather than
1586 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);
1588 if (rdev->family >= CHIP_RV770) {
1589 if (radeon_crtc->crtc_id) {
1590 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1591 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1593 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1594 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1597 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1599 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1600 radeon_crtc->crtc_offset, (u32) fb_location);
1601 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1602 if (rdev->family >= CHIP_R600)
1603 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1605 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */
1606 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1607 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1610 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1612 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1613 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1614 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1615 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1616 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1617 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1619 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1620 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1621 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1623 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1627 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1629 viewport_w = crtc->mode.hdisplay;
1630 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1631 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1632 (viewport_w << 16) | viewport_h);
1634 /* set pageflip to happen only at start of vblank interval (front porch) */
1635 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1637 if (!atomic && fb && fb != crtc->primary->fb) {
1638 radeon_fb = to_radeon_framebuffer(fb);
1639 rbo = gem_to_radeon_bo(radeon_fb->obj);
1640 r = radeon_bo_reserve(rbo, false);
1641 if (unlikely(r != 0))
1643 radeon_bo_unpin(rbo);
1644 radeon_bo_unreserve(rbo);
1647 /* Bytes per pixel may have changed */
1648 radeon_bandwidth_update(rdev);
1653 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1654 struct drm_framebuffer *old_fb)
1656 struct drm_device *dev = crtc->dev;
1657 struct radeon_device *rdev = dev->dev_private;
1659 if (ASIC_IS_DCE4(rdev))
1660 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1661 else if (ASIC_IS_AVIVO(rdev))
1662 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1664 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1667 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1668 struct drm_framebuffer *fb,
1669 int x, int y, enum mode_set_atomic state)
1671 struct drm_device *dev = crtc->dev;
1672 struct radeon_device *rdev = dev->dev_private;
1674 if (ASIC_IS_DCE4(rdev))
1675 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1676 else if (ASIC_IS_AVIVO(rdev))
1677 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1679 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1682 /* properly set additional regs when using atombios */
1683 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1685 struct drm_device *dev = crtc->dev;
1686 struct radeon_device *rdev = dev->dev_private;
1687 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1688 u32 disp_merge_cntl;
1690 switch (radeon_crtc->crtc_id) {
1692 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1693 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1694 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1697 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1698 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1699 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1700 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1701 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1707 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1711 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1713 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1715 struct drm_device *dev = crtc->dev;
1716 struct drm_crtc *test_crtc;
1717 struct radeon_crtc *test_radeon_crtc;
1720 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1721 if (crtc == test_crtc)
1724 test_radeon_crtc = to_radeon_crtc(test_crtc);
1725 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1726 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1732 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1736 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1737 * also in DP mode. For DP, a single PPLL can be used for all DP
1740 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1742 struct drm_device *dev = crtc->dev;
1743 struct radeon_device *rdev = dev->dev_private;
1744 struct drm_crtc *test_crtc;
1745 struct radeon_crtc *test_radeon_crtc;
1747 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1748 if (crtc == test_crtc)
1750 test_radeon_crtc = to_radeon_crtc(test_crtc);
1751 if (test_radeon_crtc->encoder &&
1752 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1753 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1754 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1755 test_radeon_crtc->pll_id == ATOM_PPLL2)
1757 /* for DP use the same PLL for all */
1758 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1759 return test_radeon_crtc->pll_id;
1762 return ATOM_PPLL_INVALID;
1766 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1769 * @encoder: drm encoder
1771 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1772 * be shared (i.e., same clock).
1774 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1776 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1777 struct drm_device *dev = crtc->dev;
1778 struct radeon_device *rdev = dev->dev_private;
1779 struct drm_crtc *test_crtc;
1780 struct radeon_crtc *test_radeon_crtc;
1781 u32 adjusted_clock, test_adjusted_clock;
1783 adjusted_clock = radeon_crtc->adjusted_clock;
1785 if (adjusted_clock == 0)
1786 return ATOM_PPLL_INVALID;
1788 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1789 if (crtc == test_crtc)
1791 test_radeon_crtc = to_radeon_crtc(test_crtc);
1792 if (test_radeon_crtc->encoder &&
1793 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1794 /* PPLL2 is exclusive to UNIPHYA on DCE61 */
1795 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1796 test_radeon_crtc->pll_id == ATOM_PPLL2)
1798 /* check if we are already driving this connector with another crtc */
1799 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1800 /* if we are, return that pll */
1801 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1802 return test_radeon_crtc->pll_id;
1804 /* for non-DP check the clock */
1805 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1806 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1807 (adjusted_clock == test_adjusted_clock) &&
1808 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1809 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1810 return test_radeon_crtc->pll_id;
1813 return ATOM_PPLL_INVALID;
1817 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1821 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1822 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1823 * monitors a dedicated PPLL must be used. If a particular board has
1824 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1825 * as there is no need to program the PLL itself. If we are not able to
1826 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1827 * avoid messing up an existing monitor.
1829 * Asic specific PLL information
1833 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1835 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1838 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1839 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1842 * - PPLL0 is available to all UNIPHY (DP only)
1843 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1846 * - DCPLL is available to all UNIPHY (DP only)
1847 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1850 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1853 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1855 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1856 struct drm_device *dev = crtc->dev;
1857 struct radeon_device *rdev = dev->dev_private;
1858 struct radeon_encoder *radeon_encoder =
1859 to_radeon_encoder(radeon_crtc->encoder);
1863 if (ASIC_IS_DCE8(rdev)) {
1864 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1865 if (rdev->clock.dp_extclk)
1866 /* skip PPLL programming if using ext clock */
1867 return ATOM_PPLL_INVALID;
1869 /* use the same PPLL for all DP monitors */
1870 pll = radeon_get_shared_dp_ppll(crtc);
1871 if (pll != ATOM_PPLL_INVALID)
1875 /* use the same PPLL for all monitors with the same clock */
1876 pll = radeon_get_shared_nondp_ppll(crtc);
1877 if (pll != ATOM_PPLL_INVALID)
1880 /* otherwise, pick one of the plls */
1881 if ((rdev->family == CHIP_KABINI) ||
1882 (rdev->family == CHIP_MULLINS)) {
1883 /* KB/ML has PPLL1 and PPLL2 */
1884 pll_in_use = radeon_get_pll_use_mask(crtc);
1885 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1887 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1889 DRM_ERROR("unable to allocate a PPLL\n");
1890 return ATOM_PPLL_INVALID;
1892 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
1893 pll_in_use = radeon_get_pll_use_mask(crtc);
1894 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1896 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1898 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1900 DRM_ERROR("unable to allocate a PPLL\n");
1901 return ATOM_PPLL_INVALID;
1903 } else if (ASIC_IS_DCE61(rdev)) {
1904 struct radeon_encoder_atom_dig *dig =
1905 radeon_encoder->enc_priv;
1907 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1908 (dig->linkb == false))
1909 /* UNIPHY A uses PPLL2 */
1911 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1912 /* UNIPHY B/C/D/E/F */
1913 if (rdev->clock.dp_extclk)
1914 /* skip PPLL programming if using ext clock */
1915 return ATOM_PPLL_INVALID;
1917 /* use the same PPLL for all DP monitors */
1918 pll = radeon_get_shared_dp_ppll(crtc);
1919 if (pll != ATOM_PPLL_INVALID)
1923 /* use the same PPLL for all monitors with the same clock */
1924 pll = radeon_get_shared_nondp_ppll(crtc);
1925 if (pll != ATOM_PPLL_INVALID)
1928 /* UNIPHY B/C/D/E/F */
1929 pll_in_use = radeon_get_pll_use_mask(crtc);
1930 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1932 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1934 DRM_ERROR("unable to allocate a PPLL\n");
1935 return ATOM_PPLL_INVALID;
1936 } else if (ASIC_IS_DCE41(rdev)) {
1937 /* Don't share PLLs on DCE4.1 chips */
1938 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1939 if (rdev->clock.dp_extclk)
1940 /* skip PPLL programming if using ext clock */
1941 return ATOM_PPLL_INVALID;
1943 pll_in_use = radeon_get_pll_use_mask(crtc);
1944 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1946 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1948 DRM_ERROR("unable to allocate a PPLL\n");
1949 return ATOM_PPLL_INVALID;
1950 } else if (ASIC_IS_DCE4(rdev)) {
1951 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1952 * depending on the asic:
1953 * DCE4: PPLL or ext clock
1954 * DCE5: PPLL, DCPLL, or ext clock
1955 * DCE6: PPLL, PPLL0, or ext clock
1957 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1958 * PPLL/DCPLL programming and only program the DP DTO for the
1959 * crtc virtual pixel clock.
1961 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1962 if (rdev->clock.dp_extclk)
1963 /* skip PPLL programming if using ext clock */
1964 return ATOM_PPLL_INVALID;
1965 else if (ASIC_IS_DCE6(rdev))
1966 /* use PPLL0 for all DP */
1968 else if (ASIC_IS_DCE5(rdev))
1969 /* use DCPLL for all DP */
1972 /* use the same PPLL for all DP monitors */
1973 pll = radeon_get_shared_dp_ppll(crtc);
1974 if (pll != ATOM_PPLL_INVALID)
1978 /* use the same PPLL for all monitors with the same clock */
1979 pll = radeon_get_shared_nondp_ppll(crtc);
1980 if (pll != ATOM_PPLL_INVALID)
1983 /* all other cases */
1984 pll_in_use = radeon_get_pll_use_mask(crtc);
1985 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1987 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1989 DRM_ERROR("unable to allocate a PPLL\n");
1990 return ATOM_PPLL_INVALID;
1992 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1993 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1994 * the matching btw pll and crtc is done through
1995 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1996 * pll (1 or 2) to select which register to write. ie if using
1997 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1998 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1999 * choose which value to write. Which is reverse order from
2000 * register logic. So only case that works is when pllid is
2001 * same as crtcid or when both pll and crtc are enabled and
2002 * both use same clock.
2004 * So just return crtc id as if crtc and pll were hard linked
2005 * together even if they aren't
2007 return radeon_crtc->crtc_id;
2011 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2013 /* always set DCPLL */
2014 if (ASIC_IS_DCE6(rdev))
2015 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2016 else if (ASIC_IS_DCE4(rdev)) {
2017 struct radeon_atom_ss ss;
2018 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2019 ASIC_INTERNAL_SS_ON_DCPLL,
2020 rdev->clock.default_dispclk);
2022 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2023 /* XXX: DCE5, make sure voltage, dispclk is high enough */
2024 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2026 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2031 int atombios_crtc_mode_set(struct drm_crtc *crtc,
2032 struct drm_display_mode *mode,
2033 struct drm_display_mode *adjusted_mode,
2034 int x, int y, struct drm_framebuffer *old_fb)
2036 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2037 struct drm_device *dev = crtc->dev;
2038 struct radeon_device *rdev = dev->dev_private;
2039 struct radeon_encoder *radeon_encoder =
2040 to_radeon_encoder(radeon_crtc->encoder);
2041 bool is_tvcv = false;
2043 if (radeon_encoder->active_device &
2044 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2047 if (!radeon_crtc->adjusted_clock)
2050 atombios_crtc_set_pll(crtc, adjusted_mode);
2052 if (ASIC_IS_DCE4(rdev))
2053 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2054 else if (ASIC_IS_AVIVO(rdev)) {
2056 atombios_crtc_set_timing(crtc, adjusted_mode);
2058 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2060 atombios_crtc_set_timing(crtc, adjusted_mode);
2061 if (radeon_crtc->crtc_id == 0)
2062 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2063 radeon_legacy_atom_fixup(crtc);
2065 atombios_crtc_set_base(crtc, x, y, old_fb);
2066 atombios_overscan_setup(crtc, mode, adjusted_mode);
2067 atombios_scaler_setup(crtc);
2068 radeon_cursor_reset(crtc);
2069 /* update the hw version fpr dpm */
2070 radeon_crtc->hw_mode = *adjusted_mode;
2075 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2076 const struct drm_display_mode *mode,
2077 struct drm_display_mode *adjusted_mode)
2079 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_encoder *encoder;
2083 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
2084 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2085 if (encoder->crtc == crtc) {
2086 radeon_crtc->encoder = encoder;
2087 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2091 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2092 radeon_crtc->encoder = NULL;
2093 radeon_crtc->connector = NULL;
2096 if (radeon_crtc->encoder) {
2097 struct radeon_encoder *radeon_encoder =
2098 to_radeon_encoder(radeon_crtc->encoder);
2100 radeon_crtc->output_csc = radeon_encoder->output_csc;
2102 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2104 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2107 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2108 /* if we can't get a PPLL for a non-DP encoder, fail */
2109 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2110 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2116 static void atombios_crtc_prepare(struct drm_crtc *crtc)
2118 struct drm_device *dev = crtc->dev;
2119 struct radeon_device *rdev = dev->dev_private;
2121 /* disable crtc pair power gating before programming */
2122 if (ASIC_IS_DCE6(rdev))
2123 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2125 atombios_lock_crtc(crtc, ATOM_ENABLE);
2126 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2129 static void atombios_crtc_commit(struct drm_crtc *crtc)
2131 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2132 atombios_lock_crtc(crtc, ATOM_DISABLE);
2135 static void atombios_crtc_disable(struct drm_crtc *crtc)
2137 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2138 struct drm_device *dev = crtc->dev;
2139 struct radeon_device *rdev = dev->dev_private;
2140 struct radeon_atom_ss ss;
2143 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2144 if (crtc->primary->fb) {
2146 struct radeon_framebuffer *radeon_fb;
2147 struct radeon_bo *rbo;
2149 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2150 rbo = gem_to_radeon_bo(radeon_fb->obj);
2151 r = radeon_bo_reserve(rbo, false);
2153 DRM_ERROR("failed to reserve rbo before unpin\n");
2155 radeon_bo_unpin(rbo);
2156 radeon_bo_unreserve(rbo);
2159 /* disable the GRPH */
2160 if (ASIC_IS_DCE4(rdev))
2161 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2162 else if (ASIC_IS_AVIVO(rdev))
2163 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2165 if (ASIC_IS_DCE6(rdev))
2166 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2168 for (i = 0; i < rdev->num_crtc; i++) {
2169 if (rdev->mode_info.crtcs[i] &&
2170 rdev->mode_info.crtcs[i]->enabled &&
2171 i != radeon_crtc->crtc_id &&
2172 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2173 /* one other crtc is using this pll don't turn
2180 switch (radeon_crtc->pll_id) {
2183 /* disable the ppll */
2184 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2185 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2188 /* disable the ppll */
2189 if ((rdev->family == CHIP_ARUBA) ||
2190 (rdev->family == CHIP_KAVERI) ||
2191 (rdev->family == CHIP_BONAIRE) ||
2192 (rdev->family == CHIP_HAWAII))
2193 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2194 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2200 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2201 radeon_crtc->adjusted_clock = 0;
2202 radeon_crtc->encoder = NULL;
2203 radeon_crtc->connector = NULL;
2206 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2207 .dpms = atombios_crtc_dpms,
2208 .mode_fixup = atombios_crtc_mode_fixup,
2209 .mode_set = atombios_crtc_mode_set,
2210 .mode_set_base = atombios_crtc_set_base,
2211 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2212 .prepare = atombios_crtc_prepare,
2213 .commit = atombios_crtc_commit,
2214 .load_lut = radeon_crtc_load_lut,
2215 .disable = atombios_crtc_disable,
2218 void radeon_atombios_init_crtc(struct drm_device *dev,
2219 struct radeon_crtc *radeon_crtc)
2221 struct radeon_device *rdev = dev->dev_private;
2223 if (ASIC_IS_DCE4(rdev)) {
2224 switch (radeon_crtc->crtc_id) {
2227 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2230 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2233 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2236 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2239 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2242 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2246 if (radeon_crtc->crtc_id == 1)
2247 radeon_crtc->crtc_offset =
2248 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2250 radeon_crtc->crtc_offset = 0;
2252 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2253 radeon_crtc->adjusted_clock = 0;
2254 radeon_crtc->encoder = NULL;
2255 radeon_crtc->connector = NULL;
2256 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);