1 // SPDX-License-Identifier: MIT
3 #include <drm/drm_debugfs.h>
4 #include <drm/drm_dp_mst_helper.h>
5 #include <drm/drm_fb_helper.h>
6 #include <drm/drm_file.h>
7 #include <drm/drm_probe_helper.h>
13 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
15 static int radeon_atom_set_enc_offset(int id)
17 static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
18 EVERGREEN_CRTC1_REGISTER_OFFSET,
19 EVERGREEN_CRTC2_REGISTER_OFFSET,
20 EVERGREEN_CRTC3_REGISTER_OFFSET,
21 EVERGREEN_CRTC4_REGISTER_OFFSET,
22 EVERGREEN_CRTC5_REGISTER_OFFSET,
28 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
29 struct radeon_encoder_mst *mst_enc,
30 enum radeon_hpd_id hpd, bool enable)
32 struct drm_device *dev = primary->base.dev;
33 struct radeon_device *rdev = dev->dev_private;
38 reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
41 reg &= ~NI_DIG_FE_DIG_MODE(7);
42 reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
45 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
47 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
49 reg |= NI_DIG_HPD_SELECT(hpd);
50 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
51 WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
54 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
57 temp = RREG32(NI_DIG_FE_CNTL + offset);
58 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
60 DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
65 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
70 struct drm_device *dev = primary->base.dev;
71 struct radeon_device *rdev = dev->dev_private;
76 satreg = stream_number >> 1;
77 satidx = stream_number & 1;
79 temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
81 val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
83 val <<= (16 * satidx);
85 temp &= ~(0xffff << (16 * satidx));
89 DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
90 WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
92 WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
95 unsigned value1, value2;
97 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
99 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
100 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
102 if (!value1 && !value2)
104 } while (retries++ < 50);
106 if (retries == 10000)
107 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
113 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
114 struct radeon_encoder *primary)
116 struct drm_device *dev = mst_conn->base.dev;
117 struct stream_attribs new_attribs[6];
120 struct radeon_connector *radeon_connector;
121 struct drm_connector *connector;
123 memset(new_attribs, 0, sizeof(new_attribs));
124 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
125 struct radeon_encoder *subenc;
126 struct radeon_encoder_mst *mst_enc;
128 radeon_connector = to_radeon_connector(connector);
129 if (!radeon_connector->is_mst_connector)
132 if (radeon_connector->mst_port != mst_conn)
135 subenc = radeon_connector->mst_encoder;
136 mst_enc = subenc->enc_priv;
138 if (!mst_enc->enc_active)
141 new_attribs[idx].fe = mst_enc->fe;
142 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
146 for (i = 0; i < idx; i++) {
147 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
148 new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
149 radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
150 mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
151 mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
155 for (i = idx; i < mst_conn->enabled_attribs; i++) {
156 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
157 mst_conn->cur_stream_attribs[i].fe = 0;
158 mst_conn->cur_stream_attribs[i].slots = 0;
160 mst_conn->enabled_attribs = idx;
164 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
166 struct drm_device *dev = mst->base.dev;
167 struct radeon_device *rdev = dev->dev_private;
168 struct radeon_encoder_mst *mst_enc = mst->enc_priv;
170 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
172 uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
173 uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
175 val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
177 WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
180 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
182 } while ((temp & 0x1) && (retries++ < 10000));
184 if (retries >= 10000)
185 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
189 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
191 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
192 struct radeon_connector *master = radeon_connector->mst_port;
196 edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
197 radeon_connector->edid = edid;
198 DRM_DEBUG_KMS("edid retrieved %p\n", edid);
199 if (radeon_connector->edid) {
200 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
201 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
204 drm_connector_update_edid_property(&radeon_connector->base, NULL);
209 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
211 return radeon_dp_mst_get_ddc_modes(connector);
214 static enum drm_mode_status
215 radeon_dp_mst_mode_valid(struct drm_connector *connector,
216 struct drm_display_mode *mode)
218 /* TODO - validate mode against available PBN for link */
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
229 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
231 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
233 return &radeon_connector->mst_encoder->base;
237 radeon_dp_mst_detect(struct drm_connector *connector,
238 struct drm_modeset_acquire_ctx *ctx,
241 struct radeon_connector *radeon_connector =
242 to_radeon_connector(connector);
243 struct radeon_connector *master = radeon_connector->mst_port;
245 return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
246 radeon_connector->port);
249 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
250 .get_modes = radeon_dp_mst_get_modes,
251 .mode_valid = radeon_dp_mst_mode_valid,
252 .best_encoder = radeon_mst_best_encoder,
253 .detect_ctx = radeon_dp_mst_detect,
257 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
259 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
260 struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
262 drm_encoder_cleanup(&radeon_encoder->base);
263 kfree(radeon_encoder);
264 drm_connector_cleanup(connector);
265 kfree(radeon_connector);
268 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
269 .dpms = drm_helper_connector_dpms,
270 .fill_modes = drm_helper_probe_single_connector_modes,
271 .destroy = radeon_dp_mst_connector_destroy,
274 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
275 struct drm_dp_mst_port *port,
276 const char *pathprop)
278 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
279 struct drm_device *dev = master->base.dev;
280 struct radeon_connector *radeon_connector;
281 struct drm_connector *connector;
283 radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
284 if (!radeon_connector)
287 radeon_connector->is_mst_connector = true;
288 connector = &radeon_connector->base;
289 radeon_connector->port = port;
290 radeon_connector->mst_port = master;
293 drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
294 drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
295 radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
297 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
298 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
299 drm_connector_set_path_property(connector, pathprop);
304 static void radeon_dp_register_mst_connector(struct drm_connector *connector)
306 struct drm_device *dev = connector->dev;
307 struct radeon_device *rdev = dev->dev_private;
309 radeon_fb_add_connector(rdev, connector);
311 drm_connector_register(connector);
314 static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
315 struct drm_connector *connector)
317 struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
318 struct drm_device *dev = master->base.dev;
319 struct radeon_device *rdev = dev->dev_private;
321 drm_connector_unregister(connector);
322 radeon_fb_remove_connector(rdev, connector);
323 drm_connector_cleanup(connector);
329 static const struct drm_dp_mst_topology_cbs mst_cbs = {
330 .add_connector = radeon_dp_add_mst_connector,
331 .register_connector = radeon_dp_register_mst_connector,
332 .destroy_connector = radeon_dp_destroy_mst_connector,
336 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
338 struct drm_device *dev = encoder->dev;
339 struct drm_connector *connector;
341 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
342 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
343 if (!connector->encoder)
345 if (!radeon_connector->is_mst_connector)
348 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
349 if (connector->encoder == encoder)
350 return radeon_connector;
355 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
357 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
358 struct drm_device *dev = crtc->dev;
359 struct radeon_device *rdev = dev->dev_private;
360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
361 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
362 struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
364 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
366 if (radeon_connector) {
367 radeon_connector->pixelclock_for_modeset = mode->clock;
368 if (radeon_connector->base.display_info.bpc)
369 radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
371 radeon_crtc->bpc = 8;
374 DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
375 dp_clock = dig_connector->dp_clock;
376 radeon_crtc->ss_enabled =
377 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
378 ASIC_INTERNAL_SS_ON_DP,
383 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
385 struct drm_device *dev = encoder->dev;
386 struct radeon_device *rdev = dev->dev_private;
387 struct radeon_encoder *radeon_encoder, *primary;
388 struct radeon_encoder_mst *mst_enc;
389 struct radeon_encoder_atom_dig *dig_enc;
390 struct radeon_connector *radeon_connector;
391 struct drm_crtc *crtc;
392 struct radeon_crtc *radeon_crtc;
394 s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
395 if (!ASIC_IS_DCE5(rdev)) {
396 DRM_ERROR("got mst dpms on non-DCE5\n");
400 radeon_connector = radeon_mst_find_connector(encoder);
401 if (!radeon_connector)
404 radeon_encoder = to_radeon_encoder(encoder);
406 mst_enc = radeon_encoder->enc_priv;
408 primary = mst_enc->primary;
410 dig_enc = primary->enc_priv;
412 crtc = encoder->crtc;
413 DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
416 case DRM_MODE_DPMS_ON:
417 dig_enc->active_mst_links++;
419 radeon_crtc = to_radeon_crtc(crtc);
421 if (dig_enc->active_mst_links == 1) {
422 mst_enc->fe = dig_enc->dig_encoder;
423 mst_enc->fe_from_be = true;
424 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
426 atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
427 atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
428 0, 0, dig_enc->dig_encoder);
430 if (radeon_dp_needs_link_train(mst_enc->connector) ||
431 dig_enc->active_mst_links == 1) {
432 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
436 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
437 if (mst_enc->fe == -1)
438 DRM_ERROR("failed to get frontend for dig encoder\n");
439 mst_enc->fe_from_be = false;
440 atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
443 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
444 dig_enc->linkb, radeon_crtc->crtc_id);
446 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
448 ret = drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
449 radeon_connector->port,
450 mst_enc->pbn, slots);
451 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
453 radeon_dp_mst_set_be_cntl(primary, mst_enc,
454 radeon_connector->mst_port->hpd.hpd, true);
456 mst_enc->enc_active = true;
457 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
459 fixed_pbn = drm_int2fixp(mst_enc->pbn);
460 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
461 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
462 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
464 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
466 ret = drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
468 ret = drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
471 case DRM_MODE_DPMS_STANDBY:
472 case DRM_MODE_DPMS_SUSPEND:
473 case DRM_MODE_DPMS_OFF:
474 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
476 if (!mst_enc->enc_active)
479 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
480 ret = drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
482 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
483 /* and this can also fail */
484 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
486 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
488 mst_enc->enc_active = false;
489 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
491 radeon_dp_mst_set_be_cntl(primary, mst_enc,
492 radeon_connector->mst_port->hpd.hpd, false);
493 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
496 if (!mst_enc->fe_from_be)
497 radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
499 mst_enc->fe_from_be = false;
500 dig_enc->active_mst_links--;
501 if (dig_enc->active_mst_links == 0) {
510 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
511 const struct drm_display_mode *mode,
512 struct drm_display_mode *adjusted_mode)
514 struct radeon_encoder_mst *mst_enc;
515 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
516 struct radeon_connector_atom_dig *dig_connector;
519 mst_enc = radeon_encoder->enc_priv;
521 mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);
523 mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
524 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
525 mst_enc->primary->active_device, mst_enc->primary->devices,
526 mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
529 drm_mode_set_crtcinfo(adjusted_mode, 0);
530 dig_connector = mst_enc->connector->con_priv;
531 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
532 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
533 DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
534 dig_connector->dp_lane_count, dig_connector->dp_clock);
538 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
540 struct radeon_connector *radeon_connector;
541 struct radeon_encoder *radeon_encoder, *primary;
542 struct radeon_encoder_mst *mst_enc;
543 struct radeon_encoder_atom_dig *dig_enc;
545 radeon_connector = radeon_mst_find_connector(encoder);
546 if (!radeon_connector) {
547 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
550 radeon_encoder = to_radeon_encoder(encoder);
552 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
554 mst_enc = radeon_encoder->enc_priv;
556 primary = mst_enc->primary;
558 dig_enc = primary->enc_priv;
560 mst_enc->port = radeon_connector->port;
562 if (dig_enc->dig_encoder == -1) {
563 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
564 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
565 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
569 DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
573 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
574 struct drm_display_mode *mode,
575 struct drm_display_mode *adjusted_mode)
580 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
582 radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
586 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
587 .dpms = radeon_mst_encoder_dpms,
588 .mode_fixup = radeon_mst_mode_fixup,
589 .prepare = radeon_mst_encoder_prepare,
590 .mode_set = radeon_mst_encoder_mode_set,
591 .commit = radeon_mst_encoder_commit,
594 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
596 drm_encoder_cleanup(encoder);
600 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
601 .destroy = radeon_dp_mst_encoder_destroy,
604 static struct radeon_encoder *
605 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
607 struct drm_device *dev = connector->base.dev;
608 struct radeon_device *rdev = dev->dev_private;
609 struct radeon_encoder *radeon_encoder;
610 struct radeon_encoder_mst *mst_enc;
611 struct drm_encoder *encoder;
612 const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
613 struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
615 DRM_DEBUG_KMS("enc master is %p\n", enc_master);
616 radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
620 radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
621 if (!radeon_encoder->enc_priv) {
622 kfree(radeon_encoder);
625 encoder = &radeon_encoder->base;
626 switch (rdev->num_crtc) {
628 encoder->possible_crtcs = 0x1;
632 encoder->possible_crtcs = 0x3;
635 encoder->possible_crtcs = 0xf;
638 encoder->possible_crtcs = 0x3f;
642 drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
643 DRM_MODE_ENCODER_DPMST, NULL);
644 drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
646 mst_enc = radeon_encoder->enc_priv;
647 mst_enc->connector = connector;
648 mst_enc->primary = to_radeon_encoder(enc_master);
649 radeon_encoder->is_mst_encoder = true;
650 return radeon_encoder;
654 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
656 struct drm_device *dev = radeon_connector->base.dev;
658 if (!radeon_connector->ddc_bus->has_aux)
661 radeon_connector->mst_mgr.cbs = &mst_cbs;
662 return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
663 &radeon_connector->ddc_bus->aux, 16, 6,
664 radeon_connector->base.base.id);
668 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
670 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
671 struct drm_device *dev = radeon_connector->base.dev;
672 struct radeon_device *rdev = dev->dev_private;
679 if (!ASIC_IS_DCE5(rdev))
682 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
685 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
688 if (msg[0] & DP_MST_CAP) {
689 DRM_DEBUG_KMS("Sink is MST capable\n");
690 dig_connector->is_mst = true;
692 DRM_DEBUG_KMS("Sink is not MST capable\n");
693 dig_connector->is_mst = false;
697 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
698 dig_connector->is_mst);
699 return dig_connector->is_mst;
703 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
705 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
708 if (dig_connector->is_mst) {
714 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
715 DP_SINK_COUNT_ESI, esi, 8);
718 DRM_DEBUG_KMS("got esi %3ph\n", esi);
719 ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
722 for (retry = 0; retry < 3; retry++) {
724 wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
725 DP_SINK_COUNT_ESI + 1, &esi[1], 3);
730 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
731 DP_SINK_COUNT_ESI, esi, 8);
733 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
741 DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
742 dig_connector->is_mst = false;
743 drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
744 dig_connector->is_mst);
745 /* send a hotplug event */
751 #if defined(CONFIG_DEBUG_FS)
753 static int radeon_debugfs_mst_info(struct seq_file *m, void *data)
755 struct drm_info_node *node = (struct drm_info_node *)m->private;
756 struct drm_device *dev = node->minor->dev;
757 struct drm_connector *connector;
758 struct radeon_connector *radeon_connector;
759 struct radeon_connector_atom_dig *dig_connector;
762 drm_modeset_lock_all(dev);
763 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
764 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
767 radeon_connector = to_radeon_connector(connector);
768 dig_connector = radeon_connector->con_priv;
769 if (radeon_connector->is_mst_connector)
771 if (!dig_connector->is_mst)
773 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
775 for (i = 0; i < radeon_connector->enabled_attribs; i++)
776 seq_printf(m, "attrib %d: %d %d\n", i,
777 radeon_connector->cur_stream_attribs[i].fe,
778 radeon_connector->cur_stream_attribs[i].slots);
780 drm_modeset_unlock_all(dev);
784 static struct drm_info_list radeon_debugfs_mst_list[] = {
785 {"radeon_mst_info", &radeon_debugfs_mst_info, 0, NULL},
789 int radeon_mst_debugfs_init(struct radeon_device *rdev)
791 #if defined(CONFIG_DEBUG_FS)
792 return radeon_debugfs_add_files(rdev, radeon_debugfs_mst_list, 1);