2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/module.h>
24 #include <linux/fdtable.h>
25 #include <linux/uaccess.h>
30 #include "radeon_kfd.h"
31 #include "radeon_ucode.h"
32 #include <linux/firmware.h>
33 #include "cik_structs.h"
35 #define CIK_PIPE_PER_MEC (4)
37 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
38 TCP_WATCH0_ADDR_H, TCP_WATCH0_ADDR_L, TCP_WATCH0_CNTL,
39 TCP_WATCH1_ADDR_H, TCP_WATCH1_ADDR_L, TCP_WATCH1_CNTL,
40 TCP_WATCH2_ADDR_H, TCP_WATCH2_ADDR_L, TCP_WATCH2_CNTL,
41 TCP_WATCH3_ADDR_H, TCP_WATCH3_ADDR_L, TCP_WATCH3_CNTL
51 static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
52 void **mem_obj, uint64_t *gpu_addr,
55 static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
57 static uint64_t get_vmem_size(struct kgd_dev *kgd);
58 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd);
60 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
61 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
64 * Register access functions
67 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
68 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
69 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
71 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
74 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
75 uint32_t hpd_size, uint64_t hpd_gpu_addr);
76 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
77 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
78 uint32_t queue_id, uint32_t __user *wptr);
79 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
80 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
81 uint32_t pipe_id, uint32_t queue_id);
83 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
84 unsigned int timeout, uint32_t pipe_id,
86 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
87 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
88 unsigned int timeout);
89 static int kgd_address_watch_disable(struct kgd_dev *kgd);
90 static int kgd_address_watch_execute(struct kgd_dev *kgd,
91 unsigned int watch_point_id,
95 static int kgd_wave_control_execute(struct kgd_dev *kgd,
96 uint32_t gfx_index_val,
98 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
99 unsigned int watch_point_id,
100 unsigned int reg_offset);
102 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
103 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
105 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
107 static const struct kfd2kgd_calls kfd2kgd = {
108 .init_gtt_mem_allocation = alloc_gtt_mem,
109 .free_gtt_mem = free_gtt_mem,
110 .get_vmem_size = get_vmem_size,
111 .get_gpu_clock_counter = get_gpu_clock_counter,
112 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
113 .program_sh_mem_settings = kgd_program_sh_mem_settings,
114 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
115 .init_pipeline = kgd_init_pipeline,
116 .init_interrupts = kgd_init_interrupts,
117 .hqd_load = kgd_hqd_load,
118 .hqd_sdma_load = kgd_hqd_sdma_load,
119 .hqd_is_occupied = kgd_hqd_is_occupied,
120 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
121 .hqd_destroy = kgd_hqd_destroy,
122 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
123 .address_watch_disable = kgd_address_watch_disable,
124 .address_watch_execute = kgd_address_watch_execute,
125 .wave_control_execute = kgd_wave_control_execute,
126 .address_watch_get_offset = kgd_address_watch_get_offset,
127 .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
128 .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
129 .write_vmid_invalidate_request = write_vmid_invalidate_request,
130 .get_fw_version = get_fw_version
133 static const struct kgd2kfd_calls *kgd2kfd;
135 int radeon_kfd_init(void)
139 #if defined(CONFIG_HSA_AMD_MODULE)
140 int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);
142 kgd2kfd_init_p = symbol_request(kgd2kfd_init);
144 if (kgd2kfd_init_p == NULL)
147 ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
149 symbol_put(kgd2kfd_init);
153 #elif defined(CONFIG_HSA_AMD)
154 ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
165 void radeon_kfd_fini(void)
169 symbol_put(kgd2kfd_init);
173 void radeon_kfd_device_probe(struct radeon_device *rdev)
176 rdev->kfd = kgd2kfd->probe((struct kgd_dev *)rdev,
177 rdev->pdev, &kfd2kgd);
180 void radeon_kfd_device_init(struct radeon_device *rdev)
182 int i, queue, pipe, mec;
185 struct kgd2kfd_shared_resources gpu_resources = {
186 .compute_vmid_bitmap = 0xFF00,
188 .num_pipe_per_mec = 4,
189 .num_queue_per_pipe = 8
192 bitmap_zero(gpu_resources.queue_bitmap, KGD_MAX_QUEUES);
194 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
195 queue = i % gpu_resources.num_queue_per_pipe;
196 pipe = (i / gpu_resources.num_queue_per_pipe)
197 % gpu_resources.num_pipe_per_mec;
198 mec = (i / gpu_resources.num_queue_per_pipe)
199 / gpu_resources.num_pipe_per_mec;
201 if (mec == 0 && pipe > 0)
202 set_bit(i, gpu_resources.queue_bitmap);
205 radeon_doorbell_get_kfd_info(rdev,
206 &gpu_resources.doorbell_physical_address,
207 &gpu_resources.doorbell_aperture_size,
208 &gpu_resources.doorbell_start_offset);
210 kgd2kfd->device_init(rdev->kfd, &gpu_resources);
214 void radeon_kfd_device_fini(struct radeon_device *rdev)
217 kgd2kfd->device_exit(rdev->kfd);
222 void radeon_kfd_interrupt(struct radeon_device *rdev, const void *ih_ring_entry)
225 kgd2kfd->interrupt(rdev->kfd, ih_ring_entry);
228 void radeon_kfd_suspend(struct radeon_device *rdev)
231 kgd2kfd->suspend(rdev->kfd);
234 int radeon_kfd_resume(struct radeon_device *rdev)
239 r = kgd2kfd->resume(rdev->kfd);
244 static int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
245 void **mem_obj, uint64_t *gpu_addr,
248 struct radeon_device *rdev = (struct radeon_device *)kgd;
249 struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
253 BUG_ON(gpu_addr == NULL);
254 BUG_ON(cpu_ptr == NULL);
256 *mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
260 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_GTT,
261 RADEON_GEM_GTT_WC, NULL, NULL, &(*mem)->bo);
264 "failed to allocate BO for amdkfd (%d)\n", r);
269 r = radeon_bo_reserve((*mem)->bo, true);
271 dev_err(rdev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
272 goto allocate_mem_reserve_bo_failed;
275 r = radeon_bo_pin((*mem)->bo, RADEON_GEM_DOMAIN_GTT,
278 dev_err(rdev->dev, "(%d) failed to pin bo for amdkfd\n", r);
279 goto allocate_mem_pin_bo_failed;
281 *gpu_addr = (*mem)->gpu_addr;
283 r = radeon_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
286 "(%d) failed to map bo to kernel for amdkfd\n", r);
287 goto allocate_mem_kmap_bo_failed;
289 *cpu_ptr = (*mem)->cpu_ptr;
291 radeon_bo_unreserve((*mem)->bo);
295 allocate_mem_kmap_bo_failed:
296 radeon_bo_unpin((*mem)->bo);
297 allocate_mem_pin_bo_failed:
298 radeon_bo_unreserve((*mem)->bo);
299 allocate_mem_reserve_bo_failed:
300 radeon_bo_unref(&(*mem)->bo);
305 static void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
307 struct kgd_mem *mem = (struct kgd_mem *) mem_obj;
311 radeon_bo_reserve(mem->bo, true);
312 radeon_bo_kunmap(mem->bo);
313 radeon_bo_unpin(mem->bo);
314 radeon_bo_unreserve(mem->bo);
315 radeon_bo_unref(&(mem->bo));
319 static uint64_t get_vmem_size(struct kgd_dev *kgd)
321 struct radeon_device *rdev = (struct radeon_device *)kgd;
325 return rdev->mc.real_vram_size;
328 static uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
330 struct radeon_device *rdev = (struct radeon_device *)kgd;
332 return rdev->asic->get_gpu_clock_counter(rdev);
335 static uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
337 struct radeon_device *rdev = (struct radeon_device *)kgd;
339 /* The sclk is in quantas of 10kHz */
340 return rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
343 static inline struct radeon_device *get_radeon_device(struct kgd_dev *kgd)
345 return (struct radeon_device *)kgd;
348 static void write_register(struct kgd_dev *kgd, uint32_t offset, uint32_t value)
350 struct radeon_device *rdev = get_radeon_device(kgd);
352 writel(value, (void __iomem *)(rdev->rmmio + offset));
355 static uint32_t read_register(struct kgd_dev *kgd, uint32_t offset)
357 struct radeon_device *rdev = get_radeon_device(kgd);
359 return readl((void __iomem *)(rdev->rmmio + offset));
362 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
363 uint32_t queue, uint32_t vmid)
365 struct radeon_device *rdev = get_radeon_device(kgd);
366 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
368 mutex_lock(&rdev->srbm_mutex);
369 write_register(kgd, SRBM_GFX_CNTL, value);
372 static void unlock_srbm(struct kgd_dev *kgd)
374 struct radeon_device *rdev = get_radeon_device(kgd);
376 write_register(kgd, SRBM_GFX_CNTL, 0);
377 mutex_unlock(&rdev->srbm_mutex);
380 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
383 uint32_t mec = (++pipe_id / CIK_PIPE_PER_MEC) + 1;
384 uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC);
386 lock_srbm(kgd, mec, pipe, queue_id, 0);
389 static void release_queue(struct kgd_dev *kgd)
394 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
395 uint32_t sh_mem_config,
396 uint32_t sh_mem_ape1_base,
397 uint32_t sh_mem_ape1_limit,
398 uint32_t sh_mem_bases)
400 lock_srbm(kgd, 0, 0, 0, vmid);
402 write_register(kgd, SH_MEM_CONFIG, sh_mem_config);
403 write_register(kgd, SH_MEM_APE1_BASE, sh_mem_ape1_base);
404 write_register(kgd, SH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
405 write_register(kgd, SH_MEM_BASES, sh_mem_bases);
410 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
414 * We have to assume that there is no outstanding mapping.
415 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0
416 * because a mapping is in progress or because a mapping finished and
418 * So the protocol is to always wait & clear.
420 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
421 ATC_VMID_PASID_MAPPING_VALID_MASK;
423 write_register(kgd, ATC_VMID0_PASID_MAPPING + vmid*sizeof(uint32_t),
426 while (!(read_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS) &
429 write_register(kgd, ATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
431 /* Mapping vmid to pasid also for IH block */
432 write_register(kgd, IH_VMID_0_LUT + vmid * sizeof(uint32_t),
438 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
439 uint32_t hpd_size, uint64_t hpd_gpu_addr)
441 /* nothing to do here */
445 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
450 mec = (pipe_id / CIK_PIPE_PER_MEC) + 1;
451 pipe = (pipe_id % CIK_PIPE_PER_MEC);
453 lock_srbm(kgd, mec, pipe, 0, 0);
455 write_register(kgd, CPC_INT_CNTL,
456 TIME_STAMP_INT_ENABLE | OPCODE_ERROR_INT_ENABLE);
463 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
467 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
468 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET;
470 pr_debug("kfd: sdma base address: 0x%x\n", retval);
475 static inline struct cik_mqd *get_mqd(void *mqd)
477 return (struct cik_mqd *)mqd;
480 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
482 return (struct cik_sdma_rlc_registers *)mqd;
485 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
486 uint32_t queue_id, uint32_t __user *wptr)
488 uint32_t wptr_shadow, is_wptr_shadow_valid;
493 is_wptr_shadow_valid = !get_user(wptr_shadow, wptr);
495 acquire_queue(kgd, pipe_id, queue_id);
496 write_register(kgd, CP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
497 write_register(kgd, CP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
498 write_register(kgd, CP_MQD_CONTROL, m->cp_mqd_control);
500 write_register(kgd, CP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
501 write_register(kgd, CP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
502 write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
504 write_register(kgd, CP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
505 write_register(kgd, CP_HQD_IB_BASE_ADDR, m->cp_hqd_ib_base_addr_lo);
506 write_register(kgd, CP_HQD_IB_BASE_ADDR_HI, m->cp_hqd_ib_base_addr_hi);
508 write_register(kgd, CP_HQD_IB_RPTR, m->cp_hqd_ib_rptr);
510 write_register(kgd, CP_HQD_PERSISTENT_STATE,
511 m->cp_hqd_persistent_state);
512 write_register(kgd, CP_HQD_SEMA_CMD, m->cp_hqd_sema_cmd);
513 write_register(kgd, CP_HQD_MSG_TYPE, m->cp_hqd_msg_type);
515 write_register(kgd, CP_HQD_ATOMIC0_PREOP_LO,
516 m->cp_hqd_atomic0_preop_lo);
518 write_register(kgd, CP_HQD_ATOMIC0_PREOP_HI,
519 m->cp_hqd_atomic0_preop_hi);
521 write_register(kgd, CP_HQD_ATOMIC1_PREOP_LO,
522 m->cp_hqd_atomic1_preop_lo);
524 write_register(kgd, CP_HQD_ATOMIC1_PREOP_HI,
525 m->cp_hqd_atomic1_preop_hi);
527 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR,
528 m->cp_hqd_pq_rptr_report_addr_lo);
530 write_register(kgd, CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
531 m->cp_hqd_pq_rptr_report_addr_hi);
533 write_register(kgd, CP_HQD_PQ_RPTR, m->cp_hqd_pq_rptr);
535 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR,
536 m->cp_hqd_pq_wptr_poll_addr_lo);
538 write_register(kgd, CP_HQD_PQ_WPTR_POLL_ADDR_HI,
539 m->cp_hqd_pq_wptr_poll_addr_hi);
541 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL,
542 m->cp_hqd_pq_doorbell_control);
544 write_register(kgd, CP_HQD_VMID, m->cp_hqd_vmid);
546 write_register(kgd, CP_HQD_QUANTUM, m->cp_hqd_quantum);
548 write_register(kgd, CP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
549 write_register(kgd, CP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
551 write_register(kgd, CP_HQD_IQ_RPTR, m->cp_hqd_iq_rptr);
553 if (is_wptr_shadow_valid)
554 write_register(kgd, CP_HQD_PQ_WPTR, wptr_shadow);
556 write_register(kgd, CP_HQD_ACTIVE, m->cp_hqd_active);
562 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
564 struct cik_sdma_rlc_registers *m;
565 uint32_t sdma_base_addr;
567 m = get_sdma_mqd(mqd);
568 sdma_base_addr = get_sdma_base_addr(m);
571 sdma_base_addr + SDMA0_RLC0_VIRTUAL_ADDR,
572 m->sdma_rlc_virtual_addr);
575 sdma_base_addr + SDMA0_RLC0_RB_BASE,
576 m->sdma_rlc_rb_base);
579 sdma_base_addr + SDMA0_RLC0_RB_BASE_HI,
580 m->sdma_rlc_rb_base_hi);
583 sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_LO,
584 m->sdma_rlc_rb_rptr_addr_lo);
587 sdma_base_addr + SDMA0_RLC0_RB_RPTR_ADDR_HI,
588 m->sdma_rlc_rb_rptr_addr_hi);
591 sdma_base_addr + SDMA0_RLC0_DOORBELL,
592 m->sdma_rlc_doorbell);
595 sdma_base_addr + SDMA0_RLC0_RB_CNTL,
596 m->sdma_rlc_rb_cntl);
601 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
602 uint32_t pipe_id, uint32_t queue_id)
608 acquire_queue(kgd, pipe_id, queue_id);
609 act = read_register(kgd, CP_HQD_ACTIVE);
611 low = lower_32_bits(queue_address >> 8);
612 high = upper_32_bits(queue_address >> 8);
614 if (low == read_register(kgd, CP_HQD_PQ_BASE) &&
615 high == read_register(kgd, CP_HQD_PQ_BASE_HI))
622 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
624 struct cik_sdma_rlc_registers *m;
625 uint32_t sdma_base_addr;
626 uint32_t sdma_rlc_rb_cntl;
628 m = get_sdma_mqd(mqd);
629 sdma_base_addr = get_sdma_base_addr(m);
631 sdma_rlc_rb_cntl = read_register(kgd,
632 sdma_base_addr + SDMA0_RLC0_RB_CNTL);
634 if (sdma_rlc_rb_cntl & SDMA_RB_ENABLE)
640 static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
641 unsigned int timeout, uint32_t pipe_id,
646 acquire_queue(kgd, pipe_id, queue_id);
647 write_register(kgd, CP_HQD_PQ_DOORBELL_CONTROL, 0);
649 write_register(kgd, CP_HQD_DEQUEUE_REQUEST, reset_type);
652 temp = read_register(kgd, CP_HQD_ACTIVE);
656 pr_err("kfd: cp queue preemption time out (%dms)\n",
669 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
670 unsigned int timeout)
672 struct cik_sdma_rlc_registers *m;
673 uint32_t sdma_base_addr;
676 m = get_sdma_mqd(mqd);
677 sdma_base_addr = get_sdma_base_addr(m);
679 temp = read_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL);
680 temp = temp & ~SDMA_RB_ENABLE;
681 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_CNTL, temp);
684 temp = read_register(kgd, sdma_base_addr +
685 SDMA0_RLC0_CONTEXT_STATUS);
686 if (temp & SDMA_RLC_IDLE)
694 write_register(kgd, sdma_base_addr + SDMA0_RLC0_DOORBELL, 0);
695 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_RPTR, 0);
696 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_WPTR, 0);
697 write_register(kgd, sdma_base_addr + SDMA0_RLC0_RB_BASE, 0);
702 static int kgd_address_watch_disable(struct kgd_dev *kgd)
704 union TCP_WATCH_CNTL_BITS cntl;
709 cntl.bitfields.valid = 0;
710 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
711 cntl.bitfields.atc = 1;
713 /* Turning off this address until we set all the registers */
714 for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
716 watchRegs[i * ADDRESS_WATCH_REG_MAX +
717 ADDRESS_WATCH_REG_CNTL],
723 static int kgd_address_watch_execute(struct kgd_dev *kgd,
724 unsigned int watch_point_id,
729 union TCP_WATCH_CNTL_BITS cntl;
731 cntl.u32All = cntl_val;
733 /* Turning off this watch point until we set all the registers */
734 cntl.bitfields.valid = 0;
736 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
737 ADDRESS_WATCH_REG_CNTL],
741 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
742 ADDRESS_WATCH_REG_ADDR_HI],
746 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
747 ADDRESS_WATCH_REG_ADDR_LO],
750 /* Enable the watch point */
751 cntl.bitfields.valid = 1;
754 watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
755 ADDRESS_WATCH_REG_CNTL],
761 static int kgd_wave_control_execute(struct kgd_dev *kgd,
762 uint32_t gfx_index_val,
765 struct radeon_device *rdev = get_radeon_device(kgd);
768 mutex_lock(&rdev->grbm_idx_mutex);
770 write_register(kgd, GRBM_GFX_INDEX, gfx_index_val);
771 write_register(kgd, SQ_CMD, sq_cmd);
773 /* Restore the GRBM_GFX_INDEX register */
775 data = INSTANCE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
778 write_register(kgd, GRBM_GFX_INDEX, data);
780 mutex_unlock(&rdev->grbm_idx_mutex);
785 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
786 unsigned int watch_point_id,
787 unsigned int reg_offset)
789 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
792 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid)
795 struct radeon_device *rdev = (struct radeon_device *) kgd;
797 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
798 return reg & ATC_VMID_PASID_MAPPING_VALID_MASK;
801 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
805 struct radeon_device *rdev = (struct radeon_device *) kgd;
807 reg = RREG32(ATC_VMID0_PASID_MAPPING + vmid*4);
808 return reg & ATC_VMID_PASID_MAPPING_PASID_MASK;
811 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
813 struct radeon_device *rdev = (struct radeon_device *) kgd;
815 return WREG32(VM_INVALIDATE_REQUEST, 1 << vmid);
818 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
820 struct radeon_device *rdev = (struct radeon_device *) kgd;
821 const union radeon_firmware_header *hdr;
823 BUG_ON(kgd == NULL || rdev->mec_fw == NULL);
827 hdr = (const union radeon_firmware_header *) rdev->pfp_fw->data;
831 hdr = (const union radeon_firmware_header *) rdev->me_fw->data;
835 hdr = (const union radeon_firmware_header *) rdev->ce_fw->data;
838 case KGD_ENGINE_MEC1:
839 hdr = (const union radeon_firmware_header *) rdev->mec_fw->data;
842 case KGD_ENGINE_MEC2:
843 hdr = (const union radeon_firmware_header *)
848 hdr = (const union radeon_firmware_header *) rdev->rlc_fw->data;
851 case KGD_ENGINE_SDMA1:
852 case KGD_ENGINE_SDMA2:
853 hdr = (const union radeon_firmware_header *)
864 /* Only 12 bit in use*/
865 return hdr->common.ucode_version;