2 * Copyright 2011 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include "radeon_audio.h"
31 #include <drm/radeon_drm.h>
34 #include "si_blit_shaders.h"
35 #include "clearstate_si.h"
36 #include "radeon_ucode.h"
39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
40 MODULE_FIRMWARE("radeon/TAHITI_me.bin");
41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
43 MODULE_FIRMWARE("radeon/TAHITI_mc2.bin");
44 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
45 MODULE_FIRMWARE("radeon/TAHITI_smc.bin");
47 MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48 MODULE_FIRMWARE("radeon/tahiti_me.bin");
49 MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50 MODULE_FIRMWARE("radeon/tahiti_mc.bin");
51 MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
52 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
54 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
55 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
56 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
57 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
58 MODULE_FIRMWARE("radeon/PITCAIRN_mc2.bin");
59 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
60 MODULE_FIRMWARE("radeon/PITCAIRN_smc.bin");
62 MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
63 MODULE_FIRMWARE("radeon/pitcairn_me.bin");
64 MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
65 MODULE_FIRMWARE("radeon/pitcairn_mc.bin");
66 MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
67 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
68 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
70 MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
71 MODULE_FIRMWARE("radeon/VERDE_me.bin");
72 MODULE_FIRMWARE("radeon/VERDE_ce.bin");
73 MODULE_FIRMWARE("radeon/VERDE_mc.bin");
74 MODULE_FIRMWARE("radeon/VERDE_mc2.bin");
75 MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
76 MODULE_FIRMWARE("radeon/VERDE_smc.bin");
78 MODULE_FIRMWARE("radeon/verde_pfp.bin");
79 MODULE_FIRMWARE("radeon/verde_me.bin");
80 MODULE_FIRMWARE("radeon/verde_ce.bin");
81 MODULE_FIRMWARE("radeon/verde_mc.bin");
82 MODULE_FIRMWARE("radeon/verde_rlc.bin");
83 MODULE_FIRMWARE("radeon/verde_smc.bin");
84 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
86 MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
87 MODULE_FIRMWARE("radeon/OLAND_me.bin");
88 MODULE_FIRMWARE("radeon/OLAND_ce.bin");
89 MODULE_FIRMWARE("radeon/OLAND_mc.bin");
90 MODULE_FIRMWARE("radeon/OLAND_mc2.bin");
91 MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
92 MODULE_FIRMWARE("radeon/OLAND_smc.bin");
94 MODULE_FIRMWARE("radeon/oland_pfp.bin");
95 MODULE_FIRMWARE("radeon/oland_me.bin");
96 MODULE_FIRMWARE("radeon/oland_ce.bin");
97 MODULE_FIRMWARE("radeon/oland_mc.bin");
98 MODULE_FIRMWARE("radeon/oland_rlc.bin");
99 MODULE_FIRMWARE("radeon/oland_smc.bin");
100 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
102 MODULE_FIRMWARE("radeon/HAINAN_pfp.bin");
103 MODULE_FIRMWARE("radeon/HAINAN_me.bin");
104 MODULE_FIRMWARE("radeon/HAINAN_ce.bin");
105 MODULE_FIRMWARE("radeon/HAINAN_mc.bin");
106 MODULE_FIRMWARE("radeon/HAINAN_mc2.bin");
107 MODULE_FIRMWARE("radeon/HAINAN_rlc.bin");
108 MODULE_FIRMWARE("radeon/HAINAN_smc.bin");
110 MODULE_FIRMWARE("radeon/hainan_pfp.bin");
111 MODULE_FIRMWARE("radeon/hainan_me.bin");
112 MODULE_FIRMWARE("radeon/hainan_ce.bin");
113 MODULE_FIRMWARE("radeon/hainan_mc.bin");
114 MODULE_FIRMWARE("radeon/hainan_rlc.bin");
115 MODULE_FIRMWARE("radeon/hainan_smc.bin");
116 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
117 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
119 MODULE_FIRMWARE("radeon/si58_mc.bin");
121 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
122 static void si_pcie_gen3_enable(struct radeon_device *rdev);
123 static void si_program_aspm(struct radeon_device *rdev);
124 extern void sumo_rlc_fini(struct radeon_device *rdev);
125 extern int sumo_rlc_init(struct radeon_device *rdev);
126 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
127 extern void r600_ih_ring_fini(struct radeon_device *rdev);
128 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
129 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
130 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
131 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
132 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
133 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
134 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
136 static void si_init_pg(struct radeon_device *rdev);
137 static void si_init_cg(struct radeon_device *rdev);
138 static void si_fini_pg(struct radeon_device *rdev);
139 static void si_fini_cg(struct radeon_device *rdev);
140 static void si_rlc_stop(struct radeon_device *rdev);
142 static const u32 verde_rlc_save_restore_register_list[] =
144 (0x8000 << 16) | (0x98f4 >> 2),
146 (0x8040 << 16) | (0x98f4 >> 2),
148 (0x8000 << 16) | (0xe80 >> 2),
150 (0x8040 << 16) | (0xe80 >> 2),
152 (0x8000 << 16) | (0x89bc >> 2),
154 (0x8040 << 16) | (0x89bc >> 2),
156 (0x8000 << 16) | (0x8c1c >> 2),
158 (0x8040 << 16) | (0x8c1c >> 2),
160 (0x9c00 << 16) | (0x98f0 >> 2),
162 (0x9c00 << 16) | (0xe7c >> 2),
164 (0x8000 << 16) | (0x9148 >> 2),
166 (0x8040 << 16) | (0x9148 >> 2),
168 (0x9c00 << 16) | (0x9150 >> 2),
170 (0x9c00 << 16) | (0x897c >> 2),
172 (0x9c00 << 16) | (0x8d8c >> 2),
174 (0x9c00 << 16) | (0xac54 >> 2),
177 (0x9c00 << 16) | (0x98f8 >> 2),
179 (0x9c00 << 16) | (0x9910 >> 2),
181 (0x9c00 << 16) | (0x9914 >> 2),
183 (0x9c00 << 16) | (0x9918 >> 2),
185 (0x9c00 << 16) | (0x991c >> 2),
187 (0x9c00 << 16) | (0x9920 >> 2),
189 (0x9c00 << 16) | (0x9924 >> 2),
191 (0x9c00 << 16) | (0x9928 >> 2),
193 (0x9c00 << 16) | (0x992c >> 2),
195 (0x9c00 << 16) | (0x9930 >> 2),
197 (0x9c00 << 16) | (0x9934 >> 2),
199 (0x9c00 << 16) | (0x9938 >> 2),
201 (0x9c00 << 16) | (0x993c >> 2),
203 (0x9c00 << 16) | (0x9940 >> 2),
205 (0x9c00 << 16) | (0x9944 >> 2),
207 (0x9c00 << 16) | (0x9948 >> 2),
209 (0x9c00 << 16) | (0x994c >> 2),
211 (0x9c00 << 16) | (0x9950 >> 2),
213 (0x9c00 << 16) | (0x9954 >> 2),
215 (0x9c00 << 16) | (0x9958 >> 2),
217 (0x9c00 << 16) | (0x995c >> 2),
219 (0x9c00 << 16) | (0x9960 >> 2),
221 (0x9c00 << 16) | (0x9964 >> 2),
223 (0x9c00 << 16) | (0x9968 >> 2),
225 (0x9c00 << 16) | (0x996c >> 2),
227 (0x9c00 << 16) | (0x9970 >> 2),
229 (0x9c00 << 16) | (0x9974 >> 2),
231 (0x9c00 << 16) | (0x9978 >> 2),
233 (0x9c00 << 16) | (0x997c >> 2),
235 (0x9c00 << 16) | (0x9980 >> 2),
237 (0x9c00 << 16) | (0x9984 >> 2),
239 (0x9c00 << 16) | (0x9988 >> 2),
241 (0x9c00 << 16) | (0x998c >> 2),
243 (0x9c00 << 16) | (0x8c00 >> 2),
245 (0x9c00 << 16) | (0x8c14 >> 2),
247 (0x9c00 << 16) | (0x8c04 >> 2),
249 (0x9c00 << 16) | (0x8c08 >> 2),
251 (0x8000 << 16) | (0x9b7c >> 2),
253 (0x8040 << 16) | (0x9b7c >> 2),
255 (0x8000 << 16) | (0xe84 >> 2),
257 (0x8040 << 16) | (0xe84 >> 2),
259 (0x8000 << 16) | (0x89c0 >> 2),
261 (0x8040 << 16) | (0x89c0 >> 2),
263 (0x8000 << 16) | (0x914c >> 2),
265 (0x8040 << 16) | (0x914c >> 2),
267 (0x8000 << 16) | (0x8c20 >> 2),
269 (0x8040 << 16) | (0x8c20 >> 2),
271 (0x8000 << 16) | (0x9354 >> 2),
273 (0x8040 << 16) | (0x9354 >> 2),
275 (0x9c00 << 16) | (0x9060 >> 2),
277 (0x9c00 << 16) | (0x9364 >> 2),
279 (0x9c00 << 16) | (0x9100 >> 2),
281 (0x9c00 << 16) | (0x913c >> 2),
283 (0x8000 << 16) | (0x90e0 >> 2),
285 (0x8000 << 16) | (0x90e4 >> 2),
287 (0x8000 << 16) | (0x90e8 >> 2),
289 (0x8040 << 16) | (0x90e0 >> 2),
291 (0x8040 << 16) | (0x90e4 >> 2),
293 (0x8040 << 16) | (0x90e8 >> 2),
295 (0x9c00 << 16) | (0x8bcc >> 2),
297 (0x9c00 << 16) | (0x8b24 >> 2),
299 (0x9c00 << 16) | (0x88c4 >> 2),
301 (0x9c00 << 16) | (0x8e50 >> 2),
303 (0x9c00 << 16) | (0x8c0c >> 2),
305 (0x9c00 << 16) | (0x8e58 >> 2),
307 (0x9c00 << 16) | (0x8e5c >> 2),
309 (0x9c00 << 16) | (0x9508 >> 2),
311 (0x9c00 << 16) | (0x950c >> 2),
313 (0x9c00 << 16) | (0x9494 >> 2),
315 (0x9c00 << 16) | (0xac0c >> 2),
317 (0x9c00 << 16) | (0xac10 >> 2),
319 (0x9c00 << 16) | (0xac14 >> 2),
321 (0x9c00 << 16) | (0xae00 >> 2),
323 (0x9c00 << 16) | (0xac08 >> 2),
325 (0x9c00 << 16) | (0x88d4 >> 2),
327 (0x9c00 << 16) | (0x88c8 >> 2),
329 (0x9c00 << 16) | (0x88cc >> 2),
331 (0x9c00 << 16) | (0x89b0 >> 2),
333 (0x9c00 << 16) | (0x8b10 >> 2),
335 (0x9c00 << 16) | (0x8a14 >> 2),
337 (0x9c00 << 16) | (0x9830 >> 2),
339 (0x9c00 << 16) | (0x9834 >> 2),
341 (0x9c00 << 16) | (0x9838 >> 2),
343 (0x9c00 << 16) | (0x9a10 >> 2),
345 (0x8000 << 16) | (0x9870 >> 2),
347 (0x8000 << 16) | (0x9874 >> 2),
349 (0x8001 << 16) | (0x9870 >> 2),
351 (0x8001 << 16) | (0x9874 >> 2),
353 (0x8040 << 16) | (0x9870 >> 2),
355 (0x8040 << 16) | (0x9874 >> 2),
357 (0x8041 << 16) | (0x9870 >> 2),
359 (0x8041 << 16) | (0x9874 >> 2),
364 static const u32 tahiti_golden_rlc_registers[] =
366 0xc424, 0xffffffff, 0x00601005,
367 0xc47c, 0xffffffff, 0x10104040,
368 0xc488, 0xffffffff, 0x0100000a,
369 0xc314, 0xffffffff, 0x00000800,
370 0xc30c, 0xffffffff, 0x800000f4,
371 0xf4a8, 0xffffffff, 0x00000000
374 static const u32 tahiti_golden_registers[] =
376 0x9a10, 0x00010000, 0x00018208,
377 0x9830, 0xffffffff, 0x00000000,
378 0x9834, 0xf00fffff, 0x00000400,
379 0x9838, 0x0002021c, 0x00020200,
380 0xc78, 0x00000080, 0x00000000,
381 0xd030, 0x000300c0, 0x00800040,
382 0xd830, 0x000300c0, 0x00800040,
383 0x5bb0, 0x000000f0, 0x00000070,
384 0x5bc0, 0x00200000, 0x50100000,
385 0x7030, 0x31000311, 0x00000011,
386 0x277c, 0x00000003, 0x000007ff,
387 0x240c, 0x000007ff, 0x00000000,
388 0x8a14, 0xf000001f, 0x00000007,
389 0x8b24, 0xffffffff, 0x00ffffff,
390 0x8b10, 0x0000ff0f, 0x00000000,
391 0x28a4c, 0x07ffffff, 0x4e000000,
392 0x28350, 0x3f3f3fff, 0x2a00126a,
393 0x30, 0x000000ff, 0x0040,
394 0x34, 0x00000040, 0x00004040,
395 0x9100, 0x07ffffff, 0x03000000,
396 0x8e88, 0x01ff1f3f, 0x00000000,
397 0x8e84, 0x01ff1f3f, 0x00000000,
398 0x9060, 0x0000007f, 0x00000020,
399 0x9508, 0x00010000, 0x00010000,
400 0xac14, 0x00000200, 0x000002fb,
401 0xac10, 0xffffffff, 0x0000543b,
402 0xac0c, 0xffffffff, 0xa9210876,
403 0x88d0, 0xffffffff, 0x000fff40,
404 0x88d4, 0x0000001f, 0x00000010,
405 0x1410, 0x20000000, 0x20fffed8,
406 0x15c0, 0x000c0fc0, 0x000c0400
409 static const u32 tahiti_golden_registers2[] =
411 0xc64, 0x00000001, 0x00000001
414 static const u32 pitcairn_golden_rlc_registers[] =
416 0xc424, 0xffffffff, 0x00601004,
417 0xc47c, 0xffffffff, 0x10102020,
418 0xc488, 0xffffffff, 0x01000020,
419 0xc314, 0xffffffff, 0x00000800,
420 0xc30c, 0xffffffff, 0x800000a4
423 static const u32 pitcairn_golden_registers[] =
425 0x9a10, 0x00010000, 0x00018208,
426 0x9830, 0xffffffff, 0x00000000,
427 0x9834, 0xf00fffff, 0x00000400,
428 0x9838, 0x0002021c, 0x00020200,
429 0xc78, 0x00000080, 0x00000000,
430 0xd030, 0x000300c0, 0x00800040,
431 0xd830, 0x000300c0, 0x00800040,
432 0x5bb0, 0x000000f0, 0x00000070,
433 0x5bc0, 0x00200000, 0x50100000,
434 0x7030, 0x31000311, 0x00000011,
435 0x2ae4, 0x00073ffe, 0x000022a2,
436 0x240c, 0x000007ff, 0x00000000,
437 0x8a14, 0xf000001f, 0x00000007,
438 0x8b24, 0xffffffff, 0x00ffffff,
439 0x8b10, 0x0000ff0f, 0x00000000,
440 0x28a4c, 0x07ffffff, 0x4e000000,
441 0x28350, 0x3f3f3fff, 0x2a00126a,
442 0x30, 0x000000ff, 0x0040,
443 0x34, 0x00000040, 0x00004040,
444 0x9100, 0x07ffffff, 0x03000000,
445 0x9060, 0x0000007f, 0x00000020,
446 0x9508, 0x00010000, 0x00010000,
447 0xac14, 0x000003ff, 0x000000f7,
448 0xac10, 0xffffffff, 0x00000000,
449 0xac0c, 0xffffffff, 0x32761054,
450 0x88d4, 0x0000001f, 0x00000010,
451 0x15c0, 0x000c0fc0, 0x000c0400
454 static const u32 verde_golden_rlc_registers[] =
456 0xc424, 0xffffffff, 0x033f1005,
457 0xc47c, 0xffffffff, 0x10808020,
458 0xc488, 0xffffffff, 0x00800008,
459 0xc314, 0xffffffff, 0x00001000,
460 0xc30c, 0xffffffff, 0x80010014
463 static const u32 verde_golden_registers[] =
465 0x9a10, 0x00010000, 0x00018208,
466 0x9830, 0xffffffff, 0x00000000,
467 0x9834, 0xf00fffff, 0x00000400,
468 0x9838, 0x0002021c, 0x00020200,
469 0xc78, 0x00000080, 0x00000000,
470 0xd030, 0x000300c0, 0x00800040,
471 0xd030, 0x000300c0, 0x00800040,
472 0xd830, 0x000300c0, 0x00800040,
473 0xd830, 0x000300c0, 0x00800040,
474 0x5bb0, 0x000000f0, 0x00000070,
475 0x5bc0, 0x00200000, 0x50100000,
476 0x7030, 0x31000311, 0x00000011,
477 0x2ae4, 0x00073ffe, 0x000022a2,
478 0x2ae4, 0x00073ffe, 0x000022a2,
479 0x2ae4, 0x00073ffe, 0x000022a2,
480 0x240c, 0x000007ff, 0x00000000,
481 0x240c, 0x000007ff, 0x00000000,
482 0x240c, 0x000007ff, 0x00000000,
483 0x8a14, 0xf000001f, 0x00000007,
484 0x8a14, 0xf000001f, 0x00000007,
485 0x8a14, 0xf000001f, 0x00000007,
486 0x8b24, 0xffffffff, 0x00ffffff,
487 0x8b10, 0x0000ff0f, 0x00000000,
488 0x28a4c, 0x07ffffff, 0x4e000000,
489 0x28350, 0x3f3f3fff, 0x0000124a,
490 0x28350, 0x3f3f3fff, 0x0000124a,
491 0x28350, 0x3f3f3fff, 0x0000124a,
492 0x30, 0x000000ff, 0x0040,
493 0x34, 0x00000040, 0x00004040,
494 0x9100, 0x07ffffff, 0x03000000,
495 0x9100, 0x07ffffff, 0x03000000,
496 0x8e88, 0x01ff1f3f, 0x00000000,
497 0x8e88, 0x01ff1f3f, 0x00000000,
498 0x8e88, 0x01ff1f3f, 0x00000000,
499 0x8e84, 0x01ff1f3f, 0x00000000,
500 0x8e84, 0x01ff1f3f, 0x00000000,
501 0x8e84, 0x01ff1f3f, 0x00000000,
502 0x9060, 0x0000007f, 0x00000020,
503 0x9508, 0x00010000, 0x00010000,
504 0xac14, 0x000003ff, 0x00000003,
505 0xac14, 0x000003ff, 0x00000003,
506 0xac14, 0x000003ff, 0x00000003,
507 0xac10, 0xffffffff, 0x00000000,
508 0xac10, 0xffffffff, 0x00000000,
509 0xac10, 0xffffffff, 0x00000000,
510 0xac0c, 0xffffffff, 0x00001032,
511 0xac0c, 0xffffffff, 0x00001032,
512 0xac0c, 0xffffffff, 0x00001032,
513 0x88d4, 0x0000001f, 0x00000010,
514 0x88d4, 0x0000001f, 0x00000010,
515 0x88d4, 0x0000001f, 0x00000010,
516 0x15c0, 0x000c0fc0, 0x000c0400
519 static const u32 oland_golden_rlc_registers[] =
521 0xc424, 0xffffffff, 0x00601005,
522 0xc47c, 0xffffffff, 0x10104040,
523 0xc488, 0xffffffff, 0x0100000a,
524 0xc314, 0xffffffff, 0x00000800,
525 0xc30c, 0xffffffff, 0x800000f4
528 static const u32 oland_golden_registers[] =
530 0x9a10, 0x00010000, 0x00018208,
531 0x9830, 0xffffffff, 0x00000000,
532 0x9834, 0xf00fffff, 0x00000400,
533 0x9838, 0x0002021c, 0x00020200,
534 0xc78, 0x00000080, 0x00000000,
535 0xd030, 0x000300c0, 0x00800040,
536 0xd830, 0x000300c0, 0x00800040,
537 0x5bb0, 0x000000f0, 0x00000070,
538 0x5bc0, 0x00200000, 0x50100000,
539 0x7030, 0x31000311, 0x00000011,
540 0x2ae4, 0x00073ffe, 0x000022a2,
541 0x240c, 0x000007ff, 0x00000000,
542 0x8a14, 0xf000001f, 0x00000007,
543 0x8b24, 0xffffffff, 0x00ffffff,
544 0x8b10, 0x0000ff0f, 0x00000000,
545 0x28a4c, 0x07ffffff, 0x4e000000,
546 0x28350, 0x3f3f3fff, 0x00000082,
547 0x30, 0x000000ff, 0x0040,
548 0x34, 0x00000040, 0x00004040,
549 0x9100, 0x07ffffff, 0x03000000,
550 0x9060, 0x0000007f, 0x00000020,
551 0x9508, 0x00010000, 0x00010000,
552 0xac14, 0x000003ff, 0x000000f3,
553 0xac10, 0xffffffff, 0x00000000,
554 0xac0c, 0xffffffff, 0x00003210,
555 0x88d4, 0x0000001f, 0x00000010,
556 0x15c0, 0x000c0fc0, 0x000c0400
559 static const u32 hainan_golden_registers[] =
561 0x9a10, 0x00010000, 0x00018208,
562 0x9830, 0xffffffff, 0x00000000,
563 0x9834, 0xf00fffff, 0x00000400,
564 0x9838, 0x0002021c, 0x00020200,
565 0xd0c0, 0xff000fff, 0x00000100,
566 0xd030, 0x000300c0, 0x00800040,
567 0xd8c0, 0xff000fff, 0x00000100,
568 0xd830, 0x000300c0, 0x00800040,
569 0x2ae4, 0x00073ffe, 0x000022a2,
570 0x240c, 0x000007ff, 0x00000000,
571 0x8a14, 0xf000001f, 0x00000007,
572 0x8b24, 0xffffffff, 0x00ffffff,
573 0x8b10, 0x0000ff0f, 0x00000000,
574 0x28a4c, 0x07ffffff, 0x4e000000,
575 0x28350, 0x3f3f3fff, 0x00000000,
576 0x30, 0x000000ff, 0x0040,
577 0x34, 0x00000040, 0x00004040,
578 0x9100, 0x03e00000, 0x03600000,
579 0x9060, 0x0000007f, 0x00000020,
580 0x9508, 0x00010000, 0x00010000,
581 0xac14, 0x000003ff, 0x000000f1,
582 0xac10, 0xffffffff, 0x00000000,
583 0xac0c, 0xffffffff, 0x00003210,
584 0x88d4, 0x0000001f, 0x00000010,
585 0x15c0, 0x000c0fc0, 0x000c0400
588 static const u32 hainan_golden_registers2[] =
590 0x98f8, 0xffffffff, 0x02010001
593 static const u32 tahiti_mgcg_cgcg_init[] =
595 0xc400, 0xffffffff, 0xfffffffc,
596 0x802c, 0xffffffff, 0xe0000000,
597 0x9a60, 0xffffffff, 0x00000100,
598 0x92a4, 0xffffffff, 0x00000100,
599 0xc164, 0xffffffff, 0x00000100,
600 0x9774, 0xffffffff, 0x00000100,
601 0x8984, 0xffffffff, 0x06000100,
602 0x8a18, 0xffffffff, 0x00000100,
603 0x92a0, 0xffffffff, 0x00000100,
604 0xc380, 0xffffffff, 0x00000100,
605 0x8b28, 0xffffffff, 0x00000100,
606 0x9144, 0xffffffff, 0x00000100,
607 0x8d88, 0xffffffff, 0x00000100,
608 0x8d8c, 0xffffffff, 0x00000100,
609 0x9030, 0xffffffff, 0x00000100,
610 0x9034, 0xffffffff, 0x00000100,
611 0x9038, 0xffffffff, 0x00000100,
612 0x903c, 0xffffffff, 0x00000100,
613 0xad80, 0xffffffff, 0x00000100,
614 0xac54, 0xffffffff, 0x00000100,
615 0x897c, 0xffffffff, 0x06000100,
616 0x9868, 0xffffffff, 0x00000100,
617 0x9510, 0xffffffff, 0x00000100,
618 0xaf04, 0xffffffff, 0x00000100,
619 0xae04, 0xffffffff, 0x00000100,
620 0x949c, 0xffffffff, 0x00000100,
621 0x802c, 0xffffffff, 0xe0000000,
622 0x9160, 0xffffffff, 0x00010000,
623 0x9164, 0xffffffff, 0x00030002,
624 0x9168, 0xffffffff, 0x00040007,
625 0x916c, 0xffffffff, 0x00060005,
626 0x9170, 0xffffffff, 0x00090008,
627 0x9174, 0xffffffff, 0x00020001,
628 0x9178, 0xffffffff, 0x00040003,
629 0x917c, 0xffffffff, 0x00000007,
630 0x9180, 0xffffffff, 0x00060005,
631 0x9184, 0xffffffff, 0x00090008,
632 0x9188, 0xffffffff, 0x00030002,
633 0x918c, 0xffffffff, 0x00050004,
634 0x9190, 0xffffffff, 0x00000008,
635 0x9194, 0xffffffff, 0x00070006,
636 0x9198, 0xffffffff, 0x000a0009,
637 0x919c, 0xffffffff, 0x00040003,
638 0x91a0, 0xffffffff, 0x00060005,
639 0x91a4, 0xffffffff, 0x00000009,
640 0x91a8, 0xffffffff, 0x00080007,
641 0x91ac, 0xffffffff, 0x000b000a,
642 0x91b0, 0xffffffff, 0x00050004,
643 0x91b4, 0xffffffff, 0x00070006,
644 0x91b8, 0xffffffff, 0x0008000b,
645 0x91bc, 0xffffffff, 0x000a0009,
646 0x91c0, 0xffffffff, 0x000d000c,
647 0x91c4, 0xffffffff, 0x00060005,
648 0x91c8, 0xffffffff, 0x00080007,
649 0x91cc, 0xffffffff, 0x0000000b,
650 0x91d0, 0xffffffff, 0x000a0009,
651 0x91d4, 0xffffffff, 0x000d000c,
652 0x91d8, 0xffffffff, 0x00070006,
653 0x91dc, 0xffffffff, 0x00090008,
654 0x91e0, 0xffffffff, 0x0000000c,
655 0x91e4, 0xffffffff, 0x000b000a,
656 0x91e8, 0xffffffff, 0x000e000d,
657 0x91ec, 0xffffffff, 0x00080007,
658 0x91f0, 0xffffffff, 0x000a0009,
659 0x91f4, 0xffffffff, 0x0000000d,
660 0x91f8, 0xffffffff, 0x000c000b,
661 0x91fc, 0xffffffff, 0x000f000e,
662 0x9200, 0xffffffff, 0x00090008,
663 0x9204, 0xffffffff, 0x000b000a,
664 0x9208, 0xffffffff, 0x000c000f,
665 0x920c, 0xffffffff, 0x000e000d,
666 0x9210, 0xffffffff, 0x00110010,
667 0x9214, 0xffffffff, 0x000a0009,
668 0x9218, 0xffffffff, 0x000c000b,
669 0x921c, 0xffffffff, 0x0000000f,
670 0x9220, 0xffffffff, 0x000e000d,
671 0x9224, 0xffffffff, 0x00110010,
672 0x9228, 0xffffffff, 0x000b000a,
673 0x922c, 0xffffffff, 0x000d000c,
674 0x9230, 0xffffffff, 0x00000010,
675 0x9234, 0xffffffff, 0x000f000e,
676 0x9238, 0xffffffff, 0x00120011,
677 0x923c, 0xffffffff, 0x000c000b,
678 0x9240, 0xffffffff, 0x000e000d,
679 0x9244, 0xffffffff, 0x00000011,
680 0x9248, 0xffffffff, 0x0010000f,
681 0x924c, 0xffffffff, 0x00130012,
682 0x9250, 0xffffffff, 0x000d000c,
683 0x9254, 0xffffffff, 0x000f000e,
684 0x9258, 0xffffffff, 0x00100013,
685 0x925c, 0xffffffff, 0x00120011,
686 0x9260, 0xffffffff, 0x00150014,
687 0x9264, 0xffffffff, 0x000e000d,
688 0x9268, 0xffffffff, 0x0010000f,
689 0x926c, 0xffffffff, 0x00000013,
690 0x9270, 0xffffffff, 0x00120011,
691 0x9274, 0xffffffff, 0x00150014,
692 0x9278, 0xffffffff, 0x000f000e,
693 0x927c, 0xffffffff, 0x00110010,
694 0x9280, 0xffffffff, 0x00000014,
695 0x9284, 0xffffffff, 0x00130012,
696 0x9288, 0xffffffff, 0x00160015,
697 0x928c, 0xffffffff, 0x0010000f,
698 0x9290, 0xffffffff, 0x00120011,
699 0x9294, 0xffffffff, 0x00000015,
700 0x9298, 0xffffffff, 0x00140013,
701 0x929c, 0xffffffff, 0x00170016,
702 0x9150, 0xffffffff, 0x96940200,
703 0x8708, 0xffffffff, 0x00900100,
704 0xc478, 0xffffffff, 0x00000080,
705 0xc404, 0xffffffff, 0x0020003f,
706 0x30, 0xffffffff, 0x0000001c,
707 0x34, 0x000f0000, 0x000f0000,
708 0x160c, 0xffffffff, 0x00000100,
709 0x1024, 0xffffffff, 0x00000100,
710 0x102c, 0x00000101, 0x00000000,
711 0x20a8, 0xffffffff, 0x00000104,
712 0x264c, 0x000c0000, 0x000c0000,
713 0x2648, 0x000c0000, 0x000c0000,
714 0x55e4, 0xff000fff, 0x00000100,
715 0x55e8, 0x00000001, 0x00000001,
716 0x2f50, 0x00000001, 0x00000001,
717 0x30cc, 0xc0000fff, 0x00000104,
718 0xc1e4, 0x00000001, 0x00000001,
719 0xd0c0, 0xfffffff0, 0x00000100,
720 0xd8c0, 0xfffffff0, 0x00000100
723 static const u32 pitcairn_mgcg_cgcg_init[] =
725 0xc400, 0xffffffff, 0xfffffffc,
726 0x802c, 0xffffffff, 0xe0000000,
727 0x9a60, 0xffffffff, 0x00000100,
728 0x92a4, 0xffffffff, 0x00000100,
729 0xc164, 0xffffffff, 0x00000100,
730 0x9774, 0xffffffff, 0x00000100,
731 0x8984, 0xffffffff, 0x06000100,
732 0x8a18, 0xffffffff, 0x00000100,
733 0x92a0, 0xffffffff, 0x00000100,
734 0xc380, 0xffffffff, 0x00000100,
735 0x8b28, 0xffffffff, 0x00000100,
736 0x9144, 0xffffffff, 0x00000100,
737 0x8d88, 0xffffffff, 0x00000100,
738 0x8d8c, 0xffffffff, 0x00000100,
739 0x9030, 0xffffffff, 0x00000100,
740 0x9034, 0xffffffff, 0x00000100,
741 0x9038, 0xffffffff, 0x00000100,
742 0x903c, 0xffffffff, 0x00000100,
743 0xad80, 0xffffffff, 0x00000100,
744 0xac54, 0xffffffff, 0x00000100,
745 0x897c, 0xffffffff, 0x06000100,
746 0x9868, 0xffffffff, 0x00000100,
747 0x9510, 0xffffffff, 0x00000100,
748 0xaf04, 0xffffffff, 0x00000100,
749 0xae04, 0xffffffff, 0x00000100,
750 0x949c, 0xffffffff, 0x00000100,
751 0x802c, 0xffffffff, 0xe0000000,
752 0x9160, 0xffffffff, 0x00010000,
753 0x9164, 0xffffffff, 0x00030002,
754 0x9168, 0xffffffff, 0x00040007,
755 0x916c, 0xffffffff, 0x00060005,
756 0x9170, 0xffffffff, 0x00090008,
757 0x9174, 0xffffffff, 0x00020001,
758 0x9178, 0xffffffff, 0x00040003,
759 0x917c, 0xffffffff, 0x00000007,
760 0x9180, 0xffffffff, 0x00060005,
761 0x9184, 0xffffffff, 0x00090008,
762 0x9188, 0xffffffff, 0x00030002,
763 0x918c, 0xffffffff, 0x00050004,
764 0x9190, 0xffffffff, 0x00000008,
765 0x9194, 0xffffffff, 0x00070006,
766 0x9198, 0xffffffff, 0x000a0009,
767 0x919c, 0xffffffff, 0x00040003,
768 0x91a0, 0xffffffff, 0x00060005,
769 0x91a4, 0xffffffff, 0x00000009,
770 0x91a8, 0xffffffff, 0x00080007,
771 0x91ac, 0xffffffff, 0x000b000a,
772 0x91b0, 0xffffffff, 0x00050004,
773 0x91b4, 0xffffffff, 0x00070006,
774 0x91b8, 0xffffffff, 0x0008000b,
775 0x91bc, 0xffffffff, 0x000a0009,
776 0x91c0, 0xffffffff, 0x000d000c,
777 0x9200, 0xffffffff, 0x00090008,
778 0x9204, 0xffffffff, 0x000b000a,
779 0x9208, 0xffffffff, 0x000c000f,
780 0x920c, 0xffffffff, 0x000e000d,
781 0x9210, 0xffffffff, 0x00110010,
782 0x9214, 0xffffffff, 0x000a0009,
783 0x9218, 0xffffffff, 0x000c000b,
784 0x921c, 0xffffffff, 0x0000000f,
785 0x9220, 0xffffffff, 0x000e000d,
786 0x9224, 0xffffffff, 0x00110010,
787 0x9228, 0xffffffff, 0x000b000a,
788 0x922c, 0xffffffff, 0x000d000c,
789 0x9230, 0xffffffff, 0x00000010,
790 0x9234, 0xffffffff, 0x000f000e,
791 0x9238, 0xffffffff, 0x00120011,
792 0x923c, 0xffffffff, 0x000c000b,
793 0x9240, 0xffffffff, 0x000e000d,
794 0x9244, 0xffffffff, 0x00000011,
795 0x9248, 0xffffffff, 0x0010000f,
796 0x924c, 0xffffffff, 0x00130012,
797 0x9250, 0xffffffff, 0x000d000c,
798 0x9254, 0xffffffff, 0x000f000e,
799 0x9258, 0xffffffff, 0x00100013,
800 0x925c, 0xffffffff, 0x00120011,
801 0x9260, 0xffffffff, 0x00150014,
802 0x9150, 0xffffffff, 0x96940200,
803 0x8708, 0xffffffff, 0x00900100,
804 0xc478, 0xffffffff, 0x00000080,
805 0xc404, 0xffffffff, 0x0020003f,
806 0x30, 0xffffffff, 0x0000001c,
807 0x34, 0x000f0000, 0x000f0000,
808 0x160c, 0xffffffff, 0x00000100,
809 0x1024, 0xffffffff, 0x00000100,
810 0x102c, 0x00000101, 0x00000000,
811 0x20a8, 0xffffffff, 0x00000104,
812 0x55e4, 0xff000fff, 0x00000100,
813 0x55e8, 0x00000001, 0x00000001,
814 0x2f50, 0x00000001, 0x00000001,
815 0x30cc, 0xc0000fff, 0x00000104,
816 0xc1e4, 0x00000001, 0x00000001,
817 0xd0c0, 0xfffffff0, 0x00000100,
818 0xd8c0, 0xfffffff0, 0x00000100
821 static const u32 verde_mgcg_cgcg_init[] =
823 0xc400, 0xffffffff, 0xfffffffc,
824 0x802c, 0xffffffff, 0xe0000000,
825 0x9a60, 0xffffffff, 0x00000100,
826 0x92a4, 0xffffffff, 0x00000100,
827 0xc164, 0xffffffff, 0x00000100,
828 0x9774, 0xffffffff, 0x00000100,
829 0x8984, 0xffffffff, 0x06000100,
830 0x8a18, 0xffffffff, 0x00000100,
831 0x92a0, 0xffffffff, 0x00000100,
832 0xc380, 0xffffffff, 0x00000100,
833 0x8b28, 0xffffffff, 0x00000100,
834 0x9144, 0xffffffff, 0x00000100,
835 0x8d88, 0xffffffff, 0x00000100,
836 0x8d8c, 0xffffffff, 0x00000100,
837 0x9030, 0xffffffff, 0x00000100,
838 0x9034, 0xffffffff, 0x00000100,
839 0x9038, 0xffffffff, 0x00000100,
840 0x903c, 0xffffffff, 0x00000100,
841 0xad80, 0xffffffff, 0x00000100,
842 0xac54, 0xffffffff, 0x00000100,
843 0x897c, 0xffffffff, 0x06000100,
844 0x9868, 0xffffffff, 0x00000100,
845 0x9510, 0xffffffff, 0x00000100,
846 0xaf04, 0xffffffff, 0x00000100,
847 0xae04, 0xffffffff, 0x00000100,
848 0x949c, 0xffffffff, 0x00000100,
849 0x802c, 0xffffffff, 0xe0000000,
850 0x9160, 0xffffffff, 0x00010000,
851 0x9164, 0xffffffff, 0x00030002,
852 0x9168, 0xffffffff, 0x00040007,
853 0x916c, 0xffffffff, 0x00060005,
854 0x9170, 0xffffffff, 0x00090008,
855 0x9174, 0xffffffff, 0x00020001,
856 0x9178, 0xffffffff, 0x00040003,
857 0x917c, 0xffffffff, 0x00000007,
858 0x9180, 0xffffffff, 0x00060005,
859 0x9184, 0xffffffff, 0x00090008,
860 0x9188, 0xffffffff, 0x00030002,
861 0x918c, 0xffffffff, 0x00050004,
862 0x9190, 0xffffffff, 0x00000008,
863 0x9194, 0xffffffff, 0x00070006,
864 0x9198, 0xffffffff, 0x000a0009,
865 0x919c, 0xffffffff, 0x00040003,
866 0x91a0, 0xffffffff, 0x00060005,
867 0x91a4, 0xffffffff, 0x00000009,
868 0x91a8, 0xffffffff, 0x00080007,
869 0x91ac, 0xffffffff, 0x000b000a,
870 0x91b0, 0xffffffff, 0x00050004,
871 0x91b4, 0xffffffff, 0x00070006,
872 0x91b8, 0xffffffff, 0x0008000b,
873 0x91bc, 0xffffffff, 0x000a0009,
874 0x91c0, 0xffffffff, 0x000d000c,
875 0x9200, 0xffffffff, 0x00090008,
876 0x9204, 0xffffffff, 0x000b000a,
877 0x9208, 0xffffffff, 0x000c000f,
878 0x920c, 0xffffffff, 0x000e000d,
879 0x9210, 0xffffffff, 0x00110010,
880 0x9214, 0xffffffff, 0x000a0009,
881 0x9218, 0xffffffff, 0x000c000b,
882 0x921c, 0xffffffff, 0x0000000f,
883 0x9220, 0xffffffff, 0x000e000d,
884 0x9224, 0xffffffff, 0x00110010,
885 0x9228, 0xffffffff, 0x000b000a,
886 0x922c, 0xffffffff, 0x000d000c,
887 0x9230, 0xffffffff, 0x00000010,
888 0x9234, 0xffffffff, 0x000f000e,
889 0x9238, 0xffffffff, 0x00120011,
890 0x923c, 0xffffffff, 0x000c000b,
891 0x9240, 0xffffffff, 0x000e000d,
892 0x9244, 0xffffffff, 0x00000011,
893 0x9248, 0xffffffff, 0x0010000f,
894 0x924c, 0xffffffff, 0x00130012,
895 0x9250, 0xffffffff, 0x000d000c,
896 0x9254, 0xffffffff, 0x000f000e,
897 0x9258, 0xffffffff, 0x00100013,
898 0x925c, 0xffffffff, 0x00120011,
899 0x9260, 0xffffffff, 0x00150014,
900 0x9150, 0xffffffff, 0x96940200,
901 0x8708, 0xffffffff, 0x00900100,
902 0xc478, 0xffffffff, 0x00000080,
903 0xc404, 0xffffffff, 0x0020003f,
904 0x30, 0xffffffff, 0x0000001c,
905 0x34, 0x000f0000, 0x000f0000,
906 0x160c, 0xffffffff, 0x00000100,
907 0x1024, 0xffffffff, 0x00000100,
908 0x102c, 0x00000101, 0x00000000,
909 0x20a8, 0xffffffff, 0x00000104,
910 0x264c, 0x000c0000, 0x000c0000,
911 0x2648, 0x000c0000, 0x000c0000,
912 0x55e4, 0xff000fff, 0x00000100,
913 0x55e8, 0x00000001, 0x00000001,
914 0x2f50, 0x00000001, 0x00000001,
915 0x30cc, 0xc0000fff, 0x00000104,
916 0xc1e4, 0x00000001, 0x00000001,
917 0xd0c0, 0xfffffff0, 0x00000100,
918 0xd8c0, 0xfffffff0, 0x00000100
921 static const u32 oland_mgcg_cgcg_init[] =
923 0xc400, 0xffffffff, 0xfffffffc,
924 0x802c, 0xffffffff, 0xe0000000,
925 0x9a60, 0xffffffff, 0x00000100,
926 0x92a4, 0xffffffff, 0x00000100,
927 0xc164, 0xffffffff, 0x00000100,
928 0x9774, 0xffffffff, 0x00000100,
929 0x8984, 0xffffffff, 0x06000100,
930 0x8a18, 0xffffffff, 0x00000100,
931 0x92a0, 0xffffffff, 0x00000100,
932 0xc380, 0xffffffff, 0x00000100,
933 0x8b28, 0xffffffff, 0x00000100,
934 0x9144, 0xffffffff, 0x00000100,
935 0x8d88, 0xffffffff, 0x00000100,
936 0x8d8c, 0xffffffff, 0x00000100,
937 0x9030, 0xffffffff, 0x00000100,
938 0x9034, 0xffffffff, 0x00000100,
939 0x9038, 0xffffffff, 0x00000100,
940 0x903c, 0xffffffff, 0x00000100,
941 0xad80, 0xffffffff, 0x00000100,
942 0xac54, 0xffffffff, 0x00000100,
943 0x897c, 0xffffffff, 0x06000100,
944 0x9868, 0xffffffff, 0x00000100,
945 0x9510, 0xffffffff, 0x00000100,
946 0xaf04, 0xffffffff, 0x00000100,
947 0xae04, 0xffffffff, 0x00000100,
948 0x949c, 0xffffffff, 0x00000100,
949 0x802c, 0xffffffff, 0xe0000000,
950 0x9160, 0xffffffff, 0x00010000,
951 0x9164, 0xffffffff, 0x00030002,
952 0x9168, 0xffffffff, 0x00040007,
953 0x916c, 0xffffffff, 0x00060005,
954 0x9170, 0xffffffff, 0x00090008,
955 0x9174, 0xffffffff, 0x00020001,
956 0x9178, 0xffffffff, 0x00040003,
957 0x917c, 0xffffffff, 0x00000007,
958 0x9180, 0xffffffff, 0x00060005,
959 0x9184, 0xffffffff, 0x00090008,
960 0x9188, 0xffffffff, 0x00030002,
961 0x918c, 0xffffffff, 0x00050004,
962 0x9190, 0xffffffff, 0x00000008,
963 0x9194, 0xffffffff, 0x00070006,
964 0x9198, 0xffffffff, 0x000a0009,
965 0x919c, 0xffffffff, 0x00040003,
966 0x91a0, 0xffffffff, 0x00060005,
967 0x91a4, 0xffffffff, 0x00000009,
968 0x91a8, 0xffffffff, 0x00080007,
969 0x91ac, 0xffffffff, 0x000b000a,
970 0x91b0, 0xffffffff, 0x00050004,
971 0x91b4, 0xffffffff, 0x00070006,
972 0x91b8, 0xffffffff, 0x0008000b,
973 0x91bc, 0xffffffff, 0x000a0009,
974 0x91c0, 0xffffffff, 0x000d000c,
975 0x91c4, 0xffffffff, 0x00060005,
976 0x91c8, 0xffffffff, 0x00080007,
977 0x91cc, 0xffffffff, 0x0000000b,
978 0x91d0, 0xffffffff, 0x000a0009,
979 0x91d4, 0xffffffff, 0x000d000c,
980 0x9150, 0xffffffff, 0x96940200,
981 0x8708, 0xffffffff, 0x00900100,
982 0xc478, 0xffffffff, 0x00000080,
983 0xc404, 0xffffffff, 0x0020003f,
984 0x30, 0xffffffff, 0x0000001c,
985 0x34, 0x000f0000, 0x000f0000,
986 0x160c, 0xffffffff, 0x00000100,
987 0x1024, 0xffffffff, 0x00000100,
988 0x102c, 0x00000101, 0x00000000,
989 0x20a8, 0xffffffff, 0x00000104,
990 0x264c, 0x000c0000, 0x000c0000,
991 0x2648, 0x000c0000, 0x000c0000,
992 0x55e4, 0xff000fff, 0x00000100,
993 0x55e8, 0x00000001, 0x00000001,
994 0x2f50, 0x00000001, 0x00000001,
995 0x30cc, 0xc0000fff, 0x00000104,
996 0xc1e4, 0x00000001, 0x00000001,
997 0xd0c0, 0xfffffff0, 0x00000100,
998 0xd8c0, 0xfffffff0, 0x00000100
1001 static const u32 hainan_mgcg_cgcg_init[] =
1003 0xc400, 0xffffffff, 0xfffffffc,
1004 0x802c, 0xffffffff, 0xe0000000,
1005 0x9a60, 0xffffffff, 0x00000100,
1006 0x92a4, 0xffffffff, 0x00000100,
1007 0xc164, 0xffffffff, 0x00000100,
1008 0x9774, 0xffffffff, 0x00000100,
1009 0x8984, 0xffffffff, 0x06000100,
1010 0x8a18, 0xffffffff, 0x00000100,
1011 0x92a0, 0xffffffff, 0x00000100,
1012 0xc380, 0xffffffff, 0x00000100,
1013 0x8b28, 0xffffffff, 0x00000100,
1014 0x9144, 0xffffffff, 0x00000100,
1015 0x8d88, 0xffffffff, 0x00000100,
1016 0x8d8c, 0xffffffff, 0x00000100,
1017 0x9030, 0xffffffff, 0x00000100,
1018 0x9034, 0xffffffff, 0x00000100,
1019 0x9038, 0xffffffff, 0x00000100,
1020 0x903c, 0xffffffff, 0x00000100,
1021 0xad80, 0xffffffff, 0x00000100,
1022 0xac54, 0xffffffff, 0x00000100,
1023 0x897c, 0xffffffff, 0x06000100,
1024 0x9868, 0xffffffff, 0x00000100,
1025 0x9510, 0xffffffff, 0x00000100,
1026 0xaf04, 0xffffffff, 0x00000100,
1027 0xae04, 0xffffffff, 0x00000100,
1028 0x949c, 0xffffffff, 0x00000100,
1029 0x802c, 0xffffffff, 0xe0000000,
1030 0x9160, 0xffffffff, 0x00010000,
1031 0x9164, 0xffffffff, 0x00030002,
1032 0x9168, 0xffffffff, 0x00040007,
1033 0x916c, 0xffffffff, 0x00060005,
1034 0x9170, 0xffffffff, 0x00090008,
1035 0x9174, 0xffffffff, 0x00020001,
1036 0x9178, 0xffffffff, 0x00040003,
1037 0x917c, 0xffffffff, 0x00000007,
1038 0x9180, 0xffffffff, 0x00060005,
1039 0x9184, 0xffffffff, 0x00090008,
1040 0x9188, 0xffffffff, 0x00030002,
1041 0x918c, 0xffffffff, 0x00050004,
1042 0x9190, 0xffffffff, 0x00000008,
1043 0x9194, 0xffffffff, 0x00070006,
1044 0x9198, 0xffffffff, 0x000a0009,
1045 0x919c, 0xffffffff, 0x00040003,
1046 0x91a0, 0xffffffff, 0x00060005,
1047 0x91a4, 0xffffffff, 0x00000009,
1048 0x91a8, 0xffffffff, 0x00080007,
1049 0x91ac, 0xffffffff, 0x000b000a,
1050 0x91b0, 0xffffffff, 0x00050004,
1051 0x91b4, 0xffffffff, 0x00070006,
1052 0x91b8, 0xffffffff, 0x0008000b,
1053 0x91bc, 0xffffffff, 0x000a0009,
1054 0x91c0, 0xffffffff, 0x000d000c,
1055 0x91c4, 0xffffffff, 0x00060005,
1056 0x91c8, 0xffffffff, 0x00080007,
1057 0x91cc, 0xffffffff, 0x0000000b,
1058 0x91d0, 0xffffffff, 0x000a0009,
1059 0x91d4, 0xffffffff, 0x000d000c,
1060 0x9150, 0xffffffff, 0x96940200,
1061 0x8708, 0xffffffff, 0x00900100,
1062 0xc478, 0xffffffff, 0x00000080,
1063 0xc404, 0xffffffff, 0x0020003f,
1064 0x30, 0xffffffff, 0x0000001c,
1065 0x34, 0x000f0000, 0x000f0000,
1066 0x160c, 0xffffffff, 0x00000100,
1067 0x1024, 0xffffffff, 0x00000100,
1068 0x20a8, 0xffffffff, 0x00000104,
1069 0x264c, 0x000c0000, 0x000c0000,
1070 0x2648, 0x000c0000, 0x000c0000,
1071 0x2f50, 0x00000001, 0x00000001,
1072 0x30cc, 0xc0000fff, 0x00000104,
1073 0xc1e4, 0x00000001, 0x00000001,
1074 0xd0c0, 0xfffffff0, 0x00000100,
1075 0xd8c0, 0xfffffff0, 0x00000100
1078 static u32 verde_pg_init[] =
1080 0x353c, 0xffffffff, 0x40000,
1081 0x3538, 0xffffffff, 0x200010ff,
1082 0x353c, 0xffffffff, 0x0,
1083 0x353c, 0xffffffff, 0x0,
1084 0x353c, 0xffffffff, 0x0,
1085 0x353c, 0xffffffff, 0x0,
1086 0x353c, 0xffffffff, 0x0,
1087 0x353c, 0xffffffff, 0x7007,
1088 0x3538, 0xffffffff, 0x300010ff,
1089 0x353c, 0xffffffff, 0x0,
1090 0x353c, 0xffffffff, 0x0,
1091 0x353c, 0xffffffff, 0x0,
1092 0x353c, 0xffffffff, 0x0,
1093 0x353c, 0xffffffff, 0x0,
1094 0x353c, 0xffffffff, 0x400000,
1095 0x3538, 0xffffffff, 0x100010ff,
1096 0x353c, 0xffffffff, 0x0,
1097 0x353c, 0xffffffff, 0x0,
1098 0x353c, 0xffffffff, 0x0,
1099 0x353c, 0xffffffff, 0x0,
1100 0x353c, 0xffffffff, 0x0,
1101 0x353c, 0xffffffff, 0x120200,
1102 0x3538, 0xffffffff, 0x500010ff,
1103 0x353c, 0xffffffff, 0x0,
1104 0x353c, 0xffffffff, 0x0,
1105 0x353c, 0xffffffff, 0x0,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x1e1e16,
1109 0x3538, 0xffffffff, 0x600010ff,
1110 0x353c, 0xffffffff, 0x0,
1111 0x353c, 0xffffffff, 0x0,
1112 0x353c, 0xffffffff, 0x0,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x171f1e,
1116 0x3538, 0xffffffff, 0x700010ff,
1117 0x353c, 0xffffffff, 0x0,
1118 0x353c, 0xffffffff, 0x0,
1119 0x353c, 0xffffffff, 0x0,
1120 0x353c, 0xffffffff, 0x0,
1121 0x353c, 0xffffffff, 0x0,
1122 0x353c, 0xffffffff, 0x0,
1123 0x3538, 0xffffffff, 0x9ff,
1124 0x3500, 0xffffffff, 0x0,
1125 0x3504, 0xffffffff, 0x10000800,
1126 0x3504, 0xffffffff, 0xf,
1127 0x3504, 0xffffffff, 0xf,
1128 0x3500, 0xffffffff, 0x4,
1129 0x3504, 0xffffffff, 0x1000051e,
1130 0x3504, 0xffffffff, 0xffff,
1131 0x3504, 0xffffffff, 0xffff,
1132 0x3500, 0xffffffff, 0x8,
1133 0x3504, 0xffffffff, 0x80500,
1134 0x3500, 0xffffffff, 0x12,
1135 0x3504, 0xffffffff, 0x9050c,
1136 0x3500, 0xffffffff, 0x1d,
1137 0x3504, 0xffffffff, 0xb052c,
1138 0x3500, 0xffffffff, 0x2a,
1139 0x3504, 0xffffffff, 0x1053e,
1140 0x3500, 0xffffffff, 0x2d,
1141 0x3504, 0xffffffff, 0x10546,
1142 0x3500, 0xffffffff, 0x30,
1143 0x3504, 0xffffffff, 0xa054e,
1144 0x3500, 0xffffffff, 0x3c,
1145 0x3504, 0xffffffff, 0x1055f,
1146 0x3500, 0xffffffff, 0x3f,
1147 0x3504, 0xffffffff, 0x10567,
1148 0x3500, 0xffffffff, 0x42,
1149 0x3504, 0xffffffff, 0x1056f,
1150 0x3500, 0xffffffff, 0x45,
1151 0x3504, 0xffffffff, 0x10572,
1152 0x3500, 0xffffffff, 0x48,
1153 0x3504, 0xffffffff, 0x20575,
1154 0x3500, 0xffffffff, 0x4c,
1155 0x3504, 0xffffffff, 0x190801,
1156 0x3500, 0xffffffff, 0x67,
1157 0x3504, 0xffffffff, 0x1082a,
1158 0x3500, 0xffffffff, 0x6a,
1159 0x3504, 0xffffffff, 0x1b082d,
1160 0x3500, 0xffffffff, 0x87,
1161 0x3504, 0xffffffff, 0x310851,
1162 0x3500, 0xffffffff, 0xba,
1163 0x3504, 0xffffffff, 0x891,
1164 0x3500, 0xffffffff, 0xbc,
1165 0x3504, 0xffffffff, 0x893,
1166 0x3500, 0xffffffff, 0xbe,
1167 0x3504, 0xffffffff, 0x20895,
1168 0x3500, 0xffffffff, 0xc2,
1169 0x3504, 0xffffffff, 0x20899,
1170 0x3500, 0xffffffff, 0xc6,
1171 0x3504, 0xffffffff, 0x2089d,
1172 0x3500, 0xffffffff, 0xca,
1173 0x3504, 0xffffffff, 0x8a1,
1174 0x3500, 0xffffffff, 0xcc,
1175 0x3504, 0xffffffff, 0x8a3,
1176 0x3500, 0xffffffff, 0xce,
1177 0x3504, 0xffffffff, 0x308a5,
1178 0x3500, 0xffffffff, 0xd3,
1179 0x3504, 0xffffffff, 0x6d08cd,
1180 0x3500, 0xffffffff, 0x142,
1181 0x3504, 0xffffffff, 0x2000095a,
1182 0x3504, 0xffffffff, 0x1,
1183 0x3500, 0xffffffff, 0x144,
1184 0x3504, 0xffffffff, 0x301f095b,
1185 0x3500, 0xffffffff, 0x165,
1186 0x3504, 0xffffffff, 0xc094d,
1187 0x3500, 0xffffffff, 0x173,
1188 0x3504, 0xffffffff, 0xf096d,
1189 0x3500, 0xffffffff, 0x184,
1190 0x3504, 0xffffffff, 0x15097f,
1191 0x3500, 0xffffffff, 0x19b,
1192 0x3504, 0xffffffff, 0xc0998,
1193 0x3500, 0xffffffff, 0x1a9,
1194 0x3504, 0xffffffff, 0x409a7,
1195 0x3500, 0xffffffff, 0x1af,
1196 0x3504, 0xffffffff, 0xcdc,
1197 0x3500, 0xffffffff, 0x1b1,
1198 0x3504, 0xffffffff, 0x800,
1199 0x3508, 0xffffffff, 0x6c9b2000,
1200 0x3510, 0xfc00, 0x2000,
1201 0x3544, 0xffffffff, 0xfc0,
1202 0x28d4, 0x00000100, 0x100
1205 static void si_init_golden_registers(struct radeon_device *rdev)
1207 switch (rdev->family) {
1209 radeon_program_register_sequence(rdev,
1210 tahiti_golden_registers,
1211 (const u32)ARRAY_SIZE(tahiti_golden_registers));
1212 radeon_program_register_sequence(rdev,
1213 tahiti_golden_rlc_registers,
1214 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
1215 radeon_program_register_sequence(rdev,
1216 tahiti_mgcg_cgcg_init,
1217 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
1218 radeon_program_register_sequence(rdev,
1219 tahiti_golden_registers2,
1220 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
1223 radeon_program_register_sequence(rdev,
1224 pitcairn_golden_registers,
1225 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
1226 radeon_program_register_sequence(rdev,
1227 pitcairn_golden_rlc_registers,
1228 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
1229 radeon_program_register_sequence(rdev,
1230 pitcairn_mgcg_cgcg_init,
1231 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
1234 radeon_program_register_sequence(rdev,
1235 verde_golden_registers,
1236 (const u32)ARRAY_SIZE(verde_golden_registers));
1237 radeon_program_register_sequence(rdev,
1238 verde_golden_rlc_registers,
1239 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
1240 radeon_program_register_sequence(rdev,
1241 verde_mgcg_cgcg_init,
1242 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
1243 radeon_program_register_sequence(rdev,
1245 (const u32)ARRAY_SIZE(verde_pg_init));
1248 radeon_program_register_sequence(rdev,
1249 oland_golden_registers,
1250 (const u32)ARRAY_SIZE(oland_golden_registers));
1251 radeon_program_register_sequence(rdev,
1252 oland_golden_rlc_registers,
1253 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
1254 radeon_program_register_sequence(rdev,
1255 oland_mgcg_cgcg_init,
1256 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
1259 radeon_program_register_sequence(rdev,
1260 hainan_golden_registers,
1261 (const u32)ARRAY_SIZE(hainan_golden_registers));
1262 radeon_program_register_sequence(rdev,
1263 hainan_golden_registers2,
1264 (const u32)ARRAY_SIZE(hainan_golden_registers2));
1265 radeon_program_register_sequence(rdev,
1266 hainan_mgcg_cgcg_init,
1267 (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
1275 * si_get_allowed_info_register - fetch the register for the info ioctl
1277 * @rdev: radeon_device pointer
1278 * @reg: register offset in bytes
1279 * @val: register value
1281 * Returns 0 for success or -EINVAL for an invalid register
1284 int si_get_allowed_info_register(struct radeon_device *rdev,
1290 case GRBM_STATUS_SE0:
1291 case GRBM_STATUS_SE1:
1294 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1295 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
1304 #define PCIE_BUS_CLK 10000
1305 #define TCLK (PCIE_BUS_CLK / 10)
1308 * si_get_xclk - get the xclk
1310 * @rdev: radeon_device pointer
1312 * Returns the reference clock used by the gfx engine
1315 u32 si_get_xclk(struct radeon_device *rdev)
1317 u32 reference_clock = rdev->clock.spll.reference_freq;
1320 tmp = RREG32(CG_CLKPIN_CNTL_2);
1321 if (tmp & MUX_TCLK_TO_XCLK)
1324 tmp = RREG32(CG_CLKPIN_CNTL);
1325 if (tmp & XTALIN_DIVIDE)
1326 return reference_clock / 4;
1328 return reference_clock;
1331 /* get temperature in millidegrees */
1332 int si_get_temp(struct radeon_device *rdev)
1335 int actual_temp = 0;
1337 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
1343 actual_temp = temp & 0x1ff;
1345 actual_temp = (actual_temp * 1000);
1350 #define TAHITI_IO_MC_REGS_SIZE 36
1352 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1353 {0x0000006f, 0x03044000},
1354 {0x00000070, 0x0480c018},
1355 {0x00000071, 0x00000040},
1356 {0x00000072, 0x01000000},
1357 {0x00000074, 0x000000ff},
1358 {0x00000075, 0x00143400},
1359 {0x00000076, 0x08ec0800},
1360 {0x00000077, 0x040000cc},
1361 {0x00000079, 0x00000000},
1362 {0x0000007a, 0x21000409},
1363 {0x0000007c, 0x00000000},
1364 {0x0000007d, 0xe8000000},
1365 {0x0000007e, 0x044408a8},
1366 {0x0000007f, 0x00000003},
1367 {0x00000080, 0x00000000},
1368 {0x00000081, 0x01000000},
1369 {0x00000082, 0x02000000},
1370 {0x00000083, 0x00000000},
1371 {0x00000084, 0xe3f3e4f4},
1372 {0x00000085, 0x00052024},
1373 {0x00000087, 0x00000000},
1374 {0x00000088, 0x66036603},
1375 {0x00000089, 0x01000000},
1376 {0x0000008b, 0x1c0a0000},
1377 {0x0000008c, 0xff010000},
1378 {0x0000008e, 0xffffefff},
1379 {0x0000008f, 0xfff3efff},
1380 {0x00000090, 0xfff3efbf},
1381 {0x00000094, 0x00101101},
1382 {0x00000095, 0x00000fff},
1383 {0x00000096, 0x00116fff},
1384 {0x00000097, 0x60010000},
1385 {0x00000098, 0x10010000},
1386 {0x00000099, 0x00006000},
1387 {0x0000009a, 0x00001000},
1388 {0x0000009f, 0x00a77400}
1391 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1392 {0x0000006f, 0x03044000},
1393 {0x00000070, 0x0480c018},
1394 {0x00000071, 0x00000040},
1395 {0x00000072, 0x01000000},
1396 {0x00000074, 0x000000ff},
1397 {0x00000075, 0x00143400},
1398 {0x00000076, 0x08ec0800},
1399 {0x00000077, 0x040000cc},
1400 {0x00000079, 0x00000000},
1401 {0x0000007a, 0x21000409},
1402 {0x0000007c, 0x00000000},
1403 {0x0000007d, 0xe8000000},
1404 {0x0000007e, 0x044408a8},
1405 {0x0000007f, 0x00000003},
1406 {0x00000080, 0x00000000},
1407 {0x00000081, 0x01000000},
1408 {0x00000082, 0x02000000},
1409 {0x00000083, 0x00000000},
1410 {0x00000084, 0xe3f3e4f4},
1411 {0x00000085, 0x00052024},
1412 {0x00000087, 0x00000000},
1413 {0x00000088, 0x66036603},
1414 {0x00000089, 0x01000000},
1415 {0x0000008b, 0x1c0a0000},
1416 {0x0000008c, 0xff010000},
1417 {0x0000008e, 0xffffefff},
1418 {0x0000008f, 0xfff3efff},
1419 {0x00000090, 0xfff3efbf},
1420 {0x00000094, 0x00101101},
1421 {0x00000095, 0x00000fff},
1422 {0x00000096, 0x00116fff},
1423 {0x00000097, 0x60010000},
1424 {0x00000098, 0x10010000},
1425 {0x00000099, 0x00006000},
1426 {0x0000009a, 0x00001000},
1427 {0x0000009f, 0x00a47400}
1430 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1431 {0x0000006f, 0x03044000},
1432 {0x00000070, 0x0480c018},
1433 {0x00000071, 0x00000040},
1434 {0x00000072, 0x01000000},
1435 {0x00000074, 0x000000ff},
1436 {0x00000075, 0x00143400},
1437 {0x00000076, 0x08ec0800},
1438 {0x00000077, 0x040000cc},
1439 {0x00000079, 0x00000000},
1440 {0x0000007a, 0x21000409},
1441 {0x0000007c, 0x00000000},
1442 {0x0000007d, 0xe8000000},
1443 {0x0000007e, 0x044408a8},
1444 {0x0000007f, 0x00000003},
1445 {0x00000080, 0x00000000},
1446 {0x00000081, 0x01000000},
1447 {0x00000082, 0x02000000},
1448 {0x00000083, 0x00000000},
1449 {0x00000084, 0xe3f3e4f4},
1450 {0x00000085, 0x00052024},
1451 {0x00000087, 0x00000000},
1452 {0x00000088, 0x66036603},
1453 {0x00000089, 0x01000000},
1454 {0x0000008b, 0x1c0a0000},
1455 {0x0000008c, 0xff010000},
1456 {0x0000008e, 0xffffefff},
1457 {0x0000008f, 0xfff3efff},
1458 {0x00000090, 0xfff3efbf},
1459 {0x00000094, 0x00101101},
1460 {0x00000095, 0x00000fff},
1461 {0x00000096, 0x00116fff},
1462 {0x00000097, 0x60010000},
1463 {0x00000098, 0x10010000},
1464 {0x00000099, 0x00006000},
1465 {0x0000009a, 0x00001000},
1466 {0x0000009f, 0x00a37400}
1469 static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1470 {0x0000006f, 0x03044000},
1471 {0x00000070, 0x0480c018},
1472 {0x00000071, 0x00000040},
1473 {0x00000072, 0x01000000},
1474 {0x00000074, 0x000000ff},
1475 {0x00000075, 0x00143400},
1476 {0x00000076, 0x08ec0800},
1477 {0x00000077, 0x040000cc},
1478 {0x00000079, 0x00000000},
1479 {0x0000007a, 0x21000409},
1480 {0x0000007c, 0x00000000},
1481 {0x0000007d, 0xe8000000},
1482 {0x0000007e, 0x044408a8},
1483 {0x0000007f, 0x00000003},
1484 {0x00000080, 0x00000000},
1485 {0x00000081, 0x01000000},
1486 {0x00000082, 0x02000000},
1487 {0x00000083, 0x00000000},
1488 {0x00000084, 0xe3f3e4f4},
1489 {0x00000085, 0x00052024},
1490 {0x00000087, 0x00000000},
1491 {0x00000088, 0x66036603},
1492 {0x00000089, 0x01000000},
1493 {0x0000008b, 0x1c0a0000},
1494 {0x0000008c, 0xff010000},
1495 {0x0000008e, 0xffffefff},
1496 {0x0000008f, 0xfff3efff},
1497 {0x00000090, 0xfff3efbf},
1498 {0x00000094, 0x00101101},
1499 {0x00000095, 0x00000fff},
1500 {0x00000096, 0x00116fff},
1501 {0x00000097, 0x60010000},
1502 {0x00000098, 0x10010000},
1503 {0x00000099, 0x00006000},
1504 {0x0000009a, 0x00001000},
1505 {0x0000009f, 0x00a17730}
1508 static const u32 hainan_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
1509 {0x0000006f, 0x03044000},
1510 {0x00000070, 0x0480c018},
1511 {0x00000071, 0x00000040},
1512 {0x00000072, 0x01000000},
1513 {0x00000074, 0x000000ff},
1514 {0x00000075, 0x00143400},
1515 {0x00000076, 0x08ec0800},
1516 {0x00000077, 0x040000cc},
1517 {0x00000079, 0x00000000},
1518 {0x0000007a, 0x21000409},
1519 {0x0000007c, 0x00000000},
1520 {0x0000007d, 0xe8000000},
1521 {0x0000007e, 0x044408a8},
1522 {0x0000007f, 0x00000003},
1523 {0x00000080, 0x00000000},
1524 {0x00000081, 0x01000000},
1525 {0x00000082, 0x02000000},
1526 {0x00000083, 0x00000000},
1527 {0x00000084, 0xe3f3e4f4},
1528 {0x00000085, 0x00052024},
1529 {0x00000087, 0x00000000},
1530 {0x00000088, 0x66036603},
1531 {0x00000089, 0x01000000},
1532 {0x0000008b, 0x1c0a0000},
1533 {0x0000008c, 0xff010000},
1534 {0x0000008e, 0xffffefff},
1535 {0x0000008f, 0xfff3efff},
1536 {0x00000090, 0xfff3efbf},
1537 {0x00000094, 0x00101101},
1538 {0x00000095, 0x00000fff},
1539 {0x00000096, 0x00116fff},
1540 {0x00000097, 0x60010000},
1541 {0x00000098, 0x10010000},
1542 {0x00000099, 0x00006000},
1543 {0x0000009a, 0x00001000},
1544 {0x0000009f, 0x00a07730}
1548 int si_mc_load_microcode(struct radeon_device *rdev)
1550 const __be32 *fw_data = NULL;
1551 const __le32 *new_fw_data = NULL;
1553 u32 *io_mc_regs = NULL;
1554 const __le32 *new_io_mc_regs = NULL;
1555 int i, regs_size, ucode_size;
1561 const struct mc_firmware_header_v1_0 *hdr =
1562 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data;
1564 radeon_ucode_print_mc_hdr(&hdr->header);
1565 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
1566 new_io_mc_regs = (const __le32 *)
1567 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
1568 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1569 new_fw_data = (const __le32 *)
1570 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1572 ucode_size = rdev->mc_fw->size / 4;
1574 switch (rdev->family) {
1576 io_mc_regs = (u32 *)&tahiti_io_mc_regs;
1577 regs_size = TAHITI_IO_MC_REGS_SIZE;
1580 io_mc_regs = (u32 *)&pitcairn_io_mc_regs;
1581 regs_size = TAHITI_IO_MC_REGS_SIZE;
1585 io_mc_regs = (u32 *)&verde_io_mc_regs;
1586 regs_size = TAHITI_IO_MC_REGS_SIZE;
1589 io_mc_regs = (u32 *)&oland_io_mc_regs;
1590 regs_size = TAHITI_IO_MC_REGS_SIZE;
1593 io_mc_regs = (u32 *)&hainan_io_mc_regs;
1594 regs_size = TAHITI_IO_MC_REGS_SIZE;
1597 fw_data = (const __be32 *)rdev->mc_fw->data;
1600 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1603 /* reset the engine and set to writable */
1604 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1605 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1607 /* load mc io regs */
1608 for (i = 0; i < regs_size; i++) {
1610 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
1611 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
1613 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1614 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1617 /* load the MC ucode */
1618 for (i = 0; i < ucode_size; i++) {
1620 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
1622 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1625 /* put the engine back into the active state */
1626 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1627 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1628 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1630 /* wait for training to complete */
1631 for (i = 0; i < rdev->usec_timeout; i++) {
1632 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1636 for (i = 0; i < rdev->usec_timeout; i++) {
1637 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1646 static int si_init_microcode(struct radeon_device *rdev)
1648 const char *chip_name;
1649 const char *new_chip_name;
1650 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size;
1651 size_t smc_req_size, mc2_req_size;
1655 bool new_smc = false;
1656 bool si58_fw = false;
1657 bool banks2_fw = false;
1661 switch (rdev->family) {
1663 chip_name = "TAHITI";
1664 new_chip_name = "tahiti";
1665 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1666 me_req_size = SI_PM4_UCODE_SIZE * 4;
1667 ce_req_size = SI_CE_UCODE_SIZE * 4;
1668 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1669 mc_req_size = SI_MC_UCODE_SIZE * 4;
1670 mc2_req_size = TAHITI_MC_UCODE_SIZE * 4;
1671 smc_req_size = ALIGN(TAHITI_SMC_UCODE_SIZE, 4);
1674 chip_name = "PITCAIRN";
1675 if ((rdev->pdev->revision == 0x81) &&
1676 ((rdev->pdev->device == 0x6810) ||
1677 (rdev->pdev->device == 0x6811)))
1679 new_chip_name = "pitcairn";
1680 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1681 me_req_size = SI_PM4_UCODE_SIZE * 4;
1682 ce_req_size = SI_CE_UCODE_SIZE * 4;
1683 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1684 mc_req_size = SI_MC_UCODE_SIZE * 4;
1685 mc2_req_size = PITCAIRN_MC_UCODE_SIZE * 4;
1686 smc_req_size = ALIGN(PITCAIRN_SMC_UCODE_SIZE, 4);
1689 chip_name = "VERDE";
1690 if (((rdev->pdev->device == 0x6820) &&
1691 ((rdev->pdev->revision == 0x81) ||
1692 (rdev->pdev->revision == 0x83))) ||
1693 ((rdev->pdev->device == 0x6821) &&
1694 ((rdev->pdev->revision == 0x83) ||
1695 (rdev->pdev->revision == 0x87))) ||
1696 ((rdev->pdev->revision == 0x87) &&
1697 ((rdev->pdev->device == 0x6823) ||
1698 (rdev->pdev->device == 0x682b))))
1700 new_chip_name = "verde";
1701 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1702 me_req_size = SI_PM4_UCODE_SIZE * 4;
1703 ce_req_size = SI_CE_UCODE_SIZE * 4;
1704 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1705 mc_req_size = SI_MC_UCODE_SIZE * 4;
1706 mc2_req_size = VERDE_MC_UCODE_SIZE * 4;
1707 smc_req_size = ALIGN(VERDE_SMC_UCODE_SIZE, 4);
1710 chip_name = "OLAND";
1711 if (((rdev->pdev->revision == 0x81) &&
1712 ((rdev->pdev->device == 0x6600) ||
1713 (rdev->pdev->device == 0x6604) ||
1714 (rdev->pdev->device == 0x6605) ||
1715 (rdev->pdev->device == 0x6610))) ||
1716 ((rdev->pdev->revision == 0x83) &&
1717 (rdev->pdev->device == 0x6610)))
1719 new_chip_name = "oland";
1720 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1721 me_req_size = SI_PM4_UCODE_SIZE * 4;
1722 ce_req_size = SI_CE_UCODE_SIZE * 4;
1723 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1724 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1725 smc_req_size = ALIGN(OLAND_SMC_UCODE_SIZE, 4);
1728 chip_name = "HAINAN";
1729 if (((rdev->pdev->revision == 0x81) &&
1730 (rdev->pdev->device == 0x6660)) ||
1731 ((rdev->pdev->revision == 0x83) &&
1732 ((rdev->pdev->device == 0x6660) ||
1733 (rdev->pdev->device == 0x6663) ||
1734 (rdev->pdev->device == 0x6665) ||
1735 (rdev->pdev->device == 0x6667))))
1737 else if ((rdev->pdev->revision == 0xc3) &&
1738 (rdev->pdev->device == 0x6665))
1740 new_chip_name = "hainan";
1741 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
1742 me_req_size = SI_PM4_UCODE_SIZE * 4;
1743 ce_req_size = SI_CE_UCODE_SIZE * 4;
1744 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
1745 mc_req_size = mc2_req_size = OLAND_MC_UCODE_SIZE * 4;
1746 smc_req_size = ALIGN(HAINAN_SMC_UCODE_SIZE, 4);
1751 /* this memory configuration requires special firmware */
1752 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
1755 DRM_INFO("Loading %s Microcode\n", new_chip_name);
1757 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", new_chip_name);
1758 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1760 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1761 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1764 if (rdev->pfp_fw->size != pfp_req_size) {
1766 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1767 rdev->pfp_fw->size, fw_name);
1772 err = radeon_ucode_validate(rdev->pfp_fw);
1775 "si_cp: validation failed for firmware \"%s\"\n",
1783 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", new_chip_name);
1784 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1786 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1787 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1790 if (rdev->me_fw->size != me_req_size) {
1792 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1793 rdev->me_fw->size, fw_name);
1797 err = radeon_ucode_validate(rdev->me_fw);
1800 "si_cp: validation failed for firmware \"%s\"\n",
1808 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", new_chip_name);
1809 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1811 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1812 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1815 if (rdev->ce_fw->size != ce_req_size) {
1817 "si_cp: Bogus length %zu in firmware \"%s\"\n",
1818 rdev->ce_fw->size, fw_name);
1822 err = radeon_ucode_validate(rdev->ce_fw);
1825 "si_cp: validation failed for firmware \"%s\"\n",
1833 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", new_chip_name);
1834 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1836 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1837 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1840 if (rdev->rlc_fw->size != rlc_req_size) {
1842 "si_rlc: Bogus length %zu in firmware \"%s\"\n",
1843 rdev->rlc_fw->size, fw_name);
1847 err = radeon_ucode_validate(rdev->rlc_fw);
1850 "si_cp: validation failed for firmware \"%s\"\n",
1859 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");
1861 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", new_chip_name);
1862 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1864 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc2.bin", chip_name);
1865 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1867 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1868 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1872 if ((rdev->mc_fw->size != mc_req_size) &&
1873 (rdev->mc_fw->size != mc2_req_size)) {
1875 "si_mc: Bogus length %zu in firmware \"%s\"\n",
1876 rdev->mc_fw->size, fw_name);
1879 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size);
1881 err = radeon_ucode_validate(rdev->mc_fw);
1884 "si_cp: validation failed for firmware \"%s\"\n",
1893 snprintf(fw_name, sizeof(fw_name), "radeon/banks_k_2_smc.bin");
1895 snprintf(fw_name, sizeof(fw_name), "radeon/%s_k_smc.bin", new_chip_name);
1897 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", new_chip_name);
1898 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1900 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1901 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1904 "smc: error loading firmware \"%s\"\n",
1906 release_firmware(rdev->smc_fw);
1907 rdev->smc_fw = NULL;
1909 } else if (rdev->smc_fw->size != smc_req_size) {
1911 "si_smc: Bogus length %zu in firmware \"%s\"\n",
1912 rdev->smc_fw->size, fw_name);
1916 err = radeon_ucode_validate(rdev->smc_fw);
1919 "si_cp: validation failed for firmware \"%s\"\n",
1928 rdev->new_fw = false;
1929 } else if (new_fw < 6) {
1930 printk(KERN_ERR "si_fw: mixing new and old firmware!\n");
1933 rdev->new_fw = true;
1939 "si_cp: Failed to load firmware \"%s\"\n",
1941 release_firmware(rdev->pfp_fw);
1942 rdev->pfp_fw = NULL;
1943 release_firmware(rdev->me_fw);
1945 release_firmware(rdev->ce_fw);
1947 release_firmware(rdev->rlc_fw);
1948 rdev->rlc_fw = NULL;
1949 release_firmware(rdev->mc_fw);
1951 release_firmware(rdev->smc_fw);
1952 rdev->smc_fw = NULL;
1957 /* watermark setup */
1958 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
1959 struct radeon_crtc *radeon_crtc,
1960 struct drm_display_mode *mode,
1961 struct drm_display_mode *other_mode)
1963 u32 tmp, buffer_alloc, i;
1964 u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
1967 * There are 3 line buffers, each one shared by 2 display controllers.
1968 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1969 * the display controllers. The paritioning is done via one of four
1970 * preset allocations specified in bits 21:20:
1972 * 2 - whole lb, other crtc must be disabled
1974 /* this can get tricky if we have two large displays on a paired group
1975 * of crtcs. Ideally for multiple large displays we'd assign them to
1976 * non-linked crtcs for maximum line buffer allocation.
1978 if (radeon_crtc->base.enabled && mode) {
1983 tmp = 2; /* whole */
1991 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
1992 DC_LB_MEMORY_CONFIG(tmp));
1994 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1995 DMIF_BUFFERS_ALLOCATED(buffer_alloc));
1996 for (i = 0; i < rdev->usec_timeout; i++) {
1997 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1998 DMIF_BUFFERS_ALLOCATED_COMPLETED)
2003 if (radeon_crtc->base.enabled && mode) {
2013 /* controller not enabled, so no lb used */
2017 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
2019 u32 tmp = RREG32(MC_SHARED_CHMAP);
2021 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2044 struct dce6_wm_params {
2045 u32 dram_channels; /* number of dram channels */
2046 u32 yclk; /* bandwidth per dram data pin in kHz */
2047 u32 sclk; /* engine clock in kHz */
2048 u32 disp_clk; /* display clock in kHz */
2049 u32 src_width; /* viewport width */
2050 u32 active_time; /* active display time in ns */
2051 u32 blank_time; /* blank time in ns */
2052 bool interlaced; /* mode is interlaced */
2053 fixed20_12 vsc; /* vertical scale ratio */
2054 u32 num_heads; /* number of active crtcs */
2055 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
2056 u32 lb_size; /* line buffer allocated to pipe */
2057 u32 vtaps; /* vertical scaler taps */
2060 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
2062 /* Calculate raw DRAM Bandwidth */
2063 fixed20_12 dram_efficiency; /* 0.7 */
2064 fixed20_12 yclk, dram_channels, bandwidth;
2067 a.full = dfixed_const(1000);
2068 yclk.full = dfixed_const(wm->yclk);
2069 yclk.full = dfixed_div(yclk, a);
2070 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2071 a.full = dfixed_const(10);
2072 dram_efficiency.full = dfixed_const(7);
2073 dram_efficiency.full = dfixed_div(dram_efficiency, a);
2074 bandwidth.full = dfixed_mul(dram_channels, yclk);
2075 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
2077 return dfixed_trunc(bandwidth);
2080 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2082 /* Calculate DRAM Bandwidth and the part allocated to display. */
2083 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
2084 fixed20_12 yclk, dram_channels, bandwidth;
2087 a.full = dfixed_const(1000);
2088 yclk.full = dfixed_const(wm->yclk);
2089 yclk.full = dfixed_div(yclk, a);
2090 dram_channels.full = dfixed_const(wm->dram_channels * 4);
2091 a.full = dfixed_const(10);
2092 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
2093 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
2094 bandwidth.full = dfixed_mul(dram_channels, yclk);
2095 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
2097 return dfixed_trunc(bandwidth);
2100 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
2102 /* Calculate the display Data return Bandwidth */
2103 fixed20_12 return_efficiency; /* 0.8 */
2104 fixed20_12 sclk, bandwidth;
2107 a.full = dfixed_const(1000);
2108 sclk.full = dfixed_const(wm->sclk);
2109 sclk.full = dfixed_div(sclk, a);
2110 a.full = dfixed_const(10);
2111 return_efficiency.full = dfixed_const(8);
2112 return_efficiency.full = dfixed_div(return_efficiency, a);
2113 a.full = dfixed_const(32);
2114 bandwidth.full = dfixed_mul(a, sclk);
2115 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
2117 return dfixed_trunc(bandwidth);
2120 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
2125 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
2127 /* Calculate the DMIF Request Bandwidth */
2128 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
2129 fixed20_12 disp_clk, sclk, bandwidth;
2130 fixed20_12 a, b1, b2;
2133 a.full = dfixed_const(1000);
2134 disp_clk.full = dfixed_const(wm->disp_clk);
2135 disp_clk.full = dfixed_div(disp_clk, a);
2136 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
2137 b1.full = dfixed_mul(a, disp_clk);
2139 a.full = dfixed_const(1000);
2140 sclk.full = dfixed_const(wm->sclk);
2141 sclk.full = dfixed_div(sclk, a);
2142 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
2143 b2.full = dfixed_mul(a, sclk);
2145 a.full = dfixed_const(10);
2146 disp_clk_request_efficiency.full = dfixed_const(8);
2147 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
2149 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
2151 a.full = dfixed_const(min_bandwidth);
2152 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
2154 return dfixed_trunc(bandwidth);
2157 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
2159 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
2160 u32 dram_bandwidth = dce6_dram_bandwidth(wm);
2161 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
2162 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
2164 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
2167 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
2169 /* Calculate the display mode Average Bandwidth
2170 * DisplayMode should contain the source and destination dimensions,
2174 fixed20_12 line_time;
2175 fixed20_12 src_width;
2176 fixed20_12 bandwidth;
2179 a.full = dfixed_const(1000);
2180 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
2181 line_time.full = dfixed_div(line_time, a);
2182 bpp.full = dfixed_const(wm->bytes_per_pixel);
2183 src_width.full = dfixed_const(wm->src_width);
2184 bandwidth.full = dfixed_mul(src_width, bpp);
2185 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
2186 bandwidth.full = dfixed_div(bandwidth, line_time);
2188 return dfixed_trunc(bandwidth);
2191 static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
2193 /* First calcualte the latency in ns */
2194 u32 mc_latency = 2000; /* 2000 ns. */
2195 u32 available_bandwidth = dce6_available_bandwidth(wm);
2196 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
2197 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
2198 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
2199 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
2200 (wm->num_heads * cursor_line_pair_return_time);
2201 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
2202 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
2203 u32 tmp, dmif_size = 12288;
2206 if (wm->num_heads == 0)
2209 a.full = dfixed_const(2);
2210 b.full = dfixed_const(1);
2211 if ((wm->vsc.full > a.full) ||
2212 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
2214 ((wm->vsc.full >= a.full) && wm->interlaced))
2215 max_src_lines_per_dst_line = 4;
2217 max_src_lines_per_dst_line = 2;
2219 a.full = dfixed_const(available_bandwidth);
2220 b.full = dfixed_const(wm->num_heads);
2221 a.full = dfixed_div(a, b);
2223 b.full = dfixed_const(mc_latency + 512);
2224 c.full = dfixed_const(wm->disp_clk);
2225 b.full = dfixed_div(b, c);
2227 c.full = dfixed_const(dmif_size);
2228 b.full = dfixed_div(c, b);
2230 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
2232 b.full = dfixed_const(1000);
2233 c.full = dfixed_const(wm->disp_clk);
2234 b.full = dfixed_div(c, b);
2235 c.full = dfixed_const(wm->bytes_per_pixel);
2236 b.full = dfixed_mul(b, c);
2238 lb_fill_bw = min(tmp, dfixed_trunc(b));
2240 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
2241 b.full = dfixed_const(1000);
2242 c.full = dfixed_const(lb_fill_bw);
2243 b.full = dfixed_div(c, b);
2244 a.full = dfixed_div(a, b);
2245 line_fill_time = dfixed_trunc(a);
2247 if (line_fill_time < wm->active_time)
2250 return latency + (line_fill_time - wm->active_time);
2254 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
2256 if (dce6_average_bandwidth(wm) <=
2257 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
2263 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
2265 if (dce6_average_bandwidth(wm) <=
2266 (dce6_available_bandwidth(wm) / wm->num_heads))
2272 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
2274 u32 lb_partitions = wm->lb_size / wm->src_width;
2275 u32 line_time = wm->active_time + wm->blank_time;
2276 u32 latency_tolerant_lines;
2280 a.full = dfixed_const(1);
2281 if (wm->vsc.full > a.full)
2282 latency_tolerant_lines = 1;
2284 if (lb_partitions <= (wm->vtaps + 1))
2285 latency_tolerant_lines = 1;
2287 latency_tolerant_lines = 2;
2290 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
2292 if (dce6_latency_watermark(wm) <= latency_hiding)
2298 static void dce6_program_watermarks(struct radeon_device *rdev,
2299 struct radeon_crtc *radeon_crtc,
2300 u32 lb_size, u32 num_heads)
2302 struct drm_display_mode *mode = &radeon_crtc->base.mode;
2303 struct dce6_wm_params wm_low, wm_high;
2307 u32 latency_watermark_a = 0, latency_watermark_b = 0;
2308 u32 priority_a_mark = 0, priority_b_mark = 0;
2309 u32 priority_a_cnt = PRIORITY_OFF;
2310 u32 priority_b_cnt = PRIORITY_OFF;
2311 u32 tmp, arb_control3;
2314 if (radeon_crtc->base.enabled && num_heads && mode) {
2315 pixel_period = 1000000 / (u32)mode->clock;
2316 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
2320 if (rdev->family == CHIP_ARUBA)
2321 dram_channels = evergreen_get_number_of_dram_channels(rdev);
2323 dram_channels = si_get_number_of_dram_channels(rdev);
2325 /* watermark for high clocks */
2326 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2328 radeon_dpm_get_mclk(rdev, false) * 10;
2330 radeon_dpm_get_sclk(rdev, false) * 10;
2332 wm_high.yclk = rdev->pm.current_mclk * 10;
2333 wm_high.sclk = rdev->pm.current_sclk * 10;
2336 wm_high.disp_clk = mode->clock;
2337 wm_high.src_width = mode->crtc_hdisplay;
2338 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
2339 wm_high.blank_time = line_time - wm_high.active_time;
2340 wm_high.interlaced = false;
2341 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2342 wm_high.interlaced = true;
2343 wm_high.vsc = radeon_crtc->vsc;
2345 if (radeon_crtc->rmx_type != RMX_OFF)
2347 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
2348 wm_high.lb_size = lb_size;
2349 wm_high.dram_channels = dram_channels;
2350 wm_high.num_heads = num_heads;
2352 /* watermark for low clocks */
2353 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
2355 radeon_dpm_get_mclk(rdev, true) * 10;
2357 radeon_dpm_get_sclk(rdev, true) * 10;
2359 wm_low.yclk = rdev->pm.current_mclk * 10;
2360 wm_low.sclk = rdev->pm.current_sclk * 10;
2363 wm_low.disp_clk = mode->clock;
2364 wm_low.src_width = mode->crtc_hdisplay;
2365 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
2366 wm_low.blank_time = line_time - wm_low.active_time;
2367 wm_low.interlaced = false;
2368 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2369 wm_low.interlaced = true;
2370 wm_low.vsc = radeon_crtc->vsc;
2372 if (radeon_crtc->rmx_type != RMX_OFF)
2374 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
2375 wm_low.lb_size = lb_size;
2376 wm_low.dram_channels = dram_channels;
2377 wm_low.num_heads = num_heads;
2379 /* set for high clocks */
2380 latency_watermark_a = min(dce6_latency_watermark(&wm_high), (u32)65535);
2381 /* set for low clocks */
2382 latency_watermark_b = min(dce6_latency_watermark(&wm_low), (u32)65535);
2384 /* possibly force display priority to high */
2385 /* should really do this at mode validation time... */
2386 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
2387 !dce6_average_bandwidth_vs_available_bandwidth(&wm_high) ||
2388 !dce6_check_latency_hiding(&wm_high) ||
2389 (rdev->disp_priority == 2)) {
2390 DRM_DEBUG_KMS("force priority to high\n");
2391 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2392 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2394 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
2395 !dce6_average_bandwidth_vs_available_bandwidth(&wm_low) ||
2396 !dce6_check_latency_hiding(&wm_low) ||
2397 (rdev->disp_priority == 2)) {
2398 DRM_DEBUG_KMS("force priority to high\n");
2399 priority_a_cnt |= PRIORITY_ALWAYS_ON;
2400 priority_b_cnt |= PRIORITY_ALWAYS_ON;
2403 a.full = dfixed_const(1000);
2404 b.full = dfixed_const(mode->clock);
2405 b.full = dfixed_div(b, a);
2406 c.full = dfixed_const(latency_watermark_a);
2407 c.full = dfixed_mul(c, b);
2408 c.full = dfixed_mul(c, radeon_crtc->hsc);
2409 c.full = dfixed_div(c, a);
2410 a.full = dfixed_const(16);
2411 c.full = dfixed_div(c, a);
2412 priority_a_mark = dfixed_trunc(c);
2413 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
2415 a.full = dfixed_const(1000);
2416 b.full = dfixed_const(mode->clock);
2417 b.full = dfixed_div(b, a);
2418 c.full = dfixed_const(latency_watermark_b);
2419 c.full = dfixed_mul(c, b);
2420 c.full = dfixed_mul(c, radeon_crtc->hsc);
2421 c.full = dfixed_div(c, a);
2422 a.full = dfixed_const(16);
2423 c.full = dfixed_div(c, a);
2424 priority_b_mark = dfixed_trunc(c);
2425 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
2427 /* Save number of lines the linebuffer leads before the scanout */
2428 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
2432 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2434 tmp &= ~LATENCY_WATERMARK_MASK(3);
2435 tmp |= LATENCY_WATERMARK_MASK(1);
2436 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2437 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2438 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
2439 LATENCY_HIGH_WATERMARK(line_time)));
2441 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
2442 tmp &= ~LATENCY_WATERMARK_MASK(3);
2443 tmp |= LATENCY_WATERMARK_MASK(2);
2444 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
2445 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
2446 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
2447 LATENCY_HIGH_WATERMARK(line_time)));
2448 /* restore original selection */
2449 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
2451 /* write the priority marks */
2452 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
2453 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
2455 /* save values for DPM */
2456 radeon_crtc->line_time = line_time;
2457 radeon_crtc->wm_high = latency_watermark_a;
2458 radeon_crtc->wm_low = latency_watermark_b;
2461 void dce6_bandwidth_update(struct radeon_device *rdev)
2463 struct drm_display_mode *mode0 = NULL;
2464 struct drm_display_mode *mode1 = NULL;
2465 u32 num_heads = 0, lb_size;
2468 if (!rdev->mode_info.mode_config_initialized)
2471 radeon_update_display_priority(rdev);
2473 for (i = 0; i < rdev->num_crtc; i++) {
2474 if (rdev->mode_info.crtcs[i]->base.enabled)
2477 for (i = 0; i < rdev->num_crtc; i += 2) {
2478 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
2479 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
2480 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
2481 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
2482 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
2483 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
2490 static void si_tiling_mode_table_init(struct radeon_device *rdev)
2492 u32 *tile = rdev->config.si.tile_mode_array;
2493 const u32 num_tile_mode_states =
2494 ARRAY_SIZE(rdev->config.si.tile_mode_array);
2495 u32 reg_offset, split_equal_to_row_size;
2497 switch (rdev->config.si.mem_row_size_in_kb) {
2499 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
2503 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
2506 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
2510 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2511 tile[reg_offset] = 0;
2513 switch(rdev->family) {
2516 /* non-AA compressed depth or any compressed stencil */
2517 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2518 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2519 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2520 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2521 NUM_BANKS(ADDR_SURF_16_BANK) |
2522 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2525 /* 2xAA/4xAA compressed depth only */
2526 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2527 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2528 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2529 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2530 NUM_BANKS(ADDR_SURF_16_BANK) |
2531 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2532 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2533 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2534 /* 8xAA compressed depth only */
2535 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2536 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2537 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2538 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2539 NUM_BANKS(ADDR_SURF_16_BANK) |
2540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2543 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2544 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2545 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2546 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2547 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2548 NUM_BANKS(ADDR_SURF_16_BANK) |
2549 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2552 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2553 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2554 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2555 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2557 NUM_BANKS(ADDR_SURF_16_BANK) |
2558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2561 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2562 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2563 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2564 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2565 TILE_SPLIT(split_equal_to_row_size) |
2566 NUM_BANKS(ADDR_SURF_16_BANK) |
2567 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2568 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2569 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2570 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2571 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2572 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2573 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2574 TILE_SPLIT(split_equal_to_row_size) |
2575 NUM_BANKS(ADDR_SURF_16_BANK) |
2576 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2577 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2578 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2579 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2580 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2581 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2582 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2583 TILE_SPLIT(split_equal_to_row_size) |
2584 NUM_BANKS(ADDR_SURF_16_BANK) |
2585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2588 /* 1D and 1D Array Surfaces */
2589 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2590 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2591 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2593 NUM_BANKS(ADDR_SURF_16_BANK) |
2594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2597 /* Displayable maps. */
2598 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2599 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2600 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2602 NUM_BANKS(ADDR_SURF_16_BANK) |
2603 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2604 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2605 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2607 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2608 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2609 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2610 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2611 NUM_BANKS(ADDR_SURF_16_BANK) |
2612 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2613 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2614 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2615 /* Display 16bpp. */
2616 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2617 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2618 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2619 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2620 NUM_BANKS(ADDR_SURF_16_BANK) |
2621 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2622 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2623 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2624 /* Display 32bpp. */
2625 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2626 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2627 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2628 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2629 NUM_BANKS(ADDR_SURF_16_BANK) |
2630 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2631 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2632 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2634 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2635 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2636 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2637 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2638 NUM_BANKS(ADDR_SURF_16_BANK) |
2639 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2641 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2643 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2644 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2645 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2646 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2647 NUM_BANKS(ADDR_SURF_16_BANK) |
2648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2649 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2650 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2652 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2653 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2654 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2655 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2656 NUM_BANKS(ADDR_SURF_16_BANK) |
2657 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2658 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2659 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2661 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2662 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2663 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2665 NUM_BANKS(ADDR_SURF_16_BANK) |
2666 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2670 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2671 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2672 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2673 TILE_SPLIT(split_equal_to_row_size) |
2674 NUM_BANKS(ADDR_SURF_16_BANK) |
2675 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2679 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2680 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2681 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2682 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2683 NUM_BANKS(ADDR_SURF_16_BANK) |
2684 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2685 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2686 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2688 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2689 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2690 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2691 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2692 NUM_BANKS(ADDR_SURF_16_BANK) |
2693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2697 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2698 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2699 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2700 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2701 NUM_BANKS(ADDR_SURF_16_BANK) |
2702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2706 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2707 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2708 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2709 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2710 NUM_BANKS(ADDR_SURF_16_BANK) |
2711 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2712 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2713 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2715 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2716 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2717 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2718 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2719 NUM_BANKS(ADDR_SURF_8_BANK) |
2720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2721 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2722 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2724 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2725 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2731 /* non-AA compressed depth or any compressed stencil */
2732 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2733 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2734 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2736 NUM_BANKS(ADDR_SURF_16_BANK) |
2737 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2738 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2739 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2740 /* 2xAA/4xAA compressed depth only */
2741 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2742 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2743 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2744 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2745 NUM_BANKS(ADDR_SURF_16_BANK) |
2746 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2747 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2748 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2749 /* 8xAA compressed depth only */
2750 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2751 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2752 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2753 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2754 NUM_BANKS(ADDR_SURF_16_BANK) |
2755 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2756 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2757 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2758 /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
2759 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2760 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2761 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2762 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2763 NUM_BANKS(ADDR_SURF_16_BANK) |
2764 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2765 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2766 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2767 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
2768 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2769 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2770 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2772 NUM_BANKS(ADDR_SURF_16_BANK) |
2773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2776 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
2777 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2778 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2780 TILE_SPLIT(split_equal_to_row_size) |
2781 NUM_BANKS(ADDR_SURF_16_BANK) |
2782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2785 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
2786 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2787 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2788 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2789 TILE_SPLIT(split_equal_to_row_size) |
2790 NUM_BANKS(ADDR_SURF_16_BANK) |
2791 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2792 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2793 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2794 /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
2795 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2796 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
2797 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2798 TILE_SPLIT(split_equal_to_row_size) |
2799 NUM_BANKS(ADDR_SURF_16_BANK) |
2800 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2801 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2802 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2803 /* 1D and 1D Array Surfaces */
2804 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2805 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2806 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2807 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2808 NUM_BANKS(ADDR_SURF_16_BANK) |
2809 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2810 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2811 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2812 /* Displayable maps. */
2813 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2814 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2815 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2816 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2817 NUM_BANKS(ADDR_SURF_16_BANK) |
2818 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2819 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2820 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2822 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2823 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2824 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2825 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2826 NUM_BANKS(ADDR_SURF_16_BANK) |
2827 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2830 /* Display 16bpp. */
2831 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2832 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2833 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2834 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2835 NUM_BANKS(ADDR_SURF_16_BANK) |
2836 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2837 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2838 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2839 /* Display 32bpp. */
2840 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2841 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
2842 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2843 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2844 NUM_BANKS(ADDR_SURF_16_BANK) |
2845 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2846 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2847 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2849 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2850 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2851 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2852 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2853 NUM_BANKS(ADDR_SURF_16_BANK) |
2854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2858 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2859 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2860 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2861 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2862 NUM_BANKS(ADDR_SURF_16_BANK) |
2863 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2864 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2865 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2867 tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2868 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2869 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2870 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2871 NUM_BANKS(ADDR_SURF_16_BANK) |
2872 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2873 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2874 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2876 tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2877 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2878 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2879 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2880 NUM_BANKS(ADDR_SURF_16_BANK) |
2881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2885 tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2886 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2887 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2888 TILE_SPLIT(split_equal_to_row_size) |
2889 NUM_BANKS(ADDR_SURF_16_BANK) |
2890 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2891 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2892 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2894 tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2895 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2896 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2897 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2898 NUM_BANKS(ADDR_SURF_16_BANK) |
2899 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2900 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2901 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2903 tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2904 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2905 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2907 NUM_BANKS(ADDR_SURF_16_BANK) |
2908 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2909 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2910 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
2912 tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2913 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2914 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2915 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2916 NUM_BANKS(ADDR_SURF_16_BANK) |
2917 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2918 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2919 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2921 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2922 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2923 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2924 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2925 NUM_BANKS(ADDR_SURF_16_BANK) |
2926 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2927 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2928 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
2930 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2931 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
2932 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2933 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
2934 NUM_BANKS(ADDR_SURF_8_BANK) |
2935 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2936 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2937 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
2939 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2940 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
2944 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
2948 static void si_select_se_sh(struct radeon_device *rdev,
2949 u32 se_num, u32 sh_num)
2951 u32 data = INSTANCE_BROADCAST_WRITES;
2953 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
2954 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2955 else if (se_num == 0xffffffff)
2956 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
2957 else if (sh_num == 0xffffffff)
2958 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
2960 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
2961 WREG32(GRBM_GFX_INDEX, data);
2964 static u32 si_create_bitmask(u32 bit_width)
2968 for (i = 0; i < bit_width; i++) {
2975 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
2979 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
2981 data &= INACTIVE_CUS_MASK;
2984 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
2986 data >>= INACTIVE_CUS_SHIFT;
2988 mask = si_create_bitmask(cu_per_sh);
2990 return ~data & mask;
2993 static void si_setup_spi(struct radeon_device *rdev,
2994 u32 se_num, u32 sh_per_se,
2998 u32 data, mask, active_cu;
3000 for (i = 0; i < se_num; i++) {
3001 for (j = 0; j < sh_per_se; j++) {
3002 si_select_se_sh(rdev, i, j);
3003 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
3004 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
3007 for (k = 0; k < 16; k++) {
3009 if (active_cu & mask) {
3011 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
3017 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3020 static u32 si_get_rb_disabled(struct radeon_device *rdev,
3021 u32 max_rb_num_per_se,
3026 data = RREG32(CC_RB_BACKEND_DISABLE);
3028 data &= BACKEND_DISABLE_MASK;
3031 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3033 data >>= BACKEND_DISABLE_SHIFT;
3035 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
3040 static void si_setup_rb(struct radeon_device *rdev,
3041 u32 se_num, u32 sh_per_se,
3042 u32 max_rb_num_per_se)
3046 u32 disabled_rbs = 0;
3047 u32 enabled_rbs = 0;
3049 for (i = 0; i < se_num; i++) {
3050 for (j = 0; j < sh_per_se; j++) {
3051 si_select_se_sh(rdev, i, j);
3052 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3053 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
3056 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3059 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3060 if (!(disabled_rbs & mask))
3061 enabled_rbs |= mask;
3065 rdev->config.si.backend_enable_mask = enabled_rbs;
3067 for (i = 0; i < se_num; i++) {
3068 si_select_se_sh(rdev, i, 0xffffffff);
3070 for (j = 0; j < sh_per_se; j++) {
3071 switch (enabled_rbs & 3) {
3073 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3076 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3080 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3085 WREG32(PA_SC_RASTER_CONFIG, data);
3087 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3090 static void si_gpu_init(struct radeon_device *rdev)
3092 u32 gb_addr_config = 0;
3093 u32 mc_shared_chmap, mc_arb_ramcfg;
3095 u32 hdp_host_path_cntl;
3099 switch (rdev->family) {
3101 rdev->config.si.max_shader_engines = 2;
3102 rdev->config.si.max_tile_pipes = 12;
3103 rdev->config.si.max_cu_per_sh = 8;
3104 rdev->config.si.max_sh_per_se = 2;
3105 rdev->config.si.max_backends_per_se = 4;
3106 rdev->config.si.max_texture_channel_caches = 12;
3107 rdev->config.si.max_gprs = 256;
3108 rdev->config.si.max_gs_threads = 32;
3109 rdev->config.si.max_hw_contexts = 8;
3111 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3112 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3113 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3114 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3115 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3118 rdev->config.si.max_shader_engines = 2;
3119 rdev->config.si.max_tile_pipes = 8;
3120 rdev->config.si.max_cu_per_sh = 5;
3121 rdev->config.si.max_sh_per_se = 2;
3122 rdev->config.si.max_backends_per_se = 4;
3123 rdev->config.si.max_texture_channel_caches = 8;
3124 rdev->config.si.max_gprs = 256;
3125 rdev->config.si.max_gs_threads = 32;
3126 rdev->config.si.max_hw_contexts = 8;
3128 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3129 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
3130 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3131 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3132 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
3136 rdev->config.si.max_shader_engines = 1;
3137 rdev->config.si.max_tile_pipes = 4;
3138 rdev->config.si.max_cu_per_sh = 5;
3139 rdev->config.si.max_sh_per_se = 2;
3140 rdev->config.si.max_backends_per_se = 4;
3141 rdev->config.si.max_texture_channel_caches = 4;
3142 rdev->config.si.max_gprs = 256;
3143 rdev->config.si.max_gs_threads = 32;
3144 rdev->config.si.max_hw_contexts = 8;
3146 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3147 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3148 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3149 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3150 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3153 rdev->config.si.max_shader_engines = 1;
3154 rdev->config.si.max_tile_pipes = 4;
3155 rdev->config.si.max_cu_per_sh = 6;
3156 rdev->config.si.max_sh_per_se = 1;
3157 rdev->config.si.max_backends_per_se = 2;
3158 rdev->config.si.max_texture_channel_caches = 4;
3159 rdev->config.si.max_gprs = 256;
3160 rdev->config.si.max_gs_threads = 16;
3161 rdev->config.si.max_hw_contexts = 8;
3163 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3164 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3165 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3166 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3167 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
3170 rdev->config.si.max_shader_engines = 1;
3171 rdev->config.si.max_tile_pipes = 4;
3172 rdev->config.si.max_cu_per_sh = 5;
3173 rdev->config.si.max_sh_per_se = 1;
3174 rdev->config.si.max_backends_per_se = 1;
3175 rdev->config.si.max_texture_channel_caches = 2;
3176 rdev->config.si.max_gprs = 256;
3177 rdev->config.si.max_gs_threads = 16;
3178 rdev->config.si.max_hw_contexts = 8;
3180 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
3181 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
3182 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
3183 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
3184 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
3188 /* Initialize HDP */
3189 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3190 WREG32((0x2c14 + j), 0x00000000);
3191 WREG32((0x2c18 + j), 0x00000000);
3192 WREG32((0x2c1c + j), 0x00000000);
3193 WREG32((0x2c20 + j), 0x00000000);
3194 WREG32((0x2c24 + j), 0x00000000);
3197 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3198 WREG32(SRBM_INT_CNTL, 1);
3199 WREG32(SRBM_INT_ACK, 1);
3201 evergreen_fix_pci_max_read_req_size(rdev);
3203 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3205 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3206 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3208 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
3209 rdev->config.si.mem_max_burst_length_bytes = 256;
3210 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3211 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3212 if (rdev->config.si.mem_row_size_in_kb > 4)
3213 rdev->config.si.mem_row_size_in_kb = 4;
3214 /* XXX use MC settings? */
3215 rdev->config.si.shader_engine_tile_size = 32;
3216 rdev->config.si.num_gpus = 1;
3217 rdev->config.si.multi_gpu_tile_size = 64;
3219 /* fix up row size */
3220 gb_addr_config &= ~ROW_SIZE_MASK;
3221 switch (rdev->config.si.mem_row_size_in_kb) {
3224 gb_addr_config |= ROW_SIZE(0);
3227 gb_addr_config |= ROW_SIZE(1);
3230 gb_addr_config |= ROW_SIZE(2);
3234 /* setup tiling info dword. gb_addr_config is not adequate since it does
3235 * not have bank info, so create a custom tiling dword.
3236 * bits 3:0 num_pipes
3237 * bits 7:4 num_banks
3238 * bits 11:8 group_size
3239 * bits 15:12 row_size
3241 rdev->config.si.tile_config = 0;
3242 switch (rdev->config.si.num_tile_pipes) {
3244 rdev->config.si.tile_config |= (0 << 0);
3247 rdev->config.si.tile_config |= (1 << 0);
3250 rdev->config.si.tile_config |= (2 << 0);
3254 /* XXX what about 12? */
3255 rdev->config.si.tile_config |= (3 << 0);
3258 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
3259 case 0: /* four banks */
3260 rdev->config.si.tile_config |= 0 << 4;
3262 case 1: /* eight banks */
3263 rdev->config.si.tile_config |= 1 << 4;
3265 case 2: /* sixteen banks */
3267 rdev->config.si.tile_config |= 2 << 4;
3270 rdev->config.si.tile_config |=
3271 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3272 rdev->config.si.tile_config |=
3273 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3275 WREG32(GB_ADDR_CONFIG, gb_addr_config);
3276 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
3277 WREG32(DMIF_ADDR_CALC, gb_addr_config);
3278 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3279 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3280 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
3281 if (rdev->has_uvd) {
3282 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3283 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3284 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3287 si_tiling_mode_table_init(rdev);
3289 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
3290 rdev->config.si.max_sh_per_se,
3291 rdev->config.si.max_backends_per_se);
3293 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
3294 rdev->config.si.max_sh_per_se,
3295 rdev->config.si.max_cu_per_sh);
3297 rdev->config.si.active_cus = 0;
3298 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
3299 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
3300 rdev->config.si.active_cus +=
3301 hweight32(si_get_cu_active_bitmap(rdev, i, j));
3305 /* set HW defaults for 3D engine */
3306 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
3307 ROQ_IB2_START(0x2b)));
3308 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3310 sx_debug_1 = RREG32(SX_DEBUG_1);
3311 WREG32(SX_DEBUG_1, sx_debug_1);
3313 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3315 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |
3316 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) |
3317 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) |
3318 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size)));
3320 WREG32(VGT_NUM_INSTANCES, 1);
3322 WREG32(CP_PERFMON_CNTL, 0);
3324 WREG32(SQ_CONFIG, 0);
3326 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3327 FORCE_EOV_MAX_REZ_CNT(255)));
3329 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3330 AUTO_INVLD_EN(ES_AND_GS_AUTO));
3332 WREG32(VGT_GS_VERTEX_REUSE, 16);
3333 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3335 WREG32(CB_PERFCOUNTER0_SELECT0, 0);
3336 WREG32(CB_PERFCOUNTER0_SELECT1, 0);
3337 WREG32(CB_PERFCOUNTER1_SELECT0, 0);
3338 WREG32(CB_PERFCOUNTER1_SELECT1, 0);
3339 WREG32(CB_PERFCOUNTER2_SELECT0, 0);
3340 WREG32(CB_PERFCOUNTER2_SELECT1, 0);
3341 WREG32(CB_PERFCOUNTER3_SELECT0, 0);
3342 WREG32(CB_PERFCOUNTER3_SELECT1, 0);
3344 tmp = RREG32(HDP_MISC_CNTL);
3345 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3346 WREG32(HDP_MISC_CNTL, tmp);
3348 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3349 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3351 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3357 * GPU scratch registers helpers function.
3359 static void si_scratch_init(struct radeon_device *rdev)
3363 rdev->scratch.num_reg = 7;
3364 rdev->scratch.reg_base = SCRATCH_REG0;
3365 for (i = 0; i < rdev->scratch.num_reg; i++) {
3366 rdev->scratch.free[i] = true;
3367 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3371 void si_fence_ring_emit(struct radeon_device *rdev,
3372 struct radeon_fence *fence)
3374 struct radeon_ring *ring = &rdev->ring[fence->ring];
3375 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3377 /* flush read cache over gart */
3378 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3379 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3380 radeon_ring_write(ring, 0);
3381 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3382 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3383 PACKET3_TC_ACTION_ENA |
3384 PACKET3_SH_KCACHE_ACTION_ENA |
3385 PACKET3_SH_ICACHE_ACTION_ENA);
3386 radeon_ring_write(ring, 0xFFFFFFFF);
3387 radeon_ring_write(ring, 0);
3388 radeon_ring_write(ring, 10); /* poll interval */
3389 /* EVENT_WRITE_EOP - flush caches, send int */
3390 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3391 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
3392 radeon_ring_write(ring, lower_32_bits(addr));
3393 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
3394 radeon_ring_write(ring, fence->seq);
3395 radeon_ring_write(ring, 0);
3401 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3403 struct radeon_ring *ring = &rdev->ring[ib->ring];
3404 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
3407 if (ib->is_const_ib) {
3408 /* set switch buffer packet before const IB */
3409 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3410 radeon_ring_write(ring, 0);
3412 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3415 if (ring->rptr_save_reg) {
3416 next_rptr = ring->wptr + 3 + 4 + 8;
3417 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3418 radeon_ring_write(ring, ((ring->rptr_save_reg -
3419 PACKET3_SET_CONFIG_REG_START) >> 2));
3420 radeon_ring_write(ring, next_rptr);
3421 } else if (rdev->wb.enabled) {
3422 next_rptr = ring->wptr + 5 + 4 + 8;
3423 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3424 radeon_ring_write(ring, (1 << 8));
3425 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3426 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
3427 radeon_ring_write(ring, next_rptr);
3430 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3433 radeon_ring_write(ring, header);
3434 radeon_ring_write(ring,
3438 (ib->gpu_addr & 0xFFFFFFFC));
3439 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3440 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
3442 if (!ib->is_const_ib) {
3443 /* flush read cache over gart for this vmid */
3444 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3445 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
3446 radeon_ring_write(ring, vm_id);
3447 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3448 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3449 PACKET3_TC_ACTION_ENA |
3450 PACKET3_SH_KCACHE_ACTION_ENA |
3451 PACKET3_SH_ICACHE_ACTION_ENA);
3452 radeon_ring_write(ring, 0xFFFFFFFF);
3453 radeon_ring_write(ring, 0);
3454 radeon_ring_write(ring, 10); /* poll interval */
3461 static void si_cp_enable(struct radeon_device *rdev, bool enable)
3464 WREG32(CP_ME_CNTL, 0);
3466 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3467 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
3468 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3469 WREG32(SCRATCH_UMSK, 0);
3470 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3471 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3472 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3477 static int si_cp_load_microcode(struct radeon_device *rdev)
3481 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3484 si_cp_enable(rdev, false);
3487 const struct gfx_firmware_header_v1_0 *pfp_hdr =
3488 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data;
3489 const struct gfx_firmware_header_v1_0 *ce_hdr =
3490 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data;
3491 const struct gfx_firmware_header_v1_0 *me_hdr =
3492 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data;
3493 const __le32 *fw_data;
3496 radeon_ucode_print_gfx_hdr(&pfp_hdr->header);
3497 radeon_ucode_print_gfx_hdr(&ce_hdr->header);
3498 radeon_ucode_print_gfx_hdr(&me_hdr->header);
3501 fw_data = (const __le32 *)
3502 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
3503 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
3504 WREG32(CP_PFP_UCODE_ADDR, 0);
3505 for (i = 0; i < fw_size; i++)
3506 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
3507 WREG32(CP_PFP_UCODE_ADDR, 0);
3510 fw_data = (const __le32 *)
3511 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
3512 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
3513 WREG32(CP_CE_UCODE_ADDR, 0);
3514 for (i = 0; i < fw_size; i++)
3515 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
3516 WREG32(CP_CE_UCODE_ADDR, 0);
3519 fw_data = (const __be32 *)
3520 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
3521 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
3522 WREG32(CP_ME_RAM_WADDR, 0);
3523 for (i = 0; i < fw_size; i++)
3524 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));
3525 WREG32(CP_ME_RAM_WADDR, 0);
3527 const __be32 *fw_data;
3530 fw_data = (const __be32 *)rdev->pfp_fw->data;
3531 WREG32(CP_PFP_UCODE_ADDR, 0);
3532 for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
3533 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3534 WREG32(CP_PFP_UCODE_ADDR, 0);
3537 fw_data = (const __be32 *)rdev->ce_fw->data;
3538 WREG32(CP_CE_UCODE_ADDR, 0);
3539 for (i = 0; i < SI_CE_UCODE_SIZE; i++)
3540 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3541 WREG32(CP_CE_UCODE_ADDR, 0);
3544 fw_data = (const __be32 *)rdev->me_fw->data;
3545 WREG32(CP_ME_RAM_WADDR, 0);
3546 for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
3547 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3548 WREG32(CP_ME_RAM_WADDR, 0);
3551 WREG32(CP_PFP_UCODE_ADDR, 0);
3552 WREG32(CP_CE_UCODE_ADDR, 0);
3553 WREG32(CP_ME_RAM_WADDR, 0);
3554 WREG32(CP_ME_RAM_RADDR, 0);
3558 static int si_cp_start(struct radeon_device *rdev)
3560 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3563 r = radeon_ring_lock(rdev, ring, 7 + 4);
3565 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3569 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3570 radeon_ring_write(ring, 0x1);
3571 radeon_ring_write(ring, 0x0);
3572 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
3573 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
3574 radeon_ring_write(ring, 0);
3575 radeon_ring_write(ring, 0);
3577 /* init the CE partitions */
3578 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3579 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3580 radeon_ring_write(ring, 0xc000);
3581 radeon_ring_write(ring, 0xe000);
3582 radeon_ring_unlock_commit(rdev, ring, false);
3584 si_cp_enable(rdev, true);
3586 r = radeon_ring_lock(rdev, ring, si_default_size + 10);
3588 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3592 /* setup clear context state */
3593 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3594 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3596 for (i = 0; i < si_default_size; i++)
3597 radeon_ring_write(ring, si_default_state[i]);
3599 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3600 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3602 /* set clear context state */
3603 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3604 radeon_ring_write(ring, 0);
3606 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3607 radeon_ring_write(ring, 0x00000316);
3608 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3609 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3611 radeon_ring_unlock_commit(rdev, ring, false);
3613 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
3614 ring = &rdev->ring[i];
3615 r = radeon_ring_lock(rdev, ring, 2);
3617 /* clear the compute context state */
3618 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
3619 radeon_ring_write(ring, 0);
3621 radeon_ring_unlock_commit(rdev, ring, false);
3627 static void si_cp_fini(struct radeon_device *rdev)
3629 struct radeon_ring *ring;
3630 si_cp_enable(rdev, false);
3632 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3633 radeon_ring_fini(rdev, ring);
3634 radeon_scratch_free(rdev, ring->rptr_save_reg);
3636 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3637 radeon_ring_fini(rdev, ring);
3638 radeon_scratch_free(rdev, ring->rptr_save_reg);
3640 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3641 radeon_ring_fini(rdev, ring);
3642 radeon_scratch_free(rdev, ring->rptr_save_reg);
3645 static int si_cp_resume(struct radeon_device *rdev)
3647 struct radeon_ring *ring;
3652 si_enable_gui_idle_interrupt(rdev, false);
3654 WREG32(CP_SEM_WAIT_TIMER, 0x0);
3655 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3657 /* Set the write pointer delay */
3658 WREG32(CP_RB_WPTR_DELAY, 0);
3660 WREG32(CP_DEBUG, 0);
3661 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3663 /* ring 0 - compute and gfx */
3664 /* Set ring buffer size */
3665 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3666 rb_bufsz = order_base_2(ring->ring_size / 8);
3667 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3669 tmp |= BUF_SWAP_32BIT;
3671 WREG32(CP_RB0_CNTL, tmp);
3673 /* Initialize the ring buffer's read and write pointers */
3674 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
3676 WREG32(CP_RB0_WPTR, ring->wptr);
3678 /* set the wb address whether it's enabled or not */
3679 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
3680 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
3682 if (rdev->wb.enabled)
3683 WREG32(SCRATCH_UMSK, 0xff);
3685 tmp |= RB_NO_UPDATE;
3686 WREG32(SCRATCH_UMSK, 0);
3690 WREG32(CP_RB0_CNTL, tmp);
3692 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3694 /* ring1 - compute only */
3695 /* Set ring buffer size */
3696 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
3697 rb_bufsz = order_base_2(ring->ring_size / 8);
3698 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3700 tmp |= BUF_SWAP_32BIT;
3702 WREG32(CP_RB1_CNTL, tmp);
3704 /* Initialize the ring buffer's read and write pointers */
3705 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
3707 WREG32(CP_RB1_WPTR, ring->wptr);
3709 /* set the wb address whether it's enabled or not */
3710 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
3711 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
3714 WREG32(CP_RB1_CNTL, tmp);
3716 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3718 /* ring2 - compute only */
3719 /* Set ring buffer size */
3720 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
3721 rb_bufsz = order_base_2(ring->ring_size / 8);
3722 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
3724 tmp |= BUF_SWAP_32BIT;
3726 WREG32(CP_RB2_CNTL, tmp);
3728 /* Initialize the ring buffer's read and write pointers */
3729 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
3731 WREG32(CP_RB2_WPTR, ring->wptr);
3733 /* set the wb address whether it's enabled or not */
3734 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
3735 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
3738 WREG32(CP_RB2_CNTL, tmp);
3740 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3742 /* start the rings */
3744 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
3745 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true;
3746 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true;
3747 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3749 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3750 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3751 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3754 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
3756 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
3758 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
3760 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
3763 si_enable_gui_idle_interrupt(rdev, true);
3765 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
3766 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
3771 u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
3777 tmp = RREG32(GRBM_STATUS);
3778 if (tmp & (PA_BUSY | SC_BUSY |
3779 BCI_BUSY | SX_BUSY |
3780 TA_BUSY | VGT_BUSY |
3782 GDS_BUSY | SPI_BUSY |
3783 IA_BUSY | IA_BUSY_NO_DMA))
3784 reset_mask |= RADEON_RESET_GFX;
3786 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
3787 CP_BUSY | CP_COHERENCY_BUSY))
3788 reset_mask |= RADEON_RESET_CP;
3790 if (tmp & GRBM_EE_BUSY)
3791 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
3794 tmp = RREG32(GRBM_STATUS2);
3795 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
3796 reset_mask |= RADEON_RESET_RLC;
3798 /* DMA_STATUS_REG 0 */
3799 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3800 if (!(tmp & DMA_IDLE))
3801 reset_mask |= RADEON_RESET_DMA;
3803 /* DMA_STATUS_REG 1 */
3804 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
3805 if (!(tmp & DMA_IDLE))
3806 reset_mask |= RADEON_RESET_DMA1;
3809 tmp = RREG32(SRBM_STATUS2);
3811 reset_mask |= RADEON_RESET_DMA;
3813 if (tmp & DMA1_BUSY)
3814 reset_mask |= RADEON_RESET_DMA1;
3817 tmp = RREG32(SRBM_STATUS);
3820 reset_mask |= RADEON_RESET_IH;
3823 reset_mask |= RADEON_RESET_SEM;
3825 if (tmp & GRBM_RQ_PENDING)
3826 reset_mask |= RADEON_RESET_GRBM;
3829 reset_mask |= RADEON_RESET_VMC;
3831 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
3832 MCC_BUSY | MCD_BUSY))
3833 reset_mask |= RADEON_RESET_MC;
3835 if (evergreen_is_display_hung(rdev))
3836 reset_mask |= RADEON_RESET_DISPLAY;
3839 tmp = RREG32(VM_L2_STATUS);
3841 reset_mask |= RADEON_RESET_VMC;
3843 /* Skip MC reset as it's mostly likely not hung, just busy */
3844 if (reset_mask & RADEON_RESET_MC) {
3845 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
3846 reset_mask &= ~RADEON_RESET_MC;
3852 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
3854 struct evergreen_mc_save save;
3855 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3858 if (reset_mask == 0)
3861 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
3863 evergreen_print_gpu_status_regs(rdev);
3864 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3865 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3866 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3867 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3876 /* Disable CP parsing/prefetching */
3877 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
3879 if (reset_mask & RADEON_RESET_DMA) {
3881 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3882 tmp &= ~DMA_RB_ENABLE;
3883 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
3885 if (reset_mask & RADEON_RESET_DMA1) {
3887 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
3888 tmp &= ~DMA_RB_ENABLE;
3889 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
3894 evergreen_mc_stop(rdev, &save);
3895 if (evergreen_mc_wait_for_idle(rdev)) {
3896 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3899 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
3900 grbm_soft_reset = SOFT_RESET_CB |
3914 if (reset_mask & RADEON_RESET_CP) {
3915 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
3917 srbm_soft_reset |= SOFT_RESET_GRBM;
3920 if (reset_mask & RADEON_RESET_DMA)
3921 srbm_soft_reset |= SOFT_RESET_DMA;
3923 if (reset_mask & RADEON_RESET_DMA1)
3924 srbm_soft_reset |= SOFT_RESET_DMA1;
3926 if (reset_mask & RADEON_RESET_DISPLAY)
3927 srbm_soft_reset |= SOFT_RESET_DC;
3929 if (reset_mask & RADEON_RESET_RLC)
3930 grbm_soft_reset |= SOFT_RESET_RLC;
3932 if (reset_mask & RADEON_RESET_SEM)
3933 srbm_soft_reset |= SOFT_RESET_SEM;
3935 if (reset_mask & RADEON_RESET_IH)
3936 srbm_soft_reset |= SOFT_RESET_IH;
3938 if (reset_mask & RADEON_RESET_GRBM)
3939 srbm_soft_reset |= SOFT_RESET_GRBM;
3941 if (reset_mask & RADEON_RESET_VMC)
3942 srbm_soft_reset |= SOFT_RESET_VMC;
3944 if (reset_mask & RADEON_RESET_MC)
3945 srbm_soft_reset |= SOFT_RESET_MC;
3947 if (grbm_soft_reset) {
3948 tmp = RREG32(GRBM_SOFT_RESET);
3949 tmp |= grbm_soft_reset;
3950 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3951 WREG32(GRBM_SOFT_RESET, tmp);
3952 tmp = RREG32(GRBM_SOFT_RESET);
3956 tmp &= ~grbm_soft_reset;
3957 WREG32(GRBM_SOFT_RESET, tmp);
3958 tmp = RREG32(GRBM_SOFT_RESET);
3961 if (srbm_soft_reset) {
3962 tmp = RREG32(SRBM_SOFT_RESET);
3963 tmp |= srbm_soft_reset;
3964 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3965 WREG32(SRBM_SOFT_RESET, tmp);
3966 tmp = RREG32(SRBM_SOFT_RESET);
3970 tmp &= ~srbm_soft_reset;
3971 WREG32(SRBM_SOFT_RESET, tmp);
3972 tmp = RREG32(SRBM_SOFT_RESET);
3975 /* Wait a little for things to settle down */
3978 evergreen_mc_resume(rdev, &save);
3981 evergreen_print_gpu_status_regs(rdev);
3984 static void si_set_clk_bypass_mode(struct radeon_device *rdev)
3988 tmp = RREG32(CG_SPLL_FUNC_CNTL);
3989 tmp |= SPLL_BYPASS_EN;
3990 WREG32(CG_SPLL_FUNC_CNTL, tmp);
3992 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
3993 tmp |= SPLL_CTLREQ_CHG;
3994 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
3996 for (i = 0; i < rdev->usec_timeout; i++) {
3997 if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4003 tmp &= ~(SPLL_CTLREQ_CHG | SCLK_MUX_UPDATE);
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4006 tmp = RREG32(MPLL_CNTL_MODE);
4007 tmp &= ~MPLL_MCLK_SEL;
4008 WREG32(MPLL_CNTL_MODE, tmp);
4011 static void si_spll_powerdown(struct radeon_device *rdev)
4015 tmp = RREG32(SPLL_CNTL_MODE);
4016 tmp |= SPLL_SW_DIR_CONTROL;
4017 WREG32(SPLL_CNTL_MODE, tmp);
4019 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4021 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4023 tmp = RREG32(CG_SPLL_FUNC_CNTL);
4025 WREG32(CG_SPLL_FUNC_CNTL, tmp);
4027 tmp = RREG32(SPLL_CNTL_MODE);
4028 tmp &= ~SPLL_SW_DIR_CONTROL;
4029 WREG32(SPLL_CNTL_MODE, tmp);
4032 static void si_gpu_pci_config_reset(struct radeon_device *rdev)
4034 struct evergreen_mc_save save;
4037 dev_info(rdev->dev, "GPU pci config reset\n");
4045 /* Disable CP parsing/prefetching */
4046 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4048 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4049 tmp &= ~DMA_RB_ENABLE;
4050 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4052 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
4053 tmp &= ~DMA_RB_ENABLE;
4054 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
4055 /* XXX other engines? */
4057 /* halt the rlc, disable cp internal ints */
4062 /* disable mem access */
4063 evergreen_mc_stop(rdev, &save);
4064 if (evergreen_mc_wait_for_idle(rdev)) {
4065 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
4068 /* set mclk/sclk to bypass */
4069 si_set_clk_bypass_mode(rdev);
4070 /* powerdown spll */
4071 si_spll_powerdown(rdev);
4073 pci_clear_master(rdev->pdev);
4075 radeon_pci_config_reset(rdev);
4076 /* wait for asic to come out of reset */
4077 for (i = 0; i < rdev->usec_timeout; i++) {
4078 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
4084 int si_asic_reset(struct radeon_device *rdev, bool hard)
4089 si_gpu_pci_config_reset(rdev);
4093 reset_mask = si_gpu_check_soft_reset(rdev);
4096 r600_set_bios_scratch_engine_hung(rdev, true);
4098 /* try soft reset */
4099 si_gpu_soft_reset(rdev, reset_mask);
4101 reset_mask = si_gpu_check_soft_reset(rdev);
4103 /* try pci config reset */
4104 if (reset_mask && radeon_hard_reset)
4105 si_gpu_pci_config_reset(rdev);
4107 reset_mask = si_gpu_check_soft_reset(rdev);
4110 r600_set_bios_scratch_engine_hung(rdev, false);
4116 * si_gfx_is_lockup - Check if the GFX engine is locked up
4118 * @rdev: radeon_device pointer
4119 * @ring: radeon_ring structure holding ring information
4121 * Check if the GFX engine is locked up.
4122 * Returns true if the engine appears to be locked up, false if not.
4124 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
4126 u32 reset_mask = si_gpu_check_soft_reset(rdev);
4128 if (!(reset_mask & (RADEON_RESET_GFX |
4129 RADEON_RESET_COMPUTE |
4130 RADEON_RESET_CP))) {
4131 radeon_ring_lockup_update(rdev, ring);
4134 return radeon_ring_test_lockup(rdev, ring);
4138 static void si_mc_program(struct radeon_device *rdev)
4140 struct evergreen_mc_save save;
4144 /* Initialize HDP */
4145 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
4146 WREG32((0x2c14 + j), 0x00000000);
4147 WREG32((0x2c18 + j), 0x00000000);
4148 WREG32((0x2c1c + j), 0x00000000);
4149 WREG32((0x2c20 + j), 0x00000000);
4150 WREG32((0x2c24 + j), 0x00000000);
4152 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
4154 evergreen_mc_stop(rdev, &save);
4155 if (radeon_mc_wait_for_idle(rdev)) {
4156 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4158 if (!ASIC_IS_NODCE(rdev))
4159 /* Lockout access through VGA aperture*/
4160 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
4161 /* Update configuration */
4162 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
4163 rdev->mc.vram_start >> 12);
4164 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
4165 rdev->mc.vram_end >> 12);
4166 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
4167 rdev->vram_scratch.gpu_addr >> 12);
4168 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
4169 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
4170 WREG32(MC_VM_FB_LOCATION, tmp);
4171 /* XXX double check these! */
4172 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
4173 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
4174 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
4175 WREG32(MC_VM_AGP_BASE, 0);
4176 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
4177 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
4178 if (radeon_mc_wait_for_idle(rdev)) {
4179 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4181 evergreen_mc_resume(rdev, &save);
4182 if (!ASIC_IS_NODCE(rdev)) {
4183 /* we need to own VRAM, so turn off the VGA renderer here
4184 * to stop it overwriting our objects */
4185 rv515_vga_render_disable(rdev);
4189 void si_vram_gtt_location(struct radeon_device *rdev,
4190 struct radeon_mc *mc)
4192 if (mc->mc_vram_size > 0xFFC0000000ULL) {
4193 /* leave room for at least 1024M GTT */
4194 dev_warn(rdev->dev, "limiting VRAM\n");
4195 mc->real_vram_size = 0xFFC0000000ULL;
4196 mc->mc_vram_size = 0xFFC0000000ULL;
4198 radeon_vram_location(rdev, &rdev->mc, 0);
4199 rdev->mc.gtt_base_align = 0;
4200 radeon_gtt_location(rdev, mc);
4203 static int si_mc_init(struct radeon_device *rdev)
4206 int chansize, numchan;
4208 /* Get VRAM informations */
4209 rdev->mc.vram_is_ddr = true;
4210 tmp = RREG32(MC_ARB_RAMCFG);
4211 if (tmp & CHANSIZE_OVERRIDE) {
4213 } else if (tmp & CHANSIZE_MASK) {
4218 tmp = RREG32(MC_SHARED_CHMAP);
4219 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
4249 rdev->mc.vram_width = numchan * chansize;
4250 /* Could aper size report 0 ? */
4251 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
4252 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
4253 /* size in MB on si */
4254 tmp = RREG32(CONFIG_MEMSIZE);
4255 /* some boards may have garbage in the upper 16 bits */
4256 if (tmp & 0xffff0000) {
4257 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
4261 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL;
4262 rdev->mc.real_vram_size = rdev->mc.mc_vram_size;
4263 rdev->mc.visible_vram_size = rdev->mc.aper_size;
4264 si_vram_gtt_location(rdev, &rdev->mc);
4265 radeon_update_bandwidth_info(rdev);
4273 void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
4275 /* flush hdp cache */
4276 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4278 /* bits 0-15 are the VM contexts0-15 */
4279 WREG32(VM_INVALIDATE_REQUEST, 1);
4282 static int si_pcie_gart_enable(struct radeon_device *rdev)
4286 if (rdev->gart.robj == NULL) {
4287 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
4290 r = radeon_gart_table_vram_pin(rdev);
4293 /* Setup TLB control */
4294 WREG32(MC_VM_MX_L1_TLB_CNTL,
4297 ENABLE_L1_FRAGMENT_PROCESSING |
4298 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4299 ENABLE_ADVANCED_DRIVER_MODEL |
4300 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4301 /* Setup L2 cache */
4302 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
4303 ENABLE_L2_FRAGMENT_PROCESSING |
4304 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4305 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4306 EFFECTIVE_L2_QUEUE_SIZE(7) |
4307 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4308 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
4309 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4311 L2_CACHE_BIGK_FRAGMENT_SIZE(4));
4312 /* setup context0 */
4313 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
4314 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
4315 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
4316 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
4317 (u32)(rdev->dummy_page.addr >> 12));
4318 WREG32(VM_CONTEXT0_CNTL2, 0);
4319 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
4320 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
4326 /* empty context1-15 */
4327 /* set vm size, must be a multiple of 4 */
4328 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
4329 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);
4330 /* Assign the pt base to something valid for now; the pts used for
4331 * the VMs are determined by the application and setup and assigned
4332 * on the fly in the vm part of radeon_gart.c
4334 for (i = 1; i < 16; i++) {
4336 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
4337 rdev->vm_manager.saved_table_addr[i]);
4339 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
4340 rdev->vm_manager.saved_table_addr[i]);
4343 /* enable context1-15 */
4344 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
4345 (u32)(rdev->dummy_page.addr >> 12));
4346 WREG32(VM_CONTEXT1_CNTL2, 4);
4347 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
4348 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
4349 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4350 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4351 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4352 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
4353 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
4354 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
4355 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
4356 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
4357 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
4358 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
4359 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
4360 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
4362 si_pcie_gart_tlb_flush(rdev);
4363 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
4364 (unsigned)(rdev->mc.gtt_size >> 20),
4365 (unsigned long long)rdev->gart.table_addr);
4366 rdev->gart.ready = true;
4370 static void si_pcie_gart_disable(struct radeon_device *rdev)
4374 for (i = 1; i < 16; ++i) {
4377 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2);
4379 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2);
4380 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
4383 /* Disable all tables */
4384 WREG32(VM_CONTEXT0_CNTL, 0);
4385 WREG32(VM_CONTEXT1_CNTL, 0);
4386 /* Setup TLB control */
4387 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
4388 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
4389 /* Setup L2 cache */
4390 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
4391 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
4392 EFFECTIVE_L2_QUEUE_SIZE(7) |
4393 CONTEXT1_IDENTITY_ACCESS_MODE(1));
4394 WREG32(VM_L2_CNTL2, 0);
4395 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
4396 L2_CACHE_BIGK_FRAGMENT_SIZE(0));
4397 radeon_gart_table_vram_unpin(rdev);
4400 static void si_pcie_gart_fini(struct radeon_device *rdev)
4402 si_pcie_gart_disable(rdev);
4403 radeon_gart_table_vram_free(rdev);
4404 radeon_gart_fini(rdev);
4408 static bool si_vm_reg_valid(u32 reg)
4410 /* context regs are fine */
4414 /* shader regs are also fine */
4415 if (reg >= 0xB000 && reg < 0xC000)
4418 /* check config regs */
4420 case GRBM_GFX_INDEX:
4421 case CP_STRMOUT_CNTL:
4422 case VGT_VTX_VECT_EJECT_REG:
4423 case VGT_CACHE_INVALIDATION:
4424 case VGT_ESGS_RING_SIZE:
4425 case VGT_GSVS_RING_SIZE:
4426 case VGT_GS_VERTEX_REUSE:
4427 case VGT_PRIMITIVE_TYPE:
4428 case VGT_INDEX_TYPE:
4429 case VGT_NUM_INDICES:
4430 case VGT_NUM_INSTANCES:
4431 case VGT_TF_RING_SIZE:
4432 case VGT_HS_OFFCHIP_PARAM:
4433 case VGT_TF_MEMORY_BASE:
4435 case PA_SU_LINE_STIPPLE_VALUE:
4436 case PA_SC_LINE_STIPPLE_STATE:
4439 case SPI_STATIC_THREAD_MGMT_1:
4440 case SPI_STATIC_THREAD_MGMT_2:
4441 case SPI_STATIC_THREAD_MGMT_3:
4442 case SPI_PS_MAX_WAVE_ID:
4443 case SPI_CONFIG_CNTL:
4444 case SPI_CONFIG_CNTL_1:
4446 case TA_CS_BC_BASE_ADDR:
4449 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
4454 static int si_vm_packet3_ce_check(struct radeon_device *rdev,
4455 u32 *ib, struct radeon_cs_packet *pkt)
4457 switch (pkt->opcode) {
4459 case PACKET3_SET_BASE:
4460 case PACKET3_SET_CE_DE_COUNTERS:
4461 case PACKET3_LOAD_CONST_RAM:
4462 case PACKET3_WRITE_CONST_RAM:
4463 case PACKET3_WRITE_CONST_RAM_OFFSET:
4464 case PACKET3_DUMP_CONST_RAM:
4465 case PACKET3_INCREMENT_CE_COUNTER:
4466 case PACKET3_WAIT_ON_DE_COUNTER:
4467 case PACKET3_CE_WRITE:
4470 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
4476 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx)
4478 u32 start_reg, reg, i;
4479 u32 command = ib[idx + 4];
4480 u32 info = ib[idx + 1];
4481 u32 idx_value = ib[idx];
4482 if (command & PACKET3_CP_DMA_CMD_SAS) {
4483 /* src address space is register */
4484 if (((info & 0x60000000) >> 29) == 0) {
4485 start_reg = idx_value << 2;
4486 if (command & PACKET3_CP_DMA_CMD_SAIC) {
4488 if (!si_vm_reg_valid(reg)) {
4489 DRM_ERROR("CP DMA Bad SRC register\n");
4493 for (i = 0; i < (command & 0x1fffff); i++) {
4494 reg = start_reg + (4 * i);
4495 if (!si_vm_reg_valid(reg)) {
4496 DRM_ERROR("CP DMA Bad SRC register\n");
4503 if (command & PACKET3_CP_DMA_CMD_DAS) {
4504 /* dst address space is register */
4505 if (((info & 0x00300000) >> 20) == 0) {
4506 start_reg = ib[idx + 2];
4507 if (command & PACKET3_CP_DMA_CMD_DAIC) {
4509 if (!si_vm_reg_valid(reg)) {
4510 DRM_ERROR("CP DMA Bad DST register\n");
4514 for (i = 0; i < (command & 0x1fffff); i++) {
4515 reg = start_reg + (4 * i);
4516 if (!si_vm_reg_valid(reg)) {
4517 DRM_ERROR("CP DMA Bad DST register\n");
4527 static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
4528 u32 *ib, struct radeon_cs_packet *pkt)
4531 u32 idx = pkt->idx + 1;
4532 u32 idx_value = ib[idx];
4533 u32 start_reg, end_reg, reg, i;
4535 switch (pkt->opcode) {
4537 case PACKET3_SET_BASE:
4538 case PACKET3_CLEAR_STATE:
4539 case PACKET3_INDEX_BUFFER_SIZE:
4540 case PACKET3_DISPATCH_DIRECT:
4541 case PACKET3_DISPATCH_INDIRECT:
4542 case PACKET3_ALLOC_GDS:
4543 case PACKET3_WRITE_GDS_RAM:
4544 case PACKET3_ATOMIC_GDS:
4545 case PACKET3_ATOMIC:
4546 case PACKET3_OCCLUSION_QUERY:
4547 case PACKET3_SET_PREDICATION:
4548 case PACKET3_COND_EXEC:
4549 case PACKET3_PRED_EXEC:
4550 case PACKET3_DRAW_INDIRECT:
4551 case PACKET3_DRAW_INDEX_INDIRECT:
4552 case PACKET3_INDEX_BASE:
4553 case PACKET3_DRAW_INDEX_2:
4554 case PACKET3_CONTEXT_CONTROL:
4555 case PACKET3_INDEX_TYPE:
4556 case PACKET3_DRAW_INDIRECT_MULTI:
4557 case PACKET3_DRAW_INDEX_AUTO:
4558 case PACKET3_DRAW_INDEX_IMMD:
4559 case PACKET3_NUM_INSTANCES:
4560 case PACKET3_DRAW_INDEX_MULTI_AUTO:
4561 case PACKET3_STRMOUT_BUFFER_UPDATE:
4562 case PACKET3_DRAW_INDEX_OFFSET_2:
4563 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
4564 case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
4565 case PACKET3_MPEG_INDEX:
4566 case PACKET3_WAIT_REG_MEM:
4567 case PACKET3_MEM_WRITE:
4568 case PACKET3_PFP_SYNC_ME:
4569 case PACKET3_SURFACE_SYNC:
4570 case PACKET3_EVENT_WRITE:
4571 case PACKET3_EVENT_WRITE_EOP:
4572 case PACKET3_EVENT_WRITE_EOS:
4573 case PACKET3_SET_CONTEXT_REG:
4574 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4575 case PACKET3_SET_SH_REG:
4576 case PACKET3_SET_SH_REG_OFFSET:
4577 case PACKET3_INCREMENT_DE_COUNTER:
4578 case PACKET3_WAIT_ON_CE_COUNTER:
4579 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4580 case PACKET3_ME_WRITE:
4582 case PACKET3_COPY_DATA:
4583 if ((idx_value & 0xf00) == 0) {
4584 reg = ib[idx + 3] * 4;
4585 if (!si_vm_reg_valid(reg))
4589 case PACKET3_WRITE_DATA:
4590 if ((idx_value & 0xf00) == 0) {
4591 start_reg = ib[idx + 1] * 4;
4592 if (idx_value & 0x10000) {
4593 if (!si_vm_reg_valid(start_reg))
4596 for (i = 0; i < (pkt->count - 2); i++) {
4597 reg = start_reg + (4 * i);
4598 if (!si_vm_reg_valid(reg))
4604 case PACKET3_COND_WRITE:
4605 if (idx_value & 0x100) {
4606 reg = ib[idx + 5] * 4;
4607 if (!si_vm_reg_valid(reg))
4611 case PACKET3_COPY_DW:
4612 if (idx_value & 0x2) {
4613 reg = ib[idx + 3] * 4;
4614 if (!si_vm_reg_valid(reg))
4618 case PACKET3_SET_CONFIG_REG:
4619 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
4620 end_reg = 4 * pkt->count + start_reg - 4;
4621 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
4622 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
4623 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
4624 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
4627 for (i = 0; i < pkt->count; i++) {
4628 reg = start_reg + (4 * i);
4629 if (!si_vm_reg_valid(reg))
4633 case PACKET3_CP_DMA:
4634 r = si_vm_packet3_cp_dma_check(ib, idx);
4639 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode);
4645 static int si_vm_packet3_compute_check(struct radeon_device *rdev,
4646 u32 *ib, struct radeon_cs_packet *pkt)
4649 u32 idx = pkt->idx + 1;
4650 u32 idx_value = ib[idx];
4651 u32 start_reg, reg, i;
4653 switch (pkt->opcode) {
4655 case PACKET3_SET_BASE:
4656 case PACKET3_CLEAR_STATE:
4657 case PACKET3_DISPATCH_DIRECT:
4658 case PACKET3_DISPATCH_INDIRECT:
4659 case PACKET3_ALLOC_GDS:
4660 case PACKET3_WRITE_GDS_RAM:
4661 case PACKET3_ATOMIC_GDS:
4662 case PACKET3_ATOMIC:
4663 case PACKET3_OCCLUSION_QUERY:
4664 case PACKET3_SET_PREDICATION:
4665 case PACKET3_COND_EXEC:
4666 case PACKET3_PRED_EXEC:
4667 case PACKET3_CONTEXT_CONTROL:
4668 case PACKET3_STRMOUT_BUFFER_UPDATE:
4669 case PACKET3_WAIT_REG_MEM:
4670 case PACKET3_MEM_WRITE:
4671 case PACKET3_PFP_SYNC_ME:
4672 case PACKET3_SURFACE_SYNC:
4673 case PACKET3_EVENT_WRITE:
4674 case PACKET3_EVENT_WRITE_EOP:
4675 case PACKET3_EVENT_WRITE_EOS:
4676 case PACKET3_SET_CONTEXT_REG:
4677 case PACKET3_SET_CONTEXT_REG_INDIRECT:
4678 case PACKET3_SET_SH_REG:
4679 case PACKET3_SET_SH_REG_OFFSET:
4680 case PACKET3_INCREMENT_DE_COUNTER:
4681 case PACKET3_WAIT_ON_CE_COUNTER:
4682 case PACKET3_WAIT_ON_AVAIL_BUFFER:
4683 case PACKET3_ME_WRITE:
4685 case PACKET3_COPY_DATA:
4686 if ((idx_value & 0xf00) == 0) {
4687 reg = ib[idx + 3] * 4;
4688 if (!si_vm_reg_valid(reg))
4692 case PACKET3_WRITE_DATA:
4693 if ((idx_value & 0xf00) == 0) {
4694 start_reg = ib[idx + 1] * 4;
4695 if (idx_value & 0x10000) {
4696 if (!si_vm_reg_valid(start_reg))
4699 for (i = 0; i < (pkt->count - 2); i++) {
4700 reg = start_reg + (4 * i);
4701 if (!si_vm_reg_valid(reg))
4707 case PACKET3_COND_WRITE:
4708 if (idx_value & 0x100) {
4709 reg = ib[idx + 5] * 4;
4710 if (!si_vm_reg_valid(reg))
4714 case PACKET3_COPY_DW:
4715 if (idx_value & 0x2) {
4716 reg = ib[idx + 3] * 4;
4717 if (!si_vm_reg_valid(reg))
4721 case PACKET3_CP_DMA:
4722 r = si_vm_packet3_cp_dma_check(ib, idx);
4727 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode);
4733 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4737 struct radeon_cs_packet pkt;
4741 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
4742 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
4745 case RADEON_PACKET_TYPE0:
4746 dev_err(rdev->dev, "Packet0 not allowed!\n");
4749 case RADEON_PACKET_TYPE2:
4752 case RADEON_PACKET_TYPE3:
4753 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
4754 if (ib->is_const_ib)
4755 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
4758 case RADEON_RING_TYPE_GFX_INDEX:
4759 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt);
4761 case CAYMAN_RING_TYPE_CP1_INDEX:
4762 case CAYMAN_RING_TYPE_CP2_INDEX:
4763 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt);
4766 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring);
4771 idx += pkt.count + 2;
4774 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
4779 for (i = 0; i < ib->length_dw; i++) {
4781 printk("\t0x%08x <---\n", ib->ptr[i]);
4783 printk("\t0x%08x\n", ib->ptr[i]);
4787 } while (idx < ib->length_dw);
4795 int si_vm_init(struct radeon_device *rdev)
4798 rdev->vm_manager.nvm = 16;
4799 /* base offset of vram pages */
4800 rdev->vm_manager.vram_base_offset = 0;
4805 void si_vm_fini(struct radeon_device *rdev)
4810 * si_vm_decode_fault - print human readable fault info
4812 * @rdev: radeon_device pointer
4813 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
4814 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
4816 * Print human readable fault information (SI).
4818 static void si_vm_decode_fault(struct radeon_device *rdev,
4819 u32 status, u32 addr)
4821 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
4822 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
4823 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
4826 if (rdev->family == CHIP_TAHITI) {
5067 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
5068 protections, vmid, addr,
5069 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5073 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
5074 unsigned vm_id, uint64_t pd_addr)
5076 /* write new base address */
5077 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5078 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5079 WRITE_DATA_DST_SEL(0)));
5082 radeon_ring_write(ring,
5083 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);
5085 radeon_ring_write(ring,
5086 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);
5088 radeon_ring_write(ring, 0);
5089 radeon_ring_write(ring, pd_addr >> 12);
5091 /* flush hdp cache */
5092 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5093 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5094 WRITE_DATA_DST_SEL(0)));
5095 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
5096 radeon_ring_write(ring, 0);
5097 radeon_ring_write(ring, 0x1);
5099 /* bits 0-15 are the VM contexts0-15 */
5100 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5101 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5102 WRITE_DATA_DST_SEL(0)));
5103 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5104 radeon_ring_write(ring, 0);
5105 radeon_ring_write(ring, 1 << vm_id);
5107 /* wait for the invalidate to complete */
5108 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
5109 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
5110 WAIT_REG_MEM_ENGINE(0))); /* me */
5111 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5112 radeon_ring_write(ring, 0);
5113 radeon_ring_write(ring, 0); /* ref */
5114 radeon_ring_write(ring, 0); /* mask */
5115 radeon_ring_write(ring, 0x20); /* poll interval */
5117 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5118 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5119 radeon_ring_write(ring, 0x0);
5123 * Power and clock gating
5125 static void si_wait_for_rlc_serdes(struct radeon_device *rdev)
5129 for (i = 0; i < rdev->usec_timeout; i++) {
5130 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
5135 for (i = 0; i < rdev->usec_timeout; i++) {
5136 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
5142 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
5145 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5150 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5152 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5153 WREG32(CP_INT_CNTL_RING0, tmp);
5156 /* read a gfx register */
5157 tmp = RREG32(DB_DEPTH_INFO);
5159 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
5160 for (i = 0; i < rdev->usec_timeout; i++) {
5161 if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
5168 static void si_set_uvd_dcm(struct radeon_device *rdev,
5173 tmp = RREG32(UVD_CGC_CTRL);
5174 tmp &= ~(CLK_OD_MASK | CG_DT_MASK);
5175 tmp |= DCM | CG_DT(1) | CLK_OD(4);
5179 tmp2 = DYN_OR_EN | DYN_RR_EN | G_DIV_ID(7);
5185 WREG32(UVD_CGC_CTRL, tmp);
5186 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2);
5189 void si_init_uvd_internal_cg(struct radeon_device *rdev)
5191 bool hw_mode = true;
5194 si_set_uvd_dcm(rdev, false);
5196 u32 tmp = RREG32(UVD_CGC_CTRL);
5198 WREG32(UVD_CGC_CTRL, tmp);
5202 static u32 si_halt_rlc(struct radeon_device *rdev)
5206 orig = data = RREG32(RLC_CNTL);
5208 if (data & RLC_ENABLE) {
5209 data &= ~RLC_ENABLE;
5210 WREG32(RLC_CNTL, data);
5212 si_wait_for_rlc_serdes(rdev);
5218 static void si_update_rlc(struct radeon_device *rdev, u32 rlc)
5222 tmp = RREG32(RLC_CNTL);
5224 WREG32(RLC_CNTL, rlc);
5227 static void si_enable_dma_pg(struct radeon_device *rdev, bool enable)
5231 orig = data = RREG32(DMA_PG);
5232 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA))
5233 data |= PG_CNTL_ENABLE;
5235 data &= ~PG_CNTL_ENABLE;
5237 WREG32(DMA_PG, data);
5240 static void si_init_dma_pg(struct radeon_device *rdev)
5244 WREG32(DMA_PGFSM_WRITE, 0x00002000);
5245 WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
5247 for (tmp = 0; tmp < 5; tmp++)
5248 WREG32(DMA_PGFSM_WRITE, 0);
5251 static void si_enable_gfx_cgpg(struct radeon_device *rdev,
5256 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
5257 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10);
5258 WREG32(RLC_TTOP_D, tmp);
5260 tmp = RREG32(RLC_PG_CNTL);
5261 tmp |= GFX_PG_ENABLE;
5262 WREG32(RLC_PG_CNTL, tmp);
5264 tmp = RREG32(RLC_AUTO_PG_CTRL);
5266 WREG32(RLC_AUTO_PG_CTRL, tmp);
5268 tmp = RREG32(RLC_AUTO_PG_CTRL);
5270 WREG32(RLC_AUTO_PG_CTRL, tmp);
5272 tmp = RREG32(DB_RENDER_CONTROL);
5276 static void si_init_gfx_cgpg(struct radeon_device *rdev)
5280 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5282 tmp = RREG32(RLC_PG_CNTL);
5284 WREG32(RLC_PG_CNTL, tmp);
5286 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5288 tmp = RREG32(RLC_AUTO_PG_CTRL);
5290 tmp &= ~GRBM_REG_SGIT_MASK;
5291 tmp |= GRBM_REG_SGIT(0x700);
5292 tmp &= ~PG_AFTER_GRBM_REG_ST_MASK;
5293 WREG32(RLC_AUTO_PG_CTRL, tmp);
5296 static u32 si_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
5298 u32 mask = 0, tmp, tmp1;
5301 si_select_se_sh(rdev, se, sh);
5302 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
5303 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
5304 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5311 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) {
5316 return (~tmp) & mask;
5319 static void si_init_ao_cu_mask(struct radeon_device *rdev)
5321 u32 i, j, k, active_cu_number = 0;
5322 u32 mask, counter, cu_bitmap;
5325 for (i = 0; i < rdev->config.si.max_shader_engines; i++) {
5326 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) {
5330 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) {
5331 if (si_get_cu_active_bitmap(rdev, i, j) & mask) {
5339 active_cu_number += counter;
5340 tmp |= (cu_bitmap << (i * 16 + j * 8));
5344 WREG32(RLC_PG_AO_CU_MASK, tmp);
5346 tmp = RREG32(RLC_MAX_PG_CU);
5347 tmp &= ~MAX_PU_CU_MASK;
5348 tmp |= MAX_PU_CU(active_cu_number);
5349 WREG32(RLC_MAX_PG_CU, tmp);
5352 static void si_enable_cgcg(struct radeon_device *rdev,
5355 u32 data, orig, tmp;
5357 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5359 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5360 si_enable_gui_idle_interrupt(rdev, true);
5362 WREG32(RLC_GCPM_GENERAL_3, 0x00000080);
5364 tmp = si_halt_rlc(rdev);
5366 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5367 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5368 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);
5370 si_wait_for_rlc_serdes(rdev);
5372 si_update_rlc(rdev, tmp);
5374 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);
5376 data |= CGCG_EN | CGLS_EN;
5378 si_enable_gui_idle_interrupt(rdev, false);
5380 RREG32(CB_CGTT_SCLK_CTRL);
5381 RREG32(CB_CGTT_SCLK_CTRL);
5382 RREG32(CB_CGTT_SCLK_CTRL);
5383 RREG32(CB_CGTT_SCLK_CTRL);
5385 data &= ~(CGCG_EN | CGLS_EN);
5389 WREG32(RLC_CGCG_CGLS_CTRL, data);
5392 static void si_enable_mgcg(struct radeon_device *rdev,
5395 u32 data, orig, tmp = 0;
5397 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5398 orig = data = RREG32(CGTS_SM_CTRL_REG);
5401 WREG32(CGTS_SM_CTRL_REG, data);
5403 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5404 orig = data = RREG32(CP_MEM_SLP_CNTL);
5405 data |= CP_MEM_LS_EN;
5407 WREG32(CP_MEM_SLP_CNTL, data);
5410 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5413 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5415 tmp = si_halt_rlc(rdev);
5417 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5418 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5419 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);
5421 si_update_rlc(rdev, tmp);
5423 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5426 WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5428 data = RREG32(CP_MEM_SLP_CNTL);
5429 if (data & CP_MEM_LS_EN) {
5430 data &= ~CP_MEM_LS_EN;
5431 WREG32(CP_MEM_SLP_CNTL, data);
5433 orig = data = RREG32(CGTS_SM_CTRL_REG);
5434 data |= LS_OVERRIDE | OVERRIDE;
5436 WREG32(CGTS_SM_CTRL_REG, data);
5438 tmp = si_halt_rlc(rdev);
5440 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
5441 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
5442 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);
5444 si_update_rlc(rdev, tmp);
5448 static void si_enable_uvd_mgcg(struct radeon_device *rdev,
5451 u32 orig, data, tmp;
5453 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
5454 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5456 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5458 orig = data = RREG32(UVD_CGC_CTRL);
5461 WREG32(UVD_CGC_CTRL, data);
5463 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0);
5464 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0);
5466 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
5468 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp);
5470 orig = data = RREG32(UVD_CGC_CTRL);
5473 WREG32(UVD_CGC_CTRL, data);
5475 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff);
5476 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff);
5480 static const u32 mc_cg_registers[] =
5493 static void si_enable_mc_ls(struct radeon_device *rdev,
5499 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5500 orig = data = RREG32(mc_cg_registers[i]);
5501 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5502 data |= MC_LS_ENABLE;
5504 data &= ~MC_LS_ENABLE;
5506 WREG32(mc_cg_registers[i], data);
5510 static void si_enable_mc_mgcg(struct radeon_device *rdev,
5516 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5517 orig = data = RREG32(mc_cg_registers[i]);
5518 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5519 data |= MC_CG_ENABLE;
5521 data &= ~MC_CG_ENABLE;
5523 WREG32(mc_cg_registers[i], data);
5527 static void si_enable_dma_mgcg(struct radeon_device *rdev,
5530 u32 orig, data, offset;
5533 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5534 for (i = 0; i < 2; i++) {
5536 offset = DMA0_REGISTER_OFFSET;
5538 offset = DMA1_REGISTER_OFFSET;
5539 orig = data = RREG32(DMA_POWER_CNTL + offset);
5540 data &= ~MEM_POWER_OVERRIDE;
5542 WREG32(DMA_POWER_CNTL + offset, data);
5543 WREG32(DMA_CLK_CTRL + offset, 0x00000100);
5546 for (i = 0; i < 2; i++) {
5548 offset = DMA0_REGISTER_OFFSET;
5550 offset = DMA1_REGISTER_OFFSET;
5551 orig = data = RREG32(DMA_POWER_CNTL + offset);
5552 data |= MEM_POWER_OVERRIDE;
5554 WREG32(DMA_POWER_CNTL + offset, data);
5556 orig = data = RREG32(DMA_CLK_CTRL + offset);
5559 WREG32(DMA_CLK_CTRL + offset, data);
5564 static void si_enable_bif_mgls(struct radeon_device *rdev,
5569 orig = data = RREG32_PCIE(PCIE_CNTL2);
5571 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
5572 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
5573 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
5575 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
5576 REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
5579 WREG32_PCIE(PCIE_CNTL2, data);
5582 static void si_enable_hdp_mgcg(struct radeon_device *rdev,
5587 orig = data = RREG32(HDP_HOST_PATH_CNTL);
5589 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
5590 data &= ~CLOCK_GATING_DIS;
5592 data |= CLOCK_GATING_DIS;
5595 WREG32(HDP_HOST_PATH_CNTL, data);
5598 static void si_enable_hdp_ls(struct radeon_device *rdev,
5603 orig = data = RREG32(HDP_MEM_POWER_LS);
5605 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
5606 data |= HDP_LS_ENABLE;
5608 data &= ~HDP_LS_ENABLE;
5611 WREG32(HDP_MEM_POWER_LS, data);
5614 static void si_update_cg(struct radeon_device *rdev,
5615 u32 block, bool enable)
5617 if (block & RADEON_CG_BLOCK_GFX) {
5618 si_enable_gui_idle_interrupt(rdev, false);
5619 /* order matters! */
5621 si_enable_mgcg(rdev, true);
5622 si_enable_cgcg(rdev, true);
5624 si_enable_cgcg(rdev, false);
5625 si_enable_mgcg(rdev, false);
5627 si_enable_gui_idle_interrupt(rdev, true);
5630 if (block & RADEON_CG_BLOCK_MC) {
5631 si_enable_mc_mgcg(rdev, enable);
5632 si_enable_mc_ls(rdev, enable);
5635 if (block & RADEON_CG_BLOCK_SDMA) {
5636 si_enable_dma_mgcg(rdev, enable);
5639 if (block & RADEON_CG_BLOCK_BIF) {
5640 si_enable_bif_mgls(rdev, enable);
5643 if (block & RADEON_CG_BLOCK_UVD) {
5644 if (rdev->has_uvd) {
5645 si_enable_uvd_mgcg(rdev, enable);
5649 if (block & RADEON_CG_BLOCK_HDP) {
5650 si_enable_hdp_mgcg(rdev, enable);
5651 si_enable_hdp_ls(rdev, enable);
5655 static void si_init_cg(struct radeon_device *rdev)
5657 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5658 RADEON_CG_BLOCK_MC |
5659 RADEON_CG_BLOCK_SDMA |
5660 RADEON_CG_BLOCK_BIF |
5661 RADEON_CG_BLOCK_HDP), true);
5662 if (rdev->has_uvd) {
5663 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
5664 si_init_uvd_internal_cg(rdev);
5668 static void si_fini_cg(struct radeon_device *rdev)
5670 if (rdev->has_uvd) {
5671 si_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
5673 si_update_cg(rdev, (RADEON_CG_BLOCK_GFX |
5674 RADEON_CG_BLOCK_MC |
5675 RADEON_CG_BLOCK_SDMA |
5676 RADEON_CG_BLOCK_BIF |
5677 RADEON_CG_BLOCK_HDP), false);
5680 u32 si_get_csb_size(struct radeon_device *rdev)
5683 const struct cs_section_def *sect = NULL;
5684 const struct cs_extent_def *ext = NULL;
5686 if (rdev->rlc.cs_data == NULL)
5689 /* begin clear state */
5691 /* context control state */
5694 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5695 for (ext = sect->section; ext->extent != NULL; ++ext) {
5696 if (sect->id == SECT_CONTEXT)
5697 count += 2 + ext->reg_count;
5702 /* pa_sc_raster_config */
5704 /* end clear state */
5712 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
5715 const struct cs_section_def *sect = NULL;
5716 const struct cs_extent_def *ext = NULL;
5718 if (rdev->rlc.cs_data == NULL)
5723 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5724 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5726 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5727 buffer[count++] = cpu_to_le32(0x80000000);
5728 buffer[count++] = cpu_to_le32(0x80000000);
5730 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
5731 for (ext = sect->section; ext->extent != NULL; ++ext) {
5732 if (sect->id == SECT_CONTEXT) {
5734 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
5735 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
5736 for (i = 0; i < ext->reg_count; i++)
5737 buffer[count++] = cpu_to_le32(ext->extent[i]);
5744 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5745 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
5746 switch (rdev->family) {
5749 buffer[count++] = cpu_to_le32(0x2a00126a);
5752 buffer[count++] = cpu_to_le32(0x0000124a);
5755 buffer[count++] = cpu_to_le32(0x00000082);
5758 buffer[count++] = cpu_to_le32(0x00000000);
5761 buffer[count++] = cpu_to_le32(0x00000000);
5765 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5766 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
5768 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
5769 buffer[count++] = cpu_to_le32(0);
5772 static void si_init_pg(struct radeon_device *rdev)
5774 if (rdev->pg_flags) {
5775 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) {
5776 si_init_dma_pg(rdev);
5778 si_init_ao_cu_mask(rdev);
5779 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
5780 si_init_gfx_cgpg(rdev);
5782 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5783 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5785 si_enable_dma_pg(rdev, true);
5786 si_enable_gfx_cgpg(rdev, true);
5788 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
5789 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5793 static void si_fini_pg(struct radeon_device *rdev)
5795 if (rdev->pg_flags) {
5796 si_enable_dma_pg(rdev, false);
5797 si_enable_gfx_cgpg(rdev, false);
5804 void si_rlc_reset(struct radeon_device *rdev)
5806 u32 tmp = RREG32(GRBM_SOFT_RESET);
5808 tmp |= SOFT_RESET_RLC;
5809 WREG32(GRBM_SOFT_RESET, tmp);
5811 tmp &= ~SOFT_RESET_RLC;
5812 WREG32(GRBM_SOFT_RESET, tmp);
5816 static void si_rlc_stop(struct radeon_device *rdev)
5818 WREG32(RLC_CNTL, 0);
5820 si_enable_gui_idle_interrupt(rdev, false);
5822 si_wait_for_rlc_serdes(rdev);
5825 static void si_rlc_start(struct radeon_device *rdev)
5827 WREG32(RLC_CNTL, RLC_ENABLE);
5829 si_enable_gui_idle_interrupt(rdev, true);
5834 static bool si_lbpw_supported(struct radeon_device *rdev)
5838 /* Enable LBPW only for DDR3 */
5839 tmp = RREG32(MC_SEQ_MISC0);
5840 if ((tmp & 0xF0000000) == 0xB0000000)
5845 static void si_enable_lbpw(struct radeon_device *rdev, bool enable)
5849 tmp = RREG32(RLC_LB_CNTL);
5851 tmp |= LOAD_BALANCE_ENABLE;
5853 tmp &= ~LOAD_BALANCE_ENABLE;
5854 WREG32(RLC_LB_CNTL, tmp);
5857 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5858 WREG32(SPI_LB_CU_MASK, 0x00ff);
5862 static int si_rlc_resume(struct radeon_device *rdev)
5877 WREG32(RLC_RL_BASE, 0);
5878 WREG32(RLC_RL_SIZE, 0);
5879 WREG32(RLC_LB_CNTL, 0);
5880 WREG32(RLC_LB_CNTR_MAX, 0xffffffff);
5881 WREG32(RLC_LB_CNTR_INIT, 0);
5882 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5884 WREG32(RLC_MC_CNTL, 0);
5885 WREG32(RLC_UCODE_CNTL, 0);
5888 const struct rlc_firmware_header_v1_0 *hdr =
5889 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data;
5890 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5891 const __le32 *fw_data = (const __le32 *)
5892 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5894 radeon_ucode_print_rlc_hdr(&hdr->header);
5896 for (i = 0; i < fw_size; i++) {
5897 WREG32(RLC_UCODE_ADDR, i);
5898 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));
5901 const __be32 *fw_data =
5902 (const __be32 *)rdev->rlc_fw->data;
5903 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) {
5904 WREG32(RLC_UCODE_ADDR, i);
5905 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
5908 WREG32(RLC_UCODE_ADDR, 0);
5910 si_enable_lbpw(rdev, si_lbpw_supported(rdev));
5917 static void si_enable_interrupts(struct radeon_device *rdev)
5919 u32 ih_cntl = RREG32(IH_CNTL);
5920 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5922 ih_cntl |= ENABLE_INTR;
5923 ih_rb_cntl |= IH_RB_ENABLE;
5924 WREG32(IH_CNTL, ih_cntl);
5925 WREG32(IH_RB_CNTL, ih_rb_cntl);
5926 rdev->ih.enabled = true;
5929 static void si_disable_interrupts(struct radeon_device *rdev)
5931 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
5932 u32 ih_cntl = RREG32(IH_CNTL);
5934 ih_rb_cntl &= ~IH_RB_ENABLE;
5935 ih_cntl &= ~ENABLE_INTR;
5936 WREG32(IH_RB_CNTL, ih_rb_cntl);
5937 WREG32(IH_CNTL, ih_cntl);
5938 /* set rptr, wptr to 0 */
5939 WREG32(IH_RB_RPTR, 0);
5940 WREG32(IH_RB_WPTR, 0);
5941 rdev->ih.enabled = false;
5945 static void si_disable_interrupt_state(struct radeon_device *rdev)
5949 tmp = RREG32(CP_INT_CNTL_RING0) &
5950 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5951 WREG32(CP_INT_CNTL_RING0, tmp);
5952 WREG32(CP_INT_CNTL_RING1, 0);
5953 WREG32(CP_INT_CNTL_RING2, 0);
5954 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
5955 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);
5956 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5957 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5958 WREG32(GRBM_INT_CNTL, 0);
5959 WREG32(SRBM_INT_CNTL, 0);
5960 if (rdev->num_crtc >= 2) {
5961 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5962 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5964 if (rdev->num_crtc >= 4) {
5965 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5966 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5968 if (rdev->num_crtc >= 6) {
5969 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5970 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5973 if (rdev->num_crtc >= 2) {
5974 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5975 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
5977 if (rdev->num_crtc >= 4) {
5978 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
5979 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
5981 if (rdev->num_crtc >= 6) {
5982 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
5983 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
5986 if (!ASIC_IS_NODCE(rdev)) {
5987 WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
5989 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5990 WREG32(DC_HPD1_INT_CONTROL, tmp);
5991 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5992 WREG32(DC_HPD2_INT_CONTROL, tmp);
5993 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5994 WREG32(DC_HPD3_INT_CONTROL, tmp);
5995 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5996 WREG32(DC_HPD4_INT_CONTROL, tmp);
5997 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
5998 WREG32(DC_HPD5_INT_CONTROL, tmp);
5999 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6000 WREG32(DC_HPD6_INT_CONTROL, tmp);
6004 static int si_irq_init(struct radeon_device *rdev)
6008 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
6011 ret = r600_ih_ring_alloc(rdev);
6016 si_disable_interrupts(rdev);
6019 ret = si_rlc_resume(rdev);
6021 r600_ih_ring_fini(rdev);
6025 /* setup interrupt control */
6026 /* set dummy read address to ring address */
6027 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
6028 interrupt_cntl = RREG32(INTERRUPT_CNTL);
6029 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
6030 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
6032 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
6033 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6034 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6035 WREG32(INTERRUPT_CNTL, interrupt_cntl);
6037 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6038 rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6040 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6041 IH_WPTR_OVERFLOW_CLEAR |
6044 if (rdev->wb.enabled)
6045 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6047 /* set the writeback address whether it's enabled or not */
6048 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6049 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6051 WREG32(IH_RB_CNTL, ih_rb_cntl);
6053 /* set rptr, wptr to 0 */
6054 WREG32(IH_RB_RPTR, 0);
6055 WREG32(IH_RB_WPTR, 0);
6057 /* Default settings for IH_CNTL (disabled at first) */
6058 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6059 /* RPTR_REARM only works if msi's are enabled */
6060 if (rdev->msi_enabled)
6061 ih_cntl |= RPTR_REARM;
6062 WREG32(IH_CNTL, ih_cntl);
6064 /* force the active interrupt state to all disabled */
6065 si_disable_interrupt_state(rdev);
6067 pci_set_master(rdev->pdev);
6070 si_enable_interrupts(rdev);
6075 int si_irq_set(struct radeon_device *rdev)
6078 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
6079 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
6080 u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
6081 u32 grbm_int_cntl = 0;
6082 u32 dma_cntl, dma_cntl1;
6083 u32 thermal_int = 0;
6085 if (!rdev->irq.installed) {
6086 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6089 /* don't enable anything if the ih is disabled */
6090 if (!rdev->ih.enabled) {
6091 si_disable_interrupts(rdev);
6092 /* force the active interrupt state to all disabled */
6093 si_disable_interrupt_state(rdev);
6097 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6098 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6100 if (!ASIC_IS_NODCE(rdev)) {
6101 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6102 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6103 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6104 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6105 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6106 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
6109 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6110 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6112 thermal_int = RREG32(CG_THERMAL_INT) &
6113 ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6115 /* enable CP interrupts on all rings */
6116 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6117 DRM_DEBUG("si_irq_set: sw int gfx\n");
6118 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6120 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6121 DRM_DEBUG("si_irq_set: sw int cp1\n");
6122 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
6124 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6125 DRM_DEBUG("si_irq_set: sw int cp2\n");
6126 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
6128 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6129 DRM_DEBUG("si_irq_set: sw int dma\n");
6130 dma_cntl |= TRAP_ENABLE;
6133 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6134 DRM_DEBUG("si_irq_set: sw int dma1\n");
6135 dma_cntl1 |= TRAP_ENABLE;
6137 if (rdev->irq.crtc_vblank_int[0] ||
6138 atomic_read(&rdev->irq.pflip[0])) {
6139 DRM_DEBUG("si_irq_set: vblank 0\n");
6140 crtc1 |= VBLANK_INT_MASK;
6142 if (rdev->irq.crtc_vblank_int[1] ||
6143 atomic_read(&rdev->irq.pflip[1])) {
6144 DRM_DEBUG("si_irq_set: vblank 1\n");
6145 crtc2 |= VBLANK_INT_MASK;
6147 if (rdev->irq.crtc_vblank_int[2] ||
6148 atomic_read(&rdev->irq.pflip[2])) {
6149 DRM_DEBUG("si_irq_set: vblank 2\n");
6150 crtc3 |= VBLANK_INT_MASK;
6152 if (rdev->irq.crtc_vblank_int[3] ||
6153 atomic_read(&rdev->irq.pflip[3])) {
6154 DRM_DEBUG("si_irq_set: vblank 3\n");
6155 crtc4 |= VBLANK_INT_MASK;
6157 if (rdev->irq.crtc_vblank_int[4] ||
6158 atomic_read(&rdev->irq.pflip[4])) {
6159 DRM_DEBUG("si_irq_set: vblank 4\n");
6160 crtc5 |= VBLANK_INT_MASK;
6162 if (rdev->irq.crtc_vblank_int[5] ||
6163 atomic_read(&rdev->irq.pflip[5])) {
6164 DRM_DEBUG("si_irq_set: vblank 5\n");
6165 crtc6 |= VBLANK_INT_MASK;
6167 if (rdev->irq.hpd[0]) {
6168 DRM_DEBUG("si_irq_set: hpd 1\n");
6169 hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6171 if (rdev->irq.hpd[1]) {
6172 DRM_DEBUG("si_irq_set: hpd 2\n");
6173 hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6175 if (rdev->irq.hpd[2]) {
6176 DRM_DEBUG("si_irq_set: hpd 3\n");
6177 hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6179 if (rdev->irq.hpd[3]) {
6180 DRM_DEBUG("si_irq_set: hpd 4\n");
6181 hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6183 if (rdev->irq.hpd[4]) {
6184 DRM_DEBUG("si_irq_set: hpd 5\n");
6185 hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6187 if (rdev->irq.hpd[5]) {
6188 DRM_DEBUG("si_irq_set: hpd 6\n");
6189 hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN;
6192 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6193 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
6194 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);
6196 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);
6197 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);
6199 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
6201 if (rdev->irq.dpm_thermal) {
6202 DRM_DEBUG("dpm thermal\n");
6203 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6206 if (rdev->num_crtc >= 2) {
6207 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
6208 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
6210 if (rdev->num_crtc >= 4) {
6211 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
6212 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
6214 if (rdev->num_crtc >= 6) {
6215 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
6216 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
6219 if (rdev->num_crtc >= 2) {
6220 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
6221 GRPH_PFLIP_INT_MASK);
6222 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
6223 GRPH_PFLIP_INT_MASK);
6225 if (rdev->num_crtc >= 4) {
6226 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
6227 GRPH_PFLIP_INT_MASK);
6228 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
6229 GRPH_PFLIP_INT_MASK);
6231 if (rdev->num_crtc >= 6) {
6232 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
6233 GRPH_PFLIP_INT_MASK);
6234 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
6235 GRPH_PFLIP_INT_MASK);
6238 if (!ASIC_IS_NODCE(rdev)) {
6239 WREG32(DC_HPD1_INT_CONTROL, hpd1);
6240 WREG32(DC_HPD2_INT_CONTROL, hpd2);
6241 WREG32(DC_HPD3_INT_CONTROL, hpd3);
6242 WREG32(DC_HPD4_INT_CONTROL, hpd4);
6243 WREG32(DC_HPD5_INT_CONTROL, hpd5);
6244 WREG32(DC_HPD6_INT_CONTROL, hpd6);
6247 WREG32(CG_THERMAL_INT, thermal_int);
6250 RREG32(SRBM_STATUS);
6255 static inline void si_irq_ack(struct radeon_device *rdev)
6259 if (ASIC_IS_NODCE(rdev))
6262 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
6263 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
6264 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
6265 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
6266 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
6267 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
6268 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
6269 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
6270 if (rdev->num_crtc >= 4) {
6271 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
6272 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
6274 if (rdev->num_crtc >= 6) {
6275 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
6276 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
6279 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
6280 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6281 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
6282 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6283 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
6284 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6285 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
6286 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6287 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
6288 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6289 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
6290 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
6292 if (rdev->num_crtc >= 4) {
6293 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
6294 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6295 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
6296 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6297 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
6298 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6299 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
6300 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
6301 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
6302 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6303 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
6304 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
6307 if (rdev->num_crtc >= 6) {
6308 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
6309 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6310 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
6311 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6312 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
6313 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6314 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
6315 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
6316 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
6317 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6318 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
6319 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
6322 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
6323 tmp = RREG32(DC_HPD1_INT_CONTROL);
6324 tmp |= DC_HPDx_INT_ACK;
6325 WREG32(DC_HPD1_INT_CONTROL, tmp);
6327 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
6328 tmp = RREG32(DC_HPD2_INT_CONTROL);
6329 tmp |= DC_HPDx_INT_ACK;
6330 WREG32(DC_HPD2_INT_CONTROL, tmp);
6332 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
6333 tmp = RREG32(DC_HPD3_INT_CONTROL);
6334 tmp |= DC_HPDx_INT_ACK;
6335 WREG32(DC_HPD3_INT_CONTROL, tmp);
6337 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
6338 tmp = RREG32(DC_HPD4_INT_CONTROL);
6339 tmp |= DC_HPDx_INT_ACK;
6340 WREG32(DC_HPD4_INT_CONTROL, tmp);
6342 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
6343 tmp = RREG32(DC_HPD5_INT_CONTROL);
6344 tmp |= DC_HPDx_INT_ACK;
6345 WREG32(DC_HPD5_INT_CONTROL, tmp);
6347 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
6348 tmp = RREG32(DC_HPD5_INT_CONTROL);
6349 tmp |= DC_HPDx_INT_ACK;
6350 WREG32(DC_HPD6_INT_CONTROL, tmp);
6353 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) {
6354 tmp = RREG32(DC_HPD1_INT_CONTROL);
6355 tmp |= DC_HPDx_RX_INT_ACK;
6356 WREG32(DC_HPD1_INT_CONTROL, tmp);
6358 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) {
6359 tmp = RREG32(DC_HPD2_INT_CONTROL);
6360 tmp |= DC_HPDx_RX_INT_ACK;
6361 WREG32(DC_HPD2_INT_CONTROL, tmp);
6363 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {
6364 tmp = RREG32(DC_HPD3_INT_CONTROL);
6365 tmp |= DC_HPDx_RX_INT_ACK;
6366 WREG32(DC_HPD3_INT_CONTROL, tmp);
6368 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {
6369 tmp = RREG32(DC_HPD4_INT_CONTROL);
6370 tmp |= DC_HPDx_RX_INT_ACK;
6371 WREG32(DC_HPD4_INT_CONTROL, tmp);
6373 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {
6374 tmp = RREG32(DC_HPD5_INT_CONTROL);
6375 tmp |= DC_HPDx_RX_INT_ACK;
6376 WREG32(DC_HPD5_INT_CONTROL, tmp);
6378 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {
6379 tmp = RREG32(DC_HPD5_INT_CONTROL);
6380 tmp |= DC_HPDx_RX_INT_ACK;
6381 WREG32(DC_HPD6_INT_CONTROL, tmp);
6385 static void si_irq_disable(struct radeon_device *rdev)
6387 si_disable_interrupts(rdev);
6388 /* Wait and acknowledge irq */
6391 si_disable_interrupt_state(rdev);
6394 static void si_irq_suspend(struct radeon_device *rdev)
6396 si_irq_disable(rdev);
6400 static void si_irq_fini(struct radeon_device *rdev)
6402 si_irq_suspend(rdev);
6403 r600_ih_ring_fini(rdev);
6406 static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
6410 if (rdev->wb.enabled)
6411 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
6413 wptr = RREG32(IH_RB_WPTR);
6415 if (wptr & RB_OVERFLOW) {
6416 wptr &= ~RB_OVERFLOW;
6417 /* When a ring buffer overflow happen start parsing interrupt
6418 * from the last not overwritten vector (wptr + 16). Hopefully
6419 * this should allow us to catchup.
6421 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
6422 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);
6423 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
6424 tmp = RREG32(IH_RB_CNTL);
6425 tmp |= IH_WPTR_OVERFLOW_CLEAR;
6426 WREG32(IH_RB_CNTL, tmp);
6428 return (wptr & rdev->ih.ptr_mask);
6432 * Each IV ring entry is 128 bits:
6433 * [7:0] - interrupt source id
6435 * [59:32] - interrupt source data
6436 * [63:60] - reserved
6439 * [127:80] - reserved
6441 int si_irq_process(struct radeon_device *rdev)
6445 u32 src_id, src_data, ring_id;
6447 bool queue_hotplug = false;
6448 bool queue_dp = false;
6449 bool queue_thermal = false;
6452 if (!rdev->ih.enabled || rdev->shutdown)
6455 wptr = si_get_ih_wptr(rdev);
6458 /* is somebody else already processing irqs? */
6459 if (atomic_xchg(&rdev->ih.lock, 1))
6462 rptr = rdev->ih.rptr;
6463 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
6465 /* Order reading of wptr vs. reading of IH ring data */
6468 /* display interrupts */
6471 while (rptr != wptr) {
6472 /* wptr/rptr are in bytes! */
6473 ring_index = rptr / 4;
6474 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
6475 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
6476 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
6479 case 1: /* D1 vblank/vline */
6481 case 0: /* D1 vblank */
6482 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT))
6483 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6485 if (rdev->irq.crtc_vblank_int[0]) {
6486 drm_handle_vblank(rdev->ddev, 0);
6487 rdev->pm.vblank_sync = true;
6488 wake_up(&rdev->irq.vblank_queue);
6490 if (atomic_read(&rdev->irq.pflip[0]))
6491 radeon_crtc_handle_vblank(rdev, 0);
6492 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
6493 DRM_DEBUG("IH: D1 vblank\n");
6496 case 1: /* D1 vline */
6497 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT))
6498 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6500 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
6501 DRM_DEBUG("IH: D1 vline\n");
6505 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6509 case 2: /* D2 vblank/vline */
6511 case 0: /* D2 vblank */
6512 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT))
6513 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6515 if (rdev->irq.crtc_vblank_int[1]) {
6516 drm_handle_vblank(rdev->ddev, 1);
6517 rdev->pm.vblank_sync = true;
6518 wake_up(&rdev->irq.vblank_queue);
6520 if (atomic_read(&rdev->irq.pflip[1]))
6521 radeon_crtc_handle_vblank(rdev, 1);
6522 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
6523 DRM_DEBUG("IH: D2 vblank\n");
6526 case 1: /* D2 vline */
6527 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT))
6528 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6530 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
6531 DRM_DEBUG("IH: D2 vline\n");
6535 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6539 case 3: /* D3 vblank/vline */
6541 case 0: /* D3 vblank */
6542 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))
6543 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6545 if (rdev->irq.crtc_vblank_int[2]) {
6546 drm_handle_vblank(rdev->ddev, 2);
6547 rdev->pm.vblank_sync = true;
6548 wake_up(&rdev->irq.vblank_queue);
6550 if (atomic_read(&rdev->irq.pflip[2]))
6551 radeon_crtc_handle_vblank(rdev, 2);
6552 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
6553 DRM_DEBUG("IH: D3 vblank\n");
6556 case 1: /* D3 vline */
6557 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))
6558 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6560 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
6561 DRM_DEBUG("IH: D3 vline\n");
6565 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6569 case 4: /* D4 vblank/vline */
6571 case 0: /* D4 vblank */
6572 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))
6573 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6575 if (rdev->irq.crtc_vblank_int[3]) {
6576 drm_handle_vblank(rdev->ddev, 3);
6577 rdev->pm.vblank_sync = true;
6578 wake_up(&rdev->irq.vblank_queue);
6580 if (atomic_read(&rdev->irq.pflip[3]))
6581 radeon_crtc_handle_vblank(rdev, 3);
6582 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
6583 DRM_DEBUG("IH: D4 vblank\n");
6586 case 1: /* D4 vline */
6587 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))
6588 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6590 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
6591 DRM_DEBUG("IH: D4 vline\n");
6595 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6599 case 5: /* D5 vblank/vline */
6601 case 0: /* D5 vblank */
6602 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))
6603 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6605 if (rdev->irq.crtc_vblank_int[4]) {
6606 drm_handle_vblank(rdev->ddev, 4);
6607 rdev->pm.vblank_sync = true;
6608 wake_up(&rdev->irq.vblank_queue);
6610 if (atomic_read(&rdev->irq.pflip[4]))
6611 radeon_crtc_handle_vblank(rdev, 4);
6612 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
6613 DRM_DEBUG("IH: D5 vblank\n");
6616 case 1: /* D5 vline */
6617 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))
6618 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6620 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
6621 DRM_DEBUG("IH: D5 vline\n");
6625 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6629 case 6: /* D6 vblank/vline */
6631 case 0: /* D6 vblank */
6632 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))
6633 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6635 if (rdev->irq.crtc_vblank_int[5]) {
6636 drm_handle_vblank(rdev->ddev, 5);
6637 rdev->pm.vblank_sync = true;
6638 wake_up(&rdev->irq.vblank_queue);
6640 if (atomic_read(&rdev->irq.pflip[5]))
6641 radeon_crtc_handle_vblank(rdev, 5);
6642 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
6643 DRM_DEBUG("IH: D6 vblank\n");
6646 case 1: /* D6 vline */
6647 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))
6648 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6650 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
6651 DRM_DEBUG("IH: D6 vline\n");
6655 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6659 case 8: /* D1 page flip */
6660 case 10: /* D2 page flip */
6661 case 12: /* D3 page flip */
6662 case 14: /* D4 page flip */
6663 case 16: /* D5 page flip */
6664 case 18: /* D6 page flip */
6665 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);
6666 if (radeon_use_pflipirq > 0)
6667 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);
6669 case 42: /* HPD hotplug */
6672 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT))
6673 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6675 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
6676 queue_hotplug = true;
6677 DRM_DEBUG("IH: HPD1\n");
6681 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT))
6682 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6684 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
6685 queue_hotplug = true;
6686 DRM_DEBUG("IH: HPD2\n");
6690 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT))
6691 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6693 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
6694 queue_hotplug = true;
6695 DRM_DEBUG("IH: HPD3\n");
6699 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT))
6700 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6702 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
6703 queue_hotplug = true;
6704 DRM_DEBUG("IH: HPD4\n");
6708 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT))
6709 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6711 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
6712 queue_hotplug = true;
6713 DRM_DEBUG("IH: HPD5\n");
6717 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT))
6718 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6720 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
6721 queue_hotplug = true;
6722 DRM_DEBUG("IH: HPD6\n");
6726 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT))
6727 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6729 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT;
6731 DRM_DEBUG("IH: HPD_RX 1\n");
6735 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT))
6736 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6738 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;
6740 DRM_DEBUG("IH: HPD_RX 2\n");
6744 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))
6745 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6747 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;
6749 DRM_DEBUG("IH: HPD_RX 3\n");
6753 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))
6754 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6756 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;
6758 DRM_DEBUG("IH: HPD_RX 4\n");
6762 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))
6763 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6765 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;
6767 DRM_DEBUG("IH: HPD_RX 5\n");
6771 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))
6772 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
6774 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;
6776 DRM_DEBUG("IH: HPD_RX 6\n");
6780 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6785 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6786 WREG32(SRBM_INT_ACK, 0x1);
6789 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6790 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
6794 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
6795 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
6796 /* reset addr and status */
6797 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
6798 if (addr == 0x0 && status == 0x0)
6800 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
6801 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
6803 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
6805 si_vm_decode_fault(rdev, status, addr);
6807 case 176: /* RINGID0 CP_INT */
6808 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6810 case 177: /* RINGID1 CP_INT */
6811 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6813 case 178: /* RINGID2 CP_INT */
6814 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6816 case 181: /* CP EOP event */
6817 DRM_DEBUG("IH: CP EOP\n");
6820 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
6823 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
6826 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
6830 case 224: /* DMA trap event */
6831 DRM_DEBUG("IH: DMA trap\n");
6832 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
6834 case 230: /* thermal low to high */
6835 DRM_DEBUG("IH: thermal low to high\n");
6836 rdev->pm.dpm.thermal.high_to_low = false;
6837 queue_thermal = true;
6839 case 231: /* thermal high to low */
6840 DRM_DEBUG("IH: thermal high to low\n");
6841 rdev->pm.dpm.thermal.high_to_low = true;
6842 queue_thermal = true;
6844 case 233: /* GUI IDLE */
6845 DRM_DEBUG("IH: GUI idle\n");
6847 case 244: /* DMA trap event */
6848 DRM_DEBUG("IH: DMA1 trap\n");
6849 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
6852 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
6856 /* wptr/rptr are in bytes! */
6858 rptr &= rdev->ih.ptr_mask;
6859 WREG32(IH_RB_RPTR, rptr);
6862 schedule_work(&rdev->dp_work);
6864 schedule_delayed_work(&rdev->hotplug_work, 0);
6865 if (queue_thermal && rdev->pm.dpm_enabled)
6866 schedule_work(&rdev->pm.dpm.thermal.work);
6867 rdev->ih.rptr = rptr;
6868 atomic_set(&rdev->ih.lock, 0);
6870 /* make sure wptr hasn't changed while processing */
6871 wptr = si_get_ih_wptr(rdev);
6879 * startup/shutdown callbacks
6881 static void si_uvd_init(struct radeon_device *rdev)
6888 r = radeon_uvd_init(rdev);
6890 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
6892 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
6893 * to early fails uvd_v2_2_resume() and thus nothing happens
6894 * there. So it is pointless to try to go through that code
6895 * hence why we disable uvd here.
6900 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
6901 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
6904 static void si_uvd_start(struct radeon_device *rdev)
6911 r = uvd_v2_2_resume(rdev);
6913 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
6916 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
6918 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
6924 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
6927 static void si_uvd_resume(struct radeon_device *rdev)
6929 struct radeon_ring *ring;
6932 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
6935 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
6936 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
6938 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
6941 r = uvd_v1_0_init(rdev);
6943 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
6948 static void si_vce_init(struct radeon_device *rdev)
6955 r = radeon_vce_init(rdev);
6957 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
6959 * At this point rdev->vce.vcpu_bo is NULL which trickles down
6960 * to early fails si_vce_start() and thus nothing happens
6961 * there. So it is pointless to try to go through that code
6962 * hence why we disable vce here.
6967 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
6968 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
6969 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
6970 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
6973 static void si_vce_start(struct radeon_device *rdev)
6980 r = radeon_vce_resume(rdev);
6982 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6985 r = vce_v1_0_resume(rdev);
6987 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
6990 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
6992 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
6995 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
6997 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
7003 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
7004 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
7007 static void si_vce_resume(struct radeon_device *rdev)
7009 struct radeon_ring *ring;
7012 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
7015 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
7016 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
7018 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
7021 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
7022 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP);
7024 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
7027 r = vce_v1_0_init(rdev);
7029 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
7034 static int si_startup(struct radeon_device *rdev)
7036 struct radeon_ring *ring;
7039 /* enable pcie gen2/3 link */
7040 si_pcie_gen3_enable(rdev);
7042 si_program_aspm(rdev);
7044 /* scratch needs to be initialized before MC */
7045 r = r600_vram_scratch_init(rdev);
7049 si_mc_program(rdev);
7051 if (!rdev->pm.dpm_enabled) {
7052 r = si_mc_load_microcode(rdev);
7054 DRM_ERROR("Failed to load MC firmware!\n");
7059 r = si_pcie_gart_enable(rdev);
7064 /* allocate rlc buffers */
7065 if (rdev->family == CHIP_VERDE) {
7066 rdev->rlc.reg_list = verde_rlc_save_restore_register_list;
7067 rdev->rlc.reg_list_size =
7068 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
7070 rdev->rlc.cs_data = si_cs_data;
7071 r = sumo_rlc_init(rdev);
7073 DRM_ERROR("Failed to init rlc BOs!\n");
7077 /* allocate wb buffer */
7078 r = radeon_wb_init(rdev);
7082 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
7084 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7088 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7090 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7094 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7096 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7100 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
7102 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7106 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7108 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7116 if (!rdev->irq.installed) {
7117 r = radeon_irq_kms_init(rdev);
7122 r = si_irq_init(rdev);
7124 DRM_ERROR("radeon: IH init failed (%d).\n", r);
7125 radeon_irq_kms_fini(rdev);
7130 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7131 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
7136 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7137 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
7142 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7143 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
7148 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7149 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
7150 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
7154 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7155 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
7156 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
7160 r = si_cp_load_microcode(rdev);
7163 r = si_cp_resume(rdev);
7167 r = cayman_dma_resume(rdev);
7171 si_uvd_resume(rdev);
7172 si_vce_resume(rdev);
7174 r = radeon_ib_pool_init(rdev);
7176 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7180 r = radeon_vm_manager_init(rdev);
7182 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7186 r = radeon_audio_init(rdev);
7193 int si_resume(struct radeon_device *rdev)
7197 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
7198 * posting will perform necessary task to bring back GPU into good
7202 atom_asic_init(rdev->mode_info.atom_context);
7204 /* init golden registers */
7205 si_init_golden_registers(rdev);
7207 if (rdev->pm.pm_method == PM_METHOD_DPM)
7208 radeon_pm_resume(rdev);
7210 rdev->accel_working = true;
7211 r = si_startup(rdev);
7213 DRM_ERROR("si startup failed on resume\n");
7214 rdev->accel_working = false;
7222 int si_suspend(struct radeon_device *rdev)
7224 radeon_pm_suspend(rdev);
7225 radeon_audio_fini(rdev);
7226 radeon_vm_manager_fini(rdev);
7227 si_cp_enable(rdev, false);
7228 cayman_dma_stop(rdev);
7229 if (rdev->has_uvd) {
7230 uvd_v1_0_fini(rdev);
7231 radeon_uvd_suspend(rdev);
7234 radeon_vce_suspend(rdev);
7237 si_irq_suspend(rdev);
7238 radeon_wb_disable(rdev);
7239 si_pcie_gart_disable(rdev);
7243 /* Plan is to move initialization in that function and use
7244 * helper function so that radeon_device_init pretty much
7245 * do nothing more than calling asic specific function. This
7246 * should also allow to remove a bunch of callback function
7249 int si_init(struct radeon_device *rdev)
7251 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7255 if (!radeon_get_bios(rdev)) {
7256 if (ASIC_IS_AVIVO(rdev))
7259 /* Must be an ATOMBIOS */
7260 if (!rdev->is_atom_bios) {
7261 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7264 r = radeon_atombios_init(rdev);
7268 /* Post card if necessary */
7269 if (!radeon_card_posted(rdev)) {
7271 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7274 DRM_INFO("GPU not posted. posting now...\n");
7275 atom_asic_init(rdev->mode_info.atom_context);
7277 /* init golden registers */
7278 si_init_golden_registers(rdev);
7279 /* Initialize scratch registers */
7280 si_scratch_init(rdev);
7281 /* Initialize surface registers */
7282 radeon_surface_init(rdev);
7283 /* Initialize clocks */
7284 radeon_get_clock_info(rdev->ddev);
7287 r = radeon_fence_driver_init(rdev);
7291 /* initialize memory controller */
7292 r = si_mc_init(rdev);
7295 /* Memory manager */
7296 r = radeon_bo_init(rdev);
7300 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
7301 !rdev->rlc_fw || !rdev->mc_fw) {
7302 r = si_init_microcode(rdev);
7304 DRM_ERROR("Failed to load firmware!\n");
7309 /* Initialize power management */
7310 radeon_pm_init(rdev);
7312 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7313 ring->ring_obj = NULL;
7314 r600_ring_init(rdev, ring, 1024 * 1024);
7316 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7317 ring->ring_obj = NULL;
7318 r600_ring_init(rdev, ring, 1024 * 1024);
7320 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7321 ring->ring_obj = NULL;
7322 r600_ring_init(rdev, ring, 1024 * 1024);
7324 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7325 ring->ring_obj = NULL;
7326 r600_ring_init(rdev, ring, 64 * 1024);
7328 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7329 ring->ring_obj = NULL;
7330 r600_ring_init(rdev, ring, 64 * 1024);
7335 rdev->ih.ring_obj = NULL;
7336 r600_ih_ring_init(rdev, 64 * 1024);
7338 r = r600_pcie_gart_init(rdev);
7342 rdev->accel_working = true;
7343 r = si_startup(rdev);
7345 dev_err(rdev->dev, "disabling GPU acceleration\n");
7347 cayman_dma_fini(rdev);
7349 sumo_rlc_fini(rdev);
7350 radeon_wb_fini(rdev);
7351 radeon_ib_pool_fini(rdev);
7352 radeon_vm_manager_fini(rdev);
7353 radeon_irq_kms_fini(rdev);
7354 si_pcie_gart_fini(rdev);
7355 rdev->accel_working = false;
7358 /* Don't start up if the MC ucode is missing.
7359 * The default clocks and voltages before the MC ucode
7360 * is loaded are not suffient for advanced operations.
7363 DRM_ERROR("radeon: MC ucode required for NI+.\n");
7370 void si_fini(struct radeon_device *rdev)
7372 radeon_pm_fini(rdev);
7374 cayman_dma_fini(rdev);
7378 sumo_rlc_fini(rdev);
7379 radeon_wb_fini(rdev);
7380 radeon_vm_manager_fini(rdev);
7381 radeon_ib_pool_fini(rdev);
7382 radeon_irq_kms_fini(rdev);
7383 if (rdev->has_uvd) {
7384 uvd_v1_0_fini(rdev);
7385 radeon_uvd_fini(rdev);
7388 radeon_vce_fini(rdev);
7389 si_pcie_gart_fini(rdev);
7390 r600_vram_scratch_fini(rdev);
7391 radeon_gem_fini(rdev);
7392 radeon_fence_driver_fini(rdev);
7393 radeon_bo_fini(rdev);
7394 radeon_atombios_fini(rdev);
7400 * si_get_gpu_clock_counter - return GPU clock counter snapshot
7402 * @rdev: radeon_device pointer
7404 * Fetches a GPU clock counter snapshot (SI).
7405 * Returns the 64 bit clock counter snapshot.
7407 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev)
7411 mutex_lock(&rdev->gpu_clock_mutex);
7412 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
7413 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
7414 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
7415 mutex_unlock(&rdev->gpu_clock_mutex);
7419 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
7421 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
7424 /* bypass vclk and dclk with bclk */
7425 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7426 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
7427 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7429 /* put PLL in bypass mode */
7430 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
7432 if (!vclk || !dclk) {
7433 /* keep the Bypass mode */
7437 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
7438 16384, 0x03FFFFFF, 0, 128, 5,
7439 &fb_div, &vclk_div, &dclk_div);
7443 /* set RESET_ANTI_MUX to 0 */
7444 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7446 /* set VCO_MODE to 1 */
7447 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
7449 /* disable sleep mode */
7450 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
7452 /* deassert UPLL_RESET */
7453 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7457 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7461 /* assert UPLL_RESET again */
7462 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
7464 /* disable spread spectrum. */
7465 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7467 /* set feedback divider */
7468 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
7470 /* set ref divider to 0 */
7471 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
7473 if (fb_div < 307200)
7474 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
7476 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
7478 /* set PDIV_A and PDIV_B */
7479 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7480 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
7481 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
7483 /* give the PLL some time to settle */
7486 /* deassert PLL_RESET */
7487 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
7491 /* switch from bypass mode to normal mode */
7492 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
7494 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
7498 /* switch VCLK and DCLK selection */
7499 WREG32_P(CG_UPLL_FUNC_CNTL_2,
7500 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
7501 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
7508 static void si_pcie_gen3_enable(struct radeon_device *rdev)
7510 struct pci_dev *root = rdev->pdev->bus->self;
7511 int bridge_pos, gpu_pos;
7512 u32 speed_cntl, mask, current_data_rate;
7516 if (pci_is_root_bus(rdev->pdev->bus))
7519 if (radeon_pcie_gen2 == 0)
7522 if (rdev->flags & RADEON_IS_IGP)
7525 if (!(rdev->flags & RADEON_IS_PCIE))
7528 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
7532 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
7535 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7536 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
7537 LC_CURRENT_DATA_RATE_SHIFT;
7538 if (mask & DRM_PCIE_SPEED_80) {
7539 if (current_data_rate == 2) {
7540 DRM_INFO("PCIE gen 3 link speeds already enabled\n");
7543 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
7544 } else if (mask & DRM_PCIE_SPEED_50) {
7545 if (current_data_rate == 1) {
7546 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
7549 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
7552 bridge_pos = pci_pcie_cap(root);
7556 gpu_pos = pci_pcie_cap(rdev->pdev);
7560 if (mask & DRM_PCIE_SPEED_80) {
7561 /* re-try equalization if gen3 is not already enabled */
7562 if (current_data_rate != 2) {
7563 u16 bridge_cfg, gpu_cfg;
7564 u16 bridge_cfg2, gpu_cfg2;
7565 u32 max_lw, current_lw, tmp;
7567 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7568 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7570 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
7571 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7573 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
7574 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7576 tmp = RREG32_PCIE(PCIE_LC_STATUS1);
7577 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
7578 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
7580 if (current_lw < max_lw) {
7581 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7582 if (tmp & LC_RENEGOTIATION_SUPPORT) {
7583 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
7584 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
7585 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
7586 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
7590 for (i = 0; i < 10; i++) {
7592 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
7593 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
7596 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
7597 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
7599 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
7600 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
7602 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7603 tmp |= LC_SET_QUIESCE;
7604 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7606 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7608 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7613 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
7614 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7615 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
7616 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
7618 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
7619 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
7620 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
7621 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
7624 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
7625 tmp16 &= ~((1 << 4) | (7 << 9));
7626 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
7627 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
7629 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7630 tmp16 &= ~((1 << 4) | (7 << 9));
7631 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
7632 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7634 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
7635 tmp &= ~LC_SET_QUIESCE;
7636 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
7641 /* set the link speed */
7642 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
7643 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
7644 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7646 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
7648 if (mask & DRM_PCIE_SPEED_80)
7649 tmp16 |= 3; /* gen3 */
7650 else if (mask & DRM_PCIE_SPEED_50)
7651 tmp16 |= 2; /* gen2 */
7653 tmp16 |= 1; /* gen1 */
7654 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
7656 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7657 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
7658 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
7660 for (i = 0; i < rdev->usec_timeout; i++) {
7661 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
7662 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
7668 static void si_program_aspm(struct radeon_device *rdev)
7671 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
7672 bool disable_clkreq = false;
7674 if (radeon_aspm == 0)
7677 if (!(rdev->flags & RADEON_IS_PCIE))
7680 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7681 data &= ~LC_XMIT_N_FTS_MASK;
7682 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
7684 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
7686 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
7687 data |= LC_GO_TO_RECOVERY;
7689 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
7691 orig = data = RREG32_PCIE(PCIE_P_CNTL);
7692 data |= P_IGNORE_EDB_ERR;
7694 WREG32_PCIE(PCIE_P_CNTL, data);
7696 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7697 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
7698 data |= LC_PMI_TO_L1_DIS;
7700 data |= LC_L0S_INACTIVITY(7);
7703 data |= LC_L1_INACTIVITY(7);
7704 data &= ~LC_PMI_TO_L1_DIS;
7706 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7708 if (!disable_plloff_in_l1) {
7709 bool clk_req_support;
7711 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7712 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7713 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7715 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7717 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7718 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7719 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7721 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7723 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7724 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
7725 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
7727 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7729 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7730 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
7731 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
7733 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7735 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) {
7736 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0);
7737 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7739 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_0, data);
7741 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1);
7742 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7744 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_1, data);
7746 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2);
7747 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7749 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_2, data);
7751 orig = data = RREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3);
7752 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7754 WREG32_PIF_PHY0(PB0_PIF_PWRDOWN_3, data);
7756 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0);
7757 data &= ~PLL_RAMP_UP_TIME_0_MASK;
7759 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_0, data);
7761 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1);
7762 data &= ~PLL_RAMP_UP_TIME_1_MASK;
7764 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_1, data);
7766 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2);
7767 data &= ~PLL_RAMP_UP_TIME_2_MASK;
7769 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_2, data);
7771 orig = data = RREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3);
7772 data &= ~PLL_RAMP_UP_TIME_3_MASK;
7774 WREG32_PIF_PHY1(PB1_PIF_PWRDOWN_3, data);
7776 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
7777 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
7778 data |= LC_DYN_LANES_PWR_STATE(3);
7780 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
7782 orig = data = RREG32_PIF_PHY0(PB0_PIF_CNTL);
7783 data &= ~LS2_EXIT_TIME_MASK;
7784 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7785 data |= LS2_EXIT_TIME(5);
7787 WREG32_PIF_PHY0(PB0_PIF_CNTL, data);
7789 orig = data = RREG32_PIF_PHY1(PB1_PIF_CNTL);
7790 data &= ~LS2_EXIT_TIME_MASK;
7791 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN))
7792 data |= LS2_EXIT_TIME(5);
7794 WREG32_PIF_PHY1(PB1_PIF_CNTL, data);
7796 if (!disable_clkreq &&
7797 !pci_is_root_bus(rdev->pdev->bus)) {
7798 struct pci_dev *root = rdev->pdev->bus->self;
7801 clk_req_support = false;
7802 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
7803 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
7804 clk_req_support = true;
7806 clk_req_support = false;
7809 if (clk_req_support) {
7810 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
7811 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
7813 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
7815 orig = data = RREG32(THM_CLK_CNTL);
7816 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
7817 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
7819 WREG32(THM_CLK_CNTL, data);
7821 orig = data = RREG32(MISC_CLK_CNTL);
7822 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
7823 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
7825 WREG32(MISC_CLK_CNTL, data);
7827 orig = data = RREG32(CG_CLKPIN_CNTL);
7828 data &= ~BCLK_AS_XCLK;
7830 WREG32(CG_CLKPIN_CNTL, data);
7832 orig = data = RREG32(CG_CLKPIN_CNTL_2);
7833 data &= ~FORCE_BIF_REFCLK_EN;
7835 WREG32(CG_CLKPIN_CNTL_2, data);
7837 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
7838 data &= ~MPLL_CLKOUT_SEL_MASK;
7839 data |= MPLL_CLKOUT_SEL(4);
7841 WREG32(MPLL_BYPASSCLK_SEL, data);
7843 orig = data = RREG32(SPLL_CNTL_MODE);
7844 data &= ~SPLL_REFCLK_SEL_MASK;
7846 WREG32(SPLL_CNTL_MODE, data);
7851 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7854 orig = data = RREG32_PCIE(PCIE_CNTL2);
7855 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
7857 WREG32_PCIE(PCIE_CNTL2, data);
7860 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
7861 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
7862 data = RREG32_PCIE(PCIE_LC_STATUS1);
7863 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
7864 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
7865 data &= ~LC_L0S_INACTIVITY_MASK;
7867 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
7873 static int si_vce_send_vcepll_ctlreq(struct radeon_device *rdev)
7877 /* make sure VCEPLL_CTLREQ is deasserted */
7878 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7882 /* assert UPLL_CTLREQ */
7883 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
7885 /* wait for CTLACK and CTLACK2 to get asserted */
7886 for (i = 0; i < 100; ++i) {
7887 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
7888 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask)
7893 /* deassert UPLL_CTLREQ */
7894 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
7897 DRM_ERROR("Timeout setting UVD clocks!\n");
7904 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
7906 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0;
7909 /* bypass evclk and ecclk with bclk */
7910 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7911 EVCLK_SRC_SEL(1) | ECCLK_SRC_SEL(1),
7912 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
7914 /* put PLL in bypass mode */
7915 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_BYPASS_EN_MASK,
7916 ~VCEPLL_BYPASS_EN_MASK);
7918 if (!evclk || !ecclk) {
7919 /* keep the Bypass mode, put PLL to sleep */
7920 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7921 ~VCEPLL_SLEEP_MASK);
7925 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000,
7926 16384, 0x03FFFFFF, 0, 128, 5,
7927 &fb_div, &evclk_div, &ecclk_div);
7931 /* set RESET_ANTI_MUX to 0 */
7932 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK);
7934 /* set VCO_MODE to 1 */
7935 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_VCO_MODE_MASK,
7936 ~VCEPLL_VCO_MODE_MASK);
7938 /* toggle VCEPLL_SLEEP to 1 then back to 0 */
7939 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_SLEEP_MASK,
7940 ~VCEPLL_SLEEP_MASK);
7941 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK);
7943 /* deassert VCEPLL_RESET */
7944 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7948 r = si_vce_send_vcepll_ctlreq(rdev);
7952 /* assert VCEPLL_RESET again */
7953 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, VCEPLL_RESET_MASK, ~VCEPLL_RESET_MASK);
7955 /* disable spread spectrum. */
7956 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
7958 /* set feedback divider */
7959 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK);
7961 /* set ref divider to 0 */
7962 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK);
7964 /* set PDIV_A and PDIV_B */
7965 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7966 VCEPLL_PDIV_A(evclk_div) | VCEPLL_PDIV_B(ecclk_div),
7967 ~(VCEPLL_PDIV_A_MASK | VCEPLL_PDIV_B_MASK));
7969 /* give the PLL some time to settle */
7972 /* deassert PLL_RESET */
7973 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK);
7977 /* switch from bypass mode to normal mode */
7978 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK);
7980 r = si_vce_send_vcepll_ctlreq(rdev);
7984 /* switch VCLK and DCLK selection */
7985 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_2,
7986 EVCLK_SRC_SEL(16) | ECCLK_SRC_SEL(16),
7987 ~(EVCLK_SRC_SEL_MASK | ECCLK_SRC_SEL_MASK));
projects / linux.git / blob