1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/clk.h>
11 #include <linux/mutex.h>
12 #include <linux/platform_device.h>
13 #include <linux/sys_soc.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_device.h>
19 #include <drm/drm_fb_cma_helper.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_plane_helper.h>
22 #include <drm/drm_vblank.h>
24 #include "rcar_du_crtc.h"
25 #include "rcar_du_drv.h"
26 #include "rcar_du_encoder.h"
27 #include "rcar_du_kms.h"
28 #include "rcar_du_plane.h"
29 #include "rcar_du_regs.h"
30 #include "rcar_du_vsp.h"
31 #include "rcar_lvds.h"
33 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
35 struct rcar_du_device *rcdu = rcrtc->group->dev;
37 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
40 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
42 struct rcar_du_device *rcdu = rcrtc->group->dev;
44 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
47 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
49 struct rcar_du_device *rcdu = rcrtc->group->dev;
51 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
52 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
55 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
57 struct rcar_du_device *rcdu = rcrtc->group->dev;
59 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
60 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
63 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
65 struct rcar_du_device *rcdu = rcrtc->group->dev;
67 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
68 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
71 /* -----------------------------------------------------------------------------
82 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
83 struct dpll_info *dpll,
87 unsigned long best_diff = (unsigned long)-1;
94 * fin fvco fout fclkout
95 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
98 * +---------------- [1/N] <------------+
100 * fclkout = fvco / P / FDPLL -- (1)
104 * fvco = fin * P * N / M -- (2)
106 * (1) + (2) indicates
108 * fclkout = fin * N / M / FDPLL
113 * FDPLL : (fdpll + 1)
115 * 2kHz < fvco < 4096MHz
117 * To minimize the jitter,
118 * N : as large as possible
119 * M : as small as possible
121 for (m = 0; m < 4; m++) {
122 for (n = 119; n > 38; n--) {
124 * This code only runs on 64-bit architectures, the
125 * unsigned long type can thus be used for 64-bit
126 * computation. It will still compile without any
127 * warning on 32-bit architectures.
129 * To optimize calculations, use fout instead of fvco
130 * to verify the VCO frequency constraint.
132 unsigned long fout = input * (n + 1) / (m + 1);
134 if (fout < 1000 || fout > 2048 * 1000 * 1000U)
137 for (fdpll = 1; fdpll < 32; fdpll++) {
138 unsigned long output;
140 output = fout / (fdpll + 1);
141 if (output >= 400 * 1000 * 1000)
144 diff = abs((long)output - (long)target);
145 if (best_diff > diff) {
150 dpll->output = output;
160 dev_dbg(rcrtc->group->dev->dev,
161 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
162 dpll->output, dpll->fdpll, dpll->n, dpll->m,
166 struct du_clk_params {
173 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
174 u32 escr, struct du_clk_params *params)
181 * If the target rate has already been achieved perfectly we can't do
184 if (params->diff == 0)
188 * Compute the input clock rate and internal divisor values to obtain
189 * the clock rate closest to the target frequency.
191 rate = clk_round_rate(clk, target);
192 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
193 diff = abs(rate / (div + 1) - target);
196 * Store the parameters if the resulting frequency is better than any
197 * previously calculated value.
199 if (diff < params->diff) {
203 params->escr = escr | div;
207 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
208 { .soc_id = "r8a7795", .revision = "ES1.*" },
212 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
214 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
215 struct rcar_du_device *rcdu = rcrtc->group->dev;
216 unsigned long mode_clock = mode->clock * 1000;
220 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
221 unsigned long target = mode_clock;
222 struct dpll_info dpll = { 0 };
223 unsigned long extclk;
228 * DU channels that have a display PLL can't use the internal
229 * system clock, and have no internal clock divider.
233 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
234 * We can work around them by configuring the DPLL to twice the
235 * desired frequency, coupled with a /2 post-divider. Restrict
236 * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
237 * no post-divider when a display PLL is present (as shown by
238 * the workaround breaking HDMI output on M3-W during testing).
240 if (soc_device_match(rcar_du_r8a7795_es1)) {
245 extclk = clk_get_rate(rcrtc->extclock);
246 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
248 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
249 | DPLLCR_FDPLL(dpll.fdpll)
250 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
253 if (rcrtc->index == 1)
254 dpllcr |= DPLLCR_PLCS1
255 | DPLLCR_INCS_DOTCLKIN1;
257 dpllcr |= DPLLCR_PLCS0
258 | DPLLCR_INCS_DOTCLKIN0;
260 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
262 escr = ESCR_DCLKSEL_DCLKIN | div;
263 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
265 * Use the LVDS PLL output as the dot clock when outputting to
266 * the LVDS encoder on an SoC that supports this clock routing
267 * option. We use the clock directly in that case, without any
268 * additional divider.
270 escr = ESCR_DCLKSEL_DCLKIN;
272 struct du_clk_params params = { .diff = (unsigned long)-1 };
274 rcar_du_escr_divider(rcrtc->clock, mode_clock,
275 ESCR_DCLKSEL_CLKS, ¶ms);
277 rcar_du_escr_divider(rcrtc->extclock, mode_clock,
278 ESCR_DCLKSEL_DCLKIN, ¶ms);
280 dev_dbg(rcrtc->group->dev->dev, "mode clock %lu %s rate %lu\n",
281 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
284 clk_set_rate(params.clk, params.rate);
288 dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
290 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
291 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
293 /* Signal polarities */
294 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
295 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
296 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
297 | DSMR_DIPM_DISP | DSMR_CSPM;
298 rcar_du_crtc_write(rcrtc, DSMR, dsmr);
300 /* Display timings */
301 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
302 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
303 mode->hdisplay - 19);
304 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
305 mode->hsync_start - 1);
306 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
308 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
309 mode->crtc_vsync_end - 2);
310 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
311 mode->crtc_vsync_end +
312 mode->crtc_vdisplay - 2);
313 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
314 mode->crtc_vsync_end +
315 mode->crtc_vsync_start - 1);
316 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
318 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
319 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
322 static unsigned int plane_zpos(struct rcar_du_plane *plane)
324 return plane->plane.state->normalized_zpos;
327 static const struct rcar_du_format_info *
328 plane_format(struct rcar_du_plane *plane)
330 return to_rcar_plane_state(plane->plane.state)->format;
333 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
335 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
336 struct rcar_du_device *rcdu = rcrtc->group->dev;
337 unsigned int num_planes = 0;
338 unsigned int dptsr_planes;
339 unsigned int hwplanes = 0;
340 unsigned int prio = 0;
344 for (i = 0; i < rcrtc->group->num_planes; ++i) {
345 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
348 if (plane->plane.state->crtc != &rcrtc->crtc ||
349 !plane->plane.state->visible)
352 /* Insert the plane in the sorted planes array. */
353 for (j = num_planes++; j > 0; --j) {
354 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
356 planes[j] = planes[j-1];
360 prio += plane_format(plane)->planes * 4;
363 for (i = 0; i < num_planes; ++i) {
364 struct rcar_du_plane *plane = planes[i];
365 struct drm_plane_state *state = plane->plane.state;
366 unsigned int index = to_rcar_plane_state(state)->hwindex;
369 dspr |= (index + 1) << prio;
370 hwplanes |= 1 << index;
372 if (plane_format(plane)->planes == 2) {
373 index = (index + 1) % 8;
376 dspr |= (index + 1) << prio;
377 hwplanes |= 1 << index;
381 /* If VSP+DU integration is enabled the plane assignment is fixed. */
382 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
383 if (rcdu->info->gen < 3) {
384 dspr = (rcrtc->index % 2) + 1;
385 hwplanes = 1 << (rcrtc->index % 2);
387 dspr = (rcrtc->index % 2) ? 3 : 1;
388 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
393 * Update the planes to display timing and dot clock generator
396 * Updating the DPTSR register requires restarting the CRTC group,
397 * resulting in visible flicker. To mitigate the issue only update the
398 * association if needed by enabled planes. Planes being disabled will
399 * keep their current association.
401 mutex_lock(&rcrtc->group->lock);
403 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
404 : rcrtc->group->dptsr_planes & ~hwplanes;
406 if (dptsr_planes != rcrtc->group->dptsr_planes) {
407 rcar_du_group_write(rcrtc->group, DPTSR,
408 (dptsr_planes << 16) | dptsr_planes);
409 rcrtc->group->dptsr_planes = dptsr_planes;
411 if (rcrtc->group->used_crtcs)
412 rcar_du_group_restart(rcrtc->group);
415 /* Restart the group if plane sources have changed. */
416 if (rcrtc->group->need_restart)
417 rcar_du_group_restart(rcrtc->group);
419 mutex_unlock(&rcrtc->group->lock);
421 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
425 /* -----------------------------------------------------------------------------
429 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
431 struct drm_pending_vblank_event *event;
432 struct drm_device *dev = rcrtc->crtc.dev;
435 spin_lock_irqsave(&dev->event_lock, flags);
436 event = rcrtc->event;
438 spin_unlock_irqrestore(&dev->event_lock, flags);
443 spin_lock_irqsave(&dev->event_lock, flags);
444 drm_crtc_send_vblank_event(&rcrtc->crtc, event);
445 wake_up(&rcrtc->flip_wait);
446 spin_unlock_irqrestore(&dev->event_lock, flags);
448 drm_crtc_vblank_put(&rcrtc->crtc);
451 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
453 struct drm_device *dev = rcrtc->crtc.dev;
457 spin_lock_irqsave(&dev->event_lock, flags);
458 pending = rcrtc->event != NULL;
459 spin_unlock_irqrestore(&dev->event_lock, flags);
464 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
466 struct rcar_du_device *rcdu = rcrtc->group->dev;
468 if (wait_event_timeout(rcrtc->flip_wait,
469 !rcar_du_crtc_page_flip_pending(rcrtc),
470 msecs_to_jiffies(50)))
473 dev_warn(rcdu->dev, "page flip timeout\n");
475 rcar_du_crtc_finish_page_flip(rcrtc);
478 /* -----------------------------------------------------------------------------
479 * Start/Stop and Suspend/Resume
482 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
484 /* Set display off and background to black */
485 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
486 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
488 /* Configure display timings and output routing */
489 rcar_du_crtc_set_display_timing(rcrtc);
490 rcar_du_group_set_routing(rcrtc->group);
492 /* Start with all planes disabled. */
493 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
495 /* Enable the VSP compositor. */
496 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
497 rcar_du_vsp_enable(rcrtc);
499 /* Turn vertical blanking interrupt reporting on. */
500 drm_crtc_vblank_on(&rcrtc->crtc);
503 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
508 * Guard against double-get, as the function is called from both the
509 * .atomic_enable() and .atomic_begin() handlers.
511 if (rcrtc->initialized)
514 ret = clk_prepare_enable(rcrtc->clock);
518 ret = clk_prepare_enable(rcrtc->extclock);
522 ret = rcar_du_group_get(rcrtc->group);
526 rcar_du_crtc_setup(rcrtc);
527 rcrtc->initialized = true;
532 clk_disable_unprepare(rcrtc->extclock);
534 clk_disable_unprepare(rcrtc->clock);
538 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
540 rcar_du_group_put(rcrtc->group);
542 clk_disable_unprepare(rcrtc->extclock);
543 clk_disable_unprepare(rcrtc->clock);
545 rcrtc->initialized = false;
548 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
553 * Select master sync mode. This enables display operation in master
554 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
557 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
558 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
559 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
562 rcar_du_group_start_stop(rcrtc->group, true);
565 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
567 struct rcar_du_device *rcdu = rcrtc->group->dev;
568 struct drm_crtc *crtc = &rcrtc->crtc;
571 /* Make sure vblank interrupts are enabled. */
572 drm_crtc_vblank_get(crtc);
575 * Disable planes and calculate how many vertical blanking interrupts we
576 * have to wait for. If a vertical blanking interrupt has been triggered
577 * but not processed yet, we don't know whether it occurred before or
578 * after the planes got disabled. We thus have to wait for two vblank
579 * interrupts in that case.
581 spin_lock_irq(&rcrtc->vblank_lock);
582 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
583 status = rcar_du_crtc_read(rcrtc, DSSR);
584 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
585 spin_unlock_irq(&rcrtc->vblank_lock);
587 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
588 msecs_to_jiffies(100)))
589 dev_warn(rcdu->dev, "vertical blanking timeout\n");
591 drm_crtc_vblank_put(crtc);
594 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
596 struct drm_crtc *crtc = &rcrtc->crtc;
599 * Disable all planes and wait for the change to take effect. This is
600 * required as the plane enable registers are updated on vblank, and no
601 * vblank will occur once the CRTC is stopped. Disabling planes when
602 * starting the CRTC thus wouldn't be enough as it would start scanning
603 * out immediately from old frame buffers until the next vblank.
605 * This increases the CRTC stop delay, especially when multiple CRTCs
606 * are stopped in one operation as we now wait for one vblank per CRTC.
607 * Whether this can be improved needs to be researched.
609 rcar_du_crtc_disable_planes(rcrtc);
612 * Disable vertical blanking interrupt reporting. We first need to wait
613 * for page flip completion before stopping the CRTC as userspace
614 * expects page flips to eventually complete.
616 rcar_du_crtc_wait_page_flip(rcrtc);
617 drm_crtc_vblank_off(crtc);
619 /* Disable the VSP compositor. */
620 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
621 rcar_du_vsp_disable(rcrtc);
624 * Select switch sync mode. This stops display operation and configures
625 * the HSYNC and VSYNC signals as inputs.
627 * TODO: Find another way to stop the display for DUs that don't support
630 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_TVM_SYNC))
631 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
634 rcar_du_group_start_stop(rcrtc->group, false);
637 /* -----------------------------------------------------------------------------
641 static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
642 struct drm_crtc_state *state)
644 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);
645 struct drm_encoder *encoder;
647 /* Store the routes from the CRTC output to the DU outputs. */
650 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
651 struct rcar_du_encoder *renc;
653 /* Skip the writeback encoder. */
654 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
657 renc = to_rcar_encoder(encoder);
658 rstate->outputs |= BIT(renc->output);
664 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
665 struct drm_crtc_state *old_state)
667 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
668 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
669 struct rcar_du_device *rcdu = rcrtc->group->dev;
671 rcar_du_crtc_get(rcrtc);
674 * On D3/E3 the dot clock is provided by the LVDS encoder attached to
675 * the DU channel. We need to enable its clock output explicitly if
676 * the LVDS output is disabled.
678 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
679 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
680 struct rcar_du_encoder *encoder =
681 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
682 const struct drm_display_mode *mode =
683 &crtc->state->adjusted_mode;
685 rcar_lvds_clk_enable(encoder->base.bridge,
689 rcar_du_crtc_start(rcrtc);
692 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
693 struct drm_crtc_state *old_state)
695 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
696 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
697 struct rcar_du_device *rcdu = rcrtc->group->dev;
699 rcar_du_crtc_stop(rcrtc);
700 rcar_du_crtc_put(rcrtc);
702 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
703 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
704 struct rcar_du_encoder *encoder =
705 rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
708 * Disable the LVDS clock output, see
709 * rcar_du_crtc_atomic_enable().
711 rcar_lvds_clk_disable(encoder->base.bridge);
714 spin_lock_irq(&crtc->dev->event_lock);
715 if (crtc->state->event) {
716 drm_crtc_send_vblank_event(crtc, crtc->state->event);
717 crtc->state->event = NULL;
719 spin_unlock_irq(&crtc->dev->event_lock);
722 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
723 struct drm_crtc_state *old_crtc_state)
725 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
727 WARN_ON(!crtc->state->enable);
730 * If a mode set is in progress we can be called with the CRTC disabled.
731 * We thus need to first get and setup the CRTC in order to configure
732 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
733 * kept awake until the .atomic_enable() call that will follow. The get
734 * operation in .atomic_enable() will in that case be a no-op, and the
735 * CRTC will be put later in .atomic_disable().
737 * If a mode set is not in progress the CRTC is enabled, and the
738 * following get call will be a no-op. There is thus no need to balance
739 * it in .atomic_flush() either.
741 rcar_du_crtc_get(rcrtc);
743 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
744 rcar_du_vsp_atomic_begin(rcrtc);
747 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
748 struct drm_crtc_state *old_crtc_state)
750 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
751 struct drm_device *dev = rcrtc->crtc.dev;
754 rcar_du_crtc_update_planes(rcrtc);
756 if (crtc->state->event) {
757 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
759 spin_lock_irqsave(&dev->event_lock, flags);
760 rcrtc->event = crtc->state->event;
761 crtc->state->event = NULL;
762 spin_unlock_irqrestore(&dev->event_lock, flags);
765 if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
766 rcar_du_vsp_atomic_flush(rcrtc);
769 enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
770 const struct drm_display_mode *mode)
772 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
773 struct rcar_du_device *rcdu = rcrtc->group->dev;
774 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
777 if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
778 return MODE_NO_INTERLACE;
781 * The hardware requires a minimum combined horizontal sync and back
782 * porch of 20 pixels and a minimum vertical back porch of 3 lines.
784 if (mode->htotal - mode->hsync_start < 20)
785 return MODE_HBLANK_NARROW;
787 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
789 return MODE_VBLANK_NARROW;
794 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
795 .atomic_check = rcar_du_crtc_atomic_check,
796 .atomic_begin = rcar_du_crtc_atomic_begin,
797 .atomic_flush = rcar_du_crtc_atomic_flush,
798 .atomic_enable = rcar_du_crtc_atomic_enable,
799 .atomic_disable = rcar_du_crtc_atomic_disable,
800 .mode_valid = rcar_du_crtc_mode_valid,
803 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
805 struct rcar_du_device *rcdu = rcrtc->group->dev;
806 const char **sources;
810 /* CRC available only on Gen3 HW. */
811 if (rcdu->info->gen < 3)
814 /* Reserve 1 for "auto" source. */
815 count = rcrtc->vsp->num_planes + 1;
817 sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
821 sources[0] = kstrdup("auto", GFP_KERNEL);
825 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
826 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
829 sprintf(name, "plane%u", plane->base.id);
830 sources[i + 1] = kstrdup(name, GFP_KERNEL);
835 rcrtc->sources = sources;
836 rcrtc->sources_count = count;
847 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
854 for (i = 0; i < rcrtc->sources_count; i++)
855 kfree(rcrtc->sources[i]);
856 kfree(rcrtc->sources);
858 rcrtc->sources = NULL;
859 rcrtc->sources_count = 0;
862 static struct drm_crtc_state *
863 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
865 struct rcar_du_crtc_state *state;
866 struct rcar_du_crtc_state *copy;
868 if (WARN_ON(!crtc->state))
871 state = to_rcar_crtc_state(crtc->state);
872 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
876 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
881 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
882 struct drm_crtc_state *state)
884 __drm_atomic_helper_crtc_destroy_state(state);
885 kfree(to_rcar_crtc_state(state));
888 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
890 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
892 rcar_du_crtc_crc_cleanup(rcrtc);
894 return drm_crtc_cleanup(crtc);
897 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
899 struct rcar_du_crtc_state *state;
902 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
906 state = kzalloc(sizeof(*state), GFP_KERNEL);
910 state->crc.source = VSP1_DU_CRC_NONE;
911 state->crc.index = 0;
913 crtc->state = &state->state;
914 crtc->state->crtc = crtc;
917 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
919 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
921 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
922 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
923 rcrtc->vblank_enable = true;
928 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
930 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
932 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
933 rcrtc->vblank_enable = false;
936 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
937 const char *source_name,
938 enum vsp1_du_crc_source *source)
944 * Parse the source name. Supported values are "plane%u" to compute the
945 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
946 * CRC on the composer (VSP) output.
950 *source = VSP1_DU_CRC_NONE;
952 } else if (!strcmp(source_name, "auto")) {
953 *source = VSP1_DU_CRC_OUTPUT;
955 } else if (strstarts(source_name, "plane")) {
958 *source = VSP1_DU_CRC_PLANE;
960 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
964 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
965 if (index == rcrtc->vsp->planes[i].plane.base.id)
973 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
974 const char *source_name,
977 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
978 enum vsp1_du_crc_source source;
980 if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
981 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
989 const char *const *rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc,
992 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
994 *count = rcrtc->sources_count;
995 return rcrtc->sources;
998 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
999 const char *source_name)
1001 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1002 struct drm_modeset_acquire_ctx ctx;
1003 struct drm_crtc_state *crtc_state;
1004 struct drm_atomic_state *state;
1005 enum vsp1_du_crc_source source;
1009 ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1015 /* Perform an atomic commit to set the CRC source. */
1016 drm_modeset_acquire_init(&ctx, 0);
1018 state = drm_atomic_state_alloc(crtc->dev);
1024 state->acquire_ctx = &ctx;
1027 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1028 if (!IS_ERR(crtc_state)) {
1029 struct rcar_du_crtc_state *rcrtc_state;
1031 rcrtc_state = to_rcar_crtc_state(crtc_state);
1032 rcrtc_state->crc.source = source;
1033 rcrtc_state->crc.index = index;
1035 ret = drm_atomic_commit(state);
1037 ret = PTR_ERR(crtc_state);
1040 if (ret == -EDEADLK) {
1041 drm_atomic_state_clear(state);
1042 drm_modeset_backoff(&ctx);
1046 drm_atomic_state_put(state);
1049 drm_modeset_drop_locks(&ctx);
1050 drm_modeset_acquire_fini(&ctx);
1055 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1056 .reset = rcar_du_crtc_reset,
1057 .destroy = drm_crtc_cleanup,
1058 .set_config = drm_atomic_helper_set_config,
1059 .page_flip = drm_atomic_helper_page_flip,
1060 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1061 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1062 .enable_vblank = rcar_du_crtc_enable_vblank,
1063 .disable_vblank = rcar_du_crtc_disable_vblank,
1066 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1067 .reset = rcar_du_crtc_reset,
1068 .destroy = rcar_du_crtc_cleanup,
1069 .set_config = drm_atomic_helper_set_config,
1070 .page_flip = drm_atomic_helper_page_flip,
1071 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1072 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1073 .enable_vblank = rcar_du_crtc_enable_vblank,
1074 .disable_vblank = rcar_du_crtc_disable_vblank,
1075 .set_crc_source = rcar_du_crtc_set_crc_source,
1076 .verify_crc_source = rcar_du_crtc_verify_crc_source,
1077 .get_crc_sources = rcar_du_crtc_get_crc_sources,
1080 /* -----------------------------------------------------------------------------
1081 * Interrupt Handling
1084 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1086 struct rcar_du_crtc *rcrtc = arg;
1087 struct rcar_du_device *rcdu = rcrtc->group->dev;
1088 irqreturn_t ret = IRQ_NONE;
1091 spin_lock(&rcrtc->vblank_lock);
1093 status = rcar_du_crtc_read(rcrtc, DSSR);
1094 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1096 if (status & DSSR_VBK) {
1098 * Wake up the vblank wait if the counter reaches 0. This must
1099 * be protected by the vblank_lock to avoid races in
1100 * rcar_du_crtc_disable_planes().
1102 if (rcrtc->vblank_count) {
1103 if (--rcrtc->vblank_count == 0)
1104 wake_up(&rcrtc->vblank_wait);
1108 spin_unlock(&rcrtc->vblank_lock);
1110 if (status & DSSR_VBK) {
1111 if (rcdu->info->gen < 3) {
1112 drm_crtc_handle_vblank(&rcrtc->crtc);
1113 rcar_du_crtc_finish_page_flip(rcrtc);
1122 /* -----------------------------------------------------------------------------
1126 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1127 unsigned int hwindex)
1129 static const unsigned int mmio_offsets[] = {
1130 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1133 struct rcar_du_device *rcdu = rgrp->dev;
1134 struct platform_device *pdev = to_platform_device(rcdu->dev);
1135 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1136 struct drm_crtc *crtc = &rcrtc->crtc;
1137 struct drm_plane *primary;
1138 unsigned int irqflags;
1145 /* Get the CRTC clock and the optional external clock. */
1146 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1147 sprintf(clk_name, "du.%u", hwindex);
1153 rcrtc->clock = devm_clk_get(rcdu->dev, name);
1154 if (IS_ERR(rcrtc->clock)) {
1155 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1156 return PTR_ERR(rcrtc->clock);
1159 sprintf(clk_name, "dclkin.%u", hwindex);
1160 clk = devm_clk_get(rcdu->dev, clk_name);
1162 rcrtc->extclock = clk;
1163 } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1164 return -EPROBE_DEFER;
1165 } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1167 * DU channels that have a display PLL can't use the internal
1168 * system clock and thus require an external clock.
1171 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1175 init_waitqueue_head(&rcrtc->flip_wait);
1176 init_waitqueue_head(&rcrtc->vblank_wait);
1177 spin_lock_init(&rcrtc->vblank_lock);
1179 rcrtc->group = rgrp;
1180 rcrtc->mmio_offset = mmio_offsets[hwindex];
1181 rcrtc->index = hwindex;
1182 rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1184 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1185 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1187 primary = &rgrp->planes[swindex % 2].plane;
1189 ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1190 rcdu->info->gen <= 2 ?
1191 &crtc_funcs_gen2 : &crtc_funcs_gen3,
1196 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1198 /* Start with vertical blanking interrupt reporting disabled. */
1199 drm_crtc_vblank_off(crtc);
1201 /* Register the interrupt handler. */
1202 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1203 /* The IRQ's are associated with the CRTC (sw)index. */
1204 irq = platform_get_irq(pdev, swindex);
1207 irq = platform_get_irq(pdev, 0);
1208 irqflags = IRQF_SHARED;
1212 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1216 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1217 dev_name(rcdu->dev), rcrtc);
1220 "failed to register IRQ for CRTC %u\n", swindex);
1224 rcar_du_crtc_crc_init(rcrtc);