drivers/gpu/drm/rcar-du/rcar_du_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * rcar_du_crtc.c  --  R-Car Display Unit CRTCs
   4  *
   5  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/mutex.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/sys_soc.h>
  14
  15 #include <drm/drm_atomic.h>
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_device.h>
  19 #include <drm/drm_fb_cma_helper.h>
  20 #include <drm/drm_gem_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "rcar_du_crtc.h"
  25 #include "rcar_du_drv.h"
  26 #include "rcar_du_encoder.h"
  27 #include "rcar_du_kms.h"
  28 #include "rcar_du_plane.h"
  29 #include "rcar_du_regs.h"
  30 #include "rcar_du_vsp.h"
  31 #include "rcar_lvds.h"
  32
  33 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
  34 {
  35         struct rcar_du_device *rcdu = rcrtc->group->dev;
  36
  37         return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
  38 }
  39
  40 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
  41 {
  42         struct rcar_du_device *rcdu = rcrtc->group->dev;
  43
  44         rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
  45 }
  46
  47 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
  48 {
  49         struct rcar_du_device *rcdu = rcrtc->group->dev;
  50
  51         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  52                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
  53 }
  54
  55 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
  56 {
  57         struct rcar_du_device *rcdu = rcrtc->group->dev;
  58
  59         rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
  60                       rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
  61 }
  62
  63 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
  64 {
  65         struct rcar_du_device *rcdu = rcrtc->group->dev;
  66
  67         rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
  68         rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
  69 }
  70
  71 /* -----------------------------------------------------------------------------
  72  * Hardware Setup
  73  */
  74
  75 struct dpll_info {
  76         unsigned int output;
  77         unsigned int fdpll;
  78         unsigned int n;
  79         unsigned int m;
  80 };
  81
  82 static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
  83                                  struct dpll_info *dpll,
  84                                  unsigned long input,
  85                                  unsigned long target)
  86 {
  87         unsigned long best_diff = (unsigned long)-1;
  88         unsigned long diff;
  89         unsigned int fdpll;
  90         unsigned int m;
  91         unsigned int n;
  92
  93         /*
  94          *   fin                                 fvco        fout       fclkout
  95          * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
  96          *              +-> |  |                             |
  97          *              |                                    |
  98          *              +---------------- [1/N] <------------+
  99          *
 100          *      fclkout = fvco / P / FDPLL -- (1)
 101          *
 102          * fin/M = fvco/P/N
 103          *
 104          *      fvco = fin * P *  N / M -- (2)
 105          *
 106          * (1) + (2) indicates
 107          *
 108          *      fclkout = fin * N / M / FDPLL
 109          *
 110          * NOTES
 111          *      N       : (n + 1)
 112          *      M       : (m + 1)
 113          *      FDPLL   : (fdpll + 1)
 114          *      P       : 2
 115          *      2kHz < fvco < 4096MHz
 116          *
 117          * To minimize the jitter,
 118          * N : as large as possible
 119          * M : as small as possible
 120          */
 121         for (m = 0; m < 4; m++) {
 122                 for (n = 119; n > 38; n--) {
 123                         /*
 124                          * This code only runs on 64-bit architectures, the
 125                          * unsigned long type can thus be used for 64-bit
 126                          * computation. It will still compile without any
 127                          * warning on 32-bit architectures.
 128                          *
 129                          * To optimize calculations, use fout instead of fvco
 130                          * to verify the VCO frequency constraint.
 131                          */
 132                         unsigned long fout = input * (n + 1) / (m + 1);
 133
 134                         if (fout < 1000 || fout > 2048 * 1000 * 1000U)
 135                                 continue;
 136
 137                         for (fdpll = 1; fdpll < 32; fdpll++) {
 138                                 unsigned long output;
 139
 140                                 output = fout / (fdpll + 1);
 141                                 if (output >= 400 * 1000 * 1000)
 142                                         continue;
 143
 144                                 diff = abs((long)output - (long)target);
 145                                 if (best_diff > diff) {
 146                                         best_diff = diff;
 147                                         dpll->n = n;
 148                                         dpll->m = m;
 149                                         dpll->fdpll = fdpll;
 150                                         dpll->output = output;
 151                                 }
 152
 153                                 if (diff == 0)
 154                                         goto done;
 155                         }
 156                 }
 157         }
 158
 159 done:
 160         dev_dbg(rcrtc->group->dev->dev,
 161                 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
 162                  dpll->output, dpll->fdpll, dpll->n, dpll->m,
 163                  best_diff);
 164 }
 165
 166 struct du_clk_params {
 167         struct clk *clk;
 168         unsigned long rate;
 169         unsigned long diff;
 170         u32 escr;
 171 };
 172
 173 static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
 174                                  u32 escr, struct du_clk_params *params)
 175 {
 176         unsigned long rate;
 177         unsigned long diff;
 178         u32 div;
 179
 180         /*
 181          * If the target rate has already been achieved perfectly we can't do
 182          * better.
 183          */
 184         if (params->diff == 0)
 185                 return;
 186
 187         /*
 188          * Compute the input clock rate and internal divisor values to obtain
 189          * the clock rate closest to the target frequency.
 190          */
 191         rate = clk_round_rate(clk, target);
 192         div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
 193         diff = abs(rate / (div + 1) - target);
 194
 195         /*
 196          * Store the parameters if the resulting frequency is better than any
 197          * previously calculated value.
 198          */
 199         if (diff < params->diff) {
 200                 params->clk = clk;
 201                 params->rate = rate;
 202                 params->diff = diff;
 203                 params->escr = escr | div;
 204         }
 205 }
 206
 207 static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
 208         { .soc_id = "r8a7795", .revision = "ES1.*" },
 209         { /* sentinel */ }
 210 };
 211
 212 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 213 {
 214         const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
 215         struct rcar_du_device *rcdu = rcrtc->group->dev;
 216         unsigned long mode_clock = mode->clock * 1000;
 217         u32 dsmr;
 218         u32 escr;
 219
 220         if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
 221                 unsigned long target = mode_clock;
 222                 struct dpll_info dpll = { 0 };
 223                 unsigned long extclk;
 224                 u32 dpllcr;
 225                 u32 div = 0;
 226
 227                 /*
 228                  * DU channels that have a display PLL can't use the internal
 229                  * system clock, and have no internal clock divider.
 230                  */
 231
 232                 /*
 233                  * The H3 ES1.x exhibits dot clock duty cycle stability issues.
 234                  * We can work around them by configuring the DPLL to twice the
 235                  * desired frequency, coupled with a /2 post-divider. Restrict
 236                  * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
 237                  * no post-divider when a display PLL is present (as shown by
 238                  * the workaround breaking HDMI output on M3-W during testing).
 239                  */
 240                 if (soc_device_match(rcar_du_r8a7795_es1)) {
 241                         target *= 2;
 242                         div = 1;
 243                 }
 244
 245                 extclk = clk_get_rate(rcrtc->extclock);
 246                 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
 247
 248                 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
 249                        | DPLLCR_FDPLL(dpll.fdpll)
 250                        | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
 251                        | DPLLCR_STBY;
 252
 253                 if (rcrtc->index == 1)
 254                         dpllcr |= DPLLCR_PLCS1
 255                                |  DPLLCR_INCS_DOTCLKIN1;
 256                 else
 257                         dpllcr |= DPLLCR_PLCS0
 258                                |  DPLLCR_INCS_DOTCLKIN0;
 259
 260                 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
 261
 262                 escr = ESCR_DCLKSEL_DCLKIN | div;
 263         } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) {
 264                 /*
 265                  * Use the LVDS PLL output as the dot clock when outputting to
 266                  * the LVDS encoder on an SoC that supports this clock routing
 267                  * option. We use the clock directly in that case, without any
 268                  * additional divider.
 269                  */
 270                 escr = ESCR_DCLKSEL_DCLKIN;
 271         } else {
 272                 struct du_clk_params params = { .diff = (unsigned long)-1 };
 273
 274                 rcar_du_escr_divider(rcrtc->clock, mode_clock,
 275                                      ESCR_DCLKSEL_CLKS, &params);
 276                 if (rcrtc->extclock)
 277                         rcar_du_escr_divider(rcrtc->extclock, mode_clock,
 278                                              ESCR_DCLKSEL_DCLKIN, &params);
 279
 280                 dev_dbg(rcrtc->group->dev->dev, "mode clock %lu %s rate %lu\n",
 281                         mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
 282                         params.rate);
 283
 284                 clk_set_rate(params.clk, params.rate);
 285                 escr = params.escr;
 286         }
 287
 288         dev_dbg(rcrtc->group->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
 289
 290         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 291         rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
 292
 293         /* Signal polarities */
 294         dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
 295              | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 296              | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
 297              | DSMR_DIPM_DISP | DSMR_CSPM;
 298         rcar_du_crtc_write(rcrtc, DSMR, dsmr);
 299
 300         /* Display timings */
 301         rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
 302         rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
 303                                         mode->hdisplay - 19);
 304         rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
 305                                         mode->hsync_start - 1);
 306         rcar_du_crtc_write(rcrtc, HCR,  mode->htotal - 1);
 307
 308         rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
 309                                         mode->crtc_vsync_end - 2);
 310         rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
 311                                         mode->crtc_vsync_end +
 312                                         mode->crtc_vdisplay - 2);
 313         rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
 314                                         mode->crtc_vsync_end +
 315                                         mode->crtc_vsync_start - 1);
 316         rcar_du_crtc_write(rcrtc, VCR,  mode->crtc_vtotal - 1);
 317
 318         rcar_du_crtc_write(rcrtc, DESR,  mode->htotal - mode->hsync_start - 1);
 319         rcar_du_crtc_write(rcrtc, DEWR,  mode->hdisplay);
 320 }
 321
 322 static unsigned int plane_zpos(struct rcar_du_plane *plane)
 323 {
 324         return plane->plane.state->normalized_zpos;
 325 }
 326
 327 static const struct rcar_du_format_info *
 328 plane_format(struct rcar_du_plane *plane)
 329 {
 330         return to_rcar_plane_state(plane->plane.state)->format;
 331 }
 332
 333 static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
 334 {
 335         struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
 336         struct rcar_du_device *rcdu = rcrtc->group->dev;
 337         unsigned int num_planes = 0;
 338         unsigned int dptsr_planes;
 339         unsigned int hwplanes = 0;
 340         unsigned int prio = 0;
 341         unsigned int i;
 342         u32 dspr = 0;
 343
 344         for (i = 0; i < rcrtc->group->num_planes; ++i) {
 345                 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
 346                 unsigned int j;
 347
 348                 if (plane->plane.state->crtc != &rcrtc->crtc ||
 349                     !plane->plane.state->visible)
 350                         continue;
 351
 352                 /* Insert the plane in the sorted planes array. */
 353                 for (j = num_planes++; j > 0; --j) {
 354                         if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
 355                                 break;
 356                         planes[j] = planes[j-1];
 357                 }
 358
 359                 planes[j] = plane;
 360                 prio += plane_format(plane)->planes * 4;
 361         }
 362
 363         for (i = 0; i < num_planes; ++i) {
 364                 struct rcar_du_plane *plane = planes[i];
 365                 struct drm_plane_state *state = plane->plane.state;
 366                 unsigned int index = to_rcar_plane_state(state)->hwindex;
 367
 368                 prio -= 4;
 369                 dspr |= (index + 1) << prio;
 370                 hwplanes |= 1 << index;
 371
 372                 if (plane_format(plane)->planes == 2) {
 373                         index = (index + 1) % 8;
 374
 375                         prio -= 4;
 376                         dspr |= (index + 1) << prio;
 377                         hwplanes |= 1 << index;
 378                 }
 379         }
 380
 381         /* If VSP+DU integration is enabled the plane assignment is fixed. */
 382         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
 383                 if (rcdu->info->gen < 3) {
 384                         dspr = (rcrtc->index % 2) + 1;
 385                         hwplanes = 1 << (rcrtc->index % 2);
 386                 } else {
 387                         dspr = (rcrtc->index % 2) ? 3 : 1;
 388                         hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
 389                 }
 390         }
 391
 392         /*
 393          * Update the planes to display timing and dot clock generator
 394          * associations.
 395          *
 396          * Updating the DPTSR register requires restarting the CRTC group,
 397          * resulting in visible flicker. To mitigate the issue only update the
 398          * association if needed by enabled planes. Planes being disabled will
 399          * keep their current association.
 400          */
 401         mutex_lock(&rcrtc->group->lock);
 402
 403         dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
 404                      : rcrtc->group->dptsr_planes & ~hwplanes;
 405
 406         if (dptsr_planes != rcrtc->group->dptsr_planes) {
 407                 rcar_du_group_write(rcrtc->group, DPTSR,
 408                                     (dptsr_planes << 16) | dptsr_planes);
 409                 rcrtc->group->dptsr_planes = dptsr_planes;
 410
 411                 if (rcrtc->group->used_crtcs)
 412                         rcar_du_group_restart(rcrtc->group);
 413         }
 414
 415         /* Restart the group if plane sources have changed. */
 416         if (rcrtc->group->need_restart)
 417                 rcar_du_group_restart(rcrtc->group);
 418
 419         mutex_unlock(&rcrtc->group->lock);
 420
 421         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
 422                             dspr);
 423 }
 424
 425 /* -----------------------------------------------------------------------------
 426  * Page Flip
 427  */
 428
 429 void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
 430 {
 431         struct drm_pending_vblank_event *event;
 432         struct drm_device *dev = rcrtc->crtc.dev;
 433         unsigned long flags;
 434
 435         spin_lock_irqsave(&dev->event_lock, flags);
 436         event = rcrtc->event;
 437         rcrtc->event = NULL;
 438         spin_unlock_irqrestore(&dev->event_lock, flags);
 439
 440         if (event == NULL)
 441                 return;
 442
 443         spin_lock_irqsave(&dev->event_lock, flags);
 444         drm_crtc_send_vblank_event(&rcrtc->crtc, event);
 445         wake_up(&rcrtc->flip_wait);
 446         spin_unlock_irqrestore(&dev->event_lock, flags);
 447
 448         drm_crtc_vblank_put(&rcrtc->crtc);
 449 }
 450
 451 static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
 452 {
 453         struct drm_device *dev = rcrtc->crtc.dev;
 454         unsigned long flags;
 455         bool pending;
 456
 457         spin_lock_irqsave(&dev->event_lock, flags);
 458         pending = rcrtc->event != NULL;
 459         spin_unlock_irqrestore(&dev->event_lock, flags);
 460
 461         return pending;
 462 }
 463
 464 static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
 465 {
 466         struct rcar_du_device *rcdu = rcrtc->group->dev;
 467
 468         if (wait_event_timeout(rcrtc->flip_wait,
 469                                !rcar_du_crtc_page_flip_pending(rcrtc),
 470                                msecs_to_jiffies(50)))
 471                 return;
 472
 473         dev_warn(rcdu->dev, "page flip timeout\n");
 474
 475         rcar_du_crtc_finish_page_flip(rcrtc);
 476 }
 477
 478 /* -----------------------------------------------------------------------------
 479  * Start/Stop and Suspend/Resume
 480  */
 481
 482 static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
 483 {
 484         /* Set display off and background to black */
 485         rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
 486         rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
 487
 488         /* Configure display timings and output routing */
 489         rcar_du_crtc_set_display_timing(rcrtc);
 490         rcar_du_group_set_routing(rcrtc->group);
 491
 492         /* Start with all planes disabled. */
 493         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 494
 495         /* Enable the VSP compositor. */
 496         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 497                 rcar_du_vsp_enable(rcrtc);
 498
 499         /* Turn vertical blanking interrupt reporting on. */
 500         drm_crtc_vblank_on(&rcrtc->crtc);
 501 }
 502
 503 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
 504 {
 505         int ret;
 506
 507         /*
 508          * Guard against double-get, as the function is called from both the
 509          * .atomic_enable() and .atomic_begin() handlers.
 510          */
 511         if (rcrtc->initialized)
 512                 return 0;
 513
 514         ret = clk_prepare_enable(rcrtc->clock);
 515         if (ret < 0)
 516                 return ret;
 517
 518         ret = clk_prepare_enable(rcrtc->extclock);
 519         if (ret < 0)
 520                 goto error_clock;
 521
 522         ret = rcar_du_group_get(rcrtc->group);
 523         if (ret < 0)
 524                 goto error_group;
 525
 526         rcar_du_crtc_setup(rcrtc);
 527         rcrtc->initialized = true;
 528
 529         return 0;
 530
 531 error_group:
 532         clk_disable_unprepare(rcrtc->extclock);
 533 error_clock:
 534         clk_disable_unprepare(rcrtc->clock);
 535         return ret;
 536 }
 537
 538 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
 539 {
 540         rcar_du_group_put(rcrtc->group);
 541
 542         clk_disable_unprepare(rcrtc->extclock);
 543         clk_disable_unprepare(rcrtc->clock);
 544
 545         rcrtc->initialized = false;
 546 }
 547
 548 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
 549 {
 550         bool interlaced;
 551
 552         /*
 553          * Select master sync mode. This enables display operation in master
 554          * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 555          * actively driven).
 556          */
 557         interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
 558         rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
 559                                    (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
 560                                    DSYSR_TVM_MASTER);
 561
 562         rcar_du_group_start_stop(rcrtc->group, true);
 563 }
 564
 565 static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
 566 {
 567         struct rcar_du_device *rcdu = rcrtc->group->dev;
 568         struct drm_crtc *crtc = &rcrtc->crtc;
 569         u32 status;
 570
 571         /* Make sure vblank interrupts are enabled. */
 572         drm_crtc_vblank_get(crtc);
 573
 574         /*
 575          * Disable planes and calculate how many vertical blanking interrupts we
 576          * have to wait for. If a vertical blanking interrupt has been triggered
 577          * but not processed yet, we don't know whether it occurred before or
 578          * after the planes got disabled. We thus have to wait for two vblank
 579          * interrupts in that case.
 580          */
 581         spin_lock_irq(&rcrtc->vblank_lock);
 582         rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 583         status = rcar_du_crtc_read(rcrtc, DSSR);
 584         rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
 585         spin_unlock_irq(&rcrtc->vblank_lock);
 586
 587         if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
 588                                 msecs_to_jiffies(100)))
 589                 dev_warn(rcdu->dev, "vertical blanking timeout\n");
 590
 591         drm_crtc_vblank_put(crtc);
 592 }
 593
 594 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
 595 {
 596         struct drm_crtc *crtc = &rcrtc->crtc;
 597
 598         /*
 599          * Disable all planes and wait for the change to take effect. This is
 600          * required as the plane enable registers are updated on vblank, and no
 601          * vblank will occur once the CRTC is stopped. Disabling planes when
 602          * starting the CRTC thus wouldn't be enough as it would start scanning
 603          * out immediately from old frame buffers until the next vblank.
 604          *
 605          * This increases the CRTC stop delay, especially when multiple CRTCs
 606          * are stopped in one operation as we now wait for one vblank per CRTC.
 607          * Whether this can be improved needs to be researched.
 608          */
 609         rcar_du_crtc_disable_planes(rcrtc);
 610
 611         /*
 612          * Disable vertical blanking interrupt reporting. We first need to wait
 613          * for page flip completion before stopping the CRTC as userspace
 614          * expects page flips to eventually complete.
 615          */
 616         rcar_du_crtc_wait_page_flip(rcrtc);
 617         drm_crtc_vblank_off(crtc);
 618
 619         /* Disable the VSP compositor. */
 620         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 621                 rcar_du_vsp_disable(rcrtc);
 622
 623         /*
 624          * Select switch sync mode. This stops display operation and configures
 625          * the HSYNC and VSYNC signals as inputs.
 626          *
 627          * TODO: Find another way to stop the display for DUs that don't support
 628          * TVM sync.
 629          */
 630         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_TVM_SYNC))
 631                 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
 632                                            DSYSR_TVM_SWITCH);
 633
 634         rcar_du_group_start_stop(rcrtc->group, false);
 635 }
 636
 637 /* -----------------------------------------------------------------------------
 638  * CRTC Functions
 639  */
 640
 641 static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
 642                                      struct drm_crtc_state *state)
 643 {
 644         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);
 645         struct drm_encoder *encoder;
 646
 647         /* Store the routes from the CRTC output to the DU outputs. */
 648         rstate->outputs = 0;
 649
 650         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {
 651                 struct rcar_du_encoder *renc;
 652
 653                 /* Skip the writeback encoder. */
 654                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 655                         continue;
 656
 657                 renc = to_rcar_encoder(encoder);
 658                 rstate->outputs |= BIT(renc->output);
 659         }
 660
 661         return 0;
 662 }
 663
 664 static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
 665                                        struct drm_crtc_state *old_state)
 666 {
 667         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 668         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
 669         struct rcar_du_device *rcdu = rcrtc->group->dev;
 670
 671         rcar_du_crtc_get(rcrtc);
 672
 673         /*
 674          * On D3/E3 the dot clock is provided by the LVDS encoder attached to
 675          * the DU channel. We need to enable its clock output explicitly if
 676          * the LVDS output is disabled.
 677          */
 678         if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
 679             rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
 680                 struct rcar_du_encoder *encoder =
 681                         rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
 682                 const struct drm_display_mode *mode =
 683                         &crtc->state->adjusted_mode;
 684
 685                 rcar_lvds_clk_enable(encoder->base.bridge,
 686                                      mode->clock * 1000);
 687         }
 688
 689         rcar_du_crtc_start(rcrtc);
 690 }
 691
 692 static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
 693                                         struct drm_crtc_state *old_state)
 694 {
 695         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 696         struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
 697         struct rcar_du_device *rcdu = rcrtc->group->dev;
 698
 699         rcar_du_crtc_stop(rcrtc);
 700         rcar_du_crtc_put(rcrtc);
 701
 702         if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
 703             rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
 704                 struct rcar_du_encoder *encoder =
 705                         rcdu->encoders[RCAR_DU_OUTPUT_LVDS0 + rcrtc->index];
 706
 707                 /*
 708                  * Disable the LVDS clock output, see
 709                  * rcar_du_crtc_atomic_enable().
 710                  */
 711                 rcar_lvds_clk_disable(encoder->base.bridge);
 712         }
 713
 714         spin_lock_irq(&crtc->dev->event_lock);
 715         if (crtc->state->event) {
 716                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 717                 crtc->state->event = NULL;
 718         }
 719         spin_unlock_irq(&crtc->dev->event_lock);
 720 }
 721
 722 static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
 723                                       struct drm_crtc_state *old_crtc_state)
 724 {
 725         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 726
 727         WARN_ON(!crtc->state->enable);
 728
 729         /*
 730          * If a mode set is in progress we can be called with the CRTC disabled.
 731          * We thus need to first get and setup the CRTC in order to configure
 732          * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
 733          * kept awake until the .atomic_enable() call that will follow. The get
 734          * operation in .atomic_enable() will in that case be a no-op, and the
 735          * CRTC will be put later in .atomic_disable().
 736          *
 737          * If a mode set is not in progress the CRTC is enabled, and the
 738          * following get call will be a no-op. There is thus no need to balance
 739          * it in .atomic_flush() either.
 740          */
 741         rcar_du_crtc_get(rcrtc);
 742
 743         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 744                 rcar_du_vsp_atomic_begin(rcrtc);
 745 }
 746
 747 static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
 748                                       struct drm_crtc_state *old_crtc_state)
 749 {
 750         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 751         struct drm_device *dev = rcrtc->crtc.dev;
 752         unsigned long flags;
 753
 754         rcar_du_crtc_update_planes(rcrtc);
 755
 756         if (crtc->state->event) {
 757                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 758
 759                 spin_lock_irqsave(&dev->event_lock, flags);
 760                 rcrtc->event = crtc->state->event;
 761                 crtc->state->event = NULL;
 762                 spin_unlock_irqrestore(&dev->event_lock, flags);
 763         }
 764
 765         if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
 766                 rcar_du_vsp_atomic_flush(rcrtc);
 767 }
 768
 769 static enum drm_mode_status
 770 rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
 771                         const struct drm_display_mode *mode)
 772 {
 773         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 774         struct rcar_du_device *rcdu = rcrtc->group->dev;
 775         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 776         unsigned int vbp;
 777
 778         if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
 779                 return MODE_NO_INTERLACE;
 780
 781         /*
 782          * The hardware requires a minimum combined horizontal sync and back
 783          * porch of 20 pixels and a minimum vertical back porch of 3 lines.
 784          */
 785         if (mode->htotal - mode->hsync_start < 20)
 786                 return MODE_HBLANK_NARROW;
 787
 788         vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
 789         if (vbp < 3)
 790                 return MODE_VBLANK_NARROW;
 791
 792         return MODE_OK;
 793 }
 794
 795 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
 796         .atomic_check = rcar_du_crtc_atomic_check,
 797         .atomic_begin = rcar_du_crtc_atomic_begin,
 798         .atomic_flush = rcar_du_crtc_atomic_flush,
 799         .atomic_enable = rcar_du_crtc_atomic_enable,
 800         .atomic_disable = rcar_du_crtc_atomic_disable,
 801         .mode_valid = rcar_du_crtc_mode_valid,
 802 };
 803
 804 static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
 805 {
 806         struct rcar_du_device *rcdu = rcrtc->group->dev;
 807         const char **sources;
 808         unsigned int count;
 809         int i = -1;
 810
 811         /* CRC available only on Gen3 HW. */
 812         if (rcdu->info->gen < 3)
 813                 return;
 814
 815         /* Reserve 1 for "auto" source. */
 816         count = rcrtc->vsp->num_planes + 1;
 817
 818         sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
 819         if (!sources)
 820                 return;
 821
 822         sources[0] = kstrdup("auto", GFP_KERNEL);
 823         if (!sources[0])
 824                 goto error;
 825
 826         for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 827                 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
 828                 char name[16];
 829
 830                 sprintf(name, "plane%u", plane->base.id);
 831                 sources[i + 1] = kstrdup(name, GFP_KERNEL);
 832                 if (!sources[i + 1])
 833                         goto error;
 834         }
 835
 836         rcrtc->sources = sources;
 837         rcrtc->sources_count = count;
 838         return;
 839
 840 error:
 841         while (i >= 0) {
 842                 kfree(sources[i]);
 843                 i--;
 844         }
 845         kfree(sources);
 846 }
 847
 848 static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
 849 {
 850         unsigned int i;
 851
 852         if (!rcrtc->sources)
 853                 return;
 854
 855         for (i = 0; i < rcrtc->sources_count; i++)
 856                 kfree(rcrtc->sources[i]);
 857         kfree(rcrtc->sources);
 858
 859         rcrtc->sources = NULL;
 860         rcrtc->sources_count = 0;
 861 }
 862
 863 static struct drm_crtc_state *
 864 rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
 865 {
 866         struct rcar_du_crtc_state *state;
 867         struct rcar_du_crtc_state *copy;
 868
 869         if (WARN_ON(!crtc->state))
 870                 return NULL;
 871
 872         state = to_rcar_crtc_state(crtc->state);
 873         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
 874         if (copy == NULL)
 875                 return NULL;
 876
 877         __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
 878
 879         return &copy->state;
 880 }
 881
 882 static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
 883                                               struct drm_crtc_state *state)
 884 {
 885         __drm_atomic_helper_crtc_destroy_state(state);
 886         kfree(to_rcar_crtc_state(state));
 887 }
 888
 889 static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
 890 {
 891         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 892
 893         rcar_du_crtc_crc_cleanup(rcrtc);
 894
 895         return drm_crtc_cleanup(crtc);
 896 }
 897
 898 static void rcar_du_crtc_reset(struct drm_crtc *crtc)
 899 {
 900         struct rcar_du_crtc_state *state;
 901
 902         if (crtc->state) {
 903                 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
 904                 crtc->state = NULL;
 905         }
 906
 907         state = kzalloc(sizeof(*state), GFP_KERNEL);
 908         if (state == NULL)
 909                 return;
 910
 911         state->crc.source = VSP1_DU_CRC_NONE;
 912         state->crc.index = 0;
 913
 914         crtc->state = &state->state;
 915         crtc->state->crtc = crtc;
 916 }
 917
 918 static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
 919 {
 920         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 921
 922         rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
 923         rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
 924         rcrtc->vblank_enable = true;
 925
 926         return 0;
 927 }
 928
 929 static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
 930 {
 931         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 932
 933         rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
 934         rcrtc->vblank_enable = false;
 935 }
 936
 937 static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
 938                                          const char *source_name,
 939                                          enum vsp1_du_crc_source *source)
 940 {
 941         unsigned int index;
 942         int ret;
 943
 944         /*
 945          * Parse the source name. Supported values are "plane%u" to compute the
 946          * CRC on an input plane (%u is the plane ID), and "auto" to compute the
 947          * CRC on the composer (VSP) output.
 948          */
 949
 950         if (!source_name) {
 951                 *source = VSP1_DU_CRC_NONE;
 952                 return 0;
 953         } else if (!strcmp(source_name, "auto")) {
 954                 *source = VSP1_DU_CRC_OUTPUT;
 955                 return 0;
 956         } else if (strstarts(source_name, "plane")) {
 957                 unsigned int i;
 958
 959                 *source = VSP1_DU_CRC_PLANE;
 960
 961                 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
 962                 if (ret < 0)
 963                         return ret;
 964
 965                 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
 966                         if (index == rcrtc->vsp->planes[i].plane.base.id)
 967                                 return i;
 968                 }
 969         }
 970
 971         return -EINVAL;
 972 }
 973
 974 static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
 975                                           const char *source_name,
 976                                           size_t *values_cnt)
 977 {
 978         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 979         enum vsp1_du_crc_source source;
 980
 981         if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
 982                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
 983                 return -EINVAL;
 984         }
 985
 986         *values_cnt = 1;
 987         return 0;
 988 }
 989
 990 static const char *const *
 991 rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
 992 {
 993         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
 994
 995         *count = rcrtc->sources_count;
 996         return rcrtc->sources;
 997 }
 998
 999 static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
1000                                        const char *source_name)
1001 {
1002         struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1003         struct drm_modeset_acquire_ctx ctx;
1004         struct drm_crtc_state *crtc_state;
1005         struct drm_atomic_state *state;
1006         enum vsp1_du_crc_source source;
1007         unsigned int index;
1008         int ret;
1009
1010         ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1011         if (ret < 0)
1012                 return ret;
1013
1014         index = ret;
1015
1016         /* Perform an atomic commit to set the CRC source. */
1017         drm_modeset_acquire_init(&ctx, 0);
1018
1019         state = drm_atomic_state_alloc(crtc->dev);
1020         if (!state) {
1021                 ret = -ENOMEM;
1022                 goto unlock;
1023         }
1024
1025         state->acquire_ctx = &ctx;
1026
1027 retry:
1028         crtc_state = drm_atomic_get_crtc_state(state, crtc);
1029         if (!IS_ERR(crtc_state)) {
1030                 struct rcar_du_crtc_state *rcrtc_state;
1031
1032                 rcrtc_state = to_rcar_crtc_state(crtc_state);
1033                 rcrtc_state->crc.source = source;
1034                 rcrtc_state->crc.index = index;
1035
1036                 ret = drm_atomic_commit(state);
1037         } else {
1038                 ret = PTR_ERR(crtc_state);
1039         }
1040
1041         if (ret == -EDEADLK) {
1042                 drm_atomic_state_clear(state);
1043                 drm_modeset_backoff(&ctx);
1044                 goto retry;
1045         }
1046
1047         drm_atomic_state_put(state);
1048
1049 unlock:
1050         drm_modeset_drop_locks(&ctx);
1051         drm_modeset_acquire_fini(&ctx);
1052
1053         return ret;
1054 }
1055
1056 static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1057         .reset = rcar_du_crtc_reset,
1058         .destroy = drm_crtc_cleanup,
1059         .set_config = drm_atomic_helper_set_config,
1060         .page_flip = drm_atomic_helper_page_flip,
1061         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1062         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1063         .enable_vblank = rcar_du_crtc_enable_vblank,
1064         .disable_vblank = rcar_du_crtc_disable_vblank,
1065 };
1066
1067 static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1068         .reset = rcar_du_crtc_reset,
1069         .destroy = rcar_du_crtc_cleanup,
1070         .set_config = drm_atomic_helper_set_config,
1071         .page_flip = drm_atomic_helper_page_flip,
1072         .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1073         .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1074         .enable_vblank = rcar_du_crtc_enable_vblank,
1075         .disable_vblank = rcar_du_crtc_disable_vblank,
1076         .set_crc_source = rcar_du_crtc_set_crc_source,
1077         .verify_crc_source = rcar_du_crtc_verify_crc_source,
1078         .get_crc_sources = rcar_du_crtc_get_crc_sources,
1079 };
1080
1081 /* -----------------------------------------------------------------------------
1082  * Interrupt Handling
1083  */
1084
1085 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1086 {
1087         struct rcar_du_crtc *rcrtc = arg;
1088         struct rcar_du_device *rcdu = rcrtc->group->dev;
1089         irqreturn_t ret = IRQ_NONE;
1090         u32 status;
1091
1092         spin_lock(&rcrtc->vblank_lock);
1093
1094         status = rcar_du_crtc_read(rcrtc, DSSR);
1095         rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1096
1097         if (status & DSSR_VBK) {
1098                 /*
1099                  * Wake up the vblank wait if the counter reaches 0. This must
1100                  * be protected by the vblank_lock to avoid races in
1101                  * rcar_du_crtc_disable_planes().
1102                  */
1103                 if (rcrtc->vblank_count) {
1104                         if (--rcrtc->vblank_count == 0)
1105                                 wake_up(&rcrtc->vblank_wait);
1106                 }
1107         }
1108
1109         spin_unlock(&rcrtc->vblank_lock);
1110
1111         if (status & DSSR_VBK) {
1112                 if (rcdu->info->gen < 3) {
1113                         drm_crtc_handle_vblank(&rcrtc->crtc);
1114                         rcar_du_crtc_finish_page_flip(rcrtc);
1115                 }
1116
1117                 ret = IRQ_HANDLED;
1118         }
1119
1120         return ret;
1121 }
1122
1123 /* -----------------------------------------------------------------------------
1124  * Initialization
1125  */
1126
1127 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1128                         unsigned int hwindex)
1129 {
1130         static const unsigned int mmio_offsets[] = {
1131                 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1132         };
1133
1134         struct rcar_du_device *rcdu = rgrp->dev;
1135         struct platform_device *pdev = to_platform_device(rcdu->dev);
1136         struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1137         struct drm_crtc *crtc = &rcrtc->crtc;
1138         struct drm_plane *primary;
1139         unsigned int irqflags;
1140         struct clk *clk;
1141         char clk_name[9];
1142         char *name;
1143         int irq;
1144         int ret;
1145
1146         /* Get the CRTC clock and the optional external clock. */
1147         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1148                 sprintf(clk_name, "du.%u", hwindex);
1149                 name = clk_name;
1150         } else {
1151                 name = NULL;
1152         }
1153
1154         rcrtc->clock = devm_clk_get(rcdu->dev, name);
1155         if (IS_ERR(rcrtc->clock)) {
1156                 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1157                 return PTR_ERR(rcrtc->clock);
1158         }
1159
1160         sprintf(clk_name, "dclkin.%u", hwindex);
1161         clk = devm_clk_get(rcdu->dev, clk_name);
1162         if (!IS_ERR(clk)) {
1163                 rcrtc->extclock = clk;
1164         } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1165                 return -EPROBE_DEFER;
1166         } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1167                 /*
1168                  * DU channels that have a display PLL can't use the internal
1169                  * system clock and thus require an external clock.
1170                  */
1171                 ret = PTR_ERR(clk);
1172                 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1173                 return ret;
1174         }
1175
1176         init_waitqueue_head(&rcrtc->flip_wait);
1177         init_waitqueue_head(&rcrtc->vblank_wait);
1178         spin_lock_init(&rcrtc->vblank_lock);
1179
1180         rcrtc->group = rgrp;
1181         rcrtc->mmio_offset = mmio_offsets[hwindex];
1182         rcrtc->index = hwindex;
1183         rcrtc->dsysr = (rcrtc->index % 2 ? 0 : DSYSR_DRES) | DSYSR_TVM_TVSYNC;
1184
1185         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1186                 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1187         else
1188                 primary = &rgrp->planes[swindex % 2].plane;
1189
1190         ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, primary, NULL,
1191                                         rcdu->info->gen <= 2 ?
1192                                         &crtc_funcs_gen2 : &crtc_funcs_gen3,
1193                                         NULL);
1194         if (ret < 0)
1195                 return ret;
1196
1197         drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1198
1199         /* Start with vertical blanking interrupt reporting disabled. */
1200         drm_crtc_vblank_off(crtc);
1201
1202         /* Register the interrupt handler. */
1203         if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
1204                 /* The IRQ's are associated with the CRTC (sw)index. */
1205                 irq = platform_get_irq(pdev, swindex);
1206                 irqflags = 0;
1207         } else {
1208                 irq = platform_get_irq(pdev, 0);
1209                 irqflags = IRQF_SHARED;
1210         }
1211
1212         if (irq < 0) {
1213                 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1214                 return irq;
1215         }
1216
1217         ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1218                                dev_name(rcdu->dev), rcrtc);
1219         if (ret < 0) {
1220                 dev_err(rcdu->dev,
1221                         "failed to register IRQ for CRTC %u\n", swindex);
1222                 return ret;
1223         }
1224
1225         rcar_du_crtc_crc_init(rcrtc);
1226
1227         return 0;
1228 }