1 // SPDX-License-Identifier: GPL-2.0+
3 * rcar_du_kms.c -- R-Car Display Unit Mode Setting
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_fb_cma_helper.h>
15 #include <drm/drm_gem_cma_helper.h>
16 #include <drm/drm_gem_framebuffer_helper.h>
17 #include <drm/drm_probe_helper.h>
18 #include <drm/drm_vblank.h>
20 #include <linux/of_graph.h>
21 #include <linux/wait.h>
23 #include "rcar_du_crtc.h"
24 #include "rcar_du_drv.h"
25 #include "rcar_du_encoder.h"
26 #include "rcar_du_kms.h"
27 #include "rcar_du_regs.h"
28 #include "rcar_du_vsp.h"
29 #include "rcar_du_writeback.h"
31 /* -----------------------------------------------------------------------------
35 static const struct rcar_du_format_info rcar_du_format_infos[] = {
37 .fourcc = DRM_FORMAT_RGB565,
38 .v4l2 = V4L2_PIX_FMT_RGB565,
41 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
42 .edf = PnDDCR4_EDF_NONE,
44 .fourcc = DRM_FORMAT_ARGB1555,
45 .v4l2 = V4L2_PIX_FMT_ARGB555,
48 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
49 .edf = PnDDCR4_EDF_NONE,
51 .fourcc = DRM_FORMAT_XRGB1555,
52 .v4l2 = V4L2_PIX_FMT_XRGB555,
55 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
56 .edf = PnDDCR4_EDF_NONE,
58 .fourcc = DRM_FORMAT_XRGB8888,
59 .v4l2 = V4L2_PIX_FMT_XBGR32,
62 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
63 .edf = PnDDCR4_EDF_RGB888,
65 .fourcc = DRM_FORMAT_ARGB8888,
66 .v4l2 = V4L2_PIX_FMT_ABGR32,
69 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
70 .edf = PnDDCR4_EDF_ARGB8888,
72 .fourcc = DRM_FORMAT_UYVY,
73 .v4l2 = V4L2_PIX_FMT_UYVY,
76 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
77 .edf = PnDDCR4_EDF_NONE,
79 .fourcc = DRM_FORMAT_YUYV,
80 .v4l2 = V4L2_PIX_FMT_YUYV,
83 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
84 .edf = PnDDCR4_EDF_NONE,
86 .fourcc = DRM_FORMAT_NV12,
87 .v4l2 = V4L2_PIX_FMT_NV12M,
90 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
91 .edf = PnDDCR4_EDF_NONE,
93 .fourcc = DRM_FORMAT_NV21,
94 .v4l2 = V4L2_PIX_FMT_NV21M,
97 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
98 .edf = PnDDCR4_EDF_NONE,
100 .fourcc = DRM_FORMAT_NV16,
101 .v4l2 = V4L2_PIX_FMT_NV16M,
104 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
105 .edf = PnDDCR4_EDF_NONE,
108 * The following formats are not supported on Gen2 and thus have no
109 * associated .pnmr or .edf settings.
112 .fourcc = DRM_FORMAT_RGB332,
113 .v4l2 = V4L2_PIX_FMT_RGB332,
117 .fourcc = DRM_FORMAT_ARGB4444,
118 .v4l2 = V4L2_PIX_FMT_ARGB444,
122 .fourcc = DRM_FORMAT_XRGB4444,
123 .v4l2 = V4L2_PIX_FMT_XRGB444,
127 .fourcc = DRM_FORMAT_BGR888,
128 .v4l2 = V4L2_PIX_FMT_RGB24,
132 .fourcc = DRM_FORMAT_RGB888,
133 .v4l2 = V4L2_PIX_FMT_BGR24,
137 .fourcc = DRM_FORMAT_BGRA8888,
138 .v4l2 = V4L2_PIX_FMT_ARGB32,
142 .fourcc = DRM_FORMAT_BGRX8888,
143 .v4l2 = V4L2_PIX_FMT_XRGB32,
147 .fourcc = DRM_FORMAT_YVYU,
148 .v4l2 = V4L2_PIX_FMT_YVYU,
152 .fourcc = DRM_FORMAT_NV61,
153 .v4l2 = V4L2_PIX_FMT_NV61M,
157 .fourcc = DRM_FORMAT_YUV420,
158 .v4l2 = V4L2_PIX_FMT_YUV420M,
162 .fourcc = DRM_FORMAT_YVU420,
163 .v4l2 = V4L2_PIX_FMT_YVU420M,
167 .fourcc = DRM_FORMAT_YUV422,
168 .v4l2 = V4L2_PIX_FMT_YUV422M,
172 .fourcc = DRM_FORMAT_YVU422,
173 .v4l2 = V4L2_PIX_FMT_YVU422M,
177 .fourcc = DRM_FORMAT_YUV444,
178 .v4l2 = V4L2_PIX_FMT_YUV444M,
182 .fourcc = DRM_FORMAT_YVU444,
183 .v4l2 = V4L2_PIX_FMT_YVU444M,
189 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
193 for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
194 if (rcar_du_format_infos[i].fourcc == fourcc)
195 return &rcar_du_format_infos[i];
201 /* -----------------------------------------------------------------------------
205 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
206 struct drm_mode_create_dumb *args)
208 struct rcar_du_device *rcdu = dev->dev_private;
209 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
213 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
214 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
216 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
219 align = 16 * args->bpp / 8;
221 args->pitch = roundup(min_pitch, align);
223 return drm_gem_cma_dumb_create_internal(file, dev, args);
226 static struct drm_framebuffer *
227 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
228 const struct drm_mode_fb_cmd2 *mode_cmd)
230 struct rcar_du_device *rcdu = dev->dev_private;
231 const struct rcar_du_format_info *format;
232 unsigned int max_pitch;
236 format = rcar_du_format_info(mode_cmd->pixel_format);
237 if (format == NULL) {
238 dev_dbg(dev->dev, "unsupported pixel format %08x\n",
239 mode_cmd->pixel_format);
240 return ERR_PTR(-EINVAL);
243 if (rcdu->info->gen < 3) {
245 * On Gen2 the DU limits the pitch to 4095 pixels and requires
246 * buffers to be aligned to a 16 pixels boundary (or 128 bytes
247 * on some platforms).
249 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
251 max_pitch = 4095 * bpp;
253 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
259 * On Gen3 the memory interface is handled by the VSP that
260 * limits the pitch to 65535 bytes and has no alignment
267 if (mode_cmd->pitches[0] & (align - 1) ||
268 mode_cmd->pitches[0] > max_pitch) {
269 dev_dbg(dev->dev, "invalid pitch value %u\n",
270 mode_cmd->pitches[0]);
271 return ERR_PTR(-EINVAL);
274 for (i = 1; i < format->planes; ++i) {
275 if (mode_cmd->pitches[i] != mode_cmd->pitches[0]) {
277 "luma and chroma pitches do not match\n");
278 return ERR_PTR(-EINVAL);
282 return drm_gem_fb_create(dev, file_priv, mode_cmd);
285 /* -----------------------------------------------------------------------------
286 * Atomic Check and Update
289 static int rcar_du_atomic_check(struct drm_device *dev,
290 struct drm_atomic_state *state)
292 struct rcar_du_device *rcdu = dev->dev_private;
295 ret = drm_atomic_helper_check(dev, state);
299 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
302 return rcar_du_atomic_check_planes(dev, state);
305 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
307 struct drm_device *dev = old_state->dev;
308 struct rcar_du_device *rcdu = dev->dev_private;
309 struct drm_crtc_state *crtc_state;
310 struct drm_crtc *crtc;
314 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
315 * when starting the CRTCs.
317 rcdu->dpad1_source = -1;
319 for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
320 struct rcar_du_crtc_state *rcrtc_state =
321 to_rcar_crtc_state(crtc_state);
322 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
324 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
325 rcdu->dpad0_source = rcrtc->index;
327 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
328 rcdu->dpad1_source = rcrtc->index;
331 /* Apply the atomic update. */
332 drm_atomic_helper_commit_modeset_disables(dev, old_state);
333 drm_atomic_helper_commit_planes(dev, old_state,
334 DRM_PLANE_COMMIT_ACTIVE_ONLY);
335 drm_atomic_helper_commit_modeset_enables(dev, old_state);
337 drm_atomic_helper_commit_hw_done(old_state);
338 drm_atomic_helper_wait_for_flip_done(dev, old_state);
340 drm_atomic_helper_cleanup_planes(dev, old_state);
343 /* -----------------------------------------------------------------------------
347 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
348 .atomic_commit_tail = rcar_du_atomic_commit_tail,
351 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
352 .fb_create = rcar_du_fb_create,
353 .atomic_check = rcar_du_atomic_check,
354 .atomic_commit = drm_atomic_helper_commit,
357 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
358 enum rcar_du_output output,
359 struct of_endpoint *ep)
361 struct device_node *entity;
364 /* Locate the connected entity and initialize the encoder. */
365 entity = of_graph_get_remote_port_parent(ep->local_node);
367 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
372 if (!of_device_is_available(entity)) {
374 "connected entity %pOF is disabled, skipping\n",
380 ret = rcar_du_encoder_init(rcdu, output, entity);
381 if (ret && ret != -EPROBE_DEFER)
383 "failed to initialize encoder %pOF on output %u (%d), skipping\n",
384 entity, output, ret);
391 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
393 struct device_node *np = rcdu->dev->of_node;
394 struct device_node *ep_node;
395 unsigned int num_encoders = 0;
398 * Iterate over the endpoints and create one encoder for each output
401 for_each_endpoint_of_node(np, ep_node) {
402 enum rcar_du_output output;
403 struct of_endpoint ep;
407 ret = of_graph_parse_endpoint(ep_node, &ep);
409 of_node_put(ep_node);
413 /* Find the output route corresponding to the port number. */
414 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
415 if (rcdu->info->routes[i].possible_crtcs &&
416 rcdu->info->routes[i].port == ep.port) {
422 if (i == RCAR_DU_OUTPUT_MAX) {
424 "port %u references unexisting output, skipping\n",
429 /* Process the output pipeline. */
430 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
432 if (ret == -EPROBE_DEFER) {
433 of_node_put(ep_node);
446 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
449 * The color key is expressed as an RGB888 triplet stored in a 32-bit
450 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
451 * or enable source color keying (1).
453 rcdu->props.colorkey =
454 drm_property_create_range(rcdu->ddev, 0, "colorkey",
456 if (rcdu->props.colorkey == NULL)
462 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
464 const struct device_node *np = rcdu->dev->of_node;
465 struct of_phandle_args args;
467 struct device_node *np;
468 unsigned int crtcs_mask;
469 } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
470 unsigned int vsps_count = 0;
476 * First parse the DT vsps property to populate the list of VSPs. Each
477 * entry contains a pointer to the VSP DT node and a bitmask of the
478 * connected DU CRTCs.
480 cells = of_property_count_u32_elems(np, "vsps") / rcdu->num_crtcs - 1;
484 for (i = 0; i < rcdu->num_crtcs; ++i) {
487 ret = of_parse_phandle_with_fixed_args(np, "vsps", cells, i,
493 * Add the VSP to the list or update the corresponding existing
494 * entry if the VSP has already been added.
496 for (j = 0; j < vsps_count; ++j) {
497 if (vsps[j].np == args.np)
502 of_node_put(args.np);
504 vsps[vsps_count++].np = args.np;
506 vsps[j].crtcs_mask |= BIT(i);
508 /* Store the VSP pointer and pipe index in the CRTC. */
509 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
510 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
514 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
515 * computed previously.
517 for (i = 0; i < vsps_count; ++i) {
518 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
523 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
531 for (i = 0; i < ARRAY_SIZE(vsps); ++i)
532 of_node_put(vsps[i].np);
537 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
539 static const unsigned int mmio_offsets[] = {
540 DU0_REG_OFFSET, DU2_REG_OFFSET
543 struct drm_device *dev = rcdu->ddev;
544 struct drm_encoder *encoder;
545 unsigned int dpad0_sources;
546 unsigned int num_encoders;
547 unsigned int num_groups;
548 unsigned int swindex;
549 unsigned int hwindex;
553 drm_mode_config_init(dev);
555 dev->mode_config.min_width = 0;
556 dev->mode_config.min_height = 0;
557 dev->mode_config.normalize_zpos = true;
558 dev->mode_config.funcs = &rcar_du_mode_config_funcs;
559 dev->mode_config.helper_private = &rcar_du_mode_config_helper;
561 if (rcdu->info->gen < 3) {
562 dev->mode_config.max_width = 4095;
563 dev->mode_config.max_height = 2047;
566 * The Gen3 DU uses the VSP1 for memory access, and is limited
567 * to frame sizes of 8190x8190.
569 dev->mode_config.max_width = 8190;
570 dev->mode_config.max_height = 8190;
573 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
575 ret = rcar_du_properties_init(rcdu);
580 * Initialize vertical blanking interrupts handling. Start with vblank
581 * disabled for all CRTCs.
583 ret = drm_vblank_init(dev, rcdu->num_crtcs);
587 /* Initialize the groups. */
588 num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
590 for (i = 0; i < num_groups; ++i) {
591 struct rcar_du_group *rgrp = &rcdu->groups[i];
593 mutex_init(&rgrp->lock);
596 rgrp->mmio_offset = mmio_offsets[i];
598 /* Extract the channel mask for this group only. */
599 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
601 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
604 * If we have more than one CRTCs in this group pre-associate
605 * the low-order planes with CRTC 0 and the high-order planes
606 * with CRTC 1 to minimize flicker occurring when the
607 * association is changed.
609 rgrp->dptsr_planes = rgrp->num_crtcs > 1
610 ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
613 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
614 ret = rcar_du_planes_init(rgrp);
620 /* Initialize the compositors. */
621 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
622 ret = rcar_du_vsps_init(rcdu);
627 /* Create the CRTCs. */
628 for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
629 struct rcar_du_group *rgrp;
631 /* Skip unpopulated DU channels. */
632 if (!(rcdu->info->channels_mask & BIT(hwindex)))
635 rgrp = &rcdu->groups[hwindex / 2];
637 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
642 /* Initialize the encoders. */
643 ret = rcar_du_encoders_init(rcdu);
648 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
655 * Set the possible CRTCs and possible clones. There's always at least
656 * one way for all encoders to clone each other, set all bits in the
657 * possible clones field.
659 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
660 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
661 const struct rcar_du_output_routing *route =
662 &rcdu->info->routes[renc->output];
664 encoder->possible_crtcs = route->possible_crtcs;
665 encoder->possible_clones = (1 << num_encoders) - 1;
668 /* Create the writeback connectors. */
669 if (rcdu->info->gen >= 3) {
670 for (i = 0; i < rcdu->num_crtcs; ++i) {
671 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
673 ret = rcar_du_writeback_init(rcdu, rcrtc);
680 * Initialize the default DPAD0 source to the index of the first DU
681 * channel that can be connected to DPAD0. The exact value doesn't
682 * matter as it should be overwritten by mode setting for the RGB
683 * output, but it is nonetheless required to ensure a valid initial
684 * hardware configuration on Gen3 where DU0 can't always be connected to
687 dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
688 rcdu->dpad0_source = ffs(dpad0_sources) - 1;
690 drm_mode_config_reset(dev);
692 drm_kms_helper_poll_init(dev);