1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
10 #include <linux/clk.h>
11 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #include <drm/drm_atomic.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_bridge.h>
23 #include <drm/drm_panel.h>
24 #include <drm/drm_probe_helper.h>
26 #include "rcar_lvds.h"
27 #include "rcar_lvds_regs.h"
31 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
33 RCAR_LVDS_MODE_JEIDA = 0,
34 RCAR_LVDS_MODE_MIRROR = 1,
35 RCAR_LVDS_MODE_VESA = 4,
38 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
39 #define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
40 #define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
41 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
42 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
44 struct rcar_lvds_device_info {
47 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
52 const struct rcar_lvds_device_info *info;
54 struct drm_bridge bridge;
56 struct drm_bridge *next_bridge;
57 struct drm_connector connector;
58 struct drm_panel *panel;
62 struct clk *mod; /* CPG module clock */
63 struct clk *extal; /* External clock */
64 struct clk *dotclkin[2]; /* External DU clocks */
68 struct drm_display_mode display_mode;
69 enum rcar_lvds_mode mode;
72 #define bridge_to_rcar_lvds(bridge) \
73 container_of(bridge, struct rcar_lvds, bridge)
75 #define connector_to_rcar_lvds(connector) \
76 container_of(connector, struct rcar_lvds, connector)
78 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
80 iowrite32(data, lvds->mmio + reg);
83 /* -----------------------------------------------------------------------------
87 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
89 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
91 return drm_panel_get_modes(lvds->panel);
94 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
95 struct drm_connector_state *state)
97 struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
98 const struct drm_display_mode *panel_mode;
99 struct drm_crtc_state *crtc_state;
104 if (list_empty(&connector->modes)) {
105 dev_dbg(lvds->dev, "connector: empty modes list\n");
109 panel_mode = list_first_entry(&connector->modes,
110 struct drm_display_mode, head);
112 /* We're not allowed to modify the resolution. */
113 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
114 if (IS_ERR(crtc_state))
115 return PTR_ERR(crtc_state);
117 if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
118 crtc_state->mode.vdisplay != panel_mode->vdisplay)
121 /* The flat panel mode is fixed, just copy it to the adjusted mode. */
122 drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
127 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
128 .get_modes = rcar_lvds_connector_get_modes,
129 .atomic_check = rcar_lvds_connector_atomic_check,
132 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
133 .reset = drm_atomic_helper_connector_reset,
134 .fill_modes = drm_helper_probe_single_connector_modes,
135 .destroy = drm_connector_cleanup,
136 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
137 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
140 /* -----------------------------------------------------------------------------
144 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
149 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
150 else if (freq < 61000000)
151 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
152 else if (freq < 121000000)
153 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
155 val = LVDPLLCR_PLLDLYCNT_150M;
157 rcar_lvds_write(lvds, LVDPLLCR, val);
160 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
165 val = LVDPLLCR_PLLDIVCNT_42M;
166 else if (freq < 85000000)
167 val = LVDPLLCR_PLLDIVCNT_85M;
168 else if (freq < 128000000)
169 val = LVDPLLCR_PLLDIVCNT_128M;
171 val = LVDPLLCR_PLLDIVCNT_148M;
173 rcar_lvds_write(lvds, LVDPLLCR, val);
185 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
186 unsigned long target, struct pll_info *pll,
187 u32 clksel, bool dot_clock_only)
189 unsigned int div7 = dot_clock_only ? 1 : 7;
190 unsigned long output;
201 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
202 * enough called M and N respectively), followed by a post-divider E.
204 * ,-----. ,-----. ,-----. ,-----.
205 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
206 * `-----' ,-> | | `-----' | `-----'
209 * `-------- | 1/N | <-------'
212 * The clock output by the PLL is then further divided by a programmable
213 * divider DIV to achieve the desired target frequency. Finally, an
214 * optional fixed /7 divider is used to convert the bit clock to a pixel
215 * clock (as LVDS transmits 7 bits per lane per clock sample).
217 * ,-------. ,-----. |\
218 * Fout --> | 1/DIV | --> | 1/7 | --> | |
219 * `-------' | `-----' | | --> dot clock
223 * The /7 divider is optional, it is enabled when the LVDS PLL is used
224 * to drive the LVDS encoder, and disabled when used to generate a dot
225 * clock for the DU RGB output, without using the LVDS encoder.
227 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
230 fin = clk_get_rate(clk);
231 if (fin < 12000000 || fin > 192000000)
235 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
236 * allowed values for the pre-divider M (normal range 1-8).
240 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
241 m_max = min_t(unsigned int, 8, fin / 12000000);
243 for (m = m_min; m <= m_max; ++m) {
250 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
251 * the allowed values for the multiplier N (normal range
257 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
258 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
260 for (n = n_min; n < n_max; ++n) {
266 * The output frequency is limited to 1039.5 MHz,
267 * limiting again the allowed values for the
268 * post-divider E (normal value 1, 2 or 4).
273 e_min = fvco > 1039500000 ? 1 : 0;
275 for (e = e_min; e < 3; ++e) {
281 * Finally we have a programable divider after
282 * the PLL, followed by a an optional fixed /7
285 fout = fvco / (1 << e) / div7;
286 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
287 diff = abs(fout / div - target);
289 if (diff < pll->diff) {
295 pll->clksel = clksel;
305 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
307 error = (long)(output - target) * 10000 / (long)target;
310 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
311 clk, fin, output, target, error / 100,
312 error < 0 ? -error % 100 : error % 100,
313 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
316 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
317 unsigned int freq, bool dot_clock_only)
319 struct pll_info pll = { .diff = (unsigned long)-1 };
322 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
323 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
324 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
325 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
326 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
327 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
329 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
330 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
333 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
334 | LVDPLLCR_PLLE(pll.pll_e - 1);
337 lvdpllcr |= LVDPLLCR_OCKSEL;
339 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
343 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
346 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
347 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
349 rcar_lvds_write(lvds, LVDDIV, 0);
352 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
354 __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
357 /* -----------------------------------------------------------------------------
361 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
363 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
366 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
369 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
371 WARN_ON(lvds->enabled);
373 ret = clk_prepare_enable(lvds->clocks.mod);
377 __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
379 lvds->enabled = true;
382 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
384 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
386 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
388 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
391 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
393 WARN_ON(!lvds->enabled);
395 rcar_lvds_write(lvds, LVDPLLCR, 0);
397 clk_disable_unprepare(lvds->clocks.mod);
399 lvds->enabled = false;
401 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
403 /* -----------------------------------------------------------------------------
407 static void rcar_lvds_enable(struct drm_bridge *bridge)
409 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
410 const struct drm_display_mode *mode = &lvds->display_mode;
412 * FIXME: We should really retrieve the CRTC through the state, but how
413 * do we get a state pointer?
415 struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
420 WARN_ON(lvds->enabled);
422 ret = clk_prepare_enable(lvds->clocks.mod);
427 * Hardcode the channels and control signals routing for now.
434 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
435 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
436 LVDCTRCR_CTR0SEL_HSYNC);
438 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
439 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
440 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
442 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
443 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
445 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
447 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
448 /* Disable dual-link mode. */
449 rcar_lvds_write(lvds, LVDSTRIPE, 0);
452 /* PLL clock configuration. */
453 lvds->info->pll_setup(lvds, mode->clock * 1000);
455 /* Set the LVDS mode and select the input. */
456 lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
457 if (drm_crtc_index(crtc) == 2)
458 lvdcr0 |= LVDCR0_DUSEL;
459 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
461 /* Turn all the channels on. */
462 rcar_lvds_write(lvds, LVDCR1,
463 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
464 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
466 if (lvds->info->gen < 3) {
467 /* Enable LVDS operation and turn the bias circuitry on. */
468 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
469 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
472 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
474 * Turn the PLL on (simple PLL only, extended PLL is fully
475 * controlled through LVDPLLCR).
477 lvdcr0 |= LVDCR0_PLLON;
478 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
481 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
482 /* Set LVDS normal mode. */
483 lvdcr0 |= LVDCR0_PWD;
484 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
487 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
489 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
490 * set at the same time, so don't write the register yet.
492 lvdcr0 |= LVDCR0_LVEN;
493 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
494 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
497 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
498 /* Wait for the PLL startup delay (simple PLL only). */
499 usleep_range(100, 150);
502 /* Turn the output on. */
503 lvdcr0 |= LVDCR0_LVRES;
504 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
507 drm_panel_prepare(lvds->panel);
508 drm_panel_enable(lvds->panel);
511 lvds->enabled = true;
514 static void rcar_lvds_disable(struct drm_bridge *bridge)
516 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
518 WARN_ON(!lvds->enabled);
521 drm_panel_disable(lvds->panel);
522 drm_panel_unprepare(lvds->panel);
525 rcar_lvds_write(lvds, LVDCR0, 0);
526 rcar_lvds_write(lvds, LVDCR1, 0);
527 rcar_lvds_write(lvds, LVDPLLCR, 0);
529 clk_disable_unprepare(lvds->clocks.mod);
531 lvds->enabled = false;
534 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
535 const struct drm_display_mode *mode,
536 struct drm_display_mode *adjusted_mode)
538 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
542 * The internal LVDS encoder has a restricted clock frequency operating
543 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
544 * 148.5MHz on all other platforms. Clamp the clock accordingly.
546 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
547 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
552 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
554 struct drm_display_info *info = &lvds->connector.display_info;
555 enum rcar_lvds_mode mode;
558 * There is no API yet to retrieve LVDS mode from a bridge, only panels
564 if (!info->num_bus_formats || !info->bus_formats) {
565 dev_err(lvds->dev, "no LVDS bus format reported\n");
569 switch (info->bus_formats[0]) {
570 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
571 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
572 mode = RCAR_LVDS_MODE_JEIDA;
574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
575 mode = RCAR_LVDS_MODE_VESA;
578 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
579 info->bus_formats[0]);
583 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
584 mode |= RCAR_LVDS_MODE_MIRROR;
589 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
590 const struct drm_display_mode *mode,
591 const struct drm_display_mode *adjusted_mode)
593 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
595 WARN_ON(lvds->enabled);
597 lvds->display_mode = *adjusted_mode;
599 rcar_lvds_get_lvds_mode(lvds);
602 static int rcar_lvds_attach(struct drm_bridge *bridge)
604 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
605 struct drm_connector *connector = &lvds->connector;
606 struct drm_encoder *encoder = bridge->encoder;
609 /* If we have a next bridge just attach it. */
610 if (lvds->next_bridge)
611 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
614 /* Otherwise if we have a panel, create a connector. */
618 ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
619 DRM_MODE_CONNECTOR_LVDS);
623 drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
625 ret = drm_connector_attach_encoder(connector, encoder);
629 return drm_panel_attach(lvds->panel, connector);
632 static void rcar_lvds_detach(struct drm_bridge *bridge)
634 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
637 drm_panel_detach(lvds->panel);
640 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
641 .attach = rcar_lvds_attach,
642 .detach = rcar_lvds_detach,
643 .enable = rcar_lvds_enable,
644 .disable = rcar_lvds_disable,
645 .mode_fixup = rcar_lvds_mode_fixup,
646 .mode_set = rcar_lvds_mode_set,
649 /* -----------------------------------------------------------------------------
653 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
655 struct device_node *local_output = NULL;
656 struct device_node *remote_input = NULL;
657 struct device_node *remote = NULL;
658 struct device_node *node;
659 bool is_bridge = false;
662 local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
664 dev_dbg(lvds->dev, "unconnected port@1\n");
670 * Locate the connected entity and infer its type from the number of
673 remote = of_graph_get_remote_port_parent(local_output);
675 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
680 if (!of_device_is_available(remote)) {
681 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
687 remote_input = of_graph_get_remote_endpoint(local_output);
689 for_each_endpoint_of_node(remote, node) {
690 if (node != remote_input) {
692 * We've found one endpoint other than the input, this
702 lvds->next_bridge = of_drm_find_bridge(remote);
703 if (!lvds->next_bridge)
706 lvds->panel = of_drm_find_panel(remote);
707 if (IS_ERR(lvds->panel))
708 ret = PTR_ERR(lvds->panel);
712 of_node_put(local_output);
713 of_node_put(remote_input);
717 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
718 * used for the DPAD output even when the LVDS output is not connected.
719 * Don't fail probe in that case as the DU will need the bridge to
722 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
723 return ret == -ENODEV ? 0 : ret;
728 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
733 clk = devm_clk_get(lvds->dev, name);
737 if (PTR_ERR(clk) == -ENOENT && optional)
740 if (PTR_ERR(clk) != -EPROBE_DEFER)
741 dev_err(lvds->dev, "failed to get %s clock\n",
742 name ? name : "module");
747 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
749 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
750 if (IS_ERR(lvds->clocks.mod))
751 return PTR_ERR(lvds->clocks.mod);
754 * LVDS encoders without an extended PLL have no external clock inputs.
756 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
759 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
760 if (IS_ERR(lvds->clocks.extal))
761 return PTR_ERR(lvds->clocks.extal);
763 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
764 if (IS_ERR(lvds->clocks.dotclkin[0]))
765 return PTR_ERR(lvds->clocks.dotclkin[0]);
767 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
768 if (IS_ERR(lvds->clocks.dotclkin[1]))
769 return PTR_ERR(lvds->clocks.dotclkin[1]);
771 /* At least one input to the PLL must be available. */
772 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
773 !lvds->clocks.dotclkin[1]) {
775 "no input clock (extal, dclkin.0 or dclkin.1)\n");
782 static int rcar_lvds_probe(struct platform_device *pdev)
784 struct rcar_lvds *lvds;
785 struct resource *mem;
788 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
792 platform_set_drvdata(pdev, lvds);
794 lvds->dev = &pdev->dev;
795 lvds->info = of_device_get_match_data(&pdev->dev);
796 lvds->enabled = false;
798 ret = rcar_lvds_parse_dt(lvds);
802 lvds->bridge.driver_private = lvds;
803 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
804 lvds->bridge.of_node = pdev->dev.of_node;
806 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
807 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
808 if (IS_ERR(lvds->mmio))
809 return PTR_ERR(lvds->mmio);
811 ret = rcar_lvds_get_clocks(lvds);
815 drm_bridge_add(&lvds->bridge);
820 static int rcar_lvds_remove(struct platform_device *pdev)
822 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
824 drm_bridge_remove(&lvds->bridge);
829 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
831 .pll_setup = rcar_lvds_pll_setup_gen2,
834 static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
836 .quirks = RCAR_LVDS_QUIRK_LANES,
837 .pll_setup = rcar_lvds_pll_setup_gen2,
840 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
842 .quirks = RCAR_LVDS_QUIRK_PWD,
843 .pll_setup = rcar_lvds_pll_setup_gen3,
846 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
848 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
849 .pll_setup = rcar_lvds_pll_setup_gen2,
852 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
854 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
855 | RCAR_LVDS_QUIRK_DUAL_LINK,
856 .pll_setup = rcar_lvds_pll_setup_d3_e3,
859 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
861 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
862 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
863 .pll_setup = rcar_lvds_pll_setup_d3_e3,
866 static const struct of_device_id rcar_lvds_of_table[] = {
867 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
868 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
869 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
870 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
871 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
872 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
873 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
874 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
875 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
876 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
877 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
878 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
879 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
883 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
885 static struct platform_driver rcar_lvds_platform_driver = {
886 .probe = rcar_lvds_probe,
887 .remove = rcar_lvds_remove,
890 .of_match_table = rcar_lvds_of_table,
894 module_platform_driver(rcar_lvds_platform_driver);
896 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
897 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
898 MODULE_LICENSE("GPL");