drivers/gpu/drm/rcar-du/rcar_lvds.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * rcar_lvds.c  --  R-Car LVDS Encoder
   4  *
   5  * Copyright (C) 2013-2018 Renesas Electronics Corporation
   6  *
   7  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_graph.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_bridge.h>
  23 #include <drm/drm_panel.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #include "rcar_lvds.h"
  27 #include "rcar_lvds_regs.h"
  28
  29 struct rcar_lvds;
  30
  31 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
  32 enum rcar_lvds_mode {
  33         RCAR_LVDS_MODE_JEIDA = 0,
  34         RCAR_LVDS_MODE_MIRROR = 1,
  35         RCAR_LVDS_MODE_VESA = 4,
  36 };
  37
  38 #define RCAR_LVDS_QUIRK_LANES           BIT(0)  /* LVDS lanes 1 and 3 inverted */
  39 #define RCAR_LVDS_QUIRK_GEN3_LVEN       BIT(1)  /* LVEN bit needs to be set on R8A77970/R8A7799x */
  40 #define RCAR_LVDS_QUIRK_PWD             BIT(2)  /* PWD bit available (all of Gen3 but E3) */
  41 #define RCAR_LVDS_QUIRK_EXT_PLL         BIT(3)  /* Has extended PLL */
  42 #define RCAR_LVDS_QUIRK_DUAL_LINK       BIT(4)  /* Supports dual-link operation */
  43
  44 struct rcar_lvds_device_info {
  45         unsigned int gen;
  46         unsigned int quirks;
  47         void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
  48 };
  49
  50 struct rcar_lvds {
  51         struct device *dev;
  52         const struct rcar_lvds_device_info *info;
  53
  54         struct drm_bridge bridge;
  55
  56         struct drm_bridge *next_bridge;
  57         struct drm_connector connector;
  58         struct drm_panel *panel;
  59
  60         void __iomem *mmio;
  61         struct {
  62                 struct clk *mod;                /* CPG module clock */
  63                 struct clk *extal;              /* External clock */
  64                 struct clk *dotclkin[2];        /* External DU clocks */
  65         } clocks;
  66
  67         struct drm_display_mode display_mode;
  68         enum rcar_lvds_mode mode;
  69
  70         struct drm_bridge *companion;
  71         bool dual_link;
  72 };
  73
  74 #define bridge_to_rcar_lvds(bridge) \
  75         container_of(bridge, struct rcar_lvds, bridge)
  76
  77 #define connector_to_rcar_lvds(connector) \
  78         container_of(connector, struct rcar_lvds, connector)
  79
  80 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
  81 {
  82         iowrite32(data, lvds->mmio + reg);
  83 }
  84
  85 /* -----------------------------------------------------------------------------
  86  * Connector & Panel
  87  */
  88
  89 static int rcar_lvds_connector_get_modes(struct drm_connector *connector)
  90 {
  91         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
  92
  93         return drm_panel_get_modes(lvds->panel);
  94 }
  95
  96 static int rcar_lvds_connector_atomic_check(struct drm_connector *connector,
  97                                             struct drm_connector_state *state)
  98 {
  99         struct rcar_lvds *lvds = connector_to_rcar_lvds(connector);
 100         const struct drm_display_mode *panel_mode;
 101         struct drm_crtc_state *crtc_state;
 102
 103         if (!state->crtc)
 104                 return 0;
 105
 106         if (list_empty(&connector->modes)) {
 107                 dev_dbg(lvds->dev, "connector: empty modes list\n");
 108                 return -EINVAL;
 109         }
 110
 111         panel_mode = list_first_entry(&connector->modes,
 112                                       struct drm_display_mode, head);
 113
 114         /* We're not allowed to modify the resolution. */
 115         crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
 116         if (IS_ERR(crtc_state))
 117                 return PTR_ERR(crtc_state);
 118
 119         if (crtc_state->mode.hdisplay != panel_mode->hdisplay ||
 120             crtc_state->mode.vdisplay != panel_mode->vdisplay)
 121                 return -EINVAL;
 122
 123         /* The flat panel mode is fixed, just copy it to the adjusted mode. */
 124         drm_mode_copy(&crtc_state->adjusted_mode, panel_mode);
 125
 126         return 0;
 127 }
 128
 129 static const struct drm_connector_helper_funcs rcar_lvds_conn_helper_funcs = {
 130         .get_modes = rcar_lvds_connector_get_modes,
 131         .atomic_check = rcar_lvds_connector_atomic_check,
 132 };
 133
 134 static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
 135         .reset = drm_atomic_helper_connector_reset,
 136         .fill_modes = drm_helper_probe_single_connector_modes,
 137         .destroy = drm_connector_cleanup,
 138         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 139         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 140 };
 141
 142 /* -----------------------------------------------------------------------------
 143  * PLL Setup
 144  */
 145
 146 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
 147 {
 148         u32 val;
 149
 150         if (freq < 39000000)
 151                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
 152         else if (freq < 61000000)
 153                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
 154         else if (freq < 121000000)
 155                 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
 156         else
 157                 val = LVDPLLCR_PLLDLYCNT_150M;
 158
 159         rcar_lvds_write(lvds, LVDPLLCR, val);
 160 }
 161
 162 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
 163 {
 164         u32 val;
 165
 166         if (freq < 42000000)
 167                 val = LVDPLLCR_PLLDIVCNT_42M;
 168         else if (freq < 85000000)
 169                 val = LVDPLLCR_PLLDIVCNT_85M;
 170         else if (freq < 128000000)
 171                 val = LVDPLLCR_PLLDIVCNT_128M;
 172         else
 173                 val = LVDPLLCR_PLLDIVCNT_148M;
 174
 175         rcar_lvds_write(lvds, LVDPLLCR, val);
 176 }
 177
 178 struct pll_info {
 179         unsigned long diff;
 180         unsigned int pll_m;
 181         unsigned int pll_n;
 182         unsigned int pll_e;
 183         unsigned int div;
 184         u32 clksel;
 185 };
 186
 187 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
 188                                      unsigned long target, struct pll_info *pll,
 189                                      u32 clksel, bool dot_clock_only)
 190 {
 191         unsigned int div7 = dot_clock_only ? 1 : 7;
 192         unsigned long output;
 193         unsigned long fin;
 194         unsigned int m_min;
 195         unsigned int m_max;
 196         unsigned int m;
 197         int error;
 198
 199         if (!clk)
 200                 return;
 201
 202         /*
 203          * The LVDS PLL is made of a pre-divider and a multiplier (strangely
 204          * enough called M and N respectively), followed by a post-divider E.
 205          *
 206          *         ,-----.         ,-----.     ,-----.         ,-----.
 207          * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
 208          *         `-----'     ,-> |     |     `-----'   |     `-----'
 209          *                     |   `-----'               |
 210          *                     |         ,-----.         |
 211          *                     `-------- | 1/N | <-------'
 212          *                               `-----'
 213          *
 214          * The clock output by the PLL is then further divided by a programmable
 215          * divider DIV to achieve the desired target frequency. Finally, an
 216          * optional fixed /7 divider is used to convert the bit clock to a pixel
 217          * clock (as LVDS transmits 7 bits per lane per clock sample).
 218          *
 219          *          ,-------.     ,-----.     |\
 220          * Fout --> | 1/DIV | --> | 1/7 | --> | |
 221          *          `-------'  |  `-----'     | | --> dot clock
 222          *                     `------------> | |
 223          *                                    |/
 224          *
 225          * The /7 divider is optional, it is enabled when the LVDS PLL is used
 226          * to drive the LVDS encoder, and disabled when  used to generate a dot
 227          * clock for the DU RGB output, without using the LVDS encoder.
 228          *
 229          * The PLL allowed input frequency range is 12 MHz to 192 MHz.
 230          */
 231
 232         fin = clk_get_rate(clk);
 233         if (fin < 12000000 || fin > 192000000)
 234                 return;
 235
 236         /*
 237          * The comparison frequency range is 12 MHz to 24 MHz, which limits the
 238          * allowed values for the pre-divider M (normal range 1-8).
 239          *
 240          * Fpfd = Fin / M
 241          */
 242         m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
 243         m_max = min_t(unsigned int, 8, fin / 12000000);
 244
 245         for (m = m_min; m <= m_max; ++m) {
 246                 unsigned long fpfd;
 247                 unsigned int n_min;
 248                 unsigned int n_max;
 249                 unsigned int n;
 250
 251                 /*
 252                  * The VCO operating range is 900 Mhz to 1800 MHz, which limits
 253                  * the allowed values for the multiplier N (normal range
 254                  * 60-120).
 255                  *
 256                  * Fvco = Fin * N / M
 257                  */
 258                 fpfd = fin / m;
 259                 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
 260                 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
 261
 262                 for (n = n_min; n < n_max; ++n) {
 263                         unsigned long fvco;
 264                         unsigned int e_min;
 265                         unsigned int e;
 266
 267                         /*
 268                          * The output frequency is limited to 1039.5 MHz,
 269                          * limiting again the allowed values for the
 270                          * post-divider E (normal value 1, 2 or 4).
 271                          *
 272                          * Fout = Fvco / E
 273                          */
 274                         fvco = fpfd * n;
 275                         e_min = fvco > 1039500000 ? 1 : 0;
 276
 277                         for (e = e_min; e < 3; ++e) {
 278                                 unsigned long fout;
 279                                 unsigned long diff;
 280                                 unsigned int div;
 281
 282                                 /*
 283                                  * Finally we have a programable divider after
 284                                  * the PLL, followed by a an optional fixed /7
 285                                  * divider.
 286                                  */
 287                                 fout = fvco / (1 << e) / div7;
 288                                 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
 289                                 diff = abs(fout / div - target);
 290
 291                                 if (diff < pll->diff) {
 292                                         pll->diff = diff;
 293                                         pll->pll_m = m;
 294                                         pll->pll_n = n;
 295                                         pll->pll_e = e;
 296                                         pll->div = div;
 297                                         pll->clksel = clksel;
 298
 299                                         if (diff == 0)
 300                                                 goto done;
 301                                 }
 302                         }
 303                 }
 304         }
 305
 306 done:
 307         output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
 308                / div7 / pll->div;
 309         error = (long)(output - target) * 10000 / (long)target;
 310
 311         dev_dbg(lvds->dev,
 312                 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
 313                 clk, fin, output, target, error / 100,
 314                 error < 0 ? -error % 100 : error % 100,
 315                 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
 316 }
 317
 318 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
 319                                         unsigned int freq, bool dot_clock_only)
 320 {
 321         struct pll_info pll = { .diff = (unsigned long)-1 };
 322         u32 lvdpllcr;
 323
 324         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
 325                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
 326         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
 327                                  LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
 328         rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
 329                                  LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
 330
 331         lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
 332                  | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
 333
 334         if (pll.pll_e > 0)
 335                 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
 336                          |  LVDPLLCR_PLLE(pll.pll_e - 1);
 337
 338         if (dot_clock_only)
 339                 lvdpllcr |= LVDPLLCR_OCKSEL;
 340
 341         rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
 342
 343         if (pll.div > 1)
 344                 /*
 345                  * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
 346                  * divisor reset.
 347                  */
 348                 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
 349                                 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
 350         else
 351                 rcar_lvds_write(lvds, LVDDIV, 0);
 352 }
 353
 354 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
 355 {
 356         __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
 357 }
 358
 359 /* -----------------------------------------------------------------------------
 360  * Clock - D3/E3 only
 361  */
 362
 363 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
 364 {
 365         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 366         int ret;
 367
 368         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 369                 return -ENODEV;
 370
 371         dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
 372
 373         ret = clk_prepare_enable(lvds->clocks.mod);
 374         if (ret < 0)
 375                 return ret;
 376
 377         __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
 378
 379         return 0;
 380 }
 381 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
 382
 383 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
 384 {
 385         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 386
 387         if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
 388                 return;
 389
 390         dev_dbg(lvds->dev, "disabling LVDS PLL\n");
 391
 392         rcar_lvds_write(lvds, LVDPLLCR, 0);
 393
 394         clk_disable_unprepare(lvds->clocks.mod);
 395 }
 396 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
 397
 398 /* -----------------------------------------------------------------------------
 399  * Bridge
 400  */
 401
 402 static void rcar_lvds_enable(struct drm_bridge *bridge)
 403 {
 404         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 405         const struct drm_display_mode *mode = &lvds->display_mode;
 406         u32 lvdhcr;
 407         u32 lvdcr0;
 408         int ret;
 409
 410         ret = clk_prepare_enable(lvds->clocks.mod);
 411         if (ret < 0)
 412                 return;
 413
 414         /* Enable the companion LVDS encoder in dual-link mode. */
 415         if (lvds->dual_link && lvds->companion)
 416                 lvds->companion->funcs->enable(lvds->companion);
 417
 418         /*
 419          * Hardcode the channels and control signals routing for now.
 420          *
 421          * HSYNC -> CTRL0
 422          * VSYNC -> CTRL1
 423          * DISP  -> CTRL2
 424          * 0     -> CTRL3
 425          */
 426         rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
 427                         LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
 428                         LVDCTRCR_CTR0SEL_HSYNC);
 429
 430         if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
 431                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
 432                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
 433         else
 434                 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
 435                        | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
 436
 437         rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
 438
 439         if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
 440                 /*
 441                  * Configure vertical stripe based on the mode of operation of
 442                  * the connected device.
 443                  */
 444                 rcar_lvds_write(lvds, LVDSTRIPE,
 445                                 lvds->dual_link ? LVDSTRIPE_ST_ON : 0);
 446         }
 447
 448         /*
 449          * PLL clock configuration on all instances but the companion in
 450          * dual-link mode.
 451          */
 452         if (!lvds->dual_link || lvds->companion)
 453                 lvds->info->pll_setup(lvds, mode->clock * 1000);
 454
 455         /* Set the LVDS mode and select the input. */
 456         lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
 457
 458         if (lvds->bridge.encoder) {
 459                 /*
 460                  * FIXME: We should really retrieve the CRTC through the state,
 461                  * but how do we get a state pointer?
 462                  */
 463                 if (drm_crtc_index(lvds->bridge.encoder->crtc) == 2)
 464                         lvdcr0 |= LVDCR0_DUSEL;
 465         }
 466
 467         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 468
 469         /* Turn all the channels on. */
 470         rcar_lvds_write(lvds, LVDCR1,
 471                         LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
 472                         LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
 473
 474         if (lvds->info->gen < 3) {
 475                 /* Enable LVDS operation and turn the bias circuitry on. */
 476                 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
 477                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 478         }
 479
 480         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 481                 /*
 482                  * Turn the PLL on (simple PLL only, extended PLL is fully
 483                  * controlled through LVDPLLCR).
 484                  */
 485                 lvdcr0 |= LVDCR0_PLLON;
 486                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 487         }
 488
 489         if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
 490                 /* Set LVDS normal mode. */
 491                 lvdcr0 |= LVDCR0_PWD;
 492                 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 493         }
 494
 495         if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
 496                 /*
 497                  * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
 498                  * set at the same time, so don't write the register yet.
 499                  */
 500                 lvdcr0 |= LVDCR0_LVEN;
 501                 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
 502                         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 503         }
 504
 505         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
 506                 /* Wait for the PLL startup delay (simple PLL only). */
 507                 usleep_range(100, 150);
 508         }
 509
 510         /* Turn the output on. */
 511         lvdcr0 |= LVDCR0_LVRES;
 512         rcar_lvds_write(lvds, LVDCR0, lvdcr0);
 513
 514         if (lvds->panel) {
 515                 drm_panel_prepare(lvds->panel);
 516                 drm_panel_enable(lvds->panel);
 517         }
 518 }
 519
 520 static void rcar_lvds_disable(struct drm_bridge *bridge)
 521 {
 522         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 523
 524         if (lvds->panel) {
 525                 drm_panel_disable(lvds->panel);
 526                 drm_panel_unprepare(lvds->panel);
 527         }
 528
 529         rcar_lvds_write(lvds, LVDCR0, 0);
 530         rcar_lvds_write(lvds, LVDCR1, 0);
 531         rcar_lvds_write(lvds, LVDPLLCR, 0);
 532
 533         /* Disable the companion LVDS encoder in dual-link mode. */
 534         if (lvds->dual_link && lvds->companion)
 535                 lvds->companion->funcs->disable(lvds->companion);
 536
 537         clk_disable_unprepare(lvds->clocks.mod);
 538 }
 539
 540 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
 541                                  const struct drm_display_mode *mode,
 542                                  struct drm_display_mode *adjusted_mode)
 543 {
 544         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 545         int min_freq;
 546
 547         /*
 548          * The internal LVDS encoder has a restricted clock frequency operating
 549          * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
 550          * 148.5MHz on all other platforms. Clamp the clock accordingly.
 551          */
 552         min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
 553         adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
 554
 555         return true;
 556 }
 557
 558 static void rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds)
 559 {
 560         struct drm_display_info *info = &lvds->connector.display_info;
 561         enum rcar_lvds_mode mode;
 562
 563         /*
 564          * There is no API yet to retrieve LVDS mode from a bridge, only panels
 565          * are supported.
 566          */
 567         if (!lvds->panel)
 568                 return;
 569
 570         if (!info->num_bus_formats || !info->bus_formats) {
 571                 dev_err(lvds->dev, "no LVDS bus format reported\n");
 572                 return;
 573         }
 574
 575         switch (info->bus_formats[0]) {
 576         case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
 577         case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
 578                 mode = RCAR_LVDS_MODE_JEIDA;
 579                 break;
 580         case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
 581                 mode = RCAR_LVDS_MODE_VESA;
 582                 break;
 583         default:
 584                 dev_err(lvds->dev, "unsupported LVDS bus format 0x%04x\n",
 585                         info->bus_formats[0]);
 586                 return;
 587         }
 588
 589         if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
 590                 mode |= RCAR_LVDS_MODE_MIRROR;
 591
 592         lvds->mode = mode;
 593 }
 594
 595 static void rcar_lvds_mode_set(struct drm_bridge *bridge,
 596                                const struct drm_display_mode *mode,
 597                                const struct drm_display_mode *adjusted_mode)
 598 {
 599         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 600
 601         lvds->display_mode = *adjusted_mode;
 602
 603         rcar_lvds_get_lvds_mode(lvds);
 604 }
 605
 606 static int rcar_lvds_attach(struct drm_bridge *bridge)
 607 {
 608         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 609         struct drm_connector *connector = &lvds->connector;
 610         struct drm_encoder *encoder = bridge->encoder;
 611         int ret;
 612
 613         /* If we have a next bridge just attach it. */
 614         if (lvds->next_bridge)
 615                 return drm_bridge_attach(bridge->encoder, lvds->next_bridge,
 616                                          bridge);
 617
 618         /* Otherwise if we have a panel, create a connector. */
 619         if (!lvds->panel)
 620                 return 0;
 621
 622         ret = drm_connector_init(bridge->dev, connector, &rcar_lvds_conn_funcs,
 623                                  DRM_MODE_CONNECTOR_LVDS);
 624         if (ret < 0)
 625                 return ret;
 626
 627         drm_connector_helper_add(connector, &rcar_lvds_conn_helper_funcs);
 628
 629         ret = drm_connector_attach_encoder(connector, encoder);
 630         if (ret < 0)
 631                 return ret;
 632
 633         return drm_panel_attach(lvds->panel, connector);
 634 }
 635
 636 static void rcar_lvds_detach(struct drm_bridge *bridge)
 637 {
 638         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 639
 640         if (lvds->panel)
 641                 drm_panel_detach(lvds->panel);
 642 }
 643
 644 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
 645         .attach = rcar_lvds_attach,
 646         .detach = rcar_lvds_detach,
 647         .enable = rcar_lvds_enable,
 648         .disable = rcar_lvds_disable,
 649         .mode_fixup = rcar_lvds_mode_fixup,
 650         .mode_set = rcar_lvds_mode_set,
 651 };
 652
 653 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
 654 {
 655         struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
 656
 657         return lvds->dual_link;
 658 }
 659 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
 660
 661 /* -----------------------------------------------------------------------------
 662  * Probe & Remove
 663  */
 664
 665 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
 666 {
 667         const struct of_device_id *match;
 668         struct device_node *companion;
 669         struct device *dev = lvds->dev;
 670         int ret = 0;
 671
 672         /* Locate the companion LVDS encoder for dual-link operation, if any. */
 673         companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
 674         if (!companion) {
 675                 dev_err(dev, "Companion LVDS encoder not found\n");
 676                 return -ENXIO;
 677         }
 678
 679         /*
 680          * Sanity check: the companion encoder must have the same compatible
 681          * string.
 682          */
 683         match = of_match_device(dev->driver->of_match_table, dev);
 684         if (!of_device_is_compatible(companion, match->compatible)) {
 685                 dev_err(dev, "Companion LVDS encoder is invalid\n");
 686                 ret = -ENXIO;
 687                 goto done;
 688         }
 689
 690         lvds->companion = of_drm_find_bridge(companion);
 691         if (!lvds->companion) {
 692                 ret = -EPROBE_DEFER;
 693                 goto done;
 694         }
 695
 696         dev_dbg(dev, "Found companion encoder %pOF\n", companion);
 697
 698 done:
 699         of_node_put(companion);
 700
 701         return ret;
 702 }
 703
 704 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
 705 {
 706         struct device_node *local_output = NULL;
 707         struct device_node *remote_input = NULL;
 708         struct device_node *remote = NULL;
 709         struct device_node *node;
 710         bool is_bridge = false;
 711         int ret = 0;
 712
 713         local_output = of_graph_get_endpoint_by_regs(lvds->dev->of_node, 1, 0);
 714         if (!local_output) {
 715                 dev_dbg(lvds->dev, "unconnected port@1\n");
 716                 ret = -ENODEV;
 717                 goto done;
 718         }
 719
 720         /*
 721          * Locate the connected entity and infer its type from the number of
 722          * endpoints.
 723          */
 724         remote = of_graph_get_remote_port_parent(local_output);
 725         if (!remote) {
 726                 dev_dbg(lvds->dev, "unconnected endpoint %pOF\n", local_output);
 727                 ret = -ENODEV;
 728                 goto done;
 729         }
 730
 731         if (!of_device_is_available(remote)) {
 732                 dev_dbg(lvds->dev, "connected entity %pOF is disabled\n",
 733                         remote);
 734                 ret = -ENODEV;
 735                 goto done;
 736         }
 737
 738         remote_input = of_graph_get_remote_endpoint(local_output);
 739
 740         for_each_endpoint_of_node(remote, node) {
 741                 if (node != remote_input) {
 742                         /*
 743                          * We've found one endpoint other than the input, this
 744                          * must be a bridge.
 745                          */
 746                         is_bridge = true;
 747                         of_node_put(node);
 748                         break;
 749                 }
 750         }
 751
 752         if (is_bridge) {
 753                 lvds->next_bridge = of_drm_find_bridge(remote);
 754                 if (!lvds->next_bridge) {
 755                         ret = -EPROBE_DEFER;
 756                         goto done;
 757                 }
 758
 759                 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
 760                         lvds->dual_link = lvds->next_bridge->timings
 761                                         ? lvds->next_bridge->timings->dual_link
 762                                         : false;
 763         } else {
 764                 lvds->panel = of_drm_find_panel(remote);
 765                 if (IS_ERR(lvds->panel)) {
 766                         ret = PTR_ERR(lvds->panel);
 767                         goto done;
 768                 }
 769         }
 770
 771         if (lvds->dual_link)
 772                 ret = rcar_lvds_parse_dt_companion(lvds);
 773
 774 done:
 775         of_node_put(local_output);
 776         of_node_put(remote_input);
 777         of_node_put(remote);
 778
 779         /*
 780          * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
 781          * used for the DPAD output even when the LVDS output is not connected.
 782          * Don't fail probe in that case as the DU will need the bridge to
 783          * control the clock.
 784          */
 785         if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
 786                 return ret == -ENODEV ? 0 : ret;
 787
 788         return ret;
 789 }
 790
 791 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
 792                                        bool optional)
 793 {
 794         struct clk *clk;
 795
 796         clk = devm_clk_get(lvds->dev, name);
 797         if (!IS_ERR(clk))
 798                 return clk;
 799
 800         if (PTR_ERR(clk) == -ENOENT && optional)
 801                 return NULL;
 802
 803         if (PTR_ERR(clk) != -EPROBE_DEFER)
 804                 dev_err(lvds->dev, "failed to get %s clock\n",
 805                         name ? name : "module");
 806
 807         return clk;
 808 }
 809
 810 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
 811 {
 812         lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
 813         if (IS_ERR(lvds->clocks.mod))
 814                 return PTR_ERR(lvds->clocks.mod);
 815
 816         /*
 817          * LVDS encoders without an extended PLL have no external clock inputs.
 818          */
 819         if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
 820                 return 0;
 821
 822         lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
 823         if (IS_ERR(lvds->clocks.extal))
 824                 return PTR_ERR(lvds->clocks.extal);
 825
 826         lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
 827         if (IS_ERR(lvds->clocks.dotclkin[0]))
 828                 return PTR_ERR(lvds->clocks.dotclkin[0]);
 829
 830         lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
 831         if (IS_ERR(lvds->clocks.dotclkin[1]))
 832                 return PTR_ERR(lvds->clocks.dotclkin[1]);
 833
 834         /* At least one input to the PLL must be available. */
 835         if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
 836             !lvds->clocks.dotclkin[1]) {
 837                 dev_err(lvds->dev,
 838                         "no input clock (extal, dclkin.0 or dclkin.1)\n");
 839                 return -EINVAL;
 840         }
 841
 842         return 0;
 843 }
 844
 845 static int rcar_lvds_probe(struct platform_device *pdev)
 846 {
 847         struct rcar_lvds *lvds;
 848         struct resource *mem;
 849         int ret;
 850
 851         lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
 852         if (lvds == NULL)
 853                 return -ENOMEM;
 854
 855         platform_set_drvdata(pdev, lvds);
 856
 857         lvds->dev = &pdev->dev;
 858         lvds->info = of_device_get_match_data(&pdev->dev);
 859
 860         ret = rcar_lvds_parse_dt(lvds);
 861         if (ret < 0)
 862                 return ret;
 863
 864         lvds->bridge.driver_private = lvds;
 865         lvds->bridge.funcs = &rcar_lvds_bridge_ops;
 866         lvds->bridge.of_node = pdev->dev.of_node;
 867
 868         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 869         lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
 870         if (IS_ERR(lvds->mmio))
 871                 return PTR_ERR(lvds->mmio);
 872
 873         ret = rcar_lvds_get_clocks(lvds);
 874         if (ret < 0)
 875                 return ret;
 876
 877         drm_bridge_add(&lvds->bridge);
 878
 879         return 0;
 880 }
 881
 882 static int rcar_lvds_remove(struct platform_device *pdev)
 883 {
 884         struct rcar_lvds *lvds = platform_get_drvdata(pdev);
 885
 886         drm_bridge_remove(&lvds->bridge);
 887
 888         return 0;
 889 }
 890
 891 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
 892         .gen = 2,
 893         .pll_setup = rcar_lvds_pll_setup_gen2,
 894 };
 895
 896 static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
 897         .gen = 2,
 898         .quirks = RCAR_LVDS_QUIRK_LANES,
 899         .pll_setup = rcar_lvds_pll_setup_gen2,
 900 };
 901
 902 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
 903         .gen = 3,
 904         .quirks = RCAR_LVDS_QUIRK_PWD,
 905         .pll_setup = rcar_lvds_pll_setup_gen3,
 906 };
 907
 908 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
 909         .gen = 3,
 910         .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
 911         .pll_setup = rcar_lvds_pll_setup_gen2,
 912 };
 913
 914 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
 915         .gen = 3,
 916         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
 917                 | RCAR_LVDS_QUIRK_DUAL_LINK,
 918         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 919 };
 920
 921 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
 922         .gen = 3,
 923         .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
 924                 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
 925         .pll_setup = rcar_lvds_pll_setup_d3_e3,
 926 };
 927
 928 static const struct of_device_id rcar_lvds_of_table[] = {
 929         { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
 930         { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
 931         { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
 932         { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
 933         { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_r8a7790_info },
 934         { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
 935         { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
 936         { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
 937         { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
 938         { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
 939         { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
 940         { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
 941         { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
 942         { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
 943         { }
 944 };
 945
 946 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
 947
 948 static struct platform_driver rcar_lvds_platform_driver = {
 949         .probe          = rcar_lvds_probe,
 950         .remove         = rcar_lvds_remove,
 951         .driver         = {
 952                 .name   = "rcar-lvds",
 953                 .of_match_table = rcar_lvds_of_table,
 954         },
 955 };
 956
 957 module_platform_driver(rcar_lvds_platform_driver);
 958
 959 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
 960 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
 961 MODULE_LICENSE("GPL");