1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regmap.h>
13 #include <drm/drm_of.h>
15 #include <drm/drm_edid.h>
16 #include <drm/drm_probe_helper.h>
17 #include <drm/bridge/dw_hdmi.h>
19 #include "rockchip_drm_drv.h"
20 #include "rockchip_drm_vop.h"
22 #define RK3228_GRF_SOC_CON2 0x0408
23 #define RK3228_HDMI_SDAIN_MSK BIT(14)
24 #define RK3228_HDMI_SCLIN_MSK BIT(13)
25 #define RK3228_GRF_SOC_CON6 0x0418
26 #define RK3228_HDMI_HPD_VSEL BIT(6)
27 #define RK3228_HDMI_SDA_VSEL BIT(5)
28 #define RK3228_HDMI_SCL_VSEL BIT(4)
30 #define RK3288_GRF_SOC_CON6 0x025C
31 #define RK3288_HDMI_LCDC_SEL BIT(4)
32 #define RK3328_GRF_SOC_CON2 0x0408
34 #define RK3328_HDMI_SDAIN_MSK BIT(11)
35 #define RK3328_HDMI_SCLIN_MSK BIT(10)
36 #define RK3328_HDMI_HPD_IOE BIT(2)
37 #define RK3328_GRF_SOC_CON3 0x040c
38 /* need to be unset if hdmi or i2c should control voltage */
39 #define RK3328_HDMI_SDA5V_GRF BIT(15)
40 #define RK3328_HDMI_SCL5V_GRF BIT(14)
41 #define RK3328_HDMI_HPD5V_GRF BIT(13)
42 #define RK3328_HDMI_CEC5V_GRF BIT(12)
43 #define RK3328_GRF_SOC_CON4 0x0410
44 #define RK3328_HDMI_HPD_SARADC BIT(13)
45 #define RK3328_HDMI_CEC_5V BIT(11)
46 #define RK3328_HDMI_SDA_5V BIT(10)
47 #define RK3328_HDMI_SCL_5V BIT(9)
48 #define RK3328_HDMI_HPD_5V BIT(8)
50 #define RK3399_GRF_SOC_CON20 0x6250
51 #define RK3399_HDMI_LCDC_SEL BIT(6)
53 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
56 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
57 * @lcdsel_grf_reg: grf register offset of lcdc select
58 * @lcdsel_big: reg value of selecting vop big for HDMI
59 * @lcdsel_lit: reg value of selecting vop little for HDMI
61 struct rockchip_hdmi_chip_data {
67 struct rockchip_hdmi {
69 struct regmap *regmap;
70 struct drm_encoder encoder;
71 const struct rockchip_hdmi_chip_data *chip_data;
78 #define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
80 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
160 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
161 /* pixelclk bpp8 bpp10 bpp12 */
163 40000000, { 0x0018, 0x0018, 0x0018 },
165 65000000, { 0x0028, 0x0028, 0x0028 },
167 66000000, { 0x0038, 0x0038, 0x0038 },
169 74250000, { 0x0028, 0x0038, 0x0038 },
171 83500000, { 0x0028, 0x0038, 0x0038 },
173 146250000, { 0x0038, 0x0038, 0x0038 },
175 148500000, { 0x0000, 0x0038, 0x0038 },
177 ~0UL, { 0x0000, 0x0000, 0x0000},
181 static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
182 /*pixelclk symbol term vlev*/
183 { 74250000, 0x8009, 0x0004, 0x0272},
184 { 148500000, 0x802b, 0x0004, 0x028d},
185 { 297000000, 0x8039, 0x0005, 0x028d},
186 { ~0UL, 0x0000, 0x0000, 0x0000}
189 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
191 struct device_node *np = hdmi->dev->of_node;
193 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
194 if (IS_ERR(hdmi->regmap)) {
195 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n");
196 return PTR_ERR(hdmi->regmap);
199 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
200 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
201 hdmi->vpll_clk = NULL;
202 } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
203 return -EPROBE_DEFER;
204 } else if (IS_ERR(hdmi->vpll_clk)) {
205 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
206 return PTR_ERR(hdmi->vpll_clk);
209 hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
210 if (PTR_ERR(hdmi->grf_clk) == -ENOENT) {
211 hdmi->grf_clk = NULL;
212 } else if (PTR_ERR(hdmi->grf_clk) == -EPROBE_DEFER) {
213 return -EPROBE_DEFER;
214 } else if (IS_ERR(hdmi->grf_clk)) {
215 DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
216 return PTR_ERR(hdmi->grf_clk);
222 static enum drm_mode_status
223 dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
224 const struct drm_display_mode *mode)
226 const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
227 int pclk = mode->clock * 1000;
231 for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
232 if (pclk == mpll_cfg[i].mpixelclock) {
238 return (valid) ? MODE_OK : MODE_BAD;
241 static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
242 .destroy = drm_encoder_cleanup,
245 static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
250 dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
251 const struct drm_display_mode *mode,
252 struct drm_display_mode *adj_mode)
257 static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
258 struct drm_display_mode *mode,
259 struct drm_display_mode *adj_mode)
261 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
263 clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
266 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
268 struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
272 if (hdmi->chip_data->lcdsel_grf_reg < 0)
275 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
277 val = hdmi->chip_data->lcdsel_lit;
279 val = hdmi->chip_data->lcdsel_big;
281 ret = clk_prepare_enable(hdmi->grf_clk);
283 DRM_DEV_ERROR(hdmi->dev, "failed to enable grfclk %d\n", ret);
287 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val);
289 DRM_DEV_ERROR(hdmi->dev, "Could not write to GRF: %d\n", ret);
291 clk_disable_unprepare(hdmi->grf_clk);
292 DRM_DEV_DEBUG(hdmi->dev, "vop %s output to hdmi\n",
293 ret ? "LIT" : "BIG");
297 dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
298 struct drm_crtc_state *crtc_state,
299 struct drm_connector_state *conn_state)
301 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
303 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
304 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
309 static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
310 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
311 .mode_set = dw_hdmi_rockchip_encoder_mode_set,
312 .enable = dw_hdmi_rockchip_encoder_enable,
313 .disable = dw_hdmi_rockchip_encoder_disable,
314 .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
317 static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
318 struct drm_display_mode *mode)
320 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
322 return phy_power_on(hdmi->phy);
325 static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data)
327 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
329 phy_power_off(hdmi->phy);
332 static void dw_hdmi_rk3228_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
334 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
336 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
338 regmap_write(hdmi->regmap,
340 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
341 RK3228_HDMI_SCL_VSEL,
342 RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL |
343 RK3228_HDMI_SCL_VSEL));
345 regmap_write(hdmi->regmap,
347 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK,
348 RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK));
351 static enum drm_connector_status
352 dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data)
354 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
355 enum drm_connector_status status;
357 status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
359 if (status == connector_status_connected)
360 regmap_write(hdmi->regmap,
362 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V,
363 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V));
365 regmap_write(hdmi->regmap,
367 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V |
368 RK3328_HDMI_SCL_5V));
372 static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data)
374 struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
376 dw_hdmi_phy_setup_hpd(dw_hdmi, data);
378 /* Enable and map pins to 3V grf-controlled io-voltage */
379 regmap_write(hdmi->regmap,
381 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |
382 RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |
383 RK3328_HDMI_HPD_5V));
384 regmap_write(hdmi->regmap,
386 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |
387 RK3328_HDMI_HPD5V_GRF |
388 RK3328_HDMI_CEC5V_GRF));
389 regmap_write(hdmi->regmap,
391 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,
392 RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |
393 RK3328_HDMI_HPD_IOE));
396 static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = {
397 .init = dw_hdmi_rockchip_genphy_init,
398 .disable = dw_hdmi_rockchip_genphy_disable,
399 .read_hpd = dw_hdmi_phy_read_hpd,
400 .update_hpd = dw_hdmi_phy_update_hpd,
401 .setup_hpd = dw_hdmi_rk3228_setup_hpd,
404 static struct rockchip_hdmi_chip_data rk3228_chip_data = {
405 .lcdsel_grf_reg = -1,
408 static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
409 .mode_valid = dw_hdmi_rockchip_mode_valid,
410 .mpll_cfg = rockchip_mpll_cfg,
411 .cur_ctr = rockchip_cur_ctr,
412 .phy_config = rockchip_phy_config,
413 .phy_data = &rk3228_chip_data,
414 .phy_ops = &rk3228_hdmi_phy_ops,
415 .phy_name = "inno_dw_hdmi_phy2",
416 .phy_force_vendor = true,
419 static struct rockchip_hdmi_chip_data rk3288_chip_data = {
420 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
421 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
422 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
425 static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
426 .mode_valid = dw_hdmi_rockchip_mode_valid,
427 .mpll_cfg = rockchip_mpll_cfg,
428 .cur_ctr = rockchip_cur_ctr,
429 .phy_config = rockchip_phy_config,
430 .phy_data = &rk3288_chip_data,
433 static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
434 .init = dw_hdmi_rockchip_genphy_init,
435 .disable = dw_hdmi_rockchip_genphy_disable,
436 .read_hpd = dw_hdmi_rk3328_read_hpd,
437 .update_hpd = dw_hdmi_phy_update_hpd,
438 .setup_hpd = dw_hdmi_rk3328_setup_hpd,
441 static struct rockchip_hdmi_chip_data rk3328_chip_data = {
442 .lcdsel_grf_reg = -1,
445 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
446 .mode_valid = dw_hdmi_rockchip_mode_valid,
447 .mpll_cfg = rockchip_mpll_cfg,
448 .cur_ctr = rockchip_cur_ctr,
449 .phy_config = rockchip_phy_config,
450 .phy_data = &rk3328_chip_data,
451 .phy_ops = &rk3328_hdmi_phy_ops,
452 .phy_name = "inno_dw_hdmi_phy2",
453 .phy_force_vendor = true,
456 static struct rockchip_hdmi_chip_data rk3399_chip_data = {
457 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
458 .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL),
459 .lcdsel_lit = HIWORD_UPDATE(RK3399_HDMI_LCDC_SEL, RK3399_HDMI_LCDC_SEL),
462 static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
463 .mode_valid = dw_hdmi_rockchip_mode_valid,
464 .mpll_cfg = rockchip_mpll_cfg,
465 .cur_ctr = rockchip_cur_ctr,
466 .phy_config = rockchip_phy_config,
467 .phy_data = &rk3399_chip_data,
470 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
471 { .compatible = "rockchip,rk3228-dw-hdmi",
472 .data = &rk3228_hdmi_drv_data
474 { .compatible = "rockchip,rk3288-dw-hdmi",
475 .data = &rk3288_hdmi_drv_data
477 { .compatible = "rockchip,rk3328-dw-hdmi",
478 .data = &rk3328_hdmi_drv_data
480 { .compatible = "rockchip,rk3399-dw-hdmi",
481 .data = &rk3399_hdmi_drv_data
485 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
487 static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
490 struct platform_device *pdev = to_platform_device(dev);
491 struct dw_hdmi_plat_data *plat_data;
492 const struct of_device_id *match;
493 struct drm_device *drm = data;
494 struct drm_encoder *encoder;
495 struct rockchip_hdmi *hdmi;
498 if (!pdev->dev.of_node)
501 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
505 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
506 plat_data = devm_kmemdup(&pdev->dev, match->data,
507 sizeof(*plat_data), GFP_KERNEL);
511 hdmi->dev = &pdev->dev;
512 hdmi->chip_data = plat_data->phy_data;
513 plat_data->phy_data = hdmi;
514 encoder = &hdmi->encoder;
516 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
518 * If we failed to find the CRTC(s) which this encoder is
519 * supposed to be connected to, it's because the CRTC has
520 * not been registered yet. Defer probing, and hope that
521 * the required CRTC is added later.
523 if (encoder->possible_crtcs == 0)
524 return -EPROBE_DEFER;
526 ret = rockchip_hdmi_parse_dt(hdmi);
528 DRM_DEV_ERROR(hdmi->dev, "Unable to parse OF data\n");
532 ret = clk_prepare_enable(hdmi->vpll_clk);
534 DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
539 hdmi->phy = devm_phy_optional_get(dev, "hdmi");
540 if (IS_ERR(hdmi->phy)) {
541 ret = PTR_ERR(hdmi->phy);
542 if (ret != -EPROBE_DEFER)
543 DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n");
547 drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
548 drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs,
549 DRM_MODE_ENCODER_TMDS, NULL);
551 platform_set_drvdata(pdev, hdmi);
553 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
556 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
557 * which would have called the encoder cleanup. Do it manually.
559 if (IS_ERR(hdmi->hdmi)) {
560 ret = PTR_ERR(hdmi->hdmi);
561 drm_encoder_cleanup(encoder);
562 clk_disable_unprepare(hdmi->vpll_clk);
568 static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
571 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
573 dw_hdmi_unbind(hdmi->hdmi);
574 clk_disable_unprepare(hdmi->vpll_clk);
577 static const struct component_ops dw_hdmi_rockchip_ops = {
578 .bind = dw_hdmi_rockchip_bind,
579 .unbind = dw_hdmi_rockchip_unbind,
582 static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
584 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
587 static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
589 component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
594 static int __maybe_unused dw_hdmi_rockchip_resume(struct device *dev)
596 struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
598 dw_hdmi_resume(hdmi->hdmi);
603 static const struct dev_pm_ops dw_hdmi_rockchip_pm = {
604 SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_rockchip_resume)
607 struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
608 .probe = dw_hdmi_rockchip_probe,
609 .remove = dw_hdmi_rockchip_remove,
611 .name = "dwhdmi-rockchip",
612 .pm = &dw_hdmi_rockchip_pm,
613 .of_match_table = dw_hdmi_rockchip_dt_ids,