drivers/gpu/drm/tegra/dpaux.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/gpio.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/pinctrl/pinconf-generic.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/workqueue.h>
  22
  23 #include <drm/drm_dp_helper.h>
  24 #include <drm/drm_panel.h>
  25
  26 #include "dp.h"
  27 #include "dpaux.h"
  28 #include "drm.h"
  29 #include "trace.h"
  30
  31 static DEFINE_MUTEX(dpaux_lock);
  32 static LIST_HEAD(dpaux_list);
  33
  34 struct tegra_dpaux_soc {
  35         unsigned int cmh;
  36         unsigned int drvz;
  37         unsigned int drvi;
  38 };
  39
  40 struct tegra_dpaux {
  41         struct drm_dp_aux aux;
  42         struct device *dev;
  43
  44         const struct tegra_dpaux_soc *soc;
  45
  46         void __iomem *regs;
  47         int irq;
  48
  49         struct tegra_output *output;
  50
  51         struct reset_control *rst;
  52         struct clk *clk_parent;
  53         struct clk *clk;
  54
  55         struct regulator *vdd;
  56
  57         struct completion complete;
  58         struct work_struct work;
  59         struct list_head list;
  60
  61 #ifdef CONFIG_GENERIC_PINCONF
  62         struct pinctrl_dev *pinctrl;
  63         struct pinctrl_desc desc;
  64 #endif
  65 };
  66
  67 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
  68 {
  69         return container_of(aux, struct tegra_dpaux, aux);
  70 }
  71
  72 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
  73 {
  74         return container_of(work, struct tegra_dpaux, work);
  75 }
  76
  77 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux,
  78                                     unsigned int offset)
  79 {
  80         u32 value = readl(dpaux->regs + (offset << 2));
  81
  82         trace_dpaux_readl(dpaux->dev, offset, value);
  83
  84         return value;
  85 }
  86
  87 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
  88                                       u32 value, unsigned int offset)
  89 {
  90         trace_dpaux_writel(dpaux->dev, offset, value);
  91         writel(value, dpaux->regs + (offset << 2));
  92 }
  93
  94 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
  95                                    size_t size)
  96 {
  97         size_t i, j;
  98
  99         for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
 100                 size_t num = min_t(size_t, size - i * 4, 4);
 101                 u32 value = 0;
 102
 103                 for (j = 0; j < num; j++)
 104                         value |= buffer[i * 4 + j] << (j * 8);
 105
 106                 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
 107         }
 108 }
 109
 110 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
 111                                   size_t size)
 112 {
 113         size_t i, j;
 114
 115         for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
 116                 size_t num = min_t(size_t, size - i * 4, 4);
 117                 u32 value;
 118
 119                 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
 120
 121                 for (j = 0; j < num; j++)
 122                         buffer[i * 4 + j] = value >> (j * 8);
 123         }
 124 }
 125
 126 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
 127                                     struct drm_dp_aux_msg *msg)
 128 {
 129         unsigned long timeout = msecs_to_jiffies(250);
 130         struct tegra_dpaux *dpaux = to_dpaux(aux);
 131         unsigned long status;
 132         ssize_t ret = 0;
 133         u8 reply = 0;
 134         u32 value;
 135
 136         /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
 137         if (msg->size > 16)
 138                 return -EINVAL;
 139
 140         /*
 141          * Allow zero-sized messages only for I2C, in which case they specify
 142          * address-only transactions.
 143          */
 144         if (msg->size < 1) {
 145                 switch (msg->request & ~DP_AUX_I2C_MOT) {
 146                 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 147                 case DP_AUX_I2C_WRITE:
 148                 case DP_AUX_I2C_READ:
 149                         value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
 150                         break;
 151
 152                 default:
 153                         return -EINVAL;
 154                 }
 155         } else {
 156                 /* For non-zero-sized messages, set the CMDLEN field. */
 157                 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
 158         }
 159
 160         switch (msg->request & ~DP_AUX_I2C_MOT) {
 161         case DP_AUX_I2C_WRITE:
 162                 if (msg->request & DP_AUX_I2C_MOT)
 163                         value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
 164                 else
 165                         value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
 166
 167                 break;
 168
 169         case DP_AUX_I2C_READ:
 170                 if (msg->request & DP_AUX_I2C_MOT)
 171                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
 172                 else
 173                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
 174
 175                 break;
 176
 177         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 178                 if (msg->request & DP_AUX_I2C_MOT)
 179                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
 180                 else
 181                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
 182
 183                 break;
 184
 185         case DP_AUX_NATIVE_WRITE:
 186                 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
 187                 break;
 188
 189         case DP_AUX_NATIVE_READ:
 190                 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
 191                 break;
 192
 193         default:
 194                 return -EINVAL;
 195         }
 196
 197         tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
 198         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 199
 200         if ((msg->request & DP_AUX_I2C_READ) == 0) {
 201                 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
 202                 ret = msg->size;
 203         }
 204
 205         /* start transaction */
 206         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
 207         value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
 208         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 209
 210         status = wait_for_completion_timeout(&dpaux->complete, timeout);
 211         if (!status)
 212                 return -ETIMEDOUT;
 213
 214         /* read status and clear errors */
 215         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 216         tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
 217
 218         if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
 219                 return -ETIMEDOUT;
 220
 221         if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
 222             (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
 223             (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
 224                 return -EIO;
 225
 226         switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
 227         case 0x00:
 228                 reply = DP_AUX_NATIVE_REPLY_ACK;
 229                 break;
 230
 231         case 0x01:
 232                 reply = DP_AUX_NATIVE_REPLY_NACK;
 233                 break;
 234
 235         case 0x02:
 236                 reply = DP_AUX_NATIVE_REPLY_DEFER;
 237                 break;
 238
 239         case 0x04:
 240                 reply = DP_AUX_I2C_REPLY_NACK;
 241                 break;
 242
 243         case 0x08:
 244                 reply = DP_AUX_I2C_REPLY_DEFER;
 245                 break;
 246         }
 247
 248         if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
 249                 if (msg->request & DP_AUX_I2C_READ) {
 250                         size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
 251
 252                         /*
 253                          * There might be a smarter way to do this, but since
 254                          * the DP helpers will already retry transactions for
 255                          * an -EBUSY return value, simply reuse that instead.
 256                          */
 257                         if (count != msg->size) {
 258                                 ret = -EBUSY;
 259                                 goto out;
 260                         }
 261
 262                         tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
 263                         ret = count;
 264                 }
 265         }
 266
 267         msg->reply = reply;
 268
 269 out:
 270         return ret;
 271 }
 272
 273 static void tegra_dpaux_hotplug(struct work_struct *work)
 274 {
 275         struct tegra_dpaux *dpaux = work_to_dpaux(work);
 276
 277         if (dpaux->output)
 278                 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
 279 }
 280
 281 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
 282 {
 283         struct tegra_dpaux *dpaux = data;
 284         irqreturn_t ret = IRQ_HANDLED;
 285         u32 value;
 286
 287         /* clear interrupts */
 288         value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
 289         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 290
 291         if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
 292                 schedule_work(&dpaux->work);
 293
 294         if (value & DPAUX_INTR_IRQ_EVENT) {
 295                 /* TODO: handle this */
 296         }
 297
 298         if (value & DPAUX_INTR_AUX_DONE)
 299                 complete(&dpaux->complete);
 300
 301         return ret;
 302 }
 303
 304 enum tegra_dpaux_functions {
 305         DPAUX_PADCTL_FUNC_AUX,
 306         DPAUX_PADCTL_FUNC_I2C,
 307         DPAUX_PADCTL_FUNC_OFF,
 308 };
 309
 310 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux)
 311 {
 312         u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 313
 314         value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 315
 316         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 317 }
 318
 319 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux)
 320 {
 321         u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 322
 323         value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 324
 325         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 326 }
 327
 328 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function)
 329 {
 330         u32 value;
 331
 332         switch (function) {
 333         case DPAUX_PADCTL_FUNC_AUX:
 334                 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
 335                         DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
 336                         DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
 337                         DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
 338                         DPAUX_HYBRID_PADCTL_MODE_AUX;
 339                 break;
 340
 341         case DPAUX_PADCTL_FUNC_I2C:
 342                 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV |
 343                         DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
 344                         DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) |
 345                         DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) |
 346                         DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) |
 347                         DPAUX_HYBRID_PADCTL_MODE_I2C;
 348                 break;
 349
 350         case DPAUX_PADCTL_FUNC_OFF:
 351                 tegra_dpaux_pad_power_down(dpaux);
 352                 return 0;
 353
 354         default:
 355                 return -ENOTSUPP;
 356         }
 357
 358         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
 359         tegra_dpaux_pad_power_up(dpaux);
 360
 361         return 0;
 362 }
 363
 364 #ifdef CONFIG_GENERIC_PINCONF
 365 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = {
 366         PINCTRL_PIN(0, "DP_AUX_CHx_P"),
 367         PINCTRL_PIN(1, "DP_AUX_CHx_N"),
 368 };
 369
 370 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 };
 371
 372 static const char * const tegra_dpaux_groups[] = {
 373         "dpaux-io",
 374 };
 375
 376 static const char * const tegra_dpaux_functions[] = {
 377         "aux",
 378         "i2c",
 379         "off",
 380 };
 381
 382 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl)
 383 {
 384         return ARRAY_SIZE(tegra_dpaux_groups);
 385 }
 386
 387 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl,
 388                                               unsigned int group)
 389 {
 390         return tegra_dpaux_groups[group];
 391 }
 392
 393 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl,
 394                                       unsigned group, const unsigned **pins,
 395                                       unsigned *num_pins)
 396 {
 397         *pins = tegra_dpaux_pin_numbers;
 398         *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers);
 399
 400         return 0;
 401 }
 402
 403 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = {
 404         .get_groups_count = tegra_dpaux_get_groups_count,
 405         .get_group_name = tegra_dpaux_get_group_name,
 406         .get_group_pins = tegra_dpaux_get_group_pins,
 407         .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
 408         .dt_free_map = pinconf_generic_dt_free_map,
 409 };
 410
 411 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl)
 412 {
 413         return ARRAY_SIZE(tegra_dpaux_functions);
 414 }
 415
 416 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl,
 417                                                  unsigned int function)
 418 {
 419         return tegra_dpaux_functions[function];
 420 }
 421
 422 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl,
 423                                            unsigned int function,
 424                                            const char * const **groups,
 425                                            unsigned * const num_groups)
 426 {
 427         *num_groups = ARRAY_SIZE(tegra_dpaux_groups);
 428         *groups = tegra_dpaux_groups;
 429
 430         return 0;
 431 }
 432
 433 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl,
 434                                unsigned int function, unsigned int group)
 435 {
 436         struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl);
 437
 438         return tegra_dpaux_pad_config(dpaux, function);
 439 }
 440
 441 static const struct pinmux_ops tegra_dpaux_pinmux_ops = {
 442         .get_functions_count = tegra_dpaux_get_functions_count,
 443         .get_function_name = tegra_dpaux_get_function_name,
 444         .get_function_groups = tegra_dpaux_get_function_groups,
 445         .set_mux = tegra_dpaux_set_mux,
 446 };
 447 #endif
 448
 449 static int tegra_dpaux_probe(struct platform_device *pdev)
 450 {
 451         struct tegra_dpaux *dpaux;
 452         struct resource *regs;
 453         u32 value;
 454         int err;
 455
 456         dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
 457         if (!dpaux)
 458                 return -ENOMEM;
 459
 460         dpaux->soc = of_device_get_match_data(&pdev->dev);
 461         INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
 462         init_completion(&dpaux->complete);
 463         INIT_LIST_HEAD(&dpaux->list);
 464         dpaux->dev = &pdev->dev;
 465
 466         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 467         dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
 468         if (IS_ERR(dpaux->regs))
 469                 return PTR_ERR(dpaux->regs);
 470
 471         dpaux->irq = platform_get_irq(pdev, 0);
 472         if (dpaux->irq < 0) {
 473                 dev_err(&pdev->dev, "failed to get IRQ\n");
 474                 return -ENXIO;
 475         }
 476
 477         if (!pdev->dev.pm_domain) {
 478                 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
 479                 if (IS_ERR(dpaux->rst)) {
 480                         dev_err(&pdev->dev,
 481                                 "failed to get reset control: %ld\n",
 482                                 PTR_ERR(dpaux->rst));
 483                         return PTR_ERR(dpaux->rst);
 484                 }
 485         }
 486
 487         dpaux->clk = devm_clk_get(&pdev->dev, NULL);
 488         if (IS_ERR(dpaux->clk)) {
 489                 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
 490                         PTR_ERR(dpaux->clk));
 491                 return PTR_ERR(dpaux->clk);
 492         }
 493
 494         dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
 495         if (IS_ERR(dpaux->clk_parent)) {
 496                 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
 497                         PTR_ERR(dpaux->clk_parent));
 498                 return PTR_ERR(dpaux->clk_parent);
 499         }
 500
 501         err = clk_set_rate(dpaux->clk_parent, 270000000);
 502         if (err < 0) {
 503                 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
 504                         err);
 505                 return err;
 506         }
 507
 508         dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
 509         if (IS_ERR(dpaux->vdd)) {
 510                 if (PTR_ERR(dpaux->vdd) != -ENODEV) {
 511                         if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER)
 512                                 dev_err(&pdev->dev,
 513                                         "failed to get VDD supply: %ld\n",
 514                                         PTR_ERR(dpaux->vdd));
 515
 516                         return PTR_ERR(dpaux->vdd);
 517                 }
 518
 519                 dpaux->vdd = NULL;
 520         }
 521
 522         platform_set_drvdata(pdev, dpaux);
 523         pm_runtime_enable(&pdev->dev);
 524         pm_runtime_get_sync(&pdev->dev);
 525
 526         err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
 527                                dev_name(dpaux->dev), dpaux);
 528         if (err < 0) {
 529                 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
 530                         dpaux->irq, err);
 531                 return err;
 532         }
 533
 534         disable_irq(dpaux->irq);
 535
 536         dpaux->aux.transfer = tegra_dpaux_transfer;
 537         dpaux->aux.dev = &pdev->dev;
 538
 539         err = drm_dp_aux_register(&dpaux->aux);
 540         if (err < 0)
 541                 return err;
 542
 543         /*
 544          * Assume that by default the DPAUX/I2C pads will be used for HDMI,
 545          * so power them up and configure them in I2C mode.
 546          *
 547          * The DPAUX code paths reconfigure the pads in AUX mode, but there
 548          * is no possibility to perform the I2C mode configuration in the
 549          * HDMI path.
 550          */
 551         err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C);
 552         if (err < 0)
 553                 return err;
 554
 555 #ifdef CONFIG_GENERIC_PINCONF
 556         dpaux->desc.name = dev_name(&pdev->dev);
 557         dpaux->desc.pins = tegra_dpaux_pins;
 558         dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins);
 559         dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops;
 560         dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops;
 561         dpaux->desc.owner = THIS_MODULE;
 562
 563         dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux);
 564         if (IS_ERR(dpaux->pinctrl)) {
 565                 dev_err(&pdev->dev, "failed to register pincontrol\n");
 566                 return PTR_ERR(dpaux->pinctrl);
 567         }
 568 #endif
 569         /* enable and clear all interrupts */
 570         value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
 571                 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
 572         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
 573         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 574
 575         mutex_lock(&dpaux_lock);
 576         list_add_tail(&dpaux->list, &dpaux_list);
 577         mutex_unlock(&dpaux_lock);
 578
 579         return 0;
 580 }
 581
 582 static int tegra_dpaux_remove(struct platform_device *pdev)
 583 {
 584         struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
 585
 586         cancel_work_sync(&dpaux->work);
 587
 588         /* make sure pads are powered down when not in use */
 589         tegra_dpaux_pad_power_down(dpaux);
 590
 591         pm_runtime_put(&pdev->dev);
 592         pm_runtime_disable(&pdev->dev);
 593
 594         drm_dp_aux_unregister(&dpaux->aux);
 595
 596         mutex_lock(&dpaux_lock);
 597         list_del(&dpaux->list);
 598         mutex_unlock(&dpaux_lock);
 599
 600         return 0;
 601 }
 602
 603 #ifdef CONFIG_PM
 604 static int tegra_dpaux_suspend(struct device *dev)
 605 {
 606         struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
 607         int err = 0;
 608
 609         if (dpaux->rst) {
 610                 err = reset_control_assert(dpaux->rst);
 611                 if (err < 0) {
 612                         dev_err(dev, "failed to assert reset: %d\n", err);
 613                         return err;
 614                 }
 615         }
 616
 617         usleep_range(1000, 2000);
 618
 619         clk_disable_unprepare(dpaux->clk_parent);
 620         clk_disable_unprepare(dpaux->clk);
 621
 622         return err;
 623 }
 624
 625 static int tegra_dpaux_resume(struct device *dev)
 626 {
 627         struct tegra_dpaux *dpaux = dev_get_drvdata(dev);
 628         int err;
 629
 630         err = clk_prepare_enable(dpaux->clk);
 631         if (err < 0) {
 632                 dev_err(dev, "failed to enable clock: %d\n", err);
 633                 return err;
 634         }
 635
 636         err = clk_prepare_enable(dpaux->clk_parent);
 637         if (err < 0) {
 638                 dev_err(dev, "failed to enable parent clock: %d\n", err);
 639                 goto disable_clk;
 640         }
 641
 642         usleep_range(1000, 2000);
 643
 644         if (dpaux->rst) {
 645                 err = reset_control_deassert(dpaux->rst);
 646                 if (err < 0) {
 647                         dev_err(dev, "failed to deassert reset: %d\n", err);
 648                         goto disable_parent;
 649                 }
 650
 651                 usleep_range(1000, 2000);
 652         }
 653
 654         return 0;
 655
 656 disable_parent:
 657         clk_disable_unprepare(dpaux->clk_parent);
 658 disable_clk:
 659         clk_disable_unprepare(dpaux->clk);
 660         return err;
 661 }
 662 #endif
 663
 664 static const struct dev_pm_ops tegra_dpaux_pm_ops = {
 665         SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL)
 666 };
 667
 668 static const struct tegra_dpaux_soc tegra124_dpaux_soc = {
 669         .cmh = 0x02,
 670         .drvz = 0x04,
 671         .drvi = 0x18,
 672 };
 673
 674 static const struct tegra_dpaux_soc tegra210_dpaux_soc = {
 675         .cmh = 0x02,
 676         .drvz = 0x04,
 677         .drvi = 0x30,
 678 };
 679
 680 static const struct tegra_dpaux_soc tegra194_dpaux_soc = {
 681         .cmh = 0x02,
 682         .drvz = 0x04,
 683         .drvi = 0x2c,
 684 };
 685
 686 static const struct of_device_id tegra_dpaux_of_match[] = {
 687         { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
 688         { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
 689         { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
 690         { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
 691         { },
 692 };
 693 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
 694
 695 struct platform_driver tegra_dpaux_driver = {
 696         .driver = {
 697                 .name = "tegra-dpaux",
 698                 .of_match_table = tegra_dpaux_of_match,
 699                 .pm = &tegra_dpaux_pm_ops,
 700         },
 701         .probe = tegra_dpaux_probe,
 702         .remove = tegra_dpaux_remove,
 703 };
 704
 705 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np)
 706 {
 707         struct tegra_dpaux *dpaux;
 708
 709         mutex_lock(&dpaux_lock);
 710
 711         list_for_each_entry(dpaux, &dpaux_list, list)
 712                 if (np == dpaux->dev->of_node) {
 713                         mutex_unlock(&dpaux_lock);
 714                         return &dpaux->aux;
 715                 }
 716
 717         mutex_unlock(&dpaux_lock);
 718
 719         return NULL;
 720 }
 721
 722 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output)
 723 {
 724         struct tegra_dpaux *dpaux = to_dpaux(aux);
 725         unsigned long timeout;
 726         int err;
 727
 728         output->connector.polled = DRM_CONNECTOR_POLL_HPD;
 729         dpaux->output = output;
 730
 731         if (output->panel) {
 732                 enum drm_connector_status status;
 733
 734                 if (dpaux->vdd) {
 735                         err = regulator_enable(dpaux->vdd);
 736                         if (err < 0)
 737                                 return err;
 738                 }
 739
 740                 timeout = jiffies + msecs_to_jiffies(250);
 741
 742                 while (time_before(jiffies, timeout)) {
 743                         status = drm_dp_aux_detect(aux);
 744
 745                         if (status == connector_status_connected)
 746                                 break;
 747
 748                         usleep_range(1000, 2000);
 749                 }
 750
 751                 if (status != connector_status_connected)
 752                         return -ETIMEDOUT;
 753         }
 754
 755         enable_irq(dpaux->irq);
 756         return 0;
 757 }
 758
 759 int drm_dp_aux_detach(struct drm_dp_aux *aux)
 760 {
 761         struct tegra_dpaux *dpaux = to_dpaux(aux);
 762         unsigned long timeout;
 763         int err;
 764
 765         disable_irq(dpaux->irq);
 766
 767         if (dpaux->output->panel) {
 768                 enum drm_connector_status status;
 769
 770                 if (dpaux->vdd) {
 771                         err = regulator_disable(dpaux->vdd);
 772                         if (err < 0)
 773                                 return err;
 774                 }
 775
 776                 timeout = jiffies + msecs_to_jiffies(250);
 777
 778                 while (time_before(jiffies, timeout)) {
 779                         status = drm_dp_aux_detect(aux);
 780
 781                         if (status == connector_status_disconnected)
 782                                 break;
 783
 784                         usleep_range(1000, 2000);
 785                 }
 786
 787                 if (status != connector_status_disconnected)
 788                         return -ETIMEDOUT;
 789
 790                 dpaux->output = NULL;
 791         }
 792
 793         return 0;
 794 }
 795
 796 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux)
 797 {
 798         struct tegra_dpaux *dpaux = to_dpaux(aux);
 799         u32 value;
 800
 801         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 802
 803         if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
 804                 return connector_status_connected;
 805
 806         return connector_status_disconnected;
 807 }
 808
 809 int drm_dp_aux_enable(struct drm_dp_aux *aux)
 810 {
 811         struct tegra_dpaux *dpaux = to_dpaux(aux);
 812
 813         return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX);
 814 }
 815
 816 int drm_dp_aux_disable(struct drm_dp_aux *aux)
 817 {
 818         struct tegra_dpaux *dpaux = to_dpaux(aux);
 819
 820         tegra_dpaux_pad_power_down(dpaux);
 821
 822         return 0;
 823 }
 824
 825 int drm_dp_aux_prepare(struct drm_dp_aux *aux, u8 encoding)
 826 {
 827         int err;
 828
 829         err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 830                                  encoding);
 831         if (err < 0)
 832                 return err;
 833
 834         return 0;
 835 }
 836
 837 int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link,
 838                      u8 pattern)
 839 {
 840         u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
 841         u8 status[DP_LINK_STATUS_SIZE], values[4];
 842         unsigned int i;
 843         int err;
 844
 845         err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);
 846         if (err < 0)
 847                 return err;
 848
 849         if (tp == DP_TRAINING_PATTERN_DISABLE)
 850                 return 0;
 851
 852         for (i = 0; i < link->num_lanes; i++)
 853                 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
 854                             DP_TRAIN_PRE_EMPH_LEVEL_0 |
 855                             DP_TRAIN_MAX_SWING_REACHED |
 856                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 857
 858         err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values,
 859                                 link->num_lanes);
 860         if (err < 0)
 861                 return err;
 862
 863         usleep_range(500, 1000);
 864
 865         err = drm_dp_dpcd_read_link_status(aux, status);
 866         if (err < 0)
 867                 return err;
 868
 869         switch (tp) {
 870         case DP_TRAINING_PATTERN_1:
 871                 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
 872                         return -EAGAIN;
 873
 874                 break;
 875
 876         case DP_TRAINING_PATTERN_2:
 877                 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
 878                         return -EAGAIN;
 879
 880                 break;
 881
 882         default:
 883                 dev_err(aux->dev, "unsupported training pattern %u\n", tp);
 884                 return -EINVAL;
 885         }
 886
 887         err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, 0);
 888         if (err < 0)
 889                 return err;
 890
 891         return 0;
 892 }