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drm/tegra: gr2d: Add IOMMU support
[linux.git] / drivers / gpu / drm / tegra / gr2d.c
1 /*
2  * Copyright (c) 2012-2013, NVIDIA Corporation.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 #include <linux/clk.h>
10 #include <linux/iommu.h>
11
12 #include "drm.h"
13 #include "gem.h"
14 #include "gr2d.h"
15
16 struct gr2d {
17         struct iommu_group *group;
18         struct tegra_drm_client client;
19         struct host1x_channel *channel;
20         struct clk *clk;
21
22         DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS);
23 };
24
25 static inline struct gr2d *to_gr2d(struct tegra_drm_client *client)
26 {
27         return container_of(client, struct gr2d, client);
28 }
29
30 static int gr2d_init(struct host1x_client *client)
31 {
32         struct tegra_drm_client *drm = host1x_to_drm_client(client);
33         struct drm_device *dev = dev_get_drvdata(client->parent);
34         unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
35         struct tegra_drm *tegra = dev->dev_private;
36         struct gr2d *gr2d = to_gr2d(drm);
37         int err;
38
39         gr2d->channel = host1x_channel_request(client->dev);
40         if (!gr2d->channel)
41                 return -ENOMEM;
42
43         client->syncpts[0] = host1x_syncpt_request(client, flags);
44         if (!client->syncpts[0]) {
45                 host1x_channel_put(gr2d->channel);
46                 return -ENOMEM;
47         }
48
49         if (tegra->domain) {
50                 gr2d->group = iommu_group_get(client->dev);
51
52                 if (gr2d->group) {
53                         err = iommu_attach_group(tegra->domain, gr2d->group);
54                         if (err < 0) {
55                                 dev_err(client->dev,
56                                         "failed to attach to domain: %d\n",
57                                         err);
58                                 host1x_syncpt_free(client->syncpts[0]);
59                                 host1x_channel_put(gr2d->channel);
60                                 iommu_group_put(gr2d->group);
61                                 return err;
62                         }
63                 }
64         }
65
66         return tegra_drm_register_client(tegra, drm);
67 }
68
69 static int gr2d_exit(struct host1x_client *client)
70 {
71         struct tegra_drm_client *drm = host1x_to_drm_client(client);
72         struct drm_device *dev = dev_get_drvdata(client->parent);
73         struct tegra_drm *tegra = dev->dev_private;
74         struct gr2d *gr2d = to_gr2d(drm);
75         int err;
76
77         err = tegra_drm_unregister_client(tegra, drm);
78         if (err < 0)
79                 return err;
80
81         host1x_syncpt_free(client->syncpts[0]);
82         host1x_channel_put(gr2d->channel);
83
84         if (gr2d->group) {
85                 iommu_detach_group(tegra->domain, gr2d->group);
86                 iommu_group_put(gr2d->group);
87         }
88
89         return 0;
90 }
91
92 static const struct host1x_client_ops gr2d_client_ops = {
93         .init = gr2d_init,
94         .exit = gr2d_exit,
95 };
96
97 static int gr2d_open_channel(struct tegra_drm_client *client,
98                              struct tegra_drm_context *context)
99 {
100         struct gr2d *gr2d = to_gr2d(client);
101
102         context->channel = host1x_channel_get(gr2d->channel);
103         if (!context->channel)
104                 return -ENOMEM;
105
106         return 0;
107 }
108
109 static void gr2d_close_channel(struct tegra_drm_context *context)
110 {
111         host1x_channel_put(context->channel);
112 }
113
114 static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset)
115 {
116         struct gr2d *gr2d = dev_get_drvdata(dev);
117
118         switch (class) {
119         case HOST1X_CLASS_HOST1X:
120                 if (offset == 0x2b)
121                         return 1;
122
123                 break;
124
125         case HOST1X_CLASS_GR2D:
126         case HOST1X_CLASS_GR2D_SB:
127                 if (offset >= GR2D_NUM_REGS)
128                         break;
129
130                 if (test_bit(offset, gr2d->addr_regs))
131                         return 1;
132
133                 break;
134         }
135
136         return 0;
137 }
138
139 static int gr2d_is_valid_class(u32 class)
140 {
141         return (class == HOST1X_CLASS_GR2D ||
142                 class == HOST1X_CLASS_GR2D_SB);
143 }
144
145 static const struct tegra_drm_client_ops gr2d_ops = {
146         .open_channel = gr2d_open_channel,
147         .close_channel = gr2d_close_channel,
148         .is_addr_reg = gr2d_is_addr_reg,
149         .is_valid_class = gr2d_is_valid_class,
150         .submit = tegra_drm_submit,
151 };
152
153 static const struct of_device_id gr2d_match[] = {
154         { .compatible = "nvidia,tegra30-gr2d" },
155         { .compatible = "nvidia,tegra20-gr2d" },
156         { },
157 };
158 MODULE_DEVICE_TABLE(of, gr2d_match);
159
160 static const u32 gr2d_addr_regs[] = {
161         GR2D_UA_BASE_ADDR,
162         GR2D_VA_BASE_ADDR,
163         GR2D_PAT_BASE_ADDR,
164         GR2D_DSTA_BASE_ADDR,
165         GR2D_DSTB_BASE_ADDR,
166         GR2D_DSTC_BASE_ADDR,
167         GR2D_SRCA_BASE_ADDR,
168         GR2D_SRCB_BASE_ADDR,
169         GR2D_SRC_BASE_ADDR_SB,
170         GR2D_DSTA_BASE_ADDR_SB,
171         GR2D_DSTB_BASE_ADDR_SB,
172         GR2D_UA_BASE_ADDR_SB,
173         GR2D_VA_BASE_ADDR_SB,
174 };
175
176 static int gr2d_probe(struct platform_device *pdev)
177 {
178         struct device *dev = &pdev->dev;
179         struct host1x_syncpt **syncpts;
180         struct gr2d *gr2d;
181         unsigned int i;
182         int err;
183
184         gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL);
185         if (!gr2d)
186                 return -ENOMEM;
187
188         syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
189         if (!syncpts)
190                 return -ENOMEM;
191
192         gr2d->clk = devm_clk_get(dev, NULL);
193         if (IS_ERR(gr2d->clk)) {
194                 dev_err(dev, "cannot get clock\n");
195                 return PTR_ERR(gr2d->clk);
196         }
197
198         err = clk_prepare_enable(gr2d->clk);
199         if (err) {
200                 dev_err(dev, "cannot turn on clock\n");
201                 return err;
202         }
203
204         INIT_LIST_HEAD(&gr2d->client.base.list);
205         gr2d->client.base.ops = &gr2d_client_ops;
206         gr2d->client.base.dev = dev;
207         gr2d->client.base.class = HOST1X_CLASS_GR2D;
208         gr2d->client.base.syncpts = syncpts;
209         gr2d->client.base.num_syncpts = 1;
210
211         INIT_LIST_HEAD(&gr2d->client.list);
212         gr2d->client.ops = &gr2d_ops;
213
214         err = host1x_client_register(&gr2d->client.base);
215         if (err < 0) {
216                 dev_err(dev, "failed to register host1x client: %d\n", err);
217                 clk_disable_unprepare(gr2d->clk);
218                 return err;
219         }
220
221         /* initialize address register map */
222         for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++)
223                 set_bit(gr2d_addr_regs[i], gr2d->addr_regs);
224
225         platform_set_drvdata(pdev, gr2d);
226
227         return 0;
228 }
229
230 static int gr2d_remove(struct platform_device *pdev)
231 {
232         struct gr2d *gr2d = platform_get_drvdata(pdev);
233         int err;
234
235         err = host1x_client_unregister(&gr2d->client.base);
236         if (err < 0) {
237                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
238                         err);
239                 return err;
240         }
241
242         clk_disable_unprepare(gr2d->clk);
243
244         return 0;
245 }
246
247 struct platform_driver tegra_gr2d_driver = {
248         .driver = {
249                 .name = "tegra-gr2d",
250                 .of_match_table = gr2d_match,
251         },
252         .probe = gr2d_probe,
253         .remove = gr2d_remove,
254 };