drivers/gpu/drm/tegra/hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Avionic Design GmbH
   4  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/delay.h>
  10 #include <linux/gpio.h>
  11 #include <linux/hdmi.h>
  12 #include <linux/math64.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/reset.h>
  18
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_file.h>
  23 #include <drm/drm_fourcc.h>
  24 #include <drm/drm_probe_helper.h>
  25
  26 #include "hda.h"
  27 #include "hdmi.h"
  28 #include "drm.h"
  29 #include "dc.h"
  30 #include "trace.h"
  31
  32 #define HDMI_ELD_BUFFER_SIZE 96
  33
  34 struct tmds_config {
  35         unsigned int pclk;
  36         u32 pll0;
  37         u32 pll1;
  38         u32 pe_current;
  39         u32 drive_current;
  40         u32 peak_current;
  41 };
  42
  43 struct tegra_hdmi_config {
  44         const struct tmds_config *tmds;
  45         unsigned int num_tmds;
  46
  47         unsigned long fuse_override_offset;
  48         u32 fuse_override_value;
  49
  50         bool has_sor_io_peak_current;
  51         bool has_hda;
  52         bool has_hbr;
  53 };
  54
  55 struct tegra_hdmi {
  56         struct host1x_client client;
  57         struct tegra_output output;
  58         struct device *dev;
  59
  60         struct regulator *hdmi;
  61         struct regulator *pll;
  62         struct regulator *vdd;
  63
  64         void __iomem *regs;
  65         unsigned int irq;
  66
  67         struct clk *clk_parent;
  68         struct clk *clk;
  69         struct reset_control *rst;
  70
  71         const struct tegra_hdmi_config *config;
  72
  73         unsigned int audio_source;
  74         struct tegra_hda_format format;
  75
  76         unsigned int pixel_clock;
  77         bool stereo;
  78         bool dvi;
  79
  80         struct drm_info_list *debugfs_files;
  81 };
  82
  83 static inline struct tegra_hdmi *
  84 host1x_client_to_hdmi(struct host1x_client *client)
  85 {
  86         return container_of(client, struct tegra_hdmi, client);
  87 }
  88
  89 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
  90 {
  91         return container_of(output, struct tegra_hdmi, output);
  92 }
  93
  94 #define HDMI_AUDIOCLK_FREQ 216000000
  95 #define HDMI_REKEY_DEFAULT 56
  96
  97 enum {
  98         AUTO = 0,
  99         SPDIF,
 100         HDA,
 101 };
 102
 103 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
 104                                    unsigned int offset)
 105 {
 106         u32 value = readl(hdmi->regs + (offset << 2));
 107
 108         trace_hdmi_readl(hdmi->dev, offset, value);
 109
 110         return value;
 111 }
 112
 113 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
 114                                      unsigned int offset)
 115 {
 116         trace_hdmi_writel(hdmi->dev, offset, value);
 117         writel(value, hdmi->regs + (offset << 2));
 118 }
 119
 120 struct tegra_hdmi_audio_config {
 121         unsigned int n;
 122         unsigned int cts;
 123         unsigned int aval;
 124 };
 125
 126 static const struct tmds_config tegra20_tmds_config[] = {
 127         { /* slow pixel clock modes */
 128                 .pclk = 27000000,
 129                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 130                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 131                         SOR_PLL_TX_REG_LOAD(3),
 132                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 133                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 134                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 135                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 136                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 137                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 138                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 139                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 140                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 141         },
 142         { /* high pixel clock modes */
 143                 .pclk = UINT_MAX,
 144                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 145                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 146                         SOR_PLL_TX_REG_LOAD(3),
 147                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 148                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
 149                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
 150                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
 151                         PE_CURRENT3(PE_CURRENT_6_0_mA),
 152                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
 153                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
 154                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
 155                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
 156         },
 157 };
 158
 159 static const struct tmds_config tegra30_tmds_config[] = {
 160         { /* 480p modes */
 161                 .pclk = 27000000,
 162                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 163                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
 164                         SOR_PLL_TX_REG_LOAD(0),
 165                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
 166                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
 167                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
 168                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
 169                         PE_CURRENT3(PE_CURRENT_0_0_mA),
 170                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 171                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 172                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 173                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 174         }, { /* 720p modes */
 175                 .pclk = 74250000,
 176                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 177                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
 178                         SOR_PLL_TX_REG_LOAD(0),
 179                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 180                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 181                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 182                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 183                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 184                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 185                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 186                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 187                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 188         }, { /* 1080p modes */
 189                 .pclk = UINT_MAX,
 190                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
 191                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
 192                         SOR_PLL_TX_REG_LOAD(0),
 193                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
 194                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
 195                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
 196                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
 197                         PE_CURRENT3(PE_CURRENT_5_0_mA),
 198                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
 199                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
 200                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
 201                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
 202         },
 203 };
 204
 205 static const struct tmds_config tegra114_tmds_config[] = {
 206         { /* 480p/576p / 25.2MHz/27MHz modes */
 207                 .pclk = 27000000,
 208                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 209                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 210                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 211                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 212                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 213                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 214                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 215                 .drive_current =
 216                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 217                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 218                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 219                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 220                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 221                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 222                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 223                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 224         }, { /* 720p / 74.25MHz modes */
 225                 .pclk = 74250000,
 226                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 227                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 228                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 229                         SOR_PLL_TMDS_TERMADJ(0),
 230                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 231                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 232                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 233                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 234                 .drive_current =
 235                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 236                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 237                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 238                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 239                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 240                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 241                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 242                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 243         }, { /* 1080p / 148.5MHz modes */
 244                 .pclk = 148500000,
 245                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 246                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 247                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 248                         SOR_PLL_TMDS_TERMADJ(0),
 249                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 250                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 251                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 252                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 253                 .drive_current =
 254                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 255                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 256                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 257                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 258                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 259                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 260                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 261                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 262         }, { /* 225/297MHz modes */
 263                 .pclk = UINT_MAX,
 264                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 265                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 266                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 267                         | SOR_PLL_TMDS_TERM_ENABLE,
 268                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 269                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 270                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 271                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 272                 .drive_current =
 273                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 274                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 275                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 276                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 277                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 278                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 279                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 280                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 281         },
 282 };
 283
 284 static const struct tmds_config tegra124_tmds_config[] = {
 285         { /* 480p/576p / 25.2MHz/27MHz modes */
 286                 .pclk = 27000000,
 287                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 288                         SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
 289                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
 290                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 291                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 292                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 293                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 294                 .drive_current =
 295                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 296                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 297                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 298                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 299                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 300                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 301                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 302                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 303         }, { /* 720p / 74.25MHz modes */
 304                 .pclk = 74250000,
 305                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 306                         SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
 307                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 308                         SOR_PLL_TMDS_TERMADJ(0),
 309                 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
 310                         PE_CURRENT1(PE_CURRENT_15_mA_T114) |
 311                         PE_CURRENT2(PE_CURRENT_15_mA_T114) |
 312                         PE_CURRENT3(PE_CURRENT_15_mA_T114),
 313                 .drive_current =
 314                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
 315                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
 316                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
 317                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
 318                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 319                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 320                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 321                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 322         }, { /* 1080p / 148.5MHz modes */
 323                 .pclk = 148500000,
 324                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 325                         SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
 326                 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
 327                         SOR_PLL_TMDS_TERMADJ(0),
 328                 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
 329                         PE_CURRENT1(PE_CURRENT_10_mA_T114) |
 330                         PE_CURRENT2(PE_CURRENT_10_mA_T114) |
 331                         PE_CURRENT3(PE_CURRENT_10_mA_T114),
 332                 .drive_current =
 333                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
 334                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
 335                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
 336                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
 337                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
 338                         PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
 339                         PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
 340                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
 341         }, { /* 225/297MHz modes */
 342                 .pclk = UINT_MAX,
 343                 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
 344                         SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
 345                 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
 346                         | SOR_PLL_TMDS_TERM_ENABLE,
 347                 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
 348                         PE_CURRENT1(PE_CURRENT_0_mA_T114) |
 349                         PE_CURRENT2(PE_CURRENT_0_mA_T114) |
 350                         PE_CURRENT3(PE_CURRENT_0_mA_T114),
 351                 .drive_current =
 352                         DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
 353                         DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
 354                         DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
 355                         DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
 356                 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
 357                         PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
 358                         PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
 359                         PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
 360         },
 361 };
 362
 363 static int
 364 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
 365                             struct tegra_hdmi_audio_config *config)
 366 {
 367         const unsigned int afreq = 128 * audio_freq;
 368         const unsigned int min_n = afreq / 1500;
 369         const unsigned int max_n = afreq / 300;
 370         const unsigned int ideal_n = afreq / 1000;
 371         int64_t min_err = (uint64_t)-1 >> 1;
 372         unsigned int min_delta = -1;
 373         int n;
 374
 375         memset(config, 0, sizeof(*config));
 376         config->n = -1;
 377
 378         for (n = min_n; n <= max_n; n++) {
 379                 uint64_t cts_f, aval_f;
 380                 unsigned int delta;
 381                 int64_t cts, err;
 382
 383                 /* compute aval in 48.16 fixed point */
 384                 aval_f = ((int64_t)24000000 << 16) * n;
 385                 do_div(aval_f, afreq);
 386                 /* It should round without any rest */
 387                 if (aval_f & 0xFFFF)
 388                         continue;
 389
 390                 /* Compute cts in 48.16 fixed point */
 391                 cts_f = ((int64_t)pix_clock << 16) * n;
 392                 do_div(cts_f, afreq);
 393                 /* Round it to the nearest integer */
 394                 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
 395
 396                 delta = abs(n - ideal_n);
 397
 398                 /* Compute the absolute error */
 399                 err = abs((int64_t)cts_f - cts);
 400                 if (err < min_err || (err == min_err && delta < min_delta)) {
 401                         config->n = n;
 402                         config->cts = cts >> 16;
 403                         config->aval = aval_f >> 16;
 404                         min_delta = delta;
 405                         min_err = err;
 406                 }
 407         }
 408
 409         return config->n != -1 ? 0 : -EINVAL;
 410 }
 411
 412 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
 413 {
 414         const unsigned int freqs[] = {
 415                 32000, 44100, 48000, 88200, 96000, 176400, 192000
 416         };
 417         unsigned int i;
 418
 419         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 420                 unsigned int f = freqs[i];
 421                 unsigned int eight_half;
 422                 unsigned int delta;
 423                 u32 value;
 424
 425                 if (f > 96000)
 426                         delta = 2;
 427                 else if (f > 48000)
 428                         delta = 6;
 429                 else
 430                         delta = 9;
 431
 432                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 433                 value = AUDIO_FS_LOW(eight_half - delta) |
 434                         AUDIO_FS_HIGH(eight_half + delta);
 435                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
 436         }
 437 }
 438
 439 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
 440 {
 441         static const struct {
 442                 unsigned int sample_rate;
 443                 unsigned int offset;
 444         } regs[] = {
 445                 {  32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
 446                 {  44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
 447                 {  48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
 448                 {  88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
 449                 {  96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
 450                 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
 451                 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
 452         };
 453         unsigned int i;
 454
 455         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 456                 if (regs[i].sample_rate == hdmi->format.sample_rate) {
 457                         tegra_hdmi_writel(hdmi, value, regs[i].offset);
 458                         break;
 459                 }
 460         }
 461 }
 462
 463 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
 464 {
 465         struct tegra_hdmi_audio_config config;
 466         u32 source, value;
 467         int err;
 468
 469         switch (hdmi->audio_source) {
 470         case HDA:
 471                 if (hdmi->config->has_hda)
 472                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
 473                 else
 474                         return -EINVAL;
 475
 476                 break;
 477
 478         case SPDIF:
 479                 if (hdmi->config->has_hda)
 480                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 481                 else
 482                         source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
 483                 break;
 484
 485         default:
 486                 if (hdmi->config->has_hda)
 487                         source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 488                 else
 489                         source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
 490                 break;
 491         }
 492
 493         /*
 494          * Tegra30 and later use a slightly modified version of the register
 495          * layout to accomodate for changes related to supporting HDA as the
 496          * audio input source for HDMI. The source select field has moved to
 497          * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
 498          * per block fields remain in the AUDIO_CNTRL0 register.
 499          */
 500         if (hdmi->config->has_hda) {
 501                 /*
 502                  * Inject null samples into the audio FIFO for every frame in
 503                  * which the codec did not receive any samples. This applies
 504                  * to stereo LPCM only.
 505                  *
 506                  * XXX: This seems to be a remnant of MCP days when this was
 507                  * used to work around issues with monitors not being able to
 508                  * play back system startup sounds early. It is possibly not
 509                  * needed on Linux at all.
 510                  */
 511                 if (hdmi->format.channels == 2)
 512                         value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
 513                 else
 514                         value = 0;
 515
 516                 value |= source;
 517
 518                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
 519         }
 520
 521         /*
 522          * On Tegra20, HDA is not a supported audio source and the source
 523          * select field is part of the AUDIO_CNTRL0 register.
 524          */
 525         value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 526                 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
 527
 528         if (!hdmi->config->has_hda)
 529                 value |= source;
 530
 531         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
 532
 533         /*
 534          * Advertise support for High Bit-Rate on Tegra114 and later.
 535          */
 536         if (hdmi->config->has_hbr) {
 537                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 538                 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
 539                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
 540         }
 541
 542         err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
 543                                           hdmi->pixel_clock, &config);
 544         if (err < 0) {
 545                 dev_err(hdmi->dev,
 546                         "cannot set audio to %u Hz at %u Hz pixel clock\n",
 547                         hdmi->format.sample_rate, hdmi->pixel_clock);
 548                 return err;
 549         }
 550
 551         dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
 552                 hdmi->pixel_clock, config.n, config.cts, config.aval);
 553
 554         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 555
 556         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
 557                 AUDIO_N_VALUE(config.n - 1);
 558         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 559
 560         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
 561                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 562
 563         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
 564                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 565
 566         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
 567         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
 568
 569         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
 570         value &= ~AUDIO_N_RESETF;
 571         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
 572
 573         if (hdmi->config->has_hda)
 574                 tegra_hdmi_write_aval(hdmi, config.aval);
 575
 576         tegra_hdmi_setup_audio_fs_tables(hdmi);
 577
 578         return 0;
 579 }
 580
 581 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
 582 {
 583         u32 value;
 584
 585         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 586         value &= ~GENERIC_CTRL_AUDIO;
 587         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 588 }
 589
 590 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
 591 {
 592         u32 value;
 593
 594         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 595         value |= GENERIC_CTRL_AUDIO;
 596         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 597 }
 598
 599 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
 600 {
 601         size_t length = drm_eld_size(hdmi->output.connector.eld), i;
 602         u32 value;
 603
 604         for (i = 0; i < length; i++)
 605                 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
 606                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 607
 608         /*
 609          * The HDA codec will always report an ELD buffer size of 96 bytes and
 610          * the HDA codec driver will check that each byte read from the buffer
 611          * is valid. Therefore every byte must be written, even if no 96 bytes
 612          * were parsed from EDID.
 613          */
 614         for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
 615                 tegra_hdmi_writel(hdmi, i << 8 | 0,
 616                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
 617
 618         value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
 619         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 620 }
 621
 622 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
 623 {
 624         u32 value = 0;
 625         size_t i;
 626
 627         for (i = size; i > 0; i--)
 628                 value = (value << 8) | ptr[i - 1];
 629
 630         return value;
 631 }
 632
 633 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
 634                                       size_t size)
 635 {
 636         const u8 *ptr = data;
 637         unsigned long offset;
 638         size_t i, j;
 639         u32 value;
 640
 641         switch (ptr[0]) {
 642         case HDMI_INFOFRAME_TYPE_AVI:
 643                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
 644                 break;
 645
 646         case HDMI_INFOFRAME_TYPE_AUDIO:
 647                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
 648                 break;
 649
 650         case HDMI_INFOFRAME_TYPE_VENDOR:
 651                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
 652                 break;
 653
 654         default:
 655                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
 656                         ptr[0]);
 657                 return;
 658         }
 659
 660         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
 661                 INFOFRAME_HEADER_VERSION(ptr[1]) |
 662                 INFOFRAME_HEADER_LEN(ptr[2]);
 663         tegra_hdmi_writel(hdmi, value, offset);
 664         offset++;
 665
 666         /*
 667          * Each subpack contains 7 bytes, divided into:
 668          * - subpack_low: bytes 0 - 3
 669          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
 670          */
 671         for (i = 3, j = 0; i < size; i += 7, j += 8) {
 672                 size_t rem = size - i, num = min_t(size_t, rem, 4);
 673
 674                 value = tegra_hdmi_subpack(&ptr[i], num);
 675                 tegra_hdmi_writel(hdmi, value, offset++);
 676
 677                 num = min_t(size_t, rem - num, 3);
 678
 679                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
 680                 tegra_hdmi_writel(hdmi, value, offset++);
 681         }
 682 }
 683
 684 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
 685                                            struct drm_display_mode *mode)
 686 {
 687         struct hdmi_avi_infoframe frame;
 688         u8 buffer[17];
 689         ssize_t err;
 690
 691         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
 692                                                        &hdmi->output.connector, mode);
 693         if (err < 0) {
 694                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
 695                 return;
 696         }
 697
 698         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 699         if (err < 0) {
 700                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
 701                 return;
 702         }
 703
 704         tegra_hdmi_write_infopack(hdmi, buffer, err);
 705 }
 706
 707 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
 708 {
 709         u32 value;
 710
 711         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 712         value &= ~INFOFRAME_CTRL_ENABLE;
 713         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 714 }
 715
 716 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
 717 {
 718         u32 value;
 719
 720         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 721         value |= INFOFRAME_CTRL_ENABLE;
 722         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 723 }
 724
 725 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
 726 {
 727         struct hdmi_audio_infoframe frame;
 728         u8 buffer[14];
 729         ssize_t err;
 730
 731         err = hdmi_audio_infoframe_init(&frame);
 732         if (err < 0) {
 733                 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
 734                         err);
 735                 return;
 736         }
 737
 738         frame.channels = hdmi->format.channels;
 739
 740         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 741         if (err < 0) {
 742                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
 743                         err);
 744                 return;
 745         }
 746
 747         /*
 748          * The audio infoframe has only one set of subpack registers, so the
 749          * infoframe needs to be truncated. One set of subpack registers can
 750          * contain 7 bytes. Including the 3 byte header only the first 10
 751          * bytes can be programmed.
 752          */
 753         tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
 754 }
 755
 756 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
 757 {
 758         u32 value;
 759
 760         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 761         value &= ~INFOFRAME_CTRL_ENABLE;
 762         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 763 }
 764
 765 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
 766 {
 767         u32 value;
 768
 769         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 770         value |= INFOFRAME_CTRL_ENABLE;
 771         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 772 }
 773
 774 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
 775 {
 776         struct hdmi_vendor_infoframe frame;
 777         u8 buffer[10];
 778         ssize_t err;
 779
 780         hdmi_vendor_infoframe_init(&frame);
 781         frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
 782
 783         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
 784         if (err < 0) {
 785                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
 786                         err);
 787                 return;
 788         }
 789
 790         tegra_hdmi_write_infopack(hdmi, buffer, err);
 791 }
 792
 793 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
 794 {
 795         u32 value;
 796
 797         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 798         value &= ~GENERIC_CTRL_ENABLE;
 799         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 800 }
 801
 802 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
 803 {
 804         u32 value;
 805
 806         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 807         value |= GENERIC_CTRL_ENABLE;
 808         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 809 }
 810
 811 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
 812                                   const struct tmds_config *tmds)
 813 {
 814         u32 value;
 815
 816         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
 817         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
 818         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
 819
 820         tegra_hdmi_writel(hdmi, tmds->drive_current,
 821                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 822
 823         value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
 824         value |= hdmi->config->fuse_override_value;
 825         tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
 826
 827         if (hdmi->config->has_sor_io_peak_current)
 828                 tegra_hdmi_writel(hdmi, tmds->peak_current,
 829                                   HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
 830 }
 831
 832 static bool tegra_output_is_hdmi(struct tegra_output *output)
 833 {
 834         struct edid *edid;
 835
 836         if (!output->connector.edid_blob_ptr)
 837                 return false;
 838
 839         edid = (struct edid *)output->connector.edid_blob_ptr->data;
 840
 841         return drm_detect_hdmi_monitor(edid);
 842 }
 843
 844 static enum drm_connector_status
 845 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
 846 {
 847         struct tegra_output *output = connector_to_output(connector);
 848         struct tegra_hdmi *hdmi = to_hdmi(output);
 849         enum drm_connector_status status;
 850
 851         status = tegra_output_connector_detect(connector, force);
 852         if (status == connector_status_connected)
 853                 return status;
 854
 855         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
 856         return status;
 857 }
 858
 859 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
 860
 861 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
 862         DEBUGFS_REG32(HDMI_CTXSW),
 863         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
 864         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
 865         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
 866         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
 867         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
 868         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
 869         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
 870         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
 871         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
 872         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
 873         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
 874         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
 875         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
 876         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
 877         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
 878         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
 879         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
 880         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
 881         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
 882         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
 883         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
 884         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
 885         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
 886         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
 887         DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
 888         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
 889         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
 890         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
 891         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
 892         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
 893         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
 894         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
 895         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
 896         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
 897         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
 898         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
 899         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
 900         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
 901         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
 902         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
 903         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
 904         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
 905         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
 906         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
 907         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
 908         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
 909         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
 910         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
 911         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
 912         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
 913         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
 914         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
 915         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
 916         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
 917         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
 918         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
 919         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
 920         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
 921         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
 922         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
 923         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
 924         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
 925         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
 926         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
 927         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
 928         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
 929         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
 930         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
 931         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
 932         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
 933         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
 934         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
 935         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
 936         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
 937         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
 938         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
 939         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
 940         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
 941         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
 942         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
 943         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
 944         DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
 945         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
 946         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
 947         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
 948         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
 949         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
 950         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
 951         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
 952         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
 953         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
 954         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
 955         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
 956         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
 957         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
 958         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
 959         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
 960         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
 961         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
 962         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
 963         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
 964         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
 965         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
 966         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
 967         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
 968         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
 969         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
 970         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
 971         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
 972         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
 973         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
 974         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
 975         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
 976         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
 977         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
 978         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
 979         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
 980         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
 981         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
 982         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
 983         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
 984         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
 985         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
 986         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
 987         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
 988         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
 989         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
 990         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
 991         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
 992         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
 993         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
 994         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
 995         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
 996         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
 997         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
 998         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
 999         DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1000         DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1001         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1002         DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1003         DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1004         DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1005         DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1006         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1007         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1008         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1009         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1010         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1011         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1012         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1013         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1014         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1015         DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1016         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1017         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1018         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1019         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1020         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1021         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1022         DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1023         DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1024         DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1025         DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1026 };
1027
1028 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1029 {
1030         struct drm_info_node *node = s->private;
1031         struct tegra_hdmi *hdmi = node->info_ent->data;
1032         struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1033         struct drm_device *drm = node->minor->dev;
1034         unsigned int i;
1035         int err = 0;
1036
1037         drm_modeset_lock_all(drm);
1038
1039         if (!crtc || !crtc->state->active) {
1040                 err = -EBUSY;
1041                 goto unlock;
1042         }
1043
1044         for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1045                 unsigned int offset = tegra_hdmi_regs[i].offset;
1046
1047                 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1048                            offset, tegra_hdmi_readl(hdmi, offset));
1049         }
1050
1051 unlock:
1052         drm_modeset_unlock_all(drm);
1053         return err;
1054 }
1055
1056 static struct drm_info_list debugfs_files[] = {
1057         { "regs", tegra_hdmi_show_regs, 0, NULL },
1058 };
1059
1060 static int tegra_hdmi_late_register(struct drm_connector *connector)
1061 {
1062         struct tegra_output *output = connector_to_output(connector);
1063         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1064         struct drm_minor *minor = connector->dev->primary;
1065         struct dentry *root = connector->debugfs_entry;
1066         struct tegra_hdmi *hdmi = to_hdmi(output);
1067         int err;
1068
1069         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1070                                       GFP_KERNEL);
1071         if (!hdmi->debugfs_files)
1072                 return -ENOMEM;
1073
1074         for (i = 0; i < count; i++)
1075                 hdmi->debugfs_files[i].data = hdmi;
1076
1077         err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1078         if (err < 0)
1079                 goto free;
1080
1081         return 0;
1082
1083 free:
1084         kfree(hdmi->debugfs_files);
1085         hdmi->debugfs_files = NULL;
1086
1087         return err;
1088 }
1089
1090 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1091 {
1092         struct tegra_output *output = connector_to_output(connector);
1093         struct drm_minor *minor = connector->dev->primary;
1094         unsigned int count = ARRAY_SIZE(debugfs_files);
1095         struct tegra_hdmi *hdmi = to_hdmi(output);
1096
1097         drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1098         kfree(hdmi->debugfs_files);
1099         hdmi->debugfs_files = NULL;
1100 }
1101
1102 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1103         .reset = drm_atomic_helper_connector_reset,
1104         .detect = tegra_hdmi_connector_detect,
1105         .fill_modes = drm_helper_probe_single_connector_modes,
1106         .destroy = tegra_output_connector_destroy,
1107         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1108         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1109         .late_register = tegra_hdmi_late_register,
1110         .early_unregister = tegra_hdmi_early_unregister,
1111 };
1112
1113 static enum drm_mode_status
1114 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1115                                 struct drm_display_mode *mode)
1116 {
1117         struct tegra_output *output = connector_to_output(connector);
1118         struct tegra_hdmi *hdmi = to_hdmi(output);
1119         unsigned long pclk = mode->clock * 1000;
1120         enum drm_mode_status status = MODE_OK;
1121         struct clk *parent;
1122         long err;
1123
1124         parent = clk_get_parent(hdmi->clk_parent);
1125
1126         err = clk_round_rate(parent, pclk * 4);
1127         if (err <= 0)
1128                 status = MODE_NOCLOCK;
1129
1130         return status;
1131 }
1132
1133 static const struct drm_connector_helper_funcs
1134 tegra_hdmi_connector_helper_funcs = {
1135         .get_modes = tegra_output_connector_get_modes,
1136         .mode_valid = tegra_hdmi_connector_mode_valid,
1137 };
1138
1139 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
1140         .destroy = tegra_output_encoder_destroy,
1141 };
1142
1143 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1144 {
1145         struct tegra_output *output = encoder_to_output(encoder);
1146         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1147         struct tegra_hdmi *hdmi = to_hdmi(output);
1148         u32 value;
1149
1150         /*
1151          * The following accesses registers of the display controller, so make
1152          * sure it's only executed when the output is attached to one.
1153          */
1154         if (dc) {
1155                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1156                 value &= ~HDMI_ENABLE;
1157                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1158
1159                 tegra_dc_commit(dc);
1160         }
1161
1162         if (!hdmi->dvi) {
1163                 if (hdmi->stereo)
1164                         tegra_hdmi_disable_stereo_infoframe(hdmi);
1165
1166                 tegra_hdmi_disable_audio_infoframe(hdmi);
1167                 tegra_hdmi_disable_avi_infoframe(hdmi);
1168                 tegra_hdmi_disable_audio(hdmi);
1169         }
1170
1171         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1172         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1173
1174         pm_runtime_put(hdmi->dev);
1175 }
1176
1177 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1178 {
1179         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1180         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1181         struct tegra_output *output = encoder_to_output(encoder);
1182         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1183         struct tegra_hdmi *hdmi = to_hdmi(output);
1184         unsigned int pulse_start, div82;
1185         int retries = 1000;
1186         u32 value;
1187         int err;
1188
1189         pm_runtime_get_sync(hdmi->dev);
1190
1191         /*
1192          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1193          * is used for interoperability between the HDA codec driver and the
1194          * HDMI driver.
1195          */
1196         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1197         tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1198
1199         hdmi->pixel_clock = mode->clock * 1000;
1200         h_sync_width = mode->hsync_end - mode->hsync_start;
1201         h_back_porch = mode->htotal - mode->hsync_end;
1202         h_front_porch = mode->hsync_start - mode->hdisplay;
1203
1204         err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1205         if (err < 0) {
1206                 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1207                         err);
1208         }
1209
1210         DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1211
1212         /* power up sequence */
1213         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1214         value &= ~SOR_PLL_PDBG;
1215         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1216
1217         usleep_range(10, 20);
1218
1219         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1220         value &= ~SOR_PLL_PWR;
1221         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1222
1223         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1224                         DC_DISP_DISP_TIMING_OPTIONS);
1225         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1226                         DC_DISP_DISP_COLOR_CONTROL);
1227
1228         /* video_preamble uses h_pulse2 */
1229         pulse_start = 1 + h_sync_width + h_back_porch - 10;
1230
1231         tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1232
1233         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1234                 PULSE_LAST_END_A;
1235         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1236
1237         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1238         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1239
1240         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1241                 VSYNC_WINDOW_ENABLE;
1242         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1243
1244         if (dc->pipe)
1245                 value = HDMI_SRC_DISPLAYB;
1246         else
1247                 value = HDMI_SRC_DISPLAYA;
1248
1249         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1250                                         (mode->vdisplay == 576)))
1251                 tegra_hdmi_writel(hdmi,
1252                                   value | ARM_VIDEO_RANGE_FULL,
1253                                   HDMI_NV_PDISP_INPUT_CONTROL);
1254         else
1255                 tegra_hdmi_writel(hdmi,
1256                                   value | ARM_VIDEO_RANGE_LIMITED,
1257                                   HDMI_NV_PDISP_INPUT_CONTROL);
1258
1259         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1260         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1261         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1262
1263         hdmi->dvi = !tegra_output_is_hdmi(output);
1264         if (!hdmi->dvi) {
1265                 /*
1266                  * Make sure that the audio format has been configured before
1267                  * enabling audio, otherwise we may try to divide by zero.
1268                 */
1269                 if (hdmi->format.sample_rate > 0) {
1270                         err = tegra_hdmi_setup_audio(hdmi);
1271                         if (err < 0)
1272                                 hdmi->dvi = true;
1273                 }
1274         }
1275
1276         if (hdmi->config->has_hda)
1277                 tegra_hdmi_write_eld(hdmi);
1278
1279         rekey = HDMI_REKEY_DEFAULT;
1280         value = HDMI_CTRL_REKEY(rekey);
1281         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1282                                           h_front_porch - rekey - 18) / 32);
1283
1284         if (!hdmi->dvi)
1285                 value |= HDMI_CTRL_ENABLE;
1286
1287         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1288
1289         if (!hdmi->dvi) {
1290                 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1291                 tegra_hdmi_setup_audio_infoframe(hdmi);
1292
1293                 if (hdmi->stereo)
1294                         tegra_hdmi_setup_stereo_infoframe(hdmi);
1295         }
1296
1297         /* TMDS CONFIG */
1298         for (i = 0; i < hdmi->config->num_tmds; i++) {
1299                 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1300                         tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1301                         break;
1302                 }
1303         }
1304
1305         tegra_hdmi_writel(hdmi,
1306                           SOR_SEQ_PU_PC(0) |
1307                           SOR_SEQ_PU_PC_ALT(0) |
1308                           SOR_SEQ_PD_PC(8) |
1309                           SOR_SEQ_PD_PC_ALT(8),
1310                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1311
1312         value = SOR_SEQ_INST_WAIT_TIME(1) |
1313                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1314                 SOR_SEQ_INST_HALT |
1315                 SOR_SEQ_INST_PIN_A_LOW |
1316                 SOR_SEQ_INST_PIN_B_LOW |
1317                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1318
1319         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1320         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1321
1322         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1323         value &= ~SOR_CSTM_ROTCLK(~0);
1324         value |= SOR_CSTM_ROTCLK(2);
1325         value |= SOR_CSTM_PLLDIV;
1326         value &= ~SOR_CSTM_LVDS_ENABLE;
1327         value &= ~SOR_CSTM_MODE_MASK;
1328         value |= SOR_CSTM_MODE_TMDS;
1329         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1330
1331         /* start SOR */
1332         tegra_hdmi_writel(hdmi,
1333                           SOR_PWR_NORMAL_STATE_PU |
1334                           SOR_PWR_NORMAL_START_NORMAL |
1335                           SOR_PWR_SAFE_STATE_PD |
1336                           SOR_PWR_SETTING_NEW_TRIGGER,
1337                           HDMI_NV_PDISP_SOR_PWR);
1338         tegra_hdmi_writel(hdmi,
1339                           SOR_PWR_NORMAL_STATE_PU |
1340                           SOR_PWR_NORMAL_START_NORMAL |
1341                           SOR_PWR_SAFE_STATE_PD |
1342                           SOR_PWR_SETTING_NEW_DONE,
1343                           HDMI_NV_PDISP_SOR_PWR);
1344
1345         do {
1346                 BUG_ON(--retries < 0);
1347                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1348         } while (value & SOR_PWR_SETTING_NEW_PENDING);
1349
1350         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1351                 SOR_STATE_ASY_OWNER_HEAD0 |
1352                 SOR_STATE_ASY_SUBOWNER_BOTH |
1353                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1354                 SOR_STATE_ASY_DEPOL_POS;
1355
1356         /* setup sync polarities */
1357         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1358                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1359
1360         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1361                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1362
1363         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1364                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1365
1366         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1367                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1368
1369         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1370
1371         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1372         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1373
1374         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1375         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1376         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1377                           HDMI_NV_PDISP_SOR_STATE1);
1378         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1379
1380         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1381         value |= HDMI_ENABLE;
1382         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1383
1384         tegra_dc_commit(dc);
1385
1386         if (!hdmi->dvi) {
1387                 tegra_hdmi_enable_avi_infoframe(hdmi);
1388                 tegra_hdmi_enable_audio_infoframe(hdmi);
1389                 tegra_hdmi_enable_audio(hdmi);
1390
1391                 if (hdmi->stereo)
1392                         tegra_hdmi_enable_stereo_infoframe(hdmi);
1393         }
1394
1395         /* TODO: add HDCP support */
1396 }
1397
1398 static int
1399 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1400                                 struct drm_crtc_state *crtc_state,
1401                                 struct drm_connector_state *conn_state)
1402 {
1403         struct tegra_output *output = encoder_to_output(encoder);
1404         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1405         unsigned long pclk = crtc_state->mode.clock * 1000;
1406         struct tegra_hdmi *hdmi = to_hdmi(output);
1407         int err;
1408
1409         err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1410                                          pclk, 0);
1411         if (err < 0) {
1412                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1413                 return err;
1414         }
1415
1416         return err;
1417 }
1418
1419 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1420         .disable = tegra_hdmi_encoder_disable,
1421         .enable = tegra_hdmi_encoder_enable,
1422         .atomic_check = tegra_hdmi_encoder_atomic_check,
1423 };
1424
1425 static int tegra_hdmi_init(struct host1x_client *client)
1426 {
1427         struct drm_device *drm = dev_get_drvdata(client->parent);
1428         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1429         int err;
1430
1431         hdmi->output.dev = client->dev;
1432
1433         drm_connector_init(drm, &hdmi->output.connector,
1434                            &tegra_hdmi_connector_funcs,
1435                            DRM_MODE_CONNECTOR_HDMIA);
1436         drm_connector_helper_add(&hdmi->output.connector,
1437                                  &tegra_hdmi_connector_helper_funcs);
1438         hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1439
1440         drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1441                          DRM_MODE_ENCODER_TMDS, NULL);
1442         drm_encoder_helper_add(&hdmi->output.encoder,
1443                                &tegra_hdmi_encoder_helper_funcs);
1444
1445         drm_connector_attach_encoder(&hdmi->output.connector,
1446                                           &hdmi->output.encoder);
1447         drm_connector_register(&hdmi->output.connector);
1448
1449         err = tegra_output_init(drm, &hdmi->output);
1450         if (err < 0) {
1451                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1452                 return err;
1453         }
1454
1455         hdmi->output.encoder.possible_crtcs = 0x3;
1456
1457         err = regulator_enable(hdmi->hdmi);
1458         if (err < 0) {
1459                 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1460                         err);
1461                 return err;
1462         }
1463
1464         err = regulator_enable(hdmi->pll);
1465         if (err < 0) {
1466                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1467                 return err;
1468         }
1469
1470         err = regulator_enable(hdmi->vdd);
1471         if (err < 0) {
1472                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1473                 return err;
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int tegra_hdmi_exit(struct host1x_client *client)
1480 {
1481         struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1482
1483         tegra_output_exit(&hdmi->output);
1484
1485         regulator_disable(hdmi->vdd);
1486         regulator_disable(hdmi->pll);
1487         regulator_disable(hdmi->hdmi);
1488
1489         return 0;
1490 }
1491
1492 static const struct host1x_client_ops hdmi_client_ops = {
1493         .init = tegra_hdmi_init,
1494         .exit = tegra_hdmi_exit,
1495 };
1496
1497 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1498         .tmds = tegra20_tmds_config,
1499         .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1500         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1501         .fuse_override_value = 1 << 31,
1502         .has_sor_io_peak_current = false,
1503         .has_hda = false,
1504         .has_hbr = false,
1505 };
1506
1507 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1508         .tmds = tegra30_tmds_config,
1509         .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1510         .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1511         .fuse_override_value = 1 << 31,
1512         .has_sor_io_peak_current = false,
1513         .has_hda = true,
1514         .has_hbr = false,
1515 };
1516
1517 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1518         .tmds = tegra114_tmds_config,
1519         .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1520         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1521         .fuse_override_value = 1 << 31,
1522         .has_sor_io_peak_current = true,
1523         .has_hda = true,
1524         .has_hbr = true,
1525 };
1526
1527 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1528         .tmds = tegra124_tmds_config,
1529         .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1530         .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1531         .fuse_override_value = 1 << 31,
1532         .has_sor_io_peak_current = true,
1533         .has_hda = true,
1534         .has_hbr = true,
1535 };
1536
1537 static const struct of_device_id tegra_hdmi_of_match[] = {
1538         { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1539         { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1540         { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1541         { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1542         { },
1543 };
1544 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1545
1546 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1547 {
1548         struct tegra_hdmi *hdmi = data;
1549         u32 value;
1550         int err;
1551
1552         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1553         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1554
1555         if (value & INT_CODEC_SCRATCH0) {
1556                 unsigned int format;
1557                 u32 value;
1558
1559                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1560
1561                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1562                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1563
1564                         tegra_hda_parse_format(format, &hdmi->format);
1565
1566                         err = tegra_hdmi_setup_audio(hdmi);
1567                         if (err < 0) {
1568                                 tegra_hdmi_disable_audio_infoframe(hdmi);
1569                                 tegra_hdmi_disable_audio(hdmi);
1570                         } else {
1571                                 tegra_hdmi_setup_audio_infoframe(hdmi);
1572                                 tegra_hdmi_enable_audio_infoframe(hdmi);
1573                                 tegra_hdmi_enable_audio(hdmi);
1574                         }
1575                 } else {
1576                         tegra_hdmi_disable_audio_infoframe(hdmi);
1577                         tegra_hdmi_disable_audio(hdmi);
1578                 }
1579         }
1580
1581         return IRQ_HANDLED;
1582 }
1583
1584 static int tegra_hdmi_probe(struct platform_device *pdev)
1585 {
1586         struct tegra_hdmi *hdmi;
1587         struct resource *regs;
1588         int err;
1589
1590         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1591         if (!hdmi)
1592                 return -ENOMEM;
1593
1594         hdmi->config = of_device_get_match_data(&pdev->dev);
1595         hdmi->dev = &pdev->dev;
1596
1597         hdmi->audio_source = AUTO;
1598         hdmi->stereo = false;
1599         hdmi->dvi = false;
1600
1601         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1602         if (IS_ERR(hdmi->clk)) {
1603                 dev_err(&pdev->dev, "failed to get clock\n");
1604                 return PTR_ERR(hdmi->clk);
1605         }
1606
1607         hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1608         if (IS_ERR(hdmi->rst)) {
1609                 dev_err(&pdev->dev, "failed to get reset\n");
1610                 return PTR_ERR(hdmi->rst);
1611         }
1612
1613         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1614         if (IS_ERR(hdmi->clk_parent))
1615                 return PTR_ERR(hdmi->clk_parent);
1616
1617         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1618         if (err < 0) {
1619                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1620                 return err;
1621         }
1622
1623         hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1624         if (IS_ERR(hdmi->hdmi)) {
1625                 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1626                 return PTR_ERR(hdmi->hdmi);
1627         }
1628
1629         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1630         if (IS_ERR(hdmi->pll)) {
1631                 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1632                 return PTR_ERR(hdmi->pll);
1633         }
1634
1635         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1636         if (IS_ERR(hdmi->vdd)) {
1637                 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1638                 return PTR_ERR(hdmi->vdd);
1639         }
1640
1641         hdmi->output.dev = &pdev->dev;
1642
1643         err = tegra_output_probe(&hdmi->output);
1644         if (err < 0)
1645                 return err;
1646
1647         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1648         hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1649         if (IS_ERR(hdmi->regs))
1650                 return PTR_ERR(hdmi->regs);
1651
1652         err = platform_get_irq(pdev, 0);
1653         if (err < 0)
1654                 return err;
1655
1656         hdmi->irq = err;
1657
1658         err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1659                                dev_name(hdmi->dev), hdmi);
1660         if (err < 0) {
1661                 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1662                         hdmi->irq, err);
1663                 return err;
1664         }
1665
1666         platform_set_drvdata(pdev, hdmi);
1667         pm_runtime_enable(&pdev->dev);
1668
1669         INIT_LIST_HEAD(&hdmi->client.list);
1670         hdmi->client.ops = &hdmi_client_ops;
1671         hdmi->client.dev = &pdev->dev;
1672
1673         err = host1x_client_register(&hdmi->client);
1674         if (err < 0) {
1675                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1676                         err);
1677                 return err;
1678         }
1679
1680         return 0;
1681 }
1682
1683 static int tegra_hdmi_remove(struct platform_device *pdev)
1684 {
1685         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1686         int err;
1687
1688         pm_runtime_disable(&pdev->dev);
1689
1690         err = host1x_client_unregister(&hdmi->client);
1691         if (err < 0) {
1692                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1693                         err);
1694                 return err;
1695         }
1696
1697         tegra_output_remove(&hdmi->output);
1698
1699         return 0;
1700 }
1701
1702 #ifdef CONFIG_PM
1703 static int tegra_hdmi_suspend(struct device *dev)
1704 {
1705         struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1706         int err;
1707
1708         err = reset_control_assert(hdmi->rst);
1709         if (err < 0) {
1710                 dev_err(dev, "failed to assert reset: %d\n", err);
1711                 return err;
1712         }
1713
1714         usleep_range(1000, 2000);
1715
1716         clk_disable_unprepare(hdmi->clk);
1717
1718         return 0;
1719 }
1720
1721 static int tegra_hdmi_resume(struct device *dev)
1722 {
1723         struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1724         int err;
1725
1726         err = clk_prepare_enable(hdmi->clk);
1727         if (err < 0) {
1728                 dev_err(dev, "failed to enable clock: %d\n", err);
1729                 return err;
1730         }
1731
1732         usleep_range(1000, 2000);
1733
1734         err = reset_control_deassert(hdmi->rst);
1735         if (err < 0) {
1736                 dev_err(dev, "failed to deassert reset: %d\n", err);
1737                 clk_disable_unprepare(hdmi->clk);
1738                 return err;
1739         }
1740
1741         return 0;
1742 }
1743 #endif
1744
1745 static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1746         SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1747 };
1748
1749 struct platform_driver tegra_hdmi_driver = {
1750         .driver = {
1751                 .name = "tegra-hdmi",
1752                 .of_match_table = tegra_hdmi_of_match,
1753                 .pm = &tegra_hdmi_pm_ops,
1754         },
1755         .probe = tegra_hdmi_probe,
1756         .remove = tegra_hdmi_remove,
1757 };