drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset.h>
  17
  18 #include <soc/tegra/pmc.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_dp_helper.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_scdc_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_edp;
 375         bool supports_lvds;
 376         bool supports_hdmi;
 377         bool supports_dp;
 378
 379         const struct tegra_sor_regs *regs;
 380         bool has_nvdisplay;
 381
 382         const struct tegra_sor_hdmi_settings *settings;
 383         unsigned int num_settings;
 384
 385         const u8 *xbar_cfg;
 386         const u8 *lane_map;
 387
 388         const u8 (*voltage_swing)[4][4];
 389         const u8 (*pre_emphasis)[4][4];
 390         const u8 (*post_cursor)[4][4];
 391         const u8 (*tx_pu)[4][4];
 392 };
 393
 394 struct tegra_sor;
 395
 396 struct tegra_sor_ops {
 397         const char *name;
 398         int (*probe)(struct tegra_sor *sor);
 399         int (*remove)(struct tegra_sor *sor);
 400 };
 401
 402 struct tegra_sor {
 403         struct host1x_client client;
 404         struct tegra_output output;
 405         struct device *dev;
 406
 407         const struct tegra_sor_soc *soc;
 408         void __iomem *regs;
 409         unsigned int index;
 410         unsigned int irq;
 411
 412         struct reset_control *rst;
 413         struct clk *clk_parent;
 414         struct clk *clk_safe;
 415         struct clk *clk_out;
 416         struct clk *clk_pad;
 417         struct clk *clk_dp;
 418         struct clk *clk;
 419
 420         u8 xbar_cfg[5];
 421
 422         struct drm_dp_link link;
 423         struct drm_dp_aux *aux;
 424
 425         struct drm_info_list *debugfs_files;
 426
 427         const struct tegra_sor_ops *ops;
 428         enum tegra_io_pad pad;
 429
 430         /* for HDMI 2.0 */
 431         struct tegra_sor_hdmi_settings *settings;
 432         unsigned int num_settings;
 433
 434         struct regulator *avdd_io_supply;
 435         struct regulator *vdd_pll_supply;
 436         struct regulator *hdmi_supply;
 437
 438         struct delayed_work scdc;
 439         bool scdc_enabled;
 440
 441         struct tegra_hda_format format;
 442 };
 443
 444 struct tegra_sor_state {
 445         struct drm_connector_state base;
 446
 447         unsigned int link_speed;
 448         unsigned long pclk;
 449         unsigned int bpc;
 450 };
 451
 452 static inline struct tegra_sor_state *
 453 to_sor_state(struct drm_connector_state *state)
 454 {
 455         return container_of(state, struct tegra_sor_state, base);
 456 }
 457
 458 struct tegra_sor_config {
 459         u32 bits_per_pixel;
 460
 461         u32 active_polarity;
 462         u32 active_count;
 463         u32 tu_size;
 464         u32 active_frac;
 465         u32 watermark;
 466
 467         u32 hblank_symbols;
 468         u32 vblank_symbols;
 469 };
 470
 471 static inline struct tegra_sor *
 472 host1x_client_to_sor(struct host1x_client *client)
 473 {
 474         return container_of(client, struct tegra_sor, client);
 475 }
 476
 477 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 478 {
 479         return container_of(output, struct tegra_sor, output);
 480 }
 481
 482 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 483 {
 484         u32 value = readl(sor->regs + (offset << 2));
 485
 486         trace_sor_readl(sor->dev, offset, value);
 487
 488         return value;
 489 }
 490
 491 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 492                                     unsigned int offset)
 493 {
 494         trace_sor_writel(sor->dev, offset, value);
 495         writel(value, sor->regs + (offset << 2));
 496 }
 497
 498 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 499 {
 500         int err;
 501
 502         clk_disable_unprepare(sor->clk);
 503
 504         err = clk_set_parent(sor->clk_out, parent);
 505         if (err < 0)
 506                 return err;
 507
 508         err = clk_prepare_enable(sor->clk);
 509         if (err < 0)
 510                 return err;
 511
 512         return 0;
 513 }
 514
 515 struct tegra_clk_sor_pad {
 516         struct clk_hw hw;
 517         struct tegra_sor *sor;
 518 };
 519
 520 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 521 {
 522         return container_of(hw, struct tegra_clk_sor_pad, hw);
 523 }
 524
 525 static const char * const tegra_clk_sor_pad_parents[] = {
 526         "pll_d2_out0", "pll_dp"
 527 };
 528
 529 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 530 {
 531         struct tegra_clk_sor_pad *pad = to_pad(hw);
 532         struct tegra_sor *sor = pad->sor;
 533         u32 value;
 534
 535         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 536         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 537
 538         switch (index) {
 539         case 0:
 540                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 541                 break;
 542
 543         case 1:
 544                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 545                 break;
 546         }
 547
 548         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 549
 550         return 0;
 551 }
 552
 553 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 554 {
 555         struct tegra_clk_sor_pad *pad = to_pad(hw);
 556         struct tegra_sor *sor = pad->sor;
 557         u8 parent = U8_MAX;
 558         u32 value;
 559
 560         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 561
 562         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 563         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 564         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 565                 parent = 0;
 566                 break;
 567
 568         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 569         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 570                 parent = 1;
 571                 break;
 572         }
 573
 574         return parent;
 575 }
 576
 577 static const struct clk_ops tegra_clk_sor_pad_ops = {
 578         .set_parent = tegra_clk_sor_pad_set_parent,
 579         .get_parent = tegra_clk_sor_pad_get_parent,
 580 };
 581
 582 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 583                                               const char *name)
 584 {
 585         struct tegra_clk_sor_pad *pad;
 586         struct clk_init_data init;
 587         struct clk *clk;
 588
 589         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 590         if (!pad)
 591                 return ERR_PTR(-ENOMEM);
 592
 593         pad->sor = sor;
 594
 595         init.name = name;
 596         init.flags = 0;
 597         init.parent_names = tegra_clk_sor_pad_parents;
 598         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
 599         init.ops = &tegra_clk_sor_pad_ops;
 600
 601         pad->hw.init = &init;
 602
 603         clk = devm_clk_register(sor->dev, &pad->hw);
 604
 605         return clk;
 606 }
 607
 608 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 609 {
 610         struct drm_dp_link *link = &sor->link;
 611         unsigned int i;
 612
 613         /* Tegra only supports RBR, HBR and HBR2 */
 614         for (i = 0; i < link->num_rates; i++) {
 615                 switch (link->rates[i]) {
 616                 case 1620000:
 617                 case 2700000:
 618                 case 5400000:
 619                         break;
 620
 621                 default:
 622                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 623                                       link->rates[i]);
 624                         link->rates[i] = 0;
 625                         break;
 626                 }
 627         }
 628
 629         drm_dp_link_update_rates(link);
 630 }
 631
 632 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 633 {
 634         unsigned long timeout;
 635         u32 value;
 636
 637         /*
 638          * Clear or set the PD_TXD bit corresponding to each lane, depending
 639          * on whether it is used or not.
 640          */
 641         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 642
 643         if (lanes <= 2)
 644                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 645                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 646         else
 647                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 648                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 649
 650         if (lanes <= 1)
 651                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 652         else
 653                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 654
 655         if (lanes == 0)
 656                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 657         else
 658                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 659
 660         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 661
 662         /* start lane sequencer */
 663         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 664                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 665         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 666
 667         timeout = jiffies + msecs_to_jiffies(250);
 668
 669         while (time_before(jiffies, timeout)) {
 670                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 671                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 672                         break;
 673
 674                 usleep_range(250, 1000);
 675         }
 676
 677         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 678                 return -ETIMEDOUT;
 679
 680         return 0;
 681 }
 682
 683 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 684 {
 685         unsigned long timeout;
 686         u32 value;
 687
 688         /* power down all lanes */
 689         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 690         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 691                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 692         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 693
 694         /* start lane sequencer */
 695         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 696                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 697         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 698
 699         timeout = jiffies + msecs_to_jiffies(250);
 700
 701         while (time_before(jiffies, timeout)) {
 702                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 703                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 704                         break;
 705
 706                 usleep_range(25, 100);
 707         }
 708
 709         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 710                 return -ETIMEDOUT;
 711
 712         return 0;
 713 }
 714
 715 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 716 {
 717         u32 value;
 718
 719         /* pre-charge all used lanes */
 720         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 721
 722         if (lanes <= 2)
 723                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 724                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 725         else
 726                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 727                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 728
 729         if (lanes <= 1)
 730                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 731         else
 732                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 733
 734         if (lanes == 0)
 735                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 736         else
 737                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 738
 739         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 740
 741         usleep_range(15, 100);
 742
 743         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 744         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 745                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 746         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 747 }
 748
 749 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 750 {
 751         u32 mask = 0x08, adj = 0, value;
 752
 753         /* enable pad calibration logic */
 754         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 755         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 756         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 757
 758         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 759         value |= SOR_PLL1_TMDS_TERM;
 760         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 761
 762         while (mask) {
 763                 adj |= mask;
 764
 765                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 766                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 767                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 768                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 769
 770                 usleep_range(100, 200);
 771
 772                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 773                 if (value & SOR_PLL1_TERM_COMPOUT)
 774                         adj &= ~mask;
 775
 776                 mask >>= 1;
 777         }
 778
 779         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 780         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 781         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 782         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 783
 784         /* disable pad calibration logic */
 785         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 786         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 787         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 788 }
 789
 790 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 791 {
 792         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 793         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 794         const struct tegra_sor_soc *soc = sor->soc;
 795         u32 pattern = 0, tx_pu = 0, value;
 796         unsigned int i;
 797
 798         for (value = 0, i = 0; i < link->lanes; i++) {
 799                 u8 vs = link->train.request.voltage_swing[i];
 800                 u8 pe = link->train.request.pre_emphasis[i];
 801                 u8 pc = link->train.request.post_cursor[i];
 802                 u8 shift = sor->soc->lane_map[i] << 3;
 803
 804                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 805                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 806                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 807
 808                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 809                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 810
 811                 switch (link->train.pattern) {
 812                 case DP_TRAINING_PATTERN_DISABLE:
 813                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 814                                 SOR_DP_TPG_PATTERN_NONE;
 815                         break;
 816
 817                 case DP_TRAINING_PATTERN_1:
 818                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 819                                 SOR_DP_TPG_PATTERN_TRAIN1;
 820                         break;
 821
 822                 case DP_TRAINING_PATTERN_2:
 823                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 824                                 SOR_DP_TPG_PATTERN_TRAIN2;
 825                         break;
 826
 827                 case DP_TRAINING_PATTERN_3:
 828                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 829                                 SOR_DP_TPG_PATTERN_TRAIN3;
 830                         break;
 831
 832                 default:
 833                         return -EINVAL;
 834                 }
 835
 836                 if (link->caps.channel_coding)
 837                         value |= SOR_DP_TPG_CHANNEL_CODING;
 838
 839                 pattern = pattern << 8 | value;
 840         }
 841
 842         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 843         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 844
 845         if (link->caps.tps3_supported)
 846                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 847
 848         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 849
 850         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 851         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 852         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 853         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 854         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 855
 856         usleep_range(20, 100);
 857
 858         return 0;
 859 }
 860
 861 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 862 {
 863         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 864         unsigned int rate, lanes;
 865         u32 value;
 866         int err;
 867
 868         rate = drm_dp_link_rate_to_bw_code(link->rate);
 869         lanes = link->lanes;
 870
 871         /* configure link speed and lane count */
 872         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 873         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 874         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 875         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 876
 877         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 878         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 879         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 880
 881         if (link->caps.enhanced_framing)
 882                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 883
 884         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 885
 886         usleep_range(400, 1000);
 887
 888         /* configure load pulse position adjustment */
 889         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 890         value &= ~SOR_PLL1_LOADADJ_MASK;
 891
 892         switch (rate) {
 893         case DP_LINK_BW_1_62:
 894                 value |= SOR_PLL1_LOADADJ(0x3);
 895                 break;
 896
 897         case DP_LINK_BW_2_7:
 898                 value |= SOR_PLL1_LOADADJ(0x4);
 899                 break;
 900
 901         case DP_LINK_BW_5_4:
 902                 value |= SOR_PLL1_LOADADJ(0x6);
 903                 break;
 904         }
 905
 906         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 907
 908         /* use alternate scrambler reset for eDP */
 909         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 910
 911         if (link->edp == 0)
 912                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 913         else
 914                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 915
 916         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 917
 918         err = tegra_sor_power_down_lanes(sor);
 919         if (err < 0) {
 920                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 921                 return err;
 922         }
 923
 924         /* power up and pre-charge lanes */
 925         err = tegra_sor_power_up_lanes(sor, lanes);
 926         if (err < 0) {
 927                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 928                         lanes, (lanes != 1) ? "s" : "", err);
 929                 return err;
 930         }
 931
 932         tegra_sor_dp_precharge(sor, lanes);
 933
 934         return 0;
 935 }
 936
 937 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 938         .apply_training = tegra_sor_dp_link_apply_training,
 939         .configure = tegra_sor_dp_link_configure,
 940 };
 941
 942 static void tegra_sor_super_update(struct tegra_sor *sor)
 943 {
 944         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 945         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 946         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 947 }
 948
 949 static void tegra_sor_update(struct tegra_sor *sor)
 950 {
 951         tegra_sor_writel(sor, 0, SOR_STATE0);
 952         tegra_sor_writel(sor, 1, SOR_STATE0);
 953         tegra_sor_writel(sor, 0, SOR_STATE0);
 954 }
 955
 956 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 957 {
 958         u32 value;
 959
 960         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 961         value &= ~SOR_PWM_DIV_MASK;
 962         value |= 0x400; /* period */
 963         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 964
 965         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 966         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 967         value |= 0x400; /* duty cycle */
 968         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 969         value |= SOR_PWM_CTL_TRIGGER;
 970         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 971
 972         timeout = jiffies + msecs_to_jiffies(timeout);
 973
 974         while (time_before(jiffies, timeout)) {
 975                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 976                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 977                         return 0;
 978
 979                 usleep_range(25, 100);
 980         }
 981
 982         return -ETIMEDOUT;
 983 }
 984
 985 static int tegra_sor_attach(struct tegra_sor *sor)
 986 {
 987         unsigned long value, timeout;
 988
 989         /* wake up in normal mode */
 990         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 991         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 992         value |= SOR_SUPER_STATE_MODE_NORMAL;
 993         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 994         tegra_sor_super_update(sor);
 995
 996         /* attach */
 997         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 998         value |= SOR_SUPER_STATE_ATTACHED;
 999         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1000         tegra_sor_super_update(sor);
1001
1002         timeout = jiffies + msecs_to_jiffies(250);
1003
1004         while (time_before(jiffies, timeout)) {
1005                 value = tegra_sor_readl(sor, SOR_TEST);
1006                 if ((value & SOR_TEST_ATTACHED) != 0)
1007                         return 0;
1008
1009                 usleep_range(25, 100);
1010         }
1011
1012         return -ETIMEDOUT;
1013 }
1014
1015 static int tegra_sor_wakeup(struct tegra_sor *sor)
1016 {
1017         unsigned long value, timeout;
1018
1019         timeout = jiffies + msecs_to_jiffies(250);
1020
1021         /* wait for head to wake up */
1022         while (time_before(jiffies, timeout)) {
1023                 value = tegra_sor_readl(sor, SOR_TEST);
1024                 value &= SOR_TEST_HEAD_MODE_MASK;
1025
1026                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1027                         return 0;
1028
1029                 usleep_range(25, 100);
1030         }
1031
1032         return -ETIMEDOUT;
1033 }
1034
1035 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1036 {
1037         u32 value;
1038
1039         value = tegra_sor_readl(sor, SOR_PWR);
1040         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1041         tegra_sor_writel(sor, value, SOR_PWR);
1042
1043         timeout = jiffies + msecs_to_jiffies(timeout);
1044
1045         while (time_before(jiffies, timeout)) {
1046                 value = tegra_sor_readl(sor, SOR_PWR);
1047                 if ((value & SOR_PWR_TRIGGER) == 0)
1048                         return 0;
1049
1050                 usleep_range(25, 100);
1051         }
1052
1053         return -ETIMEDOUT;
1054 }
1055
1056 struct tegra_sor_params {
1057         /* number of link clocks per line */
1058         unsigned int num_clocks;
1059         /* ratio between input and output */
1060         u64 ratio;
1061         /* precision factor */
1062         u64 precision;
1063
1064         unsigned int active_polarity;
1065         unsigned int active_count;
1066         unsigned int active_frac;
1067         unsigned int tu_size;
1068         unsigned int error;
1069 };
1070
1071 static int tegra_sor_compute_params(struct tegra_sor *sor,
1072                                     struct tegra_sor_params *params,
1073                                     unsigned int tu_size)
1074 {
1075         u64 active_sym, active_count, frac, approx;
1076         u32 active_polarity, active_frac = 0;
1077         const u64 f = params->precision;
1078         s64 error;
1079
1080         active_sym = params->ratio * tu_size;
1081         active_count = div_u64(active_sym, f) * f;
1082         frac = active_sym - active_count;
1083
1084         /* fraction < 0.5 */
1085         if (frac >= (f / 2)) {
1086                 active_polarity = 1;
1087                 frac = f - frac;
1088         } else {
1089                 active_polarity = 0;
1090         }
1091
1092         if (frac != 0) {
1093                 frac = div_u64(f * f,  frac); /* 1/fraction */
1094                 if (frac <= (15 * f)) {
1095                         active_frac = div_u64(frac, f);
1096
1097                         /* round up */
1098                         if (active_polarity)
1099                                 active_frac++;
1100                 } else {
1101                         active_frac = active_polarity ? 1 : 15;
1102                 }
1103         }
1104
1105         if (active_frac == 1)
1106                 active_polarity = 0;
1107
1108         if (active_polarity == 1) {
1109                 if (active_frac) {
1110                         approx = active_count + (active_frac * (f - 1)) * f;
1111                         approx = div_u64(approx, active_frac * f);
1112                 } else {
1113                         approx = active_count + f;
1114                 }
1115         } else {
1116                 if (active_frac)
1117                         approx = active_count + div_u64(f, active_frac);
1118                 else
1119                         approx = active_count;
1120         }
1121
1122         error = div_s64(active_sym - approx, tu_size);
1123         error *= params->num_clocks;
1124
1125         if (error <= 0 && abs(error) < params->error) {
1126                 params->active_count = div_u64(active_count, f);
1127                 params->active_polarity = active_polarity;
1128                 params->active_frac = active_frac;
1129                 params->error = abs(error);
1130                 params->tu_size = tu_size;
1131
1132                 if (error == 0)
1133                         return true;
1134         }
1135
1136         return false;
1137 }
1138
1139 static int tegra_sor_compute_config(struct tegra_sor *sor,
1140                                     const struct drm_display_mode *mode,
1141                                     struct tegra_sor_config *config,
1142                                     struct drm_dp_link *link)
1143 {
1144         const u64 f = 100000, link_rate = link->rate * 1000;
1145         const u64 pclk = mode->clock * 1000;
1146         u64 input, output, watermark, num;
1147         struct tegra_sor_params params;
1148         u32 num_syms_per_line;
1149         unsigned int i;
1150
1151         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1152                 return -EINVAL;
1153
1154         input = pclk * config->bits_per_pixel;
1155         output = link_rate * 8 * link->lanes;
1156
1157         if (input >= output)
1158                 return -ERANGE;
1159
1160         memset(&params, 0, sizeof(params));
1161         params.ratio = div64_u64(input * f, output);
1162         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1163         params.precision = f;
1164         params.error = 64 * f;
1165         params.tu_size = 64;
1166
1167         for (i = params.tu_size; i >= 32; i--)
1168                 if (tegra_sor_compute_params(sor, &params, i))
1169                         break;
1170
1171         if (params.active_frac == 0) {
1172                 config->active_polarity = 0;
1173                 config->active_count = params.active_count;
1174
1175                 if (!params.active_polarity)
1176                         config->active_count--;
1177
1178                 config->tu_size = params.tu_size;
1179                 config->active_frac = 1;
1180         } else {
1181                 config->active_polarity = params.active_polarity;
1182                 config->active_count = params.active_count;
1183                 config->active_frac = params.active_frac;
1184                 config->tu_size = params.tu_size;
1185         }
1186
1187         dev_dbg(sor->dev,
1188                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1189                 config->active_polarity, config->active_count,
1190                 config->tu_size, config->active_frac);
1191
1192         watermark = params.ratio * config->tu_size * (f - params.ratio);
1193         watermark = div_u64(watermark, f);
1194
1195         watermark = div_u64(watermark + params.error, f);
1196         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1197         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1198                             (link->lanes * 8);
1199
1200         if (config->watermark > 30) {
1201                 config->watermark = 30;
1202                 dev_err(sor->dev,
1203                         "unable to compute TU size, forcing watermark to %u\n",
1204                         config->watermark);
1205         } else if (config->watermark > num_syms_per_line) {
1206                 config->watermark = num_syms_per_line;
1207                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1208                         config->watermark);
1209         }
1210
1211         /* compute the number of symbols per horizontal blanking interval */
1212         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1213         config->hblank_symbols = div_u64(num, pclk);
1214
1215         if (link->caps.enhanced_framing)
1216                 config->hblank_symbols -= 3;
1217
1218         config->hblank_symbols -= 12 / link->lanes;
1219
1220         /* compute the number of symbols per vertical blanking interval */
1221         num = (mode->hdisplay - 25) * link_rate;
1222         config->vblank_symbols = div_u64(num, pclk);
1223         config->vblank_symbols -= 36 / link->lanes + 4;
1224
1225         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1226                 config->vblank_symbols);
1227
1228         return 0;
1229 }
1230
1231 static void tegra_sor_apply_config(struct tegra_sor *sor,
1232                                    const struct tegra_sor_config *config)
1233 {
1234         u32 value;
1235
1236         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1237         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1238         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1239         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1240
1241         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1242         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1243         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1244
1245         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1246         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1247
1248         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1249         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1250
1251         if (config->active_polarity)
1252                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1253         else
1254                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1255
1256         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1257         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1258         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1259
1260         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1261         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1262         value |= config->hblank_symbols & 0xffff;
1263         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1264
1265         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1266         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1267         value |= config->vblank_symbols & 0xffff;
1268         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1269 }
1270
1271 static void tegra_sor_mode_set(struct tegra_sor *sor,
1272                                const struct drm_display_mode *mode,
1273                                struct tegra_sor_state *state)
1274 {
1275         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1276         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1277         u32 value;
1278
1279         value = tegra_sor_readl(sor, SOR_STATE1);
1280         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1281         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1282         value &= ~SOR_STATE_ASY_OWNER_MASK;
1283
1284         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1285                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1286
1287         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1288                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1289
1290         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1291                 value |= SOR_STATE_ASY_HSYNCPOL;
1292
1293         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1294                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1295
1296         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1297                 value |= SOR_STATE_ASY_VSYNCPOL;
1298
1299         switch (state->bpc) {
1300         case 16:
1301                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1302                 break;
1303
1304         case 12:
1305                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1306                 break;
1307
1308         case 10:
1309                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1310                 break;
1311
1312         case 8:
1313                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1314                 break;
1315
1316         case 6:
1317                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1318                 break;
1319
1320         default:
1321                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1322                 break;
1323         }
1324
1325         tegra_sor_writel(sor, value, SOR_STATE1);
1326
1327         /*
1328          * TODO: The video timing programming below doesn't seem to match the
1329          * register definitions.
1330          */
1331
1332         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1333         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1334
1335         /* sync end = sync width - 1 */
1336         vse = mode->vsync_end - mode->vsync_start - 1;
1337         hse = mode->hsync_end - mode->hsync_start - 1;
1338
1339         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1340         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1341
1342         /* blank end = sync end + back porch */
1343         vbe = vse + (mode->vtotal - mode->vsync_end);
1344         hbe = hse + (mode->htotal - mode->hsync_end);
1345
1346         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1347         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1348
1349         /* blank start = blank end + active */
1350         vbs = vbe + mode->vdisplay;
1351         hbs = hbe + mode->hdisplay;
1352
1353         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1354         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1355
1356         /* XXX interlacing support */
1357         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1358 }
1359
1360 static int tegra_sor_detach(struct tegra_sor *sor)
1361 {
1362         unsigned long value, timeout;
1363
1364         /* switch to safe mode */
1365         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1366         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1367         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1368         tegra_sor_super_update(sor);
1369
1370         timeout = jiffies + msecs_to_jiffies(250);
1371
1372         while (time_before(jiffies, timeout)) {
1373                 value = tegra_sor_readl(sor, SOR_PWR);
1374                 if (value & SOR_PWR_MODE_SAFE)
1375                         break;
1376         }
1377
1378         if ((value & SOR_PWR_MODE_SAFE) == 0)
1379                 return -ETIMEDOUT;
1380
1381         /* go to sleep */
1382         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1383         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1384         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1385         tegra_sor_super_update(sor);
1386
1387         /* detach */
1388         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1389         value &= ~SOR_SUPER_STATE_ATTACHED;
1390         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1391         tegra_sor_super_update(sor);
1392
1393         timeout = jiffies + msecs_to_jiffies(250);
1394
1395         while (time_before(jiffies, timeout)) {
1396                 value = tegra_sor_readl(sor, SOR_TEST);
1397                 if ((value & SOR_TEST_ATTACHED) == 0)
1398                         break;
1399
1400                 usleep_range(25, 100);
1401         }
1402
1403         if ((value & SOR_TEST_ATTACHED) != 0)
1404                 return -ETIMEDOUT;
1405
1406         return 0;
1407 }
1408
1409 static int tegra_sor_power_down(struct tegra_sor *sor)
1410 {
1411         unsigned long value, timeout;
1412         int err;
1413
1414         value = tegra_sor_readl(sor, SOR_PWR);
1415         value &= ~SOR_PWR_NORMAL_STATE_PU;
1416         value |= SOR_PWR_TRIGGER;
1417         tegra_sor_writel(sor, value, SOR_PWR);
1418
1419         timeout = jiffies + msecs_to_jiffies(250);
1420
1421         while (time_before(jiffies, timeout)) {
1422                 value = tegra_sor_readl(sor, SOR_PWR);
1423                 if ((value & SOR_PWR_TRIGGER) == 0)
1424                         return 0;
1425
1426                 usleep_range(25, 100);
1427         }
1428
1429         if ((value & SOR_PWR_TRIGGER) != 0)
1430                 return -ETIMEDOUT;
1431
1432         /* switch to safe parent clock */
1433         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1434         if (err < 0) {
1435                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1436                 return err;
1437         }
1438
1439         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1440         value |= SOR_PLL2_PORT_POWERDOWN;
1441         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1442
1443         usleep_range(20, 100);
1444
1445         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1446         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1447         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1448
1449         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1450         value |= SOR_PLL2_SEQ_PLLCAPPD;
1451         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1452         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1453
1454         usleep_range(20, 100);
1455
1456         return 0;
1457 }
1458
1459 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1460 {
1461         u32 value;
1462
1463         timeout = jiffies + msecs_to_jiffies(timeout);
1464
1465         while (time_before(jiffies, timeout)) {
1466                 value = tegra_sor_readl(sor, SOR_CRCA);
1467                 if (value & SOR_CRCA_VALID)
1468                         return 0;
1469
1470                 usleep_range(100, 200);
1471         }
1472
1473         return -ETIMEDOUT;
1474 }
1475
1476 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1477 {
1478         struct drm_info_node *node = s->private;
1479         struct tegra_sor *sor = node->info_ent->data;
1480         struct drm_crtc *crtc = sor->output.encoder.crtc;
1481         struct drm_device *drm = node->minor->dev;
1482         int err = 0;
1483         u32 value;
1484
1485         drm_modeset_lock_all(drm);
1486
1487         if (!crtc || !crtc->state->active) {
1488                 err = -EBUSY;
1489                 goto unlock;
1490         }
1491
1492         value = tegra_sor_readl(sor, SOR_STATE1);
1493         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1494         tegra_sor_writel(sor, value, SOR_STATE1);
1495
1496         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1497         value |= SOR_CRC_CNTRL_ENABLE;
1498         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1499
1500         value = tegra_sor_readl(sor, SOR_TEST);
1501         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1502         tegra_sor_writel(sor, value, SOR_TEST);
1503
1504         err = tegra_sor_crc_wait(sor, 100);
1505         if (err < 0)
1506                 goto unlock;
1507
1508         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1509         value = tegra_sor_readl(sor, SOR_CRCB);
1510
1511         seq_printf(s, "%08x\n", value);
1512
1513 unlock:
1514         drm_modeset_unlock_all(drm);
1515         return err;
1516 }
1517
1518 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1519
1520 static const struct debugfs_reg32 tegra_sor_regs[] = {
1521         DEBUGFS_REG32(SOR_CTXSW),
1522         DEBUGFS_REG32(SOR_SUPER_STATE0),
1523         DEBUGFS_REG32(SOR_SUPER_STATE1),
1524         DEBUGFS_REG32(SOR_STATE0),
1525         DEBUGFS_REG32(SOR_STATE1),
1526         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1527         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1528         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1529         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1530         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1531         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1532         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1533         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1534         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1535         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1536         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1537         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1538         DEBUGFS_REG32(SOR_CRC_CNTRL),
1539         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1540         DEBUGFS_REG32(SOR_CLK_CNTRL),
1541         DEBUGFS_REG32(SOR_CAP),
1542         DEBUGFS_REG32(SOR_PWR),
1543         DEBUGFS_REG32(SOR_TEST),
1544         DEBUGFS_REG32(SOR_PLL0),
1545         DEBUGFS_REG32(SOR_PLL1),
1546         DEBUGFS_REG32(SOR_PLL2),
1547         DEBUGFS_REG32(SOR_PLL3),
1548         DEBUGFS_REG32(SOR_CSTM),
1549         DEBUGFS_REG32(SOR_LVDS),
1550         DEBUGFS_REG32(SOR_CRCA),
1551         DEBUGFS_REG32(SOR_CRCB),
1552         DEBUGFS_REG32(SOR_BLANK),
1553         DEBUGFS_REG32(SOR_SEQ_CTL),
1554         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1555         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1556         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1557         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1558         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1559         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1560         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1561         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1562         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1563         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1564         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1565         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1566         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1567         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1568         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1571         DEBUGFS_REG32(SOR_PWM_DIV),
1572         DEBUGFS_REG32(SOR_PWM_CTL),
1573         DEBUGFS_REG32(SOR_VCRC_A0),
1574         DEBUGFS_REG32(SOR_VCRC_A1),
1575         DEBUGFS_REG32(SOR_VCRC_B0),
1576         DEBUGFS_REG32(SOR_VCRC_B1),
1577         DEBUGFS_REG32(SOR_CCRC_A0),
1578         DEBUGFS_REG32(SOR_CCRC_A1),
1579         DEBUGFS_REG32(SOR_CCRC_B0),
1580         DEBUGFS_REG32(SOR_CCRC_B1),
1581         DEBUGFS_REG32(SOR_EDATA_A0),
1582         DEBUGFS_REG32(SOR_EDATA_A1),
1583         DEBUGFS_REG32(SOR_EDATA_B0),
1584         DEBUGFS_REG32(SOR_EDATA_B1),
1585         DEBUGFS_REG32(SOR_COUNT_A0),
1586         DEBUGFS_REG32(SOR_COUNT_A1),
1587         DEBUGFS_REG32(SOR_COUNT_B0),
1588         DEBUGFS_REG32(SOR_COUNT_B1),
1589         DEBUGFS_REG32(SOR_DEBUG_A0),
1590         DEBUGFS_REG32(SOR_DEBUG_A1),
1591         DEBUGFS_REG32(SOR_DEBUG_B0),
1592         DEBUGFS_REG32(SOR_DEBUG_B1),
1593         DEBUGFS_REG32(SOR_TRIG),
1594         DEBUGFS_REG32(SOR_MSCHECK),
1595         DEBUGFS_REG32(SOR_XBAR_CTRL),
1596         DEBUGFS_REG32(SOR_XBAR_POL),
1597         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1598         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1599         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1600         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1601         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1602         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1603         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1604         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1605         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1606         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1607         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1608         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1609         DEBUGFS_REG32(SOR_DP_CONFIG0),
1610         DEBUGFS_REG32(SOR_DP_CONFIG1),
1611         DEBUGFS_REG32(SOR_DP_MN0),
1612         DEBUGFS_REG32(SOR_DP_MN1),
1613         DEBUGFS_REG32(SOR_DP_PADCTL0),
1614         DEBUGFS_REG32(SOR_DP_PADCTL1),
1615         DEBUGFS_REG32(SOR_DP_PADCTL2),
1616         DEBUGFS_REG32(SOR_DP_DEBUG0),
1617         DEBUGFS_REG32(SOR_DP_DEBUG1),
1618         DEBUGFS_REG32(SOR_DP_SPARE0),
1619         DEBUGFS_REG32(SOR_DP_SPARE1),
1620         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1621         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1622         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1623         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1624         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1625         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1626         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1627         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1628         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1629         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1630         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1631         DEBUGFS_REG32(SOR_DP_TPG),
1632         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1633         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1634         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1635         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1636 };
1637
1638 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1639 {
1640         struct drm_info_node *node = s->private;
1641         struct tegra_sor *sor = node->info_ent->data;
1642         struct drm_crtc *crtc = sor->output.encoder.crtc;
1643         struct drm_device *drm = node->minor->dev;
1644         unsigned int i;
1645         int err = 0;
1646
1647         drm_modeset_lock_all(drm);
1648
1649         if (!crtc || !crtc->state->active) {
1650                 err = -EBUSY;
1651                 goto unlock;
1652         }
1653
1654         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1655                 unsigned int offset = tegra_sor_regs[i].offset;
1656
1657                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1658                            offset, tegra_sor_readl(sor, offset));
1659         }
1660
1661 unlock:
1662         drm_modeset_unlock_all(drm);
1663         return err;
1664 }
1665
1666 static const struct drm_info_list debugfs_files[] = {
1667         { "crc", tegra_sor_show_crc, 0, NULL },
1668         { "regs", tegra_sor_show_regs, 0, NULL },
1669 };
1670
1671 static int tegra_sor_late_register(struct drm_connector *connector)
1672 {
1673         struct tegra_output *output = connector_to_output(connector);
1674         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1675         struct drm_minor *minor = connector->dev->primary;
1676         struct dentry *root = connector->debugfs_entry;
1677         struct tegra_sor *sor = to_sor(output);
1678         int err;
1679
1680         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1681                                      GFP_KERNEL);
1682         if (!sor->debugfs_files)
1683                 return -ENOMEM;
1684
1685         for (i = 0; i < count; i++)
1686                 sor->debugfs_files[i].data = sor;
1687
1688         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1689         if (err < 0)
1690                 goto free;
1691
1692         return 0;
1693
1694 free:
1695         kfree(sor->debugfs_files);
1696         sor->debugfs_files = NULL;
1697
1698         return err;
1699 }
1700
1701 static void tegra_sor_early_unregister(struct drm_connector *connector)
1702 {
1703         struct tegra_output *output = connector_to_output(connector);
1704         unsigned int count = ARRAY_SIZE(debugfs_files);
1705         struct tegra_sor *sor = to_sor(output);
1706
1707         drm_debugfs_remove_files(sor->debugfs_files, count,
1708                                  connector->dev->primary);
1709         kfree(sor->debugfs_files);
1710         sor->debugfs_files = NULL;
1711 }
1712
1713 static void tegra_sor_connector_reset(struct drm_connector *connector)
1714 {
1715         struct tegra_sor_state *state;
1716
1717         state = kzalloc(sizeof(*state), GFP_KERNEL);
1718         if (!state)
1719                 return;
1720
1721         if (connector->state) {
1722                 __drm_atomic_helper_connector_destroy_state(connector->state);
1723                 kfree(connector->state);
1724         }
1725
1726         __drm_atomic_helper_connector_reset(connector, &state->base);
1727 }
1728
1729 static enum drm_connector_status
1730 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1731 {
1732         struct tegra_output *output = connector_to_output(connector);
1733         struct tegra_sor *sor = to_sor(output);
1734
1735         if (sor->aux)
1736                 return drm_dp_aux_detect(sor->aux);
1737
1738         return tegra_output_connector_detect(connector, force);
1739 }
1740
1741 static struct drm_connector_state *
1742 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1743 {
1744         struct tegra_sor_state *state = to_sor_state(connector->state);
1745         struct tegra_sor_state *copy;
1746
1747         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1748         if (!copy)
1749                 return NULL;
1750
1751         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1752
1753         return &copy->base;
1754 }
1755
1756 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1757         .reset = tegra_sor_connector_reset,
1758         .detect = tegra_sor_connector_detect,
1759         .fill_modes = drm_helper_probe_single_connector_modes,
1760         .destroy = tegra_output_connector_destroy,
1761         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1762         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1763         .late_register = tegra_sor_late_register,
1764         .early_unregister = tegra_sor_early_unregister,
1765 };
1766
1767 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1768 {
1769         struct tegra_output *output = connector_to_output(connector);
1770         struct tegra_sor *sor = to_sor(output);
1771         int err;
1772
1773         if (sor->aux)
1774                 drm_dp_aux_enable(sor->aux);
1775
1776         err = tegra_output_connector_get_modes(connector);
1777
1778         if (sor->aux)
1779                 drm_dp_aux_disable(sor->aux);
1780
1781         return err;
1782 }
1783
1784 static enum drm_mode_status
1785 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1786                                struct drm_display_mode *mode)
1787 {
1788         return MODE_OK;
1789 }
1790
1791 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1792         .get_modes = tegra_sor_connector_get_modes,
1793         .mode_valid = tegra_sor_connector_mode_valid,
1794 };
1795
1796 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1797         .destroy = tegra_output_encoder_destroy,
1798 };
1799
1800 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1801 {
1802         struct tegra_output *output = encoder_to_output(encoder);
1803         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1804         struct tegra_sor *sor = to_sor(output);
1805         u32 value;
1806         int err;
1807
1808         if (output->panel)
1809                 drm_panel_disable(output->panel);
1810
1811         err = tegra_sor_detach(sor);
1812         if (err < 0)
1813                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1814
1815         tegra_sor_writel(sor, 0, SOR_STATE1);
1816         tegra_sor_update(sor);
1817
1818         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1819         value &= ~SOR_ENABLE(0);
1820         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1821
1822         tegra_dc_commit(dc);
1823
1824         err = tegra_sor_power_down(sor);
1825         if (err < 0)
1826                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1827
1828         if (sor->aux) {
1829                 err = drm_dp_aux_disable(sor->aux);
1830                 if (err < 0)
1831                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1832         }
1833
1834         err = tegra_io_pad_power_disable(sor->pad);
1835         if (err < 0)
1836                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1837
1838         if (output->panel)
1839                 drm_panel_unprepare(output->panel);
1840
1841         pm_runtime_put(sor->dev);
1842 }
1843
1844 #if 0
1845 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1846                               unsigned int *value)
1847 {
1848         unsigned int hfp, hsw, hbp, a = 0, b;
1849
1850         hfp = mode->hsync_start - mode->hdisplay;
1851         hsw = mode->hsync_end - mode->hsync_start;
1852         hbp = mode->htotal - mode->hsync_end;
1853
1854         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1855
1856         b = hfp - 1;
1857
1858         pr_info("a: %u, b: %u\n", a, b);
1859         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1860
1861         if (a + hsw + hbp <= 11) {
1862                 a = 1 + 11 - hsw - hbp;
1863                 pr_info("a: %u\n", a);
1864         }
1865
1866         if (a > b)
1867                 return -EINVAL;
1868
1869         if (hsw < 1)
1870                 return -EINVAL;
1871
1872         if (mode->hdisplay < 16)
1873                 return -EINVAL;
1874
1875         if (value) {
1876                 if (b > a && a % 2)
1877                         *value = a + 1;
1878                 else
1879                         *value = a;
1880         }
1881
1882         return 0;
1883 }
1884 #endif
1885
1886 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1887 {
1888         struct tegra_output *output = encoder_to_output(encoder);
1889         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1890         struct tegra_sor *sor = to_sor(output);
1891         struct tegra_sor_config config;
1892         struct tegra_sor_state *state;
1893         struct drm_display_mode *mode;
1894         struct drm_display_info *info;
1895         unsigned int i;
1896         u32 value;
1897         int err;
1898
1899         state = to_sor_state(output->connector.state);
1900         mode = &encoder->crtc->state->adjusted_mode;
1901         info = &output->connector.display_info;
1902
1903         pm_runtime_get_sync(sor->dev);
1904
1905         /* switch to safe parent clock */
1906         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1907         if (err < 0)
1908                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1909
1910         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1911         if (err < 0)
1912                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
1913
1914         usleep_range(20, 100);
1915
1916         err = drm_dp_aux_enable(sor->aux);
1917         if (err < 0)
1918                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
1919
1920         err = drm_dp_link_probe(sor->aux, &sor->link);
1921         if (err < 0)
1922                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1923
1924         tegra_sor_filter_rates(sor);
1925
1926         err = drm_dp_link_choose(&sor->link, mode, info);
1927         if (err < 0)
1928                 dev_err(sor->dev, "failed to choose link: %d\n", err);
1929
1930         if (output->panel)
1931                 drm_panel_prepare(output->panel);
1932
1933         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1934         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1935         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1936
1937         usleep_range(20, 40);
1938
1939         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1940         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1941         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1942
1943         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1944         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
1945         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1946
1947         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1948         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1949         value |= SOR_PLL2_SEQ_PLLCAPPD;
1950         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1951
1952         usleep_range(200, 400);
1953
1954         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1955         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1956         value &= ~SOR_PLL2_PORT_POWERDOWN;
1957         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1958
1959         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1960         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1961         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1962         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1963
1964         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
1965         /* XXX not in TRM */
1966         value |= SOR_DP_SPARE_PANEL_INTERNAL;
1967         value |= SOR_DP_SPARE_SEQ_ENABLE;
1968         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
1969
1970         /* XXX not in TRM */
1971         tegra_sor_writel(sor, 0, SOR_LVDS);
1972
1973         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1974         value &= ~SOR_PLL0_ICHPMP_MASK;
1975         value &= ~SOR_PLL0_VCOCAP_MASK;
1976         value |= SOR_PLL0_ICHPMP(0x1);
1977         value |= SOR_PLL0_VCOCAP(0x3);
1978         value |= SOR_PLL0_RESISTOR_EXT;
1979         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1980
1981         /* XXX not in TRM */
1982         for (value = 0, i = 0; i < 5; i++)
1983                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1984                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1985
1986         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1987         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1988
1989         /* switch to DP parent clock */
1990         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1991         if (err < 0)
1992                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1993
1994         /* use DP-A protocol */
1995         value = tegra_sor_readl(sor, SOR_STATE1);
1996         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1997         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1998         tegra_sor_writel(sor, value, SOR_STATE1);
1999
2000         /* enable port */
2001         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2002         value |= SOR_DP_LINKCTL_ENABLE;
2003         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2004
2005         tegra_sor_dp_term_calibrate(sor);
2006
2007         err = drm_dp_link_train(&sor->link);
2008         if (err < 0)
2009                 dev_err(sor->dev, "link training failed: %d\n", err);
2010         else
2011                 dev_dbg(sor->dev, "link training succeeded\n");
2012
2013         err = drm_dp_link_power_up(sor->aux, &sor->link);
2014         if (err < 0)
2015                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
2016
2017         /* compute configuration */
2018         memset(&config, 0, sizeof(config));
2019         config.bits_per_pixel = state->bpc * 3;
2020
2021         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2022         if (err < 0)
2023                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2024
2025         tegra_sor_apply_config(sor, &config);
2026
2027         err = tegra_sor_power_up(sor, 250);
2028         if (err < 0)
2029                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2030
2031         /* CSTM (LVDS, link A/B, upper) */
2032         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2033                 SOR_CSTM_UPPER;
2034         tegra_sor_writel(sor, value, SOR_CSTM);
2035
2036         /* use DP-A protocol */
2037         value = tegra_sor_readl(sor, SOR_STATE1);
2038         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2039         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2040         tegra_sor_writel(sor, value, SOR_STATE1);
2041
2042         tegra_sor_mode_set(sor, mode, state);
2043
2044         /* PWM setup */
2045         err = tegra_sor_setup_pwm(sor, 250);
2046         if (err < 0)
2047                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2048
2049         tegra_sor_update(sor);
2050
2051         err = tegra_sor_power_up(sor, 250);
2052         if (err < 0)
2053                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2054
2055         /* attach and wake up */
2056         err = tegra_sor_attach(sor);
2057         if (err < 0)
2058                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2059
2060         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2061         value |= SOR_ENABLE(0);
2062         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2063
2064         tegra_dc_commit(dc);
2065
2066         err = tegra_sor_wakeup(sor);
2067         if (err < 0)
2068                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2069
2070         if (output->panel)
2071                 drm_panel_enable(output->panel);
2072 }
2073
2074 static int
2075 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
2076                                struct drm_crtc_state *crtc_state,
2077                                struct drm_connector_state *conn_state)
2078 {
2079         struct tegra_output *output = encoder_to_output(encoder);
2080         struct tegra_sor_state *state = to_sor_state(conn_state);
2081         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
2082         unsigned long pclk = crtc_state->mode.clock * 1000;
2083         struct tegra_sor *sor = to_sor(output);
2084         struct drm_display_info *info;
2085         int err;
2086
2087         info = &output->connector.display_info;
2088
2089         /*
2090          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2091          * the pixel clock must be corrected accordingly.
2092          */
2093         if (pclk >= 340000000) {
2094                 state->link_speed = 20;
2095                 state->pclk = pclk / 2;
2096         } else {
2097                 state->link_speed = 10;
2098                 state->pclk = pclk;
2099         }
2100
2101         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2102                                          pclk, 0);
2103         if (err < 0) {
2104                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2105                 return err;
2106         }
2107
2108         switch (info->bpc) {
2109         case 8:
2110         case 6:
2111                 state->bpc = info->bpc;
2112                 break;
2113
2114         default:
2115                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2116                 state->bpc = 8;
2117                 break;
2118         }
2119
2120         return 0;
2121 }
2122
2123 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2124         .disable = tegra_sor_edp_disable,
2125         .enable = tegra_sor_edp_enable,
2126         .atomic_check = tegra_sor_encoder_atomic_check,
2127 };
2128
2129 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2130 {
2131         u32 value = 0;
2132         size_t i;
2133
2134         for (i = size; i > 0; i--)
2135                 value = (value << 8) | ptr[i - 1];
2136
2137         return value;
2138 }
2139
2140 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2141                                           const void *data, size_t size)
2142 {
2143         const u8 *ptr = data;
2144         unsigned long offset;
2145         size_t i, j;
2146         u32 value;
2147
2148         switch (ptr[0]) {
2149         case HDMI_INFOFRAME_TYPE_AVI:
2150                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2151                 break;
2152
2153         case HDMI_INFOFRAME_TYPE_AUDIO:
2154                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2155                 break;
2156
2157         case HDMI_INFOFRAME_TYPE_VENDOR:
2158                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2159                 break;
2160
2161         default:
2162                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2163                         ptr[0]);
2164                 return;
2165         }
2166
2167         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2168                 INFOFRAME_HEADER_VERSION(ptr[1]) |
2169                 INFOFRAME_HEADER_LEN(ptr[2]);
2170         tegra_sor_writel(sor, value, offset);
2171         offset++;
2172
2173         /*
2174          * Each subpack contains 7 bytes, divided into:
2175          * - subpack_low: bytes 0 - 3
2176          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2177          */
2178         for (i = 3, j = 0; i < size; i += 7, j += 8) {
2179                 size_t rem = size - i, num = min_t(size_t, rem, 4);
2180
2181                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2182                 tegra_sor_writel(sor, value, offset++);
2183
2184                 num = min_t(size_t, rem - num, 3);
2185
2186                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2187                 tegra_sor_writel(sor, value, offset++);
2188         }
2189 }
2190
2191 static int
2192 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2193                                    const struct drm_display_mode *mode)
2194 {
2195         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2196         struct hdmi_avi_infoframe frame;
2197         u32 value;
2198         int err;
2199
2200         /* disable AVI infoframe */
2201         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2202         value &= ~INFOFRAME_CTRL_SINGLE;
2203         value &= ~INFOFRAME_CTRL_OTHER;
2204         value &= ~INFOFRAME_CTRL_ENABLE;
2205         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2206
2207         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2208                                                        &sor->output.connector, mode);
2209         if (err < 0) {
2210                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2211                 return err;
2212         }
2213
2214         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2215         if (err < 0) {
2216                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2217                 return err;
2218         }
2219
2220         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2221
2222         /* enable AVI infoframe */
2223         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2224         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2225         value |= INFOFRAME_CTRL_ENABLE;
2226         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2227
2228         return 0;
2229 }
2230
2231 static void tegra_sor_write_eld(struct tegra_sor *sor)
2232 {
2233         size_t length = drm_eld_size(sor->output.connector.eld), i;
2234
2235         for (i = 0; i < length; i++)
2236                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2237                                  SOR_AUDIO_HDA_ELD_BUFWR);
2238
2239         /*
2240          * The HDA codec will always report an ELD buffer size of 96 bytes and
2241          * the HDA codec driver will check that each byte read from the buffer
2242          * is valid. Therefore every byte must be written, even if no 96 bytes
2243          * were parsed from EDID.
2244          */
2245         for (i = length; i < 96; i++)
2246                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2247 }
2248
2249 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2250 {
2251         u32 value;
2252
2253         /*
2254          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2255          * is used for interoperability between the HDA codec driver and the
2256          * HDMI/DP driver.
2257          */
2258         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2259         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2260         tegra_sor_writel(sor, value, SOR_INT_MASK);
2261
2262         tegra_sor_write_eld(sor);
2263
2264         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2265         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2266 }
2267
2268 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2269 {
2270         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2271         tegra_sor_writel(sor, 0, SOR_INT_MASK);
2272         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2273 }
2274
2275 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2276 {
2277         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2278         struct hdmi_audio_infoframe frame;
2279         u32 value;
2280         int err;
2281
2282         err = hdmi_audio_infoframe_init(&frame);
2283         if (err < 0) {
2284                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2285                 return err;
2286         }
2287
2288         frame.channels = sor->format.channels;
2289
2290         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2291         if (err < 0) {
2292                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2293                 return err;
2294         }
2295
2296         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2297
2298         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2299         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2300         value |= INFOFRAME_CTRL_ENABLE;
2301         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2302
2303         return 0;
2304 }
2305
2306 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2307 {
2308         u32 value;
2309
2310         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2311
2312         /* select HDA audio input */
2313         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2314         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2315
2316         /* inject null samples */
2317         if (sor->format.channels != 2)
2318                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2319         else
2320                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2321
2322         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2323
2324         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2325
2326         /* enable advertising HBR capability */
2327         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2328
2329         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2330
2331         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2332                 SOR_HDMI_SPARE_CTS_RESET(1) |
2333                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2334         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2335
2336         /* enable HW CTS */
2337         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2338         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2339
2340         /* allow packet to be sent */
2341         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2342         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2343
2344         /* reset N counter and enable lookup */
2345         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2346         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2347
2348         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2349         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2350         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2351
2352         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2353         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2354
2355         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2356         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2357
2358         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2359         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2360
2361         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2362         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2363         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2364
2365         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2366         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2367         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2368
2369         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2370         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2371         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2372
2373         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2374         value &= ~SOR_HDMI_AUDIO_N_RESET;
2375         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2376
2377         tegra_sor_hdmi_enable_audio_infoframe(sor);
2378 }
2379
2380 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2381 {
2382         u32 value;
2383
2384         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2385         value &= ~INFOFRAME_CTRL_ENABLE;
2386         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2387 }
2388
2389 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2390 {
2391         tegra_sor_hdmi_disable_audio_infoframe(sor);
2392 }
2393
2394 static struct tegra_sor_hdmi_settings *
2395 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2396 {
2397         unsigned int i;
2398
2399         for (i = 0; i < sor->num_settings; i++)
2400                 if (frequency <= sor->settings[i].frequency)
2401                         return &sor->settings[i];
2402
2403         return NULL;
2404 }
2405
2406 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2407 {
2408         u32 value;
2409
2410         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2411         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2412         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2413         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2414 }
2415
2416 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2417 {
2418         struct i2c_adapter *ddc = sor->output.ddc;
2419
2420         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2421         drm_scdc_set_scrambling(ddc, false);
2422
2423         tegra_sor_hdmi_disable_scrambling(sor);
2424 }
2425
2426 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2427 {
2428         if (sor->scdc_enabled) {
2429                 cancel_delayed_work_sync(&sor->scdc);
2430                 tegra_sor_hdmi_scdc_disable(sor);
2431         }
2432 }
2433
2434 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2435 {
2436         u32 value;
2437
2438         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2439         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2440         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2441         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2442 }
2443
2444 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2445 {
2446         struct i2c_adapter *ddc = sor->output.ddc;
2447
2448         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2449         drm_scdc_set_scrambling(ddc, true);
2450
2451         tegra_sor_hdmi_enable_scrambling(sor);
2452 }
2453
2454 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2455 {
2456         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2457         struct i2c_adapter *ddc = sor->output.ddc;
2458
2459         if (!drm_scdc_get_scrambling_status(ddc)) {
2460                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2461                 tegra_sor_hdmi_scdc_enable(sor);
2462         }
2463
2464         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2465 }
2466
2467 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2468 {
2469         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2470         struct drm_display_mode *mode;
2471
2472         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2473
2474         if (mode->clock >= 340000 && scdc->supported) {
2475                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2476                 tegra_sor_hdmi_scdc_enable(sor);
2477                 sor->scdc_enabled = true;
2478         }
2479 }
2480
2481 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2482 {
2483         struct tegra_output *output = encoder_to_output(encoder);
2484         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2485         struct tegra_sor *sor = to_sor(output);
2486         u32 value;
2487         int err;
2488
2489         tegra_sor_audio_unprepare(sor);
2490         tegra_sor_hdmi_scdc_stop(sor);
2491
2492         err = tegra_sor_detach(sor);
2493         if (err < 0)
2494                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2495
2496         tegra_sor_writel(sor, 0, SOR_STATE1);
2497         tegra_sor_update(sor);
2498
2499         /* disable display to SOR clock */
2500         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2501
2502         if (!sor->soc->has_nvdisplay)
2503                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2504         else
2505                 value &= ~SOR_ENABLE(sor->index);
2506
2507         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2508
2509         tegra_dc_commit(dc);
2510
2511         err = tegra_sor_power_down(sor);
2512         if (err < 0)
2513                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2514
2515         err = tegra_io_pad_power_disable(sor->pad);
2516         if (err < 0)
2517                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2518
2519         pm_runtime_put(sor->dev);
2520 }
2521
2522 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2523 {
2524         struct tegra_output *output = encoder_to_output(encoder);
2525         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2526         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2527         struct tegra_sor_hdmi_settings *settings;
2528         struct tegra_sor *sor = to_sor(output);
2529         struct tegra_sor_state *state;
2530         struct drm_display_mode *mode;
2531         unsigned long rate, pclk;
2532         unsigned int div, i;
2533         u32 value;
2534         int err;
2535
2536         state = to_sor_state(output->connector.state);
2537         mode = &encoder->crtc->state->adjusted_mode;
2538         pclk = mode->clock * 1000;
2539
2540         pm_runtime_get_sync(sor->dev);
2541
2542         /* switch to safe parent clock */
2543         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2544         if (err < 0) {
2545                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2546                 return;
2547         }
2548
2549         div = clk_get_rate(sor->clk) / 1000000 * 4;
2550
2551         err = tegra_io_pad_power_enable(sor->pad);
2552         if (err < 0)
2553                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2554
2555         usleep_range(20, 100);
2556
2557         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2558         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2559         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2560
2561         usleep_range(20, 100);
2562
2563         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2564         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2565         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2566
2567         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2568         value &= ~SOR_PLL0_VCOPD;
2569         value &= ~SOR_PLL0_PWR;
2570         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2571
2572         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2573         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2574         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2575
2576         usleep_range(200, 400);
2577
2578         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2579         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2580         value &= ~SOR_PLL2_PORT_POWERDOWN;
2581         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2582
2583         usleep_range(20, 100);
2584
2585         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2586         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2587                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2588         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2589
2590         while (true) {
2591                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2592                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2593                         break;
2594
2595                 usleep_range(250, 1000);
2596         }
2597
2598         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2599                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2600         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2601
2602         while (true) {
2603                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2604                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2605                         break;
2606
2607                 usleep_range(250, 1000);
2608         }
2609
2610         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2611         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2612         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2613
2614         if (mode->clock < 340000) {
2615                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2616                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2617         } else {
2618                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2619                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2620         }
2621
2622         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2623         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2624
2625         /* SOR pad PLL stabilization time */
2626         usleep_range(250, 1000);
2627
2628         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2629         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2630         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2631         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2632
2633         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2634         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2635         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2636         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2637         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2638         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2639
2640         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2641                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2642         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2643
2644         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2645                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2646         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2647         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2648
2649         if (!sor->soc->has_nvdisplay) {
2650                 /* program the reference clock */
2651                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2652                 tegra_sor_writel(sor, value, SOR_REFCLK);
2653         }
2654
2655         /* XXX not in TRM */
2656         for (value = 0, i = 0; i < 5; i++)
2657                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2658                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2659
2660         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2661         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2662
2663         /* switch to parent clock */
2664         err = clk_set_parent(sor->clk, sor->clk_parent);
2665         if (err < 0) {
2666                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2667                 return;
2668         }
2669
2670         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2671         if (err < 0) {
2672                 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2673                 return;
2674         }
2675
2676         /* adjust clock rate for HDMI 2.0 modes */
2677         rate = clk_get_rate(sor->clk_parent);
2678
2679         if (mode->clock >= 340000)
2680                 rate /= 2;
2681
2682         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2683
2684         clk_set_rate(sor->clk, rate);
2685
2686         if (!sor->soc->has_nvdisplay) {
2687                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2688
2689                 /* XXX is this the proper check? */
2690                 if (mode->clock < 75000)
2691                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2692
2693                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2694         }
2695
2696         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2697
2698         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2699                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2700         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2701
2702         if (!dc->soc->has_nvdisplay) {
2703                 /* H_PULSE2 setup */
2704                 pulse_start = h_ref_to_sync +
2705                               (mode->hsync_end - mode->hsync_start) +
2706                               (mode->htotal - mode->hsync_end) - 10;
2707
2708                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2709                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2710                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2711
2712                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2713                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2714
2715                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2716                 value |= H_PULSE2_ENABLE;
2717                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2718         }
2719
2720         /* infoframe setup */
2721         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2722         if (err < 0)
2723                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2724
2725         /* XXX HDMI audio support not implemented yet */
2726         tegra_sor_hdmi_disable_audio_infoframe(sor);
2727
2728         /* use single TMDS protocol */
2729         value = tegra_sor_readl(sor, SOR_STATE1);
2730         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2731         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2732         tegra_sor_writel(sor, value, SOR_STATE1);
2733
2734         /* power up pad calibration */
2735         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2736         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2737         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2738
2739         /* production settings */
2740         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2741         if (!settings) {
2742                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2743                         mode->clock * 1000);
2744                 return;
2745         }
2746
2747         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2748         value &= ~SOR_PLL0_ICHPMP_MASK;
2749         value &= ~SOR_PLL0_FILTER_MASK;
2750         value &= ~SOR_PLL0_VCOCAP_MASK;
2751         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2752         value |= SOR_PLL0_FILTER(settings->filter);
2753         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2754         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2755
2756         /* XXX not in TRM */
2757         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2758         value &= ~SOR_PLL1_LOADADJ_MASK;
2759         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2760         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2761         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2762         value |= SOR_PLL1_TMDS_TERM;
2763         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2764
2765         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2766         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2767         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2768         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2769         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2770         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2771         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2772         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2773         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2774         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2775
2776         value = settings->drive_current[3] << 24 |
2777                 settings->drive_current[2] << 16 |
2778                 settings->drive_current[1] <<  8 |
2779                 settings->drive_current[0] <<  0;
2780         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2781
2782         value = settings->preemphasis[3] << 24 |
2783                 settings->preemphasis[2] << 16 |
2784                 settings->preemphasis[1] <<  8 |
2785                 settings->preemphasis[0] <<  0;
2786         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2787
2788         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2789         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2790         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2791         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2792         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2793
2794         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2795         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2796         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2797         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2798
2799         /* power down pad calibration */
2800         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2801         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2802         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2803
2804         if (!dc->soc->has_nvdisplay) {
2805                 /* miscellaneous display controller settings */
2806                 value = VSYNC_H_POSITION(1);
2807                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2808         }
2809
2810         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2811         value &= ~DITHER_CONTROL_MASK;
2812         value &= ~BASE_COLOR_SIZE_MASK;
2813
2814         switch (state->bpc) {
2815         case 6:
2816                 value |= BASE_COLOR_SIZE_666;
2817                 break;
2818
2819         case 8:
2820                 value |= BASE_COLOR_SIZE_888;
2821                 break;
2822
2823         case 10:
2824                 value |= BASE_COLOR_SIZE_101010;
2825                 break;
2826
2827         case 12:
2828                 value |= BASE_COLOR_SIZE_121212;
2829                 break;
2830
2831         default:
2832                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2833                 value |= BASE_COLOR_SIZE_888;
2834                 break;
2835         }
2836
2837         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2838
2839         /* XXX set display head owner */
2840         value = tegra_sor_readl(sor, SOR_STATE1);
2841         value &= ~SOR_STATE_ASY_OWNER_MASK;
2842         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2843         tegra_sor_writel(sor, value, SOR_STATE1);
2844
2845         err = tegra_sor_power_up(sor, 250);
2846         if (err < 0)
2847                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2848
2849         /* configure dynamic range of output */
2850         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2851         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2852         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2853         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2854
2855         /* configure colorspace */
2856         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2857         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2858         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2859         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2860
2861         tegra_sor_mode_set(sor, mode, state);
2862
2863         tegra_sor_update(sor);
2864
2865         /* program preamble timing in SOR (XXX) */
2866         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2867         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2868         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2869
2870         err = tegra_sor_attach(sor);
2871         if (err < 0)
2872                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2873
2874         /* enable display to SOR clock and generate HDMI preamble */
2875         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2876
2877         if (!sor->soc->has_nvdisplay)
2878                 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2879         else
2880                 value |= SOR_ENABLE(sor->index);
2881
2882         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2883
2884         if (dc->soc->has_nvdisplay) {
2885                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2886                 value &= ~PROTOCOL_MASK;
2887                 value |= PROTOCOL_SINGLE_TMDS_A;
2888                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2889         }
2890
2891         tegra_dc_commit(dc);
2892
2893         err = tegra_sor_wakeup(sor);
2894         if (err < 0)
2895                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2896
2897         tegra_sor_hdmi_scdc_start(sor);
2898         tegra_sor_audio_prepare(sor);
2899 }
2900
2901 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2902         .disable = tegra_sor_hdmi_disable,
2903         .enable = tegra_sor_hdmi_enable,
2904         .atomic_check = tegra_sor_encoder_atomic_check,
2905 };
2906
2907 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2908 {
2909         struct tegra_output *output = encoder_to_output(encoder);
2910         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2911         struct tegra_sor *sor = to_sor(output);
2912         u32 value;
2913         int err;
2914
2915         err = drm_dp_link_power_down(sor->aux, &sor->link);
2916         if (err < 0)
2917                 dev_err(sor->dev, "failed to power down link: %d\n", err);
2918
2919         err = tegra_sor_detach(sor);
2920         if (err < 0)
2921                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2922
2923         tegra_sor_writel(sor, 0, SOR_STATE1);
2924         tegra_sor_update(sor);
2925
2926         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2927
2928         if (!sor->soc->has_nvdisplay)
2929                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2930         else
2931                 value &= ~SOR_ENABLE(sor->index);
2932
2933         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2934         tegra_dc_commit(dc);
2935
2936         value = tegra_sor_readl(sor, SOR_STATE1);
2937         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2938         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2939         value &= ~SOR_STATE_ASY_OWNER_MASK;
2940         tegra_sor_writel(sor, value, SOR_STATE1);
2941         tegra_sor_update(sor);
2942
2943         /* switch to safe parent clock */
2944         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2945         if (err < 0)
2946                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2947
2948         err = tegra_sor_power_down(sor);
2949         if (err < 0)
2950                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2951
2952         err = tegra_io_pad_power_disable(sor->pad);
2953         if (err < 0)
2954                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2955
2956         err = drm_dp_aux_disable(sor->aux);
2957         if (err < 0)
2958                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2959
2960         pm_runtime_put(sor->dev);
2961 }
2962
2963 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2964 {
2965         struct tegra_output *output = encoder_to_output(encoder);
2966         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2967         struct tegra_sor *sor = to_sor(output);
2968         struct tegra_sor_config config;
2969         struct tegra_sor_state *state;
2970         struct drm_display_mode *mode;
2971         struct drm_display_info *info;
2972         unsigned int i;
2973         u32 value;
2974         int err;
2975
2976         state = to_sor_state(output->connector.state);
2977         mode = &encoder->crtc->state->adjusted_mode;
2978         info = &output->connector.display_info;
2979
2980         pm_runtime_get_sync(sor->dev);
2981
2982         /* switch to safe parent clock */
2983         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2984         if (err < 0)
2985                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2986
2987         err = tegra_io_pad_power_enable(sor->pad);
2988         if (err < 0)
2989                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2990
2991         usleep_range(20, 100);
2992
2993         err = drm_dp_aux_enable(sor->aux);
2994         if (err < 0)
2995                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2996
2997         err = drm_dp_link_probe(sor->aux, &sor->link);
2998         if (err < 0)
2999                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
3000
3001         err = drm_dp_link_choose(&sor->link, mode, info);
3002         if (err < 0)
3003                 dev_err(sor->dev, "failed to choose link: %d\n", err);
3004
3005         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3006         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
3007         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3008
3009         usleep_range(20, 40);
3010
3011         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
3012         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
3013         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
3014
3015         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3016         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
3017         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3018
3019         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3020         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
3021         value |= SOR_PLL2_SEQ_PLLCAPPD;
3022         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3023
3024         usleep_range(200, 400);
3025
3026         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3027         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
3028         value &= ~SOR_PLL2_PORT_POWERDOWN;
3029         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3030
3031         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
3032         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
3033         value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
3034         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
3035
3036         usleep_range(200, 400);
3037
3038         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
3039         /* XXX not in TRM */
3040         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
3041         value |= SOR_DP_SPARE_SEQ_ENABLE;
3042         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
3043
3044         /* XXX not in TRM */
3045         tegra_sor_writel(sor, 0, SOR_LVDS);
3046
3047         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3048         value &= ~SOR_PLL0_ICHPMP_MASK;
3049         value &= ~SOR_PLL0_VCOCAP_MASK;
3050         value |= SOR_PLL0_ICHPMP(0x1);
3051         value |= SOR_PLL0_VCOCAP(0x3);
3052         value |= SOR_PLL0_RESISTOR_EXT;
3053         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3054
3055         /* XXX not in TRM */
3056         for (value = 0, i = 0; i < 5; i++)
3057                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
3058                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
3059
3060         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
3061         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
3062
3063         /* switch to DP parent clock */
3064         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
3065         if (err < 0) {
3066                 dev_err(sor->dev, "failed to switch to pad clock: %d\n", err);
3067                 return;
3068         }
3069
3070         err = clk_set_parent(sor->clk, sor->clk_parent);
3071         if (err < 0) {
3072                 dev_err(sor->dev, "failed to switch to parent clock: %d\n", err);
3073                 return;
3074         }
3075
3076         /* use DP-A protocol */
3077         value = tegra_sor_readl(sor, SOR_STATE1);
3078         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
3079         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
3080         tegra_sor_writel(sor, value, SOR_STATE1);
3081
3082         /* enable port */
3083         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
3084         value |= SOR_DP_LINKCTL_ENABLE;
3085         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
3086
3087         tegra_sor_dp_term_calibrate(sor);
3088
3089         err = drm_dp_link_train(&sor->link);
3090         if (err < 0)
3091                 dev_err(sor->dev, "link training failed: %d\n", err);
3092         else
3093                 dev_dbg(sor->dev, "link training succeeded\n");
3094
3095         err = drm_dp_link_power_up(sor->aux, &sor->link);
3096         if (err < 0)
3097                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
3098
3099         /* compute configuration */
3100         memset(&config, 0, sizeof(config));
3101         config.bits_per_pixel = state->bpc * 3;
3102
3103         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
3104         if (err < 0)
3105                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
3106
3107         tegra_sor_apply_config(sor, &config);
3108         tegra_sor_mode_set(sor, mode, state);
3109         tegra_sor_update(sor);
3110
3111         err = tegra_sor_power_up(sor, 250);
3112         if (err < 0)
3113                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
3114
3115         /* attach and wake up */
3116         err = tegra_sor_attach(sor);
3117         if (err < 0)
3118                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
3119
3120         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
3121         value |= SOR_ENABLE(sor->index);
3122         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
3123
3124         tegra_dc_commit(dc);
3125
3126         err = tegra_sor_wakeup(sor);
3127         if (err < 0)
3128                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
3129 }
3130
3131 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
3132         .disable = tegra_sor_dp_disable,
3133         .enable = tegra_sor_dp_enable,
3134         .atomic_check = tegra_sor_encoder_atomic_check,
3135 };
3136
3137 static int tegra_sor_init(struct host1x_client *client)
3138 {
3139         struct drm_device *drm = dev_get_drvdata(client->parent);
3140         const struct drm_encoder_helper_funcs *helpers = NULL;
3141         struct tegra_sor *sor = host1x_client_to_sor(client);
3142         int connector = DRM_MODE_CONNECTOR_Unknown;
3143         int encoder = DRM_MODE_ENCODER_NONE;
3144         int err;
3145
3146         if (!sor->aux) {
3147                 if (sor->soc->supports_hdmi) {
3148                         connector = DRM_MODE_CONNECTOR_HDMIA;
3149                         encoder = DRM_MODE_ENCODER_TMDS;
3150                         helpers = &tegra_sor_hdmi_helpers;
3151                 } else if (sor->soc->supports_lvds) {
3152                         connector = DRM_MODE_CONNECTOR_LVDS;
3153                         encoder = DRM_MODE_ENCODER_LVDS;
3154                 }
3155         } else {
3156                 if (sor->soc->supports_edp) {
3157                         connector = DRM_MODE_CONNECTOR_eDP;
3158                         encoder = DRM_MODE_ENCODER_TMDS;
3159                         helpers = &tegra_sor_edp_helpers;
3160                 } else if (sor->soc->supports_dp) {
3161                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3162                         encoder = DRM_MODE_ENCODER_TMDS;
3163                         helpers = &tegra_sor_dp_helpers;
3164                 }
3165
3166                 sor->link.ops = &tegra_sor_dp_link_ops;
3167                 sor->link.aux = sor->aux;
3168         }
3169
3170         sor->output.dev = sor->dev;
3171
3172         drm_connector_init(drm, &sor->output.connector,
3173                            &tegra_sor_connector_funcs,
3174                            connector);
3175         drm_connector_helper_add(&sor->output.connector,
3176                                  &tegra_sor_connector_helper_funcs);
3177         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3178
3179         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
3180                          encoder, NULL);
3181         drm_encoder_helper_add(&sor->output.encoder, helpers);
3182
3183         drm_connector_attach_encoder(&sor->output.connector,
3184                                           &sor->output.encoder);
3185         drm_connector_register(&sor->output.connector);
3186
3187         err = tegra_output_init(drm, &sor->output);
3188         if (err < 0) {
3189                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3190                 return err;
3191         }
3192
3193         tegra_output_find_possible_crtcs(&sor->output, drm);
3194
3195         if (sor->aux) {
3196                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3197                 if (err < 0) {
3198                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3199                         return err;
3200                 }
3201         }
3202
3203         /*
3204          * XXX: Remove this reset once proper hand-over from firmware to
3205          * kernel is possible.
3206          */
3207         if (sor->rst) {
3208                 err = reset_control_acquire(sor->rst);
3209                 if (err < 0) {
3210                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3211                                 err);
3212                         return err;
3213                 }
3214
3215                 err = reset_control_assert(sor->rst);
3216                 if (err < 0) {
3217                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3218                                 err);
3219                         return err;
3220                 }
3221         }
3222
3223         err = clk_prepare_enable(sor->clk);
3224         if (err < 0) {
3225                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3226                 return err;
3227         }
3228
3229         usleep_range(1000, 3000);
3230
3231         if (sor->rst) {
3232                 err = reset_control_deassert(sor->rst);
3233                 if (err < 0) {
3234                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3235                                 err);
3236                         return err;
3237                 }
3238
3239                 reset_control_release(sor->rst);
3240         }
3241
3242         err = clk_prepare_enable(sor->clk_safe);
3243         if (err < 0)
3244                 return err;
3245
3246         err = clk_prepare_enable(sor->clk_dp);
3247         if (err < 0)
3248                 return err;
3249
3250         return 0;
3251 }
3252
3253 static int tegra_sor_exit(struct host1x_client *client)
3254 {
3255         struct tegra_sor *sor = host1x_client_to_sor(client);
3256         int err;
3257
3258         tegra_output_exit(&sor->output);
3259
3260         if (sor->aux) {
3261                 err = drm_dp_aux_detach(sor->aux);
3262                 if (err < 0) {
3263                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3264                         return err;
3265                 }
3266         }
3267
3268         clk_disable_unprepare(sor->clk_safe);
3269         clk_disable_unprepare(sor->clk_dp);
3270         clk_disable_unprepare(sor->clk);
3271
3272         return 0;
3273 }
3274
3275 static const struct host1x_client_ops sor_client_ops = {
3276         .init = tegra_sor_init,
3277         .exit = tegra_sor_exit,
3278 };
3279
3280 static const struct tegra_sor_ops tegra_sor_edp_ops = {
3281         .name = "eDP",
3282 };
3283
3284 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
3285 {
3286         int err;
3287
3288         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
3289         if (IS_ERR(sor->avdd_io_supply)) {
3290                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
3291                         PTR_ERR(sor->avdd_io_supply));
3292                 return PTR_ERR(sor->avdd_io_supply);
3293         }
3294
3295         err = regulator_enable(sor->avdd_io_supply);
3296         if (err < 0) {
3297                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
3298                         err);
3299                 return err;
3300         }
3301
3302         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
3303         if (IS_ERR(sor->vdd_pll_supply)) {
3304                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
3305                         PTR_ERR(sor->vdd_pll_supply));
3306                 return PTR_ERR(sor->vdd_pll_supply);
3307         }
3308
3309         err = regulator_enable(sor->vdd_pll_supply);
3310         if (err < 0) {
3311                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
3312                         err);
3313                 return err;
3314         }
3315
3316         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
3317         if (IS_ERR(sor->hdmi_supply)) {
3318                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
3319                         PTR_ERR(sor->hdmi_supply));
3320                 return PTR_ERR(sor->hdmi_supply);
3321         }
3322
3323         err = regulator_enable(sor->hdmi_supply);
3324         if (err < 0) {
3325                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3326                 return err;
3327         }
3328
3329         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3330
3331         return 0;
3332 }
3333
3334 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3335 {
3336         regulator_disable(sor->hdmi_supply);
3337         regulator_disable(sor->vdd_pll_supply);
3338         regulator_disable(sor->avdd_io_supply);
3339
3340         return 0;
3341 }
3342
3343 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3344         .name = "HDMI",
3345         .probe = tegra_sor_hdmi_probe,
3346         .remove = tegra_sor_hdmi_remove,
3347 };
3348
3349 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3350 {
3351         int err;
3352
3353         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3354         if (IS_ERR(sor->avdd_io_supply))
3355                 return PTR_ERR(sor->avdd_io_supply);
3356
3357         err = regulator_enable(sor->avdd_io_supply);
3358         if (err < 0)
3359                 return err;
3360
3361         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3362         if (IS_ERR(sor->vdd_pll_supply))
3363                 return PTR_ERR(sor->vdd_pll_supply);
3364
3365         err = regulator_enable(sor->vdd_pll_supply);
3366         if (err < 0)
3367                 return err;
3368
3369         return 0;
3370 }
3371
3372 static int tegra_sor_dp_remove(struct tegra_sor *sor)
3373 {
3374         regulator_disable(sor->vdd_pll_supply);
3375         regulator_disable(sor->avdd_io_supply);
3376
3377         return 0;
3378 }
3379
3380 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3381         .name = "DP",
3382         .probe = tegra_sor_dp_probe,
3383         .remove = tegra_sor_dp_remove,
3384 };
3385
3386 static const u8 tegra124_sor_xbar_cfg[5] = {
3387         0, 1, 2, 3, 4
3388 };
3389
3390 static const struct tegra_sor_regs tegra124_sor_regs = {
3391         .head_state0 = 0x05,
3392         .head_state1 = 0x07,
3393         .head_state2 = 0x09,
3394         .head_state3 = 0x0b,
3395         .head_state4 = 0x0d,
3396         .head_state5 = 0x0f,
3397         .pll0 = 0x17,
3398         .pll1 = 0x18,
3399         .pll2 = 0x19,
3400         .pll3 = 0x1a,
3401         .dp_padctl0 = 0x5c,
3402         .dp_padctl2 = 0x73,
3403 };
3404
3405 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3406 static const u8 tegra124_sor_lane_map[4] = {
3407         2, 1, 0, 3,
3408 };
3409
3410 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3411         {
3412                 { 0x13, 0x19, 0x1e, 0x28 },
3413                 { 0x1e, 0x25, 0x2d, },
3414                 { 0x28, 0x32, },
3415                 { 0x3c, },
3416         }, {
3417                 { 0x12, 0x17, 0x1b, 0x25 },
3418                 { 0x1c, 0x23, 0x2a, },
3419                 { 0x25, 0x2f, },
3420                 { 0x39, }
3421         }, {
3422                 { 0x12, 0x16, 0x1a, 0x22 },
3423                 { 0x1b, 0x20, 0x27, },
3424                 { 0x24, 0x2d, },
3425                 { 0x36, },
3426         }, {
3427                 { 0x11, 0x14, 0x17, 0x1f },
3428                 { 0x19, 0x1e, 0x24, },
3429                 { 0x22, 0x2a, },
3430                 { 0x32, },
3431         },
3432 };
3433
3434 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3435         {
3436                 { 0x00, 0x09, 0x13, 0x25 },
3437                 { 0x00, 0x0f, 0x1e, },
3438                 { 0x00, 0x14, },
3439                 { 0x00, },
3440         }, {
3441                 { 0x00, 0x0a, 0x14, 0x28 },
3442                 { 0x00, 0x0f, 0x1e, },
3443                 { 0x00, 0x14, },
3444                 { 0x00 },
3445         }, {
3446                 { 0x00, 0x0a, 0x14, 0x28 },
3447                 { 0x00, 0x0f, 0x1e, },
3448                 { 0x00, 0x14, },
3449                 { 0x00, },
3450         }, {
3451                 { 0x00, 0x0a, 0x14, 0x28 },
3452                 { 0x00, 0x0f, 0x1e, },
3453                 { 0x00, 0x14, },
3454                 { 0x00, },
3455         },
3456 };
3457
3458 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3459         {
3460                 { 0x00, 0x00, 0x00, 0x00 },
3461                 { 0x00, 0x00, 0x00, },
3462                 { 0x00, 0x00, },
3463                 { 0x00, },
3464         }, {
3465                 { 0x02, 0x02, 0x04, 0x05 },
3466                 { 0x02, 0x04, 0x05, },
3467                 { 0x04, 0x05, },
3468                 { 0x05, },
3469         }, {
3470                 { 0x04, 0x05, 0x08, 0x0b },
3471                 { 0x05, 0x09, 0x0b, },
3472                 { 0x08, 0x0a, },
3473                 { 0x0b, },
3474         }, {
3475                 { 0x05, 0x09, 0x0b, 0x12 },
3476                 { 0x09, 0x0d, 0x12, },
3477                 { 0x0b, 0x0f, },
3478                 { 0x12, },
3479         },
3480 };
3481
3482 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3483         {
3484                 { 0x20, 0x30, 0x40, 0x60 },
3485                 { 0x30, 0x40, 0x60, },
3486                 { 0x40, 0x60, },
3487                 { 0x60, },
3488         }, {
3489                 { 0x20, 0x20, 0x30, 0x50 },
3490                 { 0x30, 0x40, 0x50, },
3491                 { 0x40, 0x50, },
3492                 { 0x60, },
3493         }, {
3494                 { 0x20, 0x20, 0x30, 0x40, },
3495                 { 0x30, 0x30, 0x40, },
3496                 { 0x40, 0x50, },
3497                 { 0x60, },
3498         }, {
3499                 { 0x20, 0x20, 0x20, 0x40, },
3500                 { 0x30, 0x30, 0x40, },
3501                 { 0x40, 0x40, },
3502                 { 0x60, },
3503         },
3504 };
3505
3506 static const struct tegra_sor_soc tegra124_sor = {
3507         .supports_edp = true,
3508         .supports_lvds = true,
3509         .supports_hdmi = false,
3510         .supports_dp = false,
3511         .regs = &tegra124_sor_regs,
3512         .has_nvdisplay = false,
3513         .xbar_cfg = tegra124_sor_xbar_cfg,
3514         .lane_map = tegra124_sor_lane_map,
3515         .voltage_swing = tegra124_sor_voltage_swing,
3516         .pre_emphasis = tegra124_sor_pre_emphasis,
3517         .post_cursor = tegra124_sor_post_cursor,
3518         .tx_pu = tegra124_sor_tx_pu,
3519 };
3520
3521 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3522         {
3523                 { 0x00, 0x08, 0x12, 0x24 },
3524                 { 0x01, 0x0e, 0x1d, },
3525                 { 0x01, 0x13, },
3526                 { 0x00, },
3527         }, {
3528                 { 0x00, 0x08, 0x12, 0x24 },
3529                 { 0x00, 0x0e, 0x1d, },
3530                 { 0x00, 0x13, },
3531                 { 0x00 },
3532         }, {
3533                 { 0x00, 0x08, 0x12, 0x24 },
3534                 { 0x00, 0x0e, 0x1d, },
3535                 { 0x00, 0x13, },
3536                 { 0x00, },
3537         }, {
3538                 { 0x00, 0x08, 0x12, 0x24 },
3539                 { 0x00, 0x0e, 0x1d, },
3540                 { 0x00, 0x13, },
3541                 { 0x00, },
3542         },
3543 };
3544
3545 static const struct tegra_sor_soc tegra132_sor = {
3546         .supports_edp = true,
3547         .supports_lvds = true,
3548         .supports_hdmi = false,
3549         .supports_dp = false,
3550         .regs = &tegra124_sor_regs,
3551         .has_nvdisplay = false,
3552         .xbar_cfg = tegra124_sor_xbar_cfg,
3553         .lane_map = tegra124_sor_lane_map,
3554         .voltage_swing = tegra124_sor_voltage_swing,
3555         .pre_emphasis = tegra132_sor_pre_emphasis,
3556         .post_cursor = tegra124_sor_post_cursor,
3557         .tx_pu = tegra124_sor_tx_pu,
3558 };
3559
3560 static const struct tegra_sor_regs tegra210_sor_regs = {
3561         .head_state0 = 0x05,
3562         .head_state1 = 0x07,
3563         .head_state2 = 0x09,
3564         .head_state3 = 0x0b,
3565         .head_state4 = 0x0d,
3566         .head_state5 = 0x0f,
3567         .pll0 = 0x17,
3568         .pll1 = 0x18,
3569         .pll2 = 0x19,
3570         .pll3 = 0x1a,
3571         .dp_padctl0 = 0x5c,
3572         .dp_padctl2 = 0x73,
3573 };
3574
3575 static const u8 tegra210_sor_xbar_cfg[5] = {
3576         2, 1, 0, 3, 4
3577 };
3578
3579 static const u8 tegra210_sor_lane_map[4] = {
3580         0, 1, 2, 3,
3581 };
3582
3583 static const struct tegra_sor_soc tegra210_sor = {
3584         .supports_edp = true,
3585         .supports_lvds = false,
3586         .supports_hdmi = false,
3587         .supports_dp = false,
3588
3589         .regs = &tegra210_sor_regs,
3590         .has_nvdisplay = false,
3591
3592         .xbar_cfg = tegra210_sor_xbar_cfg,
3593         .lane_map = tegra210_sor_lane_map,
3594         .voltage_swing = tegra124_sor_voltage_swing,
3595         .pre_emphasis = tegra124_sor_pre_emphasis,
3596         .post_cursor = tegra124_sor_post_cursor,
3597         .tx_pu = tegra124_sor_tx_pu,
3598 };
3599
3600 static const struct tegra_sor_soc tegra210_sor1 = {
3601         .supports_edp = false,
3602         .supports_lvds = false,
3603         .supports_hdmi = true,
3604         .supports_dp = true,
3605
3606         .regs = &tegra210_sor_regs,
3607         .has_nvdisplay = false,
3608
3609         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3610         .settings = tegra210_sor_hdmi_defaults,
3611         .xbar_cfg = tegra210_sor_xbar_cfg,
3612         .lane_map = tegra210_sor_lane_map,
3613         .voltage_swing = tegra124_sor_voltage_swing,
3614         .pre_emphasis = tegra124_sor_pre_emphasis,
3615         .post_cursor = tegra124_sor_post_cursor,
3616         .tx_pu = tegra124_sor_tx_pu,
3617 };
3618
3619 static const struct tegra_sor_regs tegra186_sor_regs = {
3620         .head_state0 = 0x151,
3621         .head_state1 = 0x154,
3622         .head_state2 = 0x157,
3623         .head_state3 = 0x15a,
3624         .head_state4 = 0x15d,
3625         .head_state5 = 0x160,
3626         .pll0 = 0x163,
3627         .pll1 = 0x164,
3628         .pll2 = 0x165,
3629         .pll3 = 0x166,
3630         .dp_padctl0 = 0x168,
3631         .dp_padctl2 = 0x16a,
3632 };
3633
3634 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3635         {
3636                 { 0x13, 0x19, 0x1e, 0x28 },
3637                 { 0x1e, 0x25, 0x2d, },
3638                 { 0x28, 0x32, },
3639                 { 0x39, },
3640         }, {
3641                 { 0x12, 0x16, 0x1b, 0x25 },
3642                 { 0x1c, 0x23, 0x2a, },
3643                 { 0x25, 0x2f, },
3644                 { 0x37, }
3645         }, {
3646                 { 0x12, 0x16, 0x1a, 0x22 },
3647                 { 0x1b, 0x20, 0x27, },
3648                 { 0x24, 0x2d, },
3649                 { 0x35, },
3650         }, {
3651                 { 0x11, 0x14, 0x17, 0x1f },
3652                 { 0x19, 0x1e, 0x24, },
3653                 { 0x22, 0x2a, },
3654                 { 0x32, },
3655         },
3656 };
3657
3658 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3659         {
3660                 { 0x00, 0x08, 0x12, 0x24 },
3661                 { 0x01, 0x0e, 0x1d, },
3662                 { 0x01, 0x13, },
3663                 { 0x00, },
3664         }, {
3665                 { 0x00, 0x08, 0x12, 0x24 },
3666                 { 0x00, 0x0e, 0x1d, },
3667                 { 0x00, 0x13, },
3668                 { 0x00 },
3669         }, {
3670                 { 0x00, 0x08, 0x14, 0x24 },
3671                 { 0x00, 0x0e, 0x1d, },
3672                 { 0x00, 0x13, },
3673                 { 0x00, },
3674         }, {
3675                 { 0x00, 0x08, 0x12, 0x24 },
3676                 { 0x00, 0x0e, 0x1d, },
3677                 { 0x00, 0x13, },
3678                 { 0x00, },
3679         },
3680 };
3681
3682 static const struct tegra_sor_soc tegra186_sor = {
3683         .supports_edp = false,
3684         .supports_lvds = false,
3685         .supports_hdmi = true,
3686         .supports_dp = true,
3687
3688         .regs = &tegra186_sor_regs,
3689         .has_nvdisplay = true,
3690
3691         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3692         .settings = tegra186_sor_hdmi_defaults,
3693         .xbar_cfg = tegra124_sor_xbar_cfg,
3694         .lane_map = tegra124_sor_lane_map,
3695         .voltage_swing = tegra186_sor_voltage_swing,
3696         .pre_emphasis = tegra186_sor_pre_emphasis,
3697         .post_cursor = tegra124_sor_post_cursor,
3698         .tx_pu = tegra124_sor_tx_pu,
3699 };
3700
3701 static const struct tegra_sor_regs tegra194_sor_regs = {
3702         .head_state0 = 0x151,
3703         .head_state1 = 0x155,
3704         .head_state2 = 0x159,
3705         .head_state3 = 0x15d,
3706         .head_state4 = 0x161,
3707         .head_state5 = 0x165,
3708         .pll0 = 0x169,
3709         .pll1 = 0x16a,
3710         .pll2 = 0x16b,
3711         .pll3 = 0x16c,
3712         .dp_padctl0 = 0x16e,
3713         .dp_padctl2 = 0x16f,
3714 };
3715
3716 static const struct tegra_sor_soc tegra194_sor = {
3717         .supports_edp = true,
3718         .supports_lvds = false,
3719         .supports_hdmi = true,
3720         .supports_dp = true,
3721
3722         .regs = &tegra194_sor_regs,
3723         .has_nvdisplay = true,
3724
3725         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3726         .settings = tegra194_sor_hdmi_defaults,
3727
3728         .xbar_cfg = tegra210_sor_xbar_cfg,
3729 };
3730
3731 static const struct of_device_id tegra_sor_of_match[] = {
3732         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3733         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3734         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3735         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3736         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3737         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3738         { },
3739 };
3740 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3741
3742 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3743 {
3744         struct device_node *np = sor->dev->of_node;
3745         u32 xbar_cfg[5];
3746         unsigned int i;
3747         u32 value;
3748         int err;
3749
3750         if (sor->soc->has_nvdisplay) {
3751                 err = of_property_read_u32(np, "nvidia,interface", &value);
3752                 if (err < 0)
3753                         return err;
3754
3755                 sor->index = value;
3756
3757                 /*
3758                  * override the default that we already set for Tegra210 and
3759                  * earlier
3760                  */
3761                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3762         }
3763
3764         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3765         if (err < 0) {
3766                 /* fall back to default per-SoC XBAR configuration */
3767                 for (i = 0; i < 5; i++)
3768                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3769         } else {
3770                 /* copy cells to SOR XBAR configuration */
3771                 for (i = 0; i < 5; i++)
3772                         sor->xbar_cfg[i] = xbar_cfg[i];
3773         }
3774
3775         return 0;
3776 }
3777
3778 static irqreturn_t tegra_sor_irq(int irq, void *data)
3779 {
3780         struct tegra_sor *sor = data;
3781         u32 value;
3782
3783         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3784         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3785
3786         if (value & SOR_INT_CODEC_SCRATCH0) {
3787                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3788
3789                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3790                         unsigned int format;
3791
3792                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3793
3794                         tegra_hda_parse_format(format, &sor->format);
3795
3796                         tegra_sor_hdmi_audio_enable(sor);
3797                 } else {
3798                         tegra_sor_hdmi_audio_disable(sor);
3799                 }
3800         }
3801
3802         return IRQ_HANDLED;
3803 }
3804
3805 static int tegra_sor_probe(struct platform_device *pdev)
3806 {
3807         struct device_node *np;
3808         struct tegra_sor *sor;
3809         struct resource *regs;
3810         int err;
3811
3812         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3813         if (!sor)
3814                 return -ENOMEM;
3815
3816         sor->soc = of_device_get_match_data(&pdev->dev);
3817         sor->output.dev = sor->dev = &pdev->dev;
3818
3819         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3820                                      sor->soc->num_settings *
3821                                         sizeof(*sor->settings),
3822                                      GFP_KERNEL);
3823         if (!sor->settings)
3824                 return -ENOMEM;
3825
3826         sor->num_settings = sor->soc->num_settings;
3827
3828         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3829         if (np) {
3830                 sor->aux = drm_dp_aux_find_by_of_node(np);
3831                 of_node_put(np);
3832
3833                 if (!sor->aux)
3834                         return -EPROBE_DEFER;
3835
3836                 sor->output.ddc = &sor->aux->ddc;
3837         }
3838
3839         if (!sor->aux) {
3840                 if (sor->soc->supports_hdmi) {
3841                         sor->ops = &tegra_sor_hdmi_ops;
3842                         sor->pad = TEGRA_IO_PAD_HDMI;
3843                 } else if (sor->soc->supports_lvds) {
3844                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3845                         return -ENODEV;
3846                 } else {
3847                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3848                         return -ENODEV;
3849                 }
3850         } else {
3851                 if (sor->soc->supports_edp) {
3852                         sor->ops = &tegra_sor_edp_ops;
3853                         sor->pad = TEGRA_IO_PAD_LVDS;
3854                 } else if (sor->soc->supports_dp) {
3855                         sor->ops = &tegra_sor_dp_ops;
3856                 } else {
3857                         dev_err(&pdev->dev, "unknown (DP) support\n");
3858                         return -ENODEV;
3859                 }
3860         }
3861
3862         err = tegra_sor_parse_dt(sor);
3863         if (err < 0)
3864                 return err;
3865
3866         err = tegra_output_probe(&sor->output);
3867         if (err < 0) {
3868                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3869                 return err;
3870         }
3871
3872         if (sor->ops && sor->ops->probe) {
3873                 err = sor->ops->probe(sor);
3874                 if (err < 0) {
3875                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3876                                 sor->ops->name, err);
3877                         goto output;
3878                 }
3879         }
3880
3881         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3882         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3883         if (IS_ERR(sor->regs)) {
3884                 err = PTR_ERR(sor->regs);
3885                 goto remove;
3886         }
3887
3888         err = platform_get_irq(pdev, 0);
3889         if (err < 0) {
3890                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3891                 goto remove;
3892         }
3893
3894         sor->irq = err;
3895
3896         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3897                                dev_name(sor->dev), sor);
3898         if (err < 0) {
3899                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3900                 goto remove;
3901         }
3902
3903         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3904         if (IS_ERR(sor->rst)) {
3905                 err = PTR_ERR(sor->rst);
3906
3907                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3908                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3909                                 err);
3910                         goto remove;
3911                 }
3912
3913                 /*
3914                  * At this point, the reset control is most likely being used
3915                  * by the generic power domain implementation. With any luck
3916                  * the power domain will have taken care of resetting the SOR
3917                  * and we don't have to do anything.
3918                  */
3919                 sor->rst = NULL;
3920         }
3921
3922         sor->clk = devm_clk_get(&pdev->dev, NULL);
3923         if (IS_ERR(sor->clk)) {
3924                 err = PTR_ERR(sor->clk);
3925                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3926                 goto remove;
3927         }
3928
3929         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3930                 struct device_node *np = pdev->dev.of_node;
3931                 const char *name;
3932
3933                 /*
3934                  * For backwards compatibility with Tegra210 device trees,
3935                  * fall back to the old clock name "source" if the new "out"
3936                  * clock is not available.
3937                  */
3938                 if (of_property_match_string(np, "clock-names", "out") < 0)
3939                         name = "source";
3940                 else
3941                         name = "out";
3942
3943                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3944                 if (IS_ERR(sor->clk_out)) {
3945                         err = PTR_ERR(sor->clk_out);
3946                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3947                                 name, err);
3948                         goto remove;
3949                 }
3950         } else {
3951                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3952                 sor->clk_out = sor->clk;
3953         }
3954
3955         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3956         if (IS_ERR(sor->clk_parent)) {
3957                 err = PTR_ERR(sor->clk_parent);
3958                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3959                 goto remove;
3960         }
3961
3962         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3963         if (IS_ERR(sor->clk_safe)) {
3964                 err = PTR_ERR(sor->clk_safe);
3965                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3966                 goto remove;
3967         }
3968
3969         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3970         if (IS_ERR(sor->clk_dp)) {
3971                 err = PTR_ERR(sor->clk_dp);
3972                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3973                 goto remove;
3974         }
3975
3976         /*
3977          * Starting with Tegra186, the BPMP provides an implementation for
3978          * the pad output clock, so we have to look it up from device tree.
3979          */
3980         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3981         if (IS_ERR(sor->clk_pad)) {
3982                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3983                         err = PTR_ERR(sor->clk_pad);
3984                         goto remove;
3985                 }
3986
3987                 /*
3988                  * If the pad output clock is not available, then we assume
3989                  * we're on Tegra210 or earlier and have to provide our own
3990                  * implementation.
3991                  */
3992                 sor->clk_pad = NULL;
3993         }
3994
3995         /*
3996          * The bootloader may have set up the SOR such that it's module clock
3997          * is sourced by one of the display PLLs. However, that doesn't work
3998          * without properly having set up other bits of the SOR.
3999          */
4000         err = clk_set_parent(sor->clk_out, sor->clk_safe);
4001         if (err < 0) {
4002                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
4003                 goto remove;
4004         }
4005
4006         platform_set_drvdata(pdev, sor);
4007         pm_runtime_enable(&pdev->dev);
4008
4009         /*
4010          * On Tegra210 and earlier, provide our own implementation for the
4011          * pad output clock.
4012          */
4013         if (!sor->clk_pad) {
4014                 err = pm_runtime_get_sync(&pdev->dev);
4015                 if (err < 0) {
4016                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
4017                                 err);
4018                         goto remove;
4019                 }
4020
4021                 sor->clk_pad = tegra_clk_sor_pad_register(sor,
4022                                                           "sor1_pad_clkout");
4023                 pm_runtime_put(&pdev->dev);
4024         }
4025
4026         if (IS_ERR(sor->clk_pad)) {
4027                 err = PTR_ERR(sor->clk_pad);
4028                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
4029                         err);
4030                 goto remove;
4031         }
4032
4033         INIT_LIST_HEAD(&sor->client.list);
4034         sor->client.ops = &sor_client_ops;
4035         sor->client.dev = &pdev->dev;
4036
4037         err = host1x_client_register(&sor->client);
4038         if (err < 0) {
4039                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
4040                         err);
4041                 goto remove;
4042         }
4043
4044         return 0;
4045
4046 remove:
4047         if (sor->ops && sor->ops->remove)
4048                 sor->ops->remove(sor);
4049 output:
4050         tegra_output_remove(&sor->output);
4051         return err;
4052 }
4053
4054 static int tegra_sor_remove(struct platform_device *pdev)
4055 {
4056         struct tegra_sor *sor = platform_get_drvdata(pdev);
4057         int err;
4058
4059         pm_runtime_disable(&pdev->dev);
4060
4061         err = host1x_client_unregister(&sor->client);
4062         if (err < 0) {
4063                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
4064                         err);
4065                 return err;
4066         }
4067
4068         if (sor->ops && sor->ops->remove) {
4069                 err = sor->ops->remove(sor);
4070                 if (err < 0)
4071                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
4072         }
4073
4074         tegra_output_remove(&sor->output);
4075
4076         return 0;
4077 }
4078
4079 #ifdef CONFIG_PM
4080 static int tegra_sor_suspend(struct device *dev)
4081 {
4082         struct tegra_sor *sor = dev_get_drvdata(dev);
4083         int err;
4084
4085         if (sor->rst) {
4086                 err = reset_control_assert(sor->rst);
4087                 if (err < 0) {
4088                         dev_err(dev, "failed to assert reset: %d\n", err);
4089                         return err;
4090                 }
4091
4092                 reset_control_release(sor->rst);
4093         }
4094
4095         usleep_range(1000, 2000);
4096
4097         clk_disable_unprepare(sor->clk);
4098
4099         return 0;
4100 }
4101
4102 static int tegra_sor_resume(struct device *dev)
4103 {
4104         struct tegra_sor *sor = dev_get_drvdata(dev);
4105         int err;
4106
4107         err = clk_prepare_enable(sor->clk);
4108         if (err < 0) {
4109                 dev_err(dev, "failed to enable clock: %d\n", err);
4110                 return err;
4111         }
4112
4113         usleep_range(1000, 2000);
4114
4115         if (sor->rst) {
4116                 err = reset_control_acquire(sor->rst);
4117                 if (err < 0) {
4118                         dev_err(dev, "failed to acquire reset: %d\n", err);
4119                         clk_disable_unprepare(sor->clk);
4120                         return err;
4121                 }
4122
4123                 err = reset_control_deassert(sor->rst);
4124                 if (err < 0) {
4125                         dev_err(dev, "failed to deassert reset: %d\n", err);
4126                         reset_control_release(sor->rst);
4127                         clk_disable_unprepare(sor->clk);
4128                         return err;
4129                 }
4130         }
4131
4132         return 0;
4133 }
4134 #endif
4135
4136 static const struct dev_pm_ops tegra_sor_pm_ops = {
4137         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
4138 };
4139
4140 struct platform_driver tegra_sor_driver = {
4141         .driver = {
4142                 .name = "tegra-sor",
4143                 .of_match_table = tegra_sor_of_match,
4144                 .pm = &tegra_sor_pm_ops,
4145         },
4146         .probe = tegra_sor_probe,
4147         .remove = tegra_sor_remove,
4148 };