drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset.h>
  17
  18 #include <soc/tegra/pmc.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_dp_helper.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_scdc_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_edp;
 375         bool supports_lvds;
 376         bool supports_hdmi;
 377         bool supports_dp;
 378
 379         const struct tegra_sor_regs *regs;
 380         bool has_nvdisplay;
 381
 382         const struct tegra_sor_hdmi_settings *settings;
 383         unsigned int num_settings;
 384
 385         const u8 *xbar_cfg;
 386 };
 387
 388 struct tegra_sor;
 389
 390 struct tegra_sor_ops {
 391         const char *name;
 392         int (*probe)(struct tegra_sor *sor);
 393         int (*remove)(struct tegra_sor *sor);
 394 };
 395
 396 struct tegra_sor {
 397         struct host1x_client client;
 398         struct tegra_output output;
 399         struct device *dev;
 400
 401         const struct tegra_sor_soc *soc;
 402         void __iomem *regs;
 403         unsigned int index;
 404         unsigned int irq;
 405
 406         struct reset_control *rst;
 407         struct clk *clk_parent;
 408         struct clk *clk_safe;
 409         struct clk *clk_out;
 410         struct clk *clk_pad;
 411         struct clk *clk_dp;
 412         struct clk *clk;
 413
 414         u8 xbar_cfg[5];
 415
 416         struct drm_dp_aux *aux;
 417
 418         struct drm_info_list *debugfs_files;
 419
 420         const struct tegra_sor_ops *ops;
 421         enum tegra_io_pad pad;
 422
 423         /* for HDMI 2.0 */
 424         struct tegra_sor_hdmi_settings *settings;
 425         unsigned int num_settings;
 426
 427         struct regulator *avdd_io_supply;
 428         struct regulator *vdd_pll_supply;
 429         struct regulator *hdmi_supply;
 430
 431         struct delayed_work scdc;
 432         bool scdc_enabled;
 433
 434         struct tegra_hda_format format;
 435 };
 436
 437 struct tegra_sor_state {
 438         struct drm_connector_state base;
 439
 440         unsigned int link_speed;
 441         unsigned long pclk;
 442         unsigned int bpc;
 443 };
 444
 445 static inline struct tegra_sor_state *
 446 to_sor_state(struct drm_connector_state *state)
 447 {
 448         return container_of(state, struct tegra_sor_state, base);
 449 }
 450
 451 struct tegra_sor_config {
 452         u32 bits_per_pixel;
 453
 454         u32 active_polarity;
 455         u32 active_count;
 456         u32 tu_size;
 457         u32 active_frac;
 458         u32 watermark;
 459
 460         u32 hblank_symbols;
 461         u32 vblank_symbols;
 462 };
 463
 464 static inline struct tegra_sor *
 465 host1x_client_to_sor(struct host1x_client *client)
 466 {
 467         return container_of(client, struct tegra_sor, client);
 468 }
 469
 470 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 471 {
 472         return container_of(output, struct tegra_sor, output);
 473 }
 474
 475 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 476 {
 477         u32 value = readl(sor->regs + (offset << 2));
 478
 479         trace_sor_readl(sor->dev, offset, value);
 480
 481         return value;
 482 }
 483
 484 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 485                                     unsigned int offset)
 486 {
 487         trace_sor_writel(sor->dev, offset, value);
 488         writel(value, sor->regs + (offset << 2));
 489 }
 490
 491 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 492 {
 493         int err;
 494
 495         clk_disable_unprepare(sor->clk);
 496
 497         err = clk_set_parent(sor->clk_out, parent);
 498         if (err < 0)
 499                 return err;
 500
 501         err = clk_prepare_enable(sor->clk);
 502         if (err < 0)
 503                 return err;
 504
 505         return 0;
 506 }
 507
 508 struct tegra_clk_sor_pad {
 509         struct clk_hw hw;
 510         struct tegra_sor *sor;
 511 };
 512
 513 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 514 {
 515         return container_of(hw, struct tegra_clk_sor_pad, hw);
 516 }
 517
 518 static const char * const tegra_clk_sor_pad_parents[] = {
 519         "pll_d2_out0", "pll_dp"
 520 };
 521
 522 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 523 {
 524         struct tegra_clk_sor_pad *pad = to_pad(hw);
 525         struct tegra_sor *sor = pad->sor;
 526         u32 value;
 527
 528         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 529         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 530
 531         switch (index) {
 532         case 0:
 533                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 534                 break;
 535
 536         case 1:
 537                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 538                 break;
 539         }
 540
 541         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 542
 543         return 0;
 544 }
 545
 546 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 547 {
 548         struct tegra_clk_sor_pad *pad = to_pad(hw);
 549         struct tegra_sor *sor = pad->sor;
 550         u8 parent = U8_MAX;
 551         u32 value;
 552
 553         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 554
 555         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 556         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 557         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 558                 parent = 0;
 559                 break;
 560
 561         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 562         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 563                 parent = 1;
 564                 break;
 565         }
 566
 567         return parent;
 568 }
 569
 570 static const struct clk_ops tegra_clk_sor_pad_ops = {
 571         .set_parent = tegra_clk_sor_pad_set_parent,
 572         .get_parent = tegra_clk_sor_pad_get_parent,
 573 };
 574
 575 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 576                                               const char *name)
 577 {
 578         struct tegra_clk_sor_pad *pad;
 579         struct clk_init_data init;
 580         struct clk *clk;
 581
 582         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 583         if (!pad)
 584                 return ERR_PTR(-ENOMEM);
 585
 586         pad->sor = sor;
 587
 588         init.name = name;
 589         init.flags = 0;
 590         init.parent_names = tegra_clk_sor_pad_parents;
 591         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
 592         init.ops = &tegra_clk_sor_pad_ops;
 593
 594         pad->hw.init = &init;
 595
 596         clk = devm_clk_register(sor->dev, &pad->hw);
 597
 598         return clk;
 599 }
 600
 601 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
 602                                    struct drm_dp_link *link)
 603 {
 604         unsigned int i;
 605         u8 pattern;
 606         u32 value;
 607         int err;
 608
 609         /* setup lane parameters */
 610         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
 611                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
 612                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
 613                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
 614         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
 615
 616         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
 617                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 618                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 619                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 620         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
 621
 622         value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
 623                 SOR_LANE_POSTCURSOR_LANE2(0x00) |
 624                 SOR_LANE_POSTCURSOR_LANE1(0x00) |
 625                 SOR_LANE_POSTCURSOR_LANE0(0x00);
 626         tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
 627
 628         /* disable LVDS mode */
 629         tegra_sor_writel(sor, 0, SOR_LVDS);
 630
 631         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 632         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 633         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 634         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 635         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 636
 637         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 638         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 639                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 640         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 641
 642         usleep_range(10, 100);
 643
 644         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 645         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 646                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 647         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 648
 649         err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
 650         if (err < 0)
 651                 return err;
 652
 653         for (i = 0, value = 0; i < link->num_lanes; i++) {
 654                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 655                                      SOR_DP_TPG_SCRAMBLER_NONE |
 656                                      SOR_DP_TPG_PATTERN_TRAIN1;
 657                 value = (value << 8) | lane;
 658         }
 659
 660         tegra_sor_writel(sor, value, SOR_DP_TPG);
 661
 662         pattern = DP_TRAINING_PATTERN_1;
 663
 664         err = drm_dp_aux_train(sor->aux, link, pattern);
 665         if (err < 0)
 666                 return err;
 667
 668         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 669         value |= SOR_DP_SPARE_SEQ_ENABLE;
 670         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 671         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 672         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 673
 674         for (i = 0, value = 0; i < link->num_lanes; i++) {
 675                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 676                                      SOR_DP_TPG_SCRAMBLER_NONE |
 677                                      SOR_DP_TPG_PATTERN_TRAIN2;
 678                 value = (value << 8) | lane;
 679         }
 680
 681         tegra_sor_writel(sor, value, SOR_DP_TPG);
 682
 683         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 684
 685         err = drm_dp_aux_train(sor->aux, link, pattern);
 686         if (err < 0)
 687                 return err;
 688
 689         for (i = 0, value = 0; i < link->num_lanes; i++) {
 690                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 691                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 692                                      SOR_DP_TPG_PATTERN_NONE;
 693                 value = (value << 8) | lane;
 694         }
 695
 696         tegra_sor_writel(sor, value, SOR_DP_TPG);
 697
 698         pattern = DP_TRAINING_PATTERN_DISABLE;
 699
 700         err = drm_dp_aux_train(sor->aux, link, pattern);
 701         if (err < 0)
 702                 return err;
 703
 704         return 0;
 705 }
 706
 707 static void tegra_sor_super_update(struct tegra_sor *sor)
 708 {
 709         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 710         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 711         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 712 }
 713
 714 static void tegra_sor_update(struct tegra_sor *sor)
 715 {
 716         tegra_sor_writel(sor, 0, SOR_STATE0);
 717         tegra_sor_writel(sor, 1, SOR_STATE0);
 718         tegra_sor_writel(sor, 0, SOR_STATE0);
 719 }
 720
 721 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 722 {
 723         u32 value;
 724
 725         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 726         value &= ~SOR_PWM_DIV_MASK;
 727         value |= 0x400; /* period */
 728         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 729
 730         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 731         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 732         value |= 0x400; /* duty cycle */
 733         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 734         value |= SOR_PWM_CTL_TRIGGER;
 735         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 736
 737         timeout = jiffies + msecs_to_jiffies(timeout);
 738
 739         while (time_before(jiffies, timeout)) {
 740                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 741                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 742                         return 0;
 743
 744                 usleep_range(25, 100);
 745         }
 746
 747         return -ETIMEDOUT;
 748 }
 749
 750 static int tegra_sor_attach(struct tegra_sor *sor)
 751 {
 752         unsigned long value, timeout;
 753
 754         /* wake up in normal mode */
 755         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 756         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 757         value |= SOR_SUPER_STATE_MODE_NORMAL;
 758         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 759         tegra_sor_super_update(sor);
 760
 761         /* attach */
 762         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
 763         value |= SOR_SUPER_STATE_ATTACHED;
 764         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
 765         tegra_sor_super_update(sor);
 766
 767         timeout = jiffies + msecs_to_jiffies(250);
 768
 769         while (time_before(jiffies, timeout)) {
 770                 value = tegra_sor_readl(sor, SOR_TEST);
 771                 if ((value & SOR_TEST_ATTACHED) != 0)
 772                         return 0;
 773
 774                 usleep_range(25, 100);
 775         }
 776
 777         return -ETIMEDOUT;
 778 }
 779
 780 static int tegra_sor_wakeup(struct tegra_sor *sor)
 781 {
 782         unsigned long value, timeout;
 783
 784         timeout = jiffies + msecs_to_jiffies(250);
 785
 786         /* wait for head to wake up */
 787         while (time_before(jiffies, timeout)) {
 788                 value = tegra_sor_readl(sor, SOR_TEST);
 789                 value &= SOR_TEST_HEAD_MODE_MASK;
 790
 791                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 792                         return 0;
 793
 794                 usleep_range(25, 100);
 795         }
 796
 797         return -ETIMEDOUT;
 798 }
 799
 800 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 801 {
 802         u32 value;
 803
 804         value = tegra_sor_readl(sor, SOR_PWR);
 805         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 806         tegra_sor_writel(sor, value, SOR_PWR);
 807
 808         timeout = jiffies + msecs_to_jiffies(timeout);
 809
 810         while (time_before(jiffies, timeout)) {
 811                 value = tegra_sor_readl(sor, SOR_PWR);
 812                 if ((value & SOR_PWR_TRIGGER) == 0)
 813                         return 0;
 814
 815                 usleep_range(25, 100);
 816         }
 817
 818         return -ETIMEDOUT;
 819 }
 820
 821 struct tegra_sor_params {
 822         /* number of link clocks per line */
 823         unsigned int num_clocks;
 824         /* ratio between input and output */
 825         u64 ratio;
 826         /* precision factor */
 827         u64 precision;
 828
 829         unsigned int active_polarity;
 830         unsigned int active_count;
 831         unsigned int active_frac;
 832         unsigned int tu_size;
 833         unsigned int error;
 834 };
 835
 836 static int tegra_sor_compute_params(struct tegra_sor *sor,
 837                                     struct tegra_sor_params *params,
 838                                     unsigned int tu_size)
 839 {
 840         u64 active_sym, active_count, frac, approx;
 841         u32 active_polarity, active_frac = 0;
 842         const u64 f = params->precision;
 843         s64 error;
 844
 845         active_sym = params->ratio * tu_size;
 846         active_count = div_u64(active_sym, f) * f;
 847         frac = active_sym - active_count;
 848
 849         /* fraction < 0.5 */
 850         if (frac >= (f / 2)) {
 851                 active_polarity = 1;
 852                 frac = f - frac;
 853         } else {
 854                 active_polarity = 0;
 855         }
 856
 857         if (frac != 0) {
 858                 frac = div_u64(f * f,  frac); /* 1/fraction */
 859                 if (frac <= (15 * f)) {
 860                         active_frac = div_u64(frac, f);
 861
 862                         /* round up */
 863                         if (active_polarity)
 864                                 active_frac++;
 865                 } else {
 866                         active_frac = active_polarity ? 1 : 15;
 867                 }
 868         }
 869
 870         if (active_frac == 1)
 871                 active_polarity = 0;
 872
 873         if (active_polarity == 1) {
 874                 if (active_frac) {
 875                         approx = active_count + (active_frac * (f - 1)) * f;
 876                         approx = div_u64(approx, active_frac * f);
 877                 } else {
 878                         approx = active_count + f;
 879                 }
 880         } else {
 881                 if (active_frac)
 882                         approx = active_count + div_u64(f, active_frac);
 883                 else
 884                         approx = active_count;
 885         }
 886
 887         error = div_s64(active_sym - approx, tu_size);
 888         error *= params->num_clocks;
 889
 890         if (error <= 0 && abs(error) < params->error) {
 891                 params->active_count = div_u64(active_count, f);
 892                 params->active_polarity = active_polarity;
 893                 params->active_frac = active_frac;
 894                 params->error = abs(error);
 895                 params->tu_size = tu_size;
 896
 897                 if (error == 0)
 898                         return true;
 899         }
 900
 901         return false;
 902 }
 903
 904 static int tegra_sor_compute_config(struct tegra_sor *sor,
 905                                     const struct drm_display_mode *mode,
 906                                     struct tegra_sor_config *config,
 907                                     struct drm_dp_link *link)
 908 {
 909         const u64 f = 100000, link_rate = link->rate * 1000;
 910         const u64 pclk = mode->clock * 1000;
 911         u64 input, output, watermark, num;
 912         struct tegra_sor_params params;
 913         u32 num_syms_per_line;
 914         unsigned int i;
 915
 916         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 917                 return -EINVAL;
 918
 919         output = link_rate * 8 * link->num_lanes;
 920         input = pclk * config->bits_per_pixel;
 921
 922         if (input >= output)
 923                 return -ERANGE;
 924
 925         memset(&params, 0, sizeof(params));
 926         params.ratio = div64_u64(input * f, output);
 927         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 928         params.precision = f;
 929         params.error = 64 * f;
 930         params.tu_size = 64;
 931
 932         for (i = params.tu_size; i >= 32; i--)
 933                 if (tegra_sor_compute_params(sor, &params, i))
 934                         break;
 935
 936         if (params.active_frac == 0) {
 937                 config->active_polarity = 0;
 938                 config->active_count = params.active_count;
 939
 940                 if (!params.active_polarity)
 941                         config->active_count--;
 942
 943                 config->tu_size = params.tu_size;
 944                 config->active_frac = 1;
 945         } else {
 946                 config->active_polarity = params.active_polarity;
 947                 config->active_count = params.active_count;
 948                 config->active_frac = params.active_frac;
 949                 config->tu_size = params.tu_size;
 950         }
 951
 952         dev_dbg(sor->dev,
 953                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 954                 config->active_polarity, config->active_count,
 955                 config->tu_size, config->active_frac);
 956
 957         watermark = params.ratio * config->tu_size * (f - params.ratio);
 958         watermark = div_u64(watermark, f);
 959
 960         watermark = div_u64(watermark + params.error, f);
 961         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 962         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 963                             (link->num_lanes * 8);
 964
 965         if (config->watermark > 30) {
 966                 config->watermark = 30;
 967                 dev_err(sor->dev,
 968                         "unable to compute TU size, forcing watermark to %u\n",
 969                         config->watermark);
 970         } else if (config->watermark > num_syms_per_line) {
 971                 config->watermark = num_syms_per_line;
 972                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 973                         config->watermark);
 974         }
 975
 976         /* compute the number of symbols per horizontal blanking interval */
 977         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 978         config->hblank_symbols = div_u64(num, pclk);
 979
 980         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 981                 config->hblank_symbols -= 3;
 982
 983         config->hblank_symbols -= 12 / link->num_lanes;
 984
 985         /* compute the number of symbols per vertical blanking interval */
 986         num = (mode->hdisplay - 25) * link_rate;
 987         config->vblank_symbols = div_u64(num, pclk);
 988         config->vblank_symbols -= 36 / link->num_lanes + 4;
 989
 990         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 991                 config->vblank_symbols);
 992
 993         return 0;
 994 }
 995
 996 static void tegra_sor_apply_config(struct tegra_sor *sor,
 997                                    const struct tegra_sor_config *config)
 998 {
 999         u32 value;
1000
1001         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1002         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1003         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1004         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1005
1006         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1007         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1008         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1009
1010         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1011         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1012
1013         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1014         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1015
1016         if (config->active_polarity)
1017                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1018         else
1019                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1020
1021         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1022         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1023         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1024
1025         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1026         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1027         value |= config->hblank_symbols & 0xffff;
1028         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1029
1030         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1031         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1032         value |= config->vblank_symbols & 0xffff;
1033         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1034 }
1035
1036 static void tegra_sor_mode_set(struct tegra_sor *sor,
1037                                const struct drm_display_mode *mode,
1038                                struct tegra_sor_state *state)
1039 {
1040         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1041         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1042         u32 value;
1043
1044         value = tegra_sor_readl(sor, SOR_STATE1);
1045         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1046         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1047         value &= ~SOR_STATE_ASY_OWNER_MASK;
1048
1049         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1050                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1051
1052         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1053                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1054
1055         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1056                 value |= SOR_STATE_ASY_HSYNCPOL;
1057
1058         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1059                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1060
1061         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1062                 value |= SOR_STATE_ASY_VSYNCPOL;
1063
1064         switch (state->bpc) {
1065         case 16:
1066                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1067                 break;
1068
1069         case 12:
1070                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1071                 break;
1072
1073         case 10:
1074                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1075                 break;
1076
1077         case 8:
1078                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1079                 break;
1080
1081         case 6:
1082                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1083                 break;
1084
1085         default:
1086                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1087                 break;
1088         }
1089
1090         tegra_sor_writel(sor, value, SOR_STATE1);
1091
1092         /*
1093          * TODO: The video timing programming below doesn't seem to match the
1094          * register definitions.
1095          */
1096
1097         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1098         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1099
1100         /* sync end = sync width - 1 */
1101         vse = mode->vsync_end - mode->vsync_start - 1;
1102         hse = mode->hsync_end - mode->hsync_start - 1;
1103
1104         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1105         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1106
1107         /* blank end = sync end + back porch */
1108         vbe = vse + (mode->vtotal - mode->vsync_end);
1109         hbe = hse + (mode->htotal - mode->hsync_end);
1110
1111         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1112         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1113
1114         /* blank start = blank end + active */
1115         vbs = vbe + mode->vdisplay;
1116         hbs = hbe + mode->hdisplay;
1117
1118         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1119         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1120
1121         /* XXX interlacing support */
1122         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1123 }
1124
1125 static int tegra_sor_detach(struct tegra_sor *sor)
1126 {
1127         unsigned long value, timeout;
1128
1129         /* switch to safe mode */
1130         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1131         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1132         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1133         tegra_sor_super_update(sor);
1134
1135         timeout = jiffies + msecs_to_jiffies(250);
1136
1137         while (time_before(jiffies, timeout)) {
1138                 value = tegra_sor_readl(sor, SOR_PWR);
1139                 if (value & SOR_PWR_MODE_SAFE)
1140                         break;
1141         }
1142
1143         if ((value & SOR_PWR_MODE_SAFE) == 0)
1144                 return -ETIMEDOUT;
1145
1146         /* go to sleep */
1147         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1148         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1149         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1150         tegra_sor_super_update(sor);
1151
1152         /* detach */
1153         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1154         value &= ~SOR_SUPER_STATE_ATTACHED;
1155         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1156         tegra_sor_super_update(sor);
1157
1158         timeout = jiffies + msecs_to_jiffies(250);
1159
1160         while (time_before(jiffies, timeout)) {
1161                 value = tegra_sor_readl(sor, SOR_TEST);
1162                 if ((value & SOR_TEST_ATTACHED) == 0)
1163                         break;
1164
1165                 usleep_range(25, 100);
1166         }
1167
1168         if ((value & SOR_TEST_ATTACHED) != 0)
1169                 return -ETIMEDOUT;
1170
1171         return 0;
1172 }
1173
1174 static int tegra_sor_power_down(struct tegra_sor *sor)
1175 {
1176         unsigned long value, timeout;
1177         int err;
1178
1179         value = tegra_sor_readl(sor, SOR_PWR);
1180         value &= ~SOR_PWR_NORMAL_STATE_PU;
1181         value |= SOR_PWR_TRIGGER;
1182         tegra_sor_writel(sor, value, SOR_PWR);
1183
1184         timeout = jiffies + msecs_to_jiffies(250);
1185
1186         while (time_before(jiffies, timeout)) {
1187                 value = tegra_sor_readl(sor, SOR_PWR);
1188                 if ((value & SOR_PWR_TRIGGER) == 0)
1189                         return 0;
1190
1191                 usleep_range(25, 100);
1192         }
1193
1194         if ((value & SOR_PWR_TRIGGER) != 0)
1195                 return -ETIMEDOUT;
1196
1197         /* switch to safe parent clock */
1198         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1199         if (err < 0) {
1200                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1201                 return err;
1202         }
1203
1204         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1205         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1206                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1207         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1208
1209         /* stop lane sequencer */
1210         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1211                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1212         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1213
1214         timeout = jiffies + msecs_to_jiffies(250);
1215
1216         while (time_before(jiffies, timeout)) {
1217                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1218                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1219                         break;
1220
1221                 usleep_range(25, 100);
1222         }
1223
1224         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1225                 return -ETIMEDOUT;
1226
1227         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1228         value |= SOR_PLL2_PORT_POWERDOWN;
1229         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1230
1231         usleep_range(20, 100);
1232
1233         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1234         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1235         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1236
1237         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1238         value |= SOR_PLL2_SEQ_PLLCAPPD;
1239         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1240         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1241
1242         usleep_range(20, 100);
1243
1244         return 0;
1245 }
1246
1247 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1248 {
1249         u32 value;
1250
1251         timeout = jiffies + msecs_to_jiffies(timeout);
1252
1253         while (time_before(jiffies, timeout)) {
1254                 value = tegra_sor_readl(sor, SOR_CRCA);
1255                 if (value & SOR_CRCA_VALID)
1256                         return 0;
1257
1258                 usleep_range(100, 200);
1259         }
1260
1261         return -ETIMEDOUT;
1262 }
1263
1264 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1265 {
1266         struct drm_info_node *node = s->private;
1267         struct tegra_sor *sor = node->info_ent->data;
1268         struct drm_crtc *crtc = sor->output.encoder.crtc;
1269         struct drm_device *drm = node->minor->dev;
1270         int err = 0;
1271         u32 value;
1272
1273         drm_modeset_lock_all(drm);
1274
1275         if (!crtc || !crtc->state->active) {
1276                 err = -EBUSY;
1277                 goto unlock;
1278         }
1279
1280         value = tegra_sor_readl(sor, SOR_STATE1);
1281         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1282         tegra_sor_writel(sor, value, SOR_STATE1);
1283
1284         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1285         value |= SOR_CRC_CNTRL_ENABLE;
1286         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1287
1288         value = tegra_sor_readl(sor, SOR_TEST);
1289         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1290         tegra_sor_writel(sor, value, SOR_TEST);
1291
1292         err = tegra_sor_crc_wait(sor, 100);
1293         if (err < 0)
1294                 goto unlock;
1295
1296         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1297         value = tegra_sor_readl(sor, SOR_CRCB);
1298
1299         seq_printf(s, "%08x\n", value);
1300
1301 unlock:
1302         drm_modeset_unlock_all(drm);
1303         return err;
1304 }
1305
1306 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1307
1308 static const struct debugfs_reg32 tegra_sor_regs[] = {
1309         DEBUGFS_REG32(SOR_CTXSW),
1310         DEBUGFS_REG32(SOR_SUPER_STATE0),
1311         DEBUGFS_REG32(SOR_SUPER_STATE1),
1312         DEBUGFS_REG32(SOR_STATE0),
1313         DEBUGFS_REG32(SOR_STATE1),
1314         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1315         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1316         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1317         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1318         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1319         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1320         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1321         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1322         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1323         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1324         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1325         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1326         DEBUGFS_REG32(SOR_CRC_CNTRL),
1327         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1328         DEBUGFS_REG32(SOR_CLK_CNTRL),
1329         DEBUGFS_REG32(SOR_CAP),
1330         DEBUGFS_REG32(SOR_PWR),
1331         DEBUGFS_REG32(SOR_TEST),
1332         DEBUGFS_REG32(SOR_PLL0),
1333         DEBUGFS_REG32(SOR_PLL1),
1334         DEBUGFS_REG32(SOR_PLL2),
1335         DEBUGFS_REG32(SOR_PLL3),
1336         DEBUGFS_REG32(SOR_CSTM),
1337         DEBUGFS_REG32(SOR_LVDS),
1338         DEBUGFS_REG32(SOR_CRCA),
1339         DEBUGFS_REG32(SOR_CRCB),
1340         DEBUGFS_REG32(SOR_BLANK),
1341         DEBUGFS_REG32(SOR_SEQ_CTL),
1342         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1343         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1344         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1345         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1346         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1347         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1348         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1349         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1350         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1351         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1352         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1353         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1354         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1355         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1356         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1357         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1358         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1359         DEBUGFS_REG32(SOR_PWM_DIV),
1360         DEBUGFS_REG32(SOR_PWM_CTL),
1361         DEBUGFS_REG32(SOR_VCRC_A0),
1362         DEBUGFS_REG32(SOR_VCRC_A1),
1363         DEBUGFS_REG32(SOR_VCRC_B0),
1364         DEBUGFS_REG32(SOR_VCRC_B1),
1365         DEBUGFS_REG32(SOR_CCRC_A0),
1366         DEBUGFS_REG32(SOR_CCRC_A1),
1367         DEBUGFS_REG32(SOR_CCRC_B0),
1368         DEBUGFS_REG32(SOR_CCRC_B1),
1369         DEBUGFS_REG32(SOR_EDATA_A0),
1370         DEBUGFS_REG32(SOR_EDATA_A1),
1371         DEBUGFS_REG32(SOR_EDATA_B0),
1372         DEBUGFS_REG32(SOR_EDATA_B1),
1373         DEBUGFS_REG32(SOR_COUNT_A0),
1374         DEBUGFS_REG32(SOR_COUNT_A1),
1375         DEBUGFS_REG32(SOR_COUNT_B0),
1376         DEBUGFS_REG32(SOR_COUNT_B1),
1377         DEBUGFS_REG32(SOR_DEBUG_A0),
1378         DEBUGFS_REG32(SOR_DEBUG_A1),
1379         DEBUGFS_REG32(SOR_DEBUG_B0),
1380         DEBUGFS_REG32(SOR_DEBUG_B1),
1381         DEBUGFS_REG32(SOR_TRIG),
1382         DEBUGFS_REG32(SOR_MSCHECK),
1383         DEBUGFS_REG32(SOR_XBAR_CTRL),
1384         DEBUGFS_REG32(SOR_XBAR_POL),
1385         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1386         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1387         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1388         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1389         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1390         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1391         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1392         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1393         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1394         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1395         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1396         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1397         DEBUGFS_REG32(SOR_DP_CONFIG0),
1398         DEBUGFS_REG32(SOR_DP_CONFIG1),
1399         DEBUGFS_REG32(SOR_DP_MN0),
1400         DEBUGFS_REG32(SOR_DP_MN1),
1401         DEBUGFS_REG32(SOR_DP_PADCTL0),
1402         DEBUGFS_REG32(SOR_DP_PADCTL1),
1403         DEBUGFS_REG32(SOR_DP_PADCTL2),
1404         DEBUGFS_REG32(SOR_DP_DEBUG0),
1405         DEBUGFS_REG32(SOR_DP_DEBUG1),
1406         DEBUGFS_REG32(SOR_DP_SPARE0),
1407         DEBUGFS_REG32(SOR_DP_SPARE1),
1408         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1409         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1410         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1411         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1412         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1413         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1414         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1415         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1416         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1417         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1418         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1419         DEBUGFS_REG32(SOR_DP_TPG),
1420         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1421         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1422         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1423         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1424 };
1425
1426 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1427 {
1428         struct drm_info_node *node = s->private;
1429         struct tegra_sor *sor = node->info_ent->data;
1430         struct drm_crtc *crtc = sor->output.encoder.crtc;
1431         struct drm_device *drm = node->minor->dev;
1432         unsigned int i;
1433         int err = 0;
1434
1435         drm_modeset_lock_all(drm);
1436
1437         if (!crtc || !crtc->state->active) {
1438                 err = -EBUSY;
1439                 goto unlock;
1440         }
1441
1442         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1443                 unsigned int offset = tegra_sor_regs[i].offset;
1444
1445                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1446                            offset, tegra_sor_readl(sor, offset));
1447         }
1448
1449 unlock:
1450         drm_modeset_unlock_all(drm);
1451         return err;
1452 }
1453
1454 static const struct drm_info_list debugfs_files[] = {
1455         { "crc", tegra_sor_show_crc, 0, NULL },
1456         { "regs", tegra_sor_show_regs, 0, NULL },
1457 };
1458
1459 static int tegra_sor_late_register(struct drm_connector *connector)
1460 {
1461         struct tegra_output *output = connector_to_output(connector);
1462         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1463         struct drm_minor *minor = connector->dev->primary;
1464         struct dentry *root = connector->debugfs_entry;
1465         struct tegra_sor *sor = to_sor(output);
1466         int err;
1467
1468         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1469                                      GFP_KERNEL);
1470         if (!sor->debugfs_files)
1471                 return -ENOMEM;
1472
1473         for (i = 0; i < count; i++)
1474                 sor->debugfs_files[i].data = sor;
1475
1476         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1477         if (err < 0)
1478                 goto free;
1479
1480         return 0;
1481
1482 free:
1483         kfree(sor->debugfs_files);
1484         sor->debugfs_files = NULL;
1485
1486         return err;
1487 }
1488
1489 static void tegra_sor_early_unregister(struct drm_connector *connector)
1490 {
1491         struct tegra_output *output = connector_to_output(connector);
1492         unsigned int count = ARRAY_SIZE(debugfs_files);
1493         struct tegra_sor *sor = to_sor(output);
1494
1495         drm_debugfs_remove_files(sor->debugfs_files, count,
1496                                  connector->dev->primary);
1497         kfree(sor->debugfs_files);
1498         sor->debugfs_files = NULL;
1499 }
1500
1501 static void tegra_sor_connector_reset(struct drm_connector *connector)
1502 {
1503         struct tegra_sor_state *state;
1504
1505         state = kzalloc(sizeof(*state), GFP_KERNEL);
1506         if (!state)
1507                 return;
1508
1509         if (connector->state) {
1510                 __drm_atomic_helper_connector_destroy_state(connector->state);
1511                 kfree(connector->state);
1512         }
1513
1514         __drm_atomic_helper_connector_reset(connector, &state->base);
1515 }
1516
1517 static enum drm_connector_status
1518 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1519 {
1520         struct tegra_output *output = connector_to_output(connector);
1521         struct tegra_sor *sor = to_sor(output);
1522
1523         if (sor->aux)
1524                 return drm_dp_aux_detect(sor->aux);
1525
1526         return tegra_output_connector_detect(connector, force);
1527 }
1528
1529 static struct drm_connector_state *
1530 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1531 {
1532         struct tegra_sor_state *state = to_sor_state(connector->state);
1533         struct tegra_sor_state *copy;
1534
1535         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1536         if (!copy)
1537                 return NULL;
1538
1539         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1540
1541         return &copy->base;
1542 }
1543
1544 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1545         .reset = tegra_sor_connector_reset,
1546         .detect = tegra_sor_connector_detect,
1547         .fill_modes = drm_helper_probe_single_connector_modes,
1548         .destroy = tegra_output_connector_destroy,
1549         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1550         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1551         .late_register = tegra_sor_late_register,
1552         .early_unregister = tegra_sor_early_unregister,
1553 };
1554
1555 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1556 {
1557         struct tegra_output *output = connector_to_output(connector);
1558         struct tegra_sor *sor = to_sor(output);
1559         int err;
1560
1561         if (sor->aux)
1562                 drm_dp_aux_enable(sor->aux);
1563
1564         err = tegra_output_connector_get_modes(connector);
1565
1566         if (sor->aux)
1567                 drm_dp_aux_disable(sor->aux);
1568
1569         return err;
1570 }
1571
1572 static enum drm_mode_status
1573 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1574                                struct drm_display_mode *mode)
1575 {
1576         return MODE_OK;
1577 }
1578
1579 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1580         .get_modes = tegra_sor_connector_get_modes,
1581         .mode_valid = tegra_sor_connector_mode_valid,
1582 };
1583
1584 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1585         .destroy = tegra_output_encoder_destroy,
1586 };
1587
1588 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1589 {
1590         struct tegra_output *output = encoder_to_output(encoder);
1591         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1592         struct tegra_sor *sor = to_sor(output);
1593         u32 value;
1594         int err;
1595
1596         if (output->panel)
1597                 drm_panel_disable(output->panel);
1598
1599         err = tegra_sor_detach(sor);
1600         if (err < 0)
1601                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1602
1603         tegra_sor_writel(sor, 0, SOR_STATE1);
1604         tegra_sor_update(sor);
1605
1606         /*
1607          * The following accesses registers of the display controller, so make
1608          * sure it's only executed when the output is attached to one.
1609          */
1610         if (dc) {
1611                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1612                 value &= ~SOR_ENABLE(0);
1613                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1614
1615                 tegra_dc_commit(dc);
1616         }
1617
1618         err = tegra_sor_power_down(sor);
1619         if (err < 0)
1620                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1621
1622         if (sor->aux) {
1623                 err = drm_dp_aux_disable(sor->aux);
1624                 if (err < 0)
1625                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1626         }
1627
1628         err = tegra_io_pad_power_disable(sor->pad);
1629         if (err < 0)
1630                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1631
1632         if (output->panel)
1633                 drm_panel_unprepare(output->panel);
1634
1635         pm_runtime_put(sor->dev);
1636 }
1637
1638 #if 0
1639 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1640                               unsigned int *value)
1641 {
1642         unsigned int hfp, hsw, hbp, a = 0, b;
1643
1644         hfp = mode->hsync_start - mode->hdisplay;
1645         hsw = mode->hsync_end - mode->hsync_start;
1646         hbp = mode->htotal - mode->hsync_end;
1647
1648         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1649
1650         b = hfp - 1;
1651
1652         pr_info("a: %u, b: %u\n", a, b);
1653         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1654
1655         if (a + hsw + hbp <= 11) {
1656                 a = 1 + 11 - hsw - hbp;
1657                 pr_info("a: %u\n", a);
1658         }
1659
1660         if (a > b)
1661                 return -EINVAL;
1662
1663         if (hsw < 1)
1664                 return -EINVAL;
1665
1666         if (mode->hdisplay < 16)
1667                 return -EINVAL;
1668
1669         if (value) {
1670                 if (b > a && a % 2)
1671                         *value = a + 1;
1672                 else
1673                         *value = a;
1674         }
1675
1676         return 0;
1677 }
1678 #endif
1679
1680 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1681 {
1682         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1683         struct tegra_output *output = encoder_to_output(encoder);
1684         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1685         struct tegra_sor *sor = to_sor(output);
1686         struct tegra_sor_config config;
1687         struct tegra_sor_state *state;
1688         struct drm_dp_link link;
1689         u8 rate, lanes;
1690         unsigned int i;
1691         int err = 0;
1692         u32 value;
1693
1694         state = to_sor_state(output->connector.state);
1695
1696         pm_runtime_get_sync(sor->dev);
1697
1698         if (output->panel)
1699                 drm_panel_prepare(output->panel);
1700
1701         err = drm_dp_aux_enable(sor->aux);
1702         if (err < 0)
1703                 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1704
1705         err = drm_dp_link_probe(sor->aux, &link);
1706         if (err < 0) {
1707                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1708                 return;
1709         }
1710
1711         /* switch to safe parent clock */
1712         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1713         if (err < 0)
1714                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1715
1716         memset(&config, 0, sizeof(config));
1717         config.bits_per_pixel = state->bpc * 3;
1718
1719         err = tegra_sor_compute_config(sor, mode, &config, &link);
1720         if (err < 0)
1721                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1722
1723         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1724         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1725         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1726         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1727
1728         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1729         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1730         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1731         usleep_range(20, 100);
1732
1733         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1734         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1735         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1736
1737         value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1738                 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1739         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1740
1741         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1742         value |= SOR_PLL2_SEQ_PLLCAPPD;
1743         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1744         value |= SOR_PLL2_LVDS_ENABLE;
1745         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1746
1747         value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1748         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1749
1750         while (true) {
1751                 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1752                 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1753                         break;
1754
1755                 usleep_range(250, 1000);
1756         }
1757
1758         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1759         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1760         value &= ~SOR_PLL2_PORT_POWERDOWN;
1761         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1762
1763         /*
1764          * power up
1765          */
1766
1767         /* set safe link bandwidth (1.62 Gbps) */
1768         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1769         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1770         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1771         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1772
1773         /* step 1 */
1774         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1775         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1776                  SOR_PLL2_BANDGAP_POWERDOWN;
1777         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1778
1779         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1780         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1781         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1782
1783         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1784         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1785         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1786
1787         /* step 2 */
1788         err = tegra_io_pad_power_enable(sor->pad);
1789         if (err < 0)
1790                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1791
1792         usleep_range(5, 100);
1793
1794         /* step 3 */
1795         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1796         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1797         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1798
1799         usleep_range(20, 100);
1800
1801         /* step 4 */
1802         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1803         value &= ~SOR_PLL0_VCOPD;
1804         value &= ~SOR_PLL0_PWR;
1805         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1806
1807         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1808         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1809         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1810
1811         usleep_range(200, 1000);
1812
1813         /* step 5 */
1814         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1815         value &= ~SOR_PLL2_PORT_POWERDOWN;
1816         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1817
1818         /* XXX not in TRM */
1819         for (value = 0, i = 0; i < 5; i++)
1820                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1821                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1822
1823         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1824         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1825
1826         /* switch to DP parent clock */
1827         err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1828         if (err < 0)
1829                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1830
1831         /* power DP lanes */
1832         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1833
1834         if (link.num_lanes <= 2)
1835                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1836         else
1837                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1838
1839         if (link.num_lanes <= 1)
1840                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1841         else
1842                 value |= SOR_DP_PADCTL_PD_TXD_1;
1843
1844         if (link.num_lanes == 0)
1845                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1846         else
1847                 value |= SOR_DP_PADCTL_PD_TXD_0;
1848
1849         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1850
1851         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1852         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1853         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
1854         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1855
1856         /* start lane sequencer */
1857         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1858                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1859         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1860
1861         while (true) {
1862                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1863                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1864                         break;
1865
1866                 usleep_range(250, 1000);
1867         }
1868
1869         /* set link bandwidth */
1870         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1871         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1872         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1873         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1874
1875         tegra_sor_apply_config(sor, &config);
1876
1877         /* enable link */
1878         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1879         value |= SOR_DP_LINKCTL_ENABLE;
1880         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1881         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1882
1883         for (i = 0, value = 0; i < 4; i++) {
1884                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1885                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1886                                      SOR_DP_TPG_PATTERN_NONE;
1887                 value = (value << 8) | lane;
1888         }
1889
1890         tegra_sor_writel(sor, value, SOR_DP_TPG);
1891
1892         /* enable pad calibration logic */
1893         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1894         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1895         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1896
1897         err = drm_dp_link_probe(sor->aux, &link);
1898         if (err < 0)
1899                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1900
1901         err = drm_dp_link_power_up(sor->aux, &link);
1902         if (err < 0)
1903                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1904
1905         err = drm_dp_link_configure(sor->aux, &link);
1906         if (err < 0)
1907                 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1908
1909         rate = drm_dp_link_rate_to_bw_code(link.rate);
1910         lanes = link.num_lanes;
1911
1912         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1913         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1914         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1915         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1916
1917         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1918         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1919         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1920
1921         if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1922                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1923
1924         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1925
1926         /* disable training pattern generator */
1927
1928         for (i = 0; i < link.num_lanes; i++) {
1929                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1930                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1931                                      SOR_DP_TPG_PATTERN_NONE;
1932                 value = (value << 8) | lane;
1933         }
1934
1935         tegra_sor_writel(sor, value, SOR_DP_TPG);
1936
1937         err = tegra_sor_dp_train_fast(sor, &link);
1938         if (err < 0)
1939                 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1940
1941         dev_dbg(sor->dev, "fast link training succeeded\n");
1942
1943         err = tegra_sor_power_up(sor, 250);
1944         if (err < 0)
1945                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1946
1947         /* CSTM (LVDS, link A/B, upper) */
1948         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1949                 SOR_CSTM_UPPER;
1950         tegra_sor_writel(sor, value, SOR_CSTM);
1951
1952         /* use DP-A protocol */
1953         value = tegra_sor_readl(sor, SOR_STATE1);
1954         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1955         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1956         tegra_sor_writel(sor, value, SOR_STATE1);
1957
1958         tegra_sor_mode_set(sor, mode, state);
1959
1960         /* PWM setup */
1961         err = tegra_sor_setup_pwm(sor, 250);
1962         if (err < 0)
1963                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1964
1965         tegra_sor_update(sor);
1966
1967         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1968         value |= SOR_ENABLE(0);
1969         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1970
1971         tegra_dc_commit(dc);
1972
1973         err = tegra_sor_attach(sor);
1974         if (err < 0)
1975                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1976
1977         err = tegra_sor_wakeup(sor);
1978         if (err < 0)
1979                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1980
1981         if (output->panel)
1982                 drm_panel_enable(output->panel);
1983 }
1984
1985 static int
1986 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1987                                struct drm_crtc_state *crtc_state,
1988                                struct drm_connector_state *conn_state)
1989 {
1990         struct tegra_output *output = encoder_to_output(encoder);
1991         struct tegra_sor_state *state = to_sor_state(conn_state);
1992         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1993         unsigned long pclk = crtc_state->mode.clock * 1000;
1994         struct tegra_sor *sor = to_sor(output);
1995         struct drm_display_info *info;
1996         int err;
1997
1998         info = &output->connector.display_info;
1999
2000         /*
2001          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2002          * the pixel clock must be corrected accordingly.
2003          */
2004         if (pclk >= 340000000) {
2005                 state->link_speed = 20;
2006                 state->pclk = pclk / 2;
2007         } else {
2008                 state->link_speed = 10;
2009                 state->pclk = pclk;
2010         }
2011
2012         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2013                                          pclk, 0);
2014         if (err < 0) {
2015                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2016                 return err;
2017         }
2018
2019         switch (info->bpc) {
2020         case 8:
2021         case 6:
2022                 state->bpc = info->bpc;
2023                 break;
2024
2025         default:
2026                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2027                 state->bpc = 8;
2028                 break;
2029         }
2030
2031         return 0;
2032 }
2033
2034 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2035         .disable = tegra_sor_edp_disable,
2036         .enable = tegra_sor_edp_enable,
2037         .atomic_check = tegra_sor_encoder_atomic_check,
2038 };
2039
2040 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2041 {
2042         u32 value = 0;
2043         size_t i;
2044
2045         for (i = size; i > 0; i--)
2046                 value = (value << 8) | ptr[i - 1];
2047
2048         return value;
2049 }
2050
2051 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2052                                           const void *data, size_t size)
2053 {
2054         const u8 *ptr = data;
2055         unsigned long offset;
2056         size_t i, j;
2057         u32 value;
2058
2059         switch (ptr[0]) {
2060         case HDMI_INFOFRAME_TYPE_AVI:
2061                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2062                 break;
2063
2064         case HDMI_INFOFRAME_TYPE_AUDIO:
2065                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2066                 break;
2067
2068         case HDMI_INFOFRAME_TYPE_VENDOR:
2069                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2070                 break;
2071
2072         default:
2073                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2074                         ptr[0]);
2075                 return;
2076         }
2077
2078         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2079                 INFOFRAME_HEADER_VERSION(ptr[1]) |
2080                 INFOFRAME_HEADER_LEN(ptr[2]);
2081         tegra_sor_writel(sor, value, offset);
2082         offset++;
2083
2084         /*
2085          * Each subpack contains 7 bytes, divided into:
2086          * - subpack_low: bytes 0 - 3
2087          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2088          */
2089         for (i = 3, j = 0; i < size; i += 7, j += 8) {
2090                 size_t rem = size - i, num = min_t(size_t, rem, 4);
2091
2092                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2093                 tegra_sor_writel(sor, value, offset++);
2094
2095                 num = min_t(size_t, rem - num, 3);
2096
2097                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2098                 tegra_sor_writel(sor, value, offset++);
2099         }
2100 }
2101
2102 static int
2103 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2104                                    const struct drm_display_mode *mode)
2105 {
2106         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2107         struct hdmi_avi_infoframe frame;
2108         u32 value;
2109         int err;
2110
2111         /* disable AVI infoframe */
2112         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2113         value &= ~INFOFRAME_CTRL_SINGLE;
2114         value &= ~INFOFRAME_CTRL_OTHER;
2115         value &= ~INFOFRAME_CTRL_ENABLE;
2116         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2117
2118         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2119                                                        &sor->output.connector, mode);
2120         if (err < 0) {
2121                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2122                 return err;
2123         }
2124
2125         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2126         if (err < 0) {
2127                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2128                 return err;
2129         }
2130
2131         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2132
2133         /* enable AVI infoframe */
2134         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2135         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2136         value |= INFOFRAME_CTRL_ENABLE;
2137         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2138
2139         return 0;
2140 }
2141
2142 static void tegra_sor_write_eld(struct tegra_sor *sor)
2143 {
2144         size_t length = drm_eld_size(sor->output.connector.eld), i;
2145
2146         for (i = 0; i < length; i++)
2147                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2148                                  SOR_AUDIO_HDA_ELD_BUFWR);
2149
2150         /*
2151          * The HDA codec will always report an ELD buffer size of 96 bytes and
2152          * the HDA codec driver will check that each byte read from the buffer
2153          * is valid. Therefore every byte must be written, even if no 96 bytes
2154          * were parsed from EDID.
2155          */
2156         for (i = length; i < 96; i++)
2157                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2158 }
2159
2160 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2161 {
2162         u32 value;
2163
2164         /*
2165          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2166          * is used for interoperability between the HDA codec driver and the
2167          * HDMI/DP driver.
2168          */
2169         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2170         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2171         tegra_sor_writel(sor, value, SOR_INT_MASK);
2172
2173         tegra_sor_write_eld(sor);
2174
2175         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2176         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2177 }
2178
2179 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2180 {
2181         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2182         tegra_sor_writel(sor, 0, SOR_INT_MASK);
2183         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2184 }
2185
2186 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2187 {
2188         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2189         struct hdmi_audio_infoframe frame;
2190         u32 value;
2191         int err;
2192
2193         err = hdmi_audio_infoframe_init(&frame);
2194         if (err < 0) {
2195                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2196                 return err;
2197         }
2198
2199         frame.channels = sor->format.channels;
2200
2201         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2202         if (err < 0) {
2203                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2204                 return err;
2205         }
2206
2207         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2208
2209         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2210         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2211         value |= INFOFRAME_CTRL_ENABLE;
2212         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2213
2214         return 0;
2215 }
2216
2217 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2218 {
2219         u32 value;
2220
2221         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2222
2223         /* select HDA audio input */
2224         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2225         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2226
2227         /* inject null samples */
2228         if (sor->format.channels != 2)
2229                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2230         else
2231                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2232
2233         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2234
2235         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2236
2237         /* enable advertising HBR capability */
2238         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2239
2240         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2241
2242         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2243                 SOR_HDMI_SPARE_CTS_RESET(1) |
2244                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2245         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2246
2247         /* enable HW CTS */
2248         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2249         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2250
2251         /* allow packet to be sent */
2252         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2253         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2254
2255         /* reset N counter and enable lookup */
2256         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2257         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2258
2259         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2260         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2261         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2262
2263         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2264         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2265
2266         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2267         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2268
2269         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2270         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2271
2272         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2273         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2274         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2275
2276         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2277         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2278         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2279
2280         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2281         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2282         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2283
2284         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2285         value &= ~SOR_HDMI_AUDIO_N_RESET;
2286         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2287
2288         tegra_sor_hdmi_enable_audio_infoframe(sor);
2289 }
2290
2291 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2292 {
2293         u32 value;
2294
2295         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2296         value &= ~INFOFRAME_CTRL_ENABLE;
2297         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2298 }
2299
2300 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2301 {
2302         tegra_sor_hdmi_disable_audio_infoframe(sor);
2303 }
2304
2305 static struct tegra_sor_hdmi_settings *
2306 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2307 {
2308         unsigned int i;
2309
2310         for (i = 0; i < sor->num_settings; i++)
2311                 if (frequency <= sor->settings[i].frequency)
2312                         return &sor->settings[i];
2313
2314         return NULL;
2315 }
2316
2317 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2318 {
2319         u32 value;
2320
2321         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2322         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2323         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2324         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2325 }
2326
2327 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2328 {
2329         struct i2c_adapter *ddc = sor->output.ddc;
2330
2331         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2332         drm_scdc_set_scrambling(ddc, false);
2333
2334         tegra_sor_hdmi_disable_scrambling(sor);
2335 }
2336
2337 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2338 {
2339         if (sor->scdc_enabled) {
2340                 cancel_delayed_work_sync(&sor->scdc);
2341                 tegra_sor_hdmi_scdc_disable(sor);
2342         }
2343 }
2344
2345 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2346 {
2347         u32 value;
2348
2349         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2350         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2351         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2352         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2353 }
2354
2355 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2356 {
2357         struct i2c_adapter *ddc = sor->output.ddc;
2358
2359         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2360         drm_scdc_set_scrambling(ddc, true);
2361
2362         tegra_sor_hdmi_enable_scrambling(sor);
2363 }
2364
2365 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2366 {
2367         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2368         struct i2c_adapter *ddc = sor->output.ddc;
2369
2370         if (!drm_scdc_get_scrambling_status(ddc)) {
2371                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2372                 tegra_sor_hdmi_scdc_enable(sor);
2373         }
2374
2375         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2376 }
2377
2378 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2379 {
2380         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2381         struct drm_display_mode *mode;
2382
2383         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2384
2385         if (mode->clock >= 340000 && scdc->supported) {
2386                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2387                 tegra_sor_hdmi_scdc_enable(sor);
2388                 sor->scdc_enabled = true;
2389         }
2390 }
2391
2392 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2393 {
2394         struct tegra_output *output = encoder_to_output(encoder);
2395         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2396         struct tegra_sor *sor = to_sor(output);
2397         u32 value;
2398         int err;
2399
2400         tegra_sor_audio_unprepare(sor);
2401         tegra_sor_hdmi_scdc_stop(sor);
2402
2403         err = tegra_sor_detach(sor);
2404         if (err < 0)
2405                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2406
2407         tegra_sor_writel(sor, 0, SOR_STATE1);
2408         tegra_sor_update(sor);
2409
2410         /* disable display to SOR clock */
2411         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2412
2413         if (!sor->soc->has_nvdisplay)
2414                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2415         else
2416                 value &= ~SOR_ENABLE(sor->index);
2417
2418         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2419
2420         tegra_dc_commit(dc);
2421
2422         err = tegra_sor_power_down(sor);
2423         if (err < 0)
2424                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2425
2426         err = tegra_io_pad_power_disable(sor->pad);
2427         if (err < 0)
2428                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2429
2430         pm_runtime_put(sor->dev);
2431 }
2432
2433 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2434 {
2435         struct tegra_output *output = encoder_to_output(encoder);
2436         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2437         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2438         struct tegra_sor_hdmi_settings *settings;
2439         struct tegra_sor *sor = to_sor(output);
2440         struct tegra_sor_state *state;
2441         struct drm_display_mode *mode;
2442         unsigned long rate, pclk;
2443         unsigned int div, i;
2444         u32 value;
2445         int err;
2446
2447         state = to_sor_state(output->connector.state);
2448         mode = &encoder->crtc->state->adjusted_mode;
2449         pclk = mode->clock * 1000;
2450
2451         pm_runtime_get_sync(sor->dev);
2452
2453         /* switch to safe parent clock */
2454         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2455         if (err < 0) {
2456                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2457                 return;
2458         }
2459
2460         div = clk_get_rate(sor->clk) / 1000000 * 4;
2461
2462         err = tegra_io_pad_power_enable(sor->pad);
2463         if (err < 0)
2464                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2465
2466         usleep_range(20, 100);
2467
2468         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2469         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2470         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2471
2472         usleep_range(20, 100);
2473
2474         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2475         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2476         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2477
2478         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2479         value &= ~SOR_PLL0_VCOPD;
2480         value &= ~SOR_PLL0_PWR;
2481         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2482
2483         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2484         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2485         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2486
2487         usleep_range(200, 400);
2488
2489         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2490         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2491         value &= ~SOR_PLL2_PORT_POWERDOWN;
2492         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2493
2494         usleep_range(20, 100);
2495
2496         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2497         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2498                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2499         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2500
2501         while (true) {
2502                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2503                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2504                         break;
2505
2506                 usleep_range(250, 1000);
2507         }
2508
2509         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2510                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2511         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2512
2513         while (true) {
2514                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2515                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2516                         break;
2517
2518                 usleep_range(250, 1000);
2519         }
2520
2521         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2522         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2523         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2524
2525         if (mode->clock < 340000) {
2526                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2527                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2528         } else {
2529                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2530                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2531         }
2532
2533         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2534         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2535
2536         /* SOR pad PLL stabilization time */
2537         usleep_range(250, 1000);
2538
2539         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2540         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2541         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2542         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2543
2544         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2545         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2546         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2547         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2548         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2549         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2550
2551         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2552                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2553         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2554
2555         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2556                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2557         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2558         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2559
2560         if (!sor->soc->has_nvdisplay) {
2561                 /* program the reference clock */
2562                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2563                 tegra_sor_writel(sor, value, SOR_REFCLK);
2564         }
2565
2566         /* XXX not in TRM */
2567         for (value = 0, i = 0; i < 5; i++)
2568                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2569                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2570
2571         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2572         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2573
2574         /* switch to parent clock */
2575         err = clk_set_parent(sor->clk, sor->clk_parent);
2576         if (err < 0) {
2577                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2578                 return;
2579         }
2580
2581         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2582         if (err < 0) {
2583                 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2584                 return;
2585         }
2586
2587         /* adjust clock rate for HDMI 2.0 modes */
2588         rate = clk_get_rate(sor->clk_parent);
2589
2590         if (mode->clock >= 340000)
2591                 rate /= 2;
2592
2593         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2594
2595         clk_set_rate(sor->clk, rate);
2596
2597         if (!sor->soc->has_nvdisplay) {
2598                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2599
2600                 /* XXX is this the proper check? */
2601                 if (mode->clock < 75000)
2602                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2603
2604                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2605         }
2606
2607         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2608
2609         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2610                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2611         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2612
2613         if (!dc->soc->has_nvdisplay) {
2614                 /* H_PULSE2 setup */
2615                 pulse_start = h_ref_to_sync +
2616                               (mode->hsync_end - mode->hsync_start) +
2617                               (mode->htotal - mode->hsync_end) - 10;
2618
2619                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2620                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2621                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2622
2623                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2624                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2625
2626                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2627                 value |= H_PULSE2_ENABLE;
2628                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2629         }
2630
2631         /* infoframe setup */
2632         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2633         if (err < 0)
2634                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2635
2636         /* XXX HDMI audio support not implemented yet */
2637         tegra_sor_hdmi_disable_audio_infoframe(sor);
2638
2639         /* use single TMDS protocol */
2640         value = tegra_sor_readl(sor, SOR_STATE1);
2641         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2642         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2643         tegra_sor_writel(sor, value, SOR_STATE1);
2644
2645         /* power up pad calibration */
2646         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2647         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2648         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2649
2650         /* production settings */
2651         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2652         if (!settings) {
2653                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2654                         mode->clock * 1000);
2655                 return;
2656         }
2657
2658         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2659         value &= ~SOR_PLL0_ICHPMP_MASK;
2660         value &= ~SOR_PLL0_FILTER_MASK;
2661         value &= ~SOR_PLL0_VCOCAP_MASK;
2662         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2663         value |= SOR_PLL0_FILTER(settings->filter);
2664         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2665         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2666
2667         /* XXX not in TRM */
2668         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2669         value &= ~SOR_PLL1_LOADADJ_MASK;
2670         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2671         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2672         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2673         value |= SOR_PLL1_TMDS_TERM;
2674         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2675
2676         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2677         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2678         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2679         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2680         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2681         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2682         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2683         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2684         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2685         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2686
2687         value = settings->drive_current[3] << 24 |
2688                 settings->drive_current[2] << 16 |
2689                 settings->drive_current[1] <<  8 |
2690                 settings->drive_current[0] <<  0;
2691         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2692
2693         value = settings->preemphasis[3] << 24 |
2694                 settings->preemphasis[2] << 16 |
2695                 settings->preemphasis[1] <<  8 |
2696                 settings->preemphasis[0] <<  0;
2697         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2698
2699         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2700         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2701         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2702         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2703         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2704
2705         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2706         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2707         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2708         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2709
2710         /* power down pad calibration */
2711         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2712         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2713         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2714
2715         if (!dc->soc->has_nvdisplay) {
2716                 /* miscellaneous display controller settings */
2717                 value = VSYNC_H_POSITION(1);
2718                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2719         }
2720
2721         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2722         value &= ~DITHER_CONTROL_MASK;
2723         value &= ~BASE_COLOR_SIZE_MASK;
2724
2725         switch (state->bpc) {
2726         case 6:
2727                 value |= BASE_COLOR_SIZE_666;
2728                 break;
2729
2730         case 8:
2731                 value |= BASE_COLOR_SIZE_888;
2732                 break;
2733
2734         case 10:
2735                 value |= BASE_COLOR_SIZE_101010;
2736                 break;
2737
2738         case 12:
2739                 value |= BASE_COLOR_SIZE_121212;
2740                 break;
2741
2742         default:
2743                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2744                 value |= BASE_COLOR_SIZE_888;
2745                 break;
2746         }
2747
2748         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2749
2750         /* XXX set display head owner */
2751         value = tegra_sor_readl(sor, SOR_STATE1);
2752         value &= ~SOR_STATE_ASY_OWNER_MASK;
2753         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2754         tegra_sor_writel(sor, value, SOR_STATE1);
2755
2756         err = tegra_sor_power_up(sor, 250);
2757         if (err < 0)
2758                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2759
2760         /* configure dynamic range of output */
2761         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2762         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2763         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2764         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2765
2766         /* configure colorspace */
2767         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2768         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2769         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2770         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2771
2772         tegra_sor_mode_set(sor, mode, state);
2773
2774         tegra_sor_update(sor);
2775
2776         /* program preamble timing in SOR (XXX) */
2777         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2778         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2779         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2780
2781         err = tegra_sor_attach(sor);
2782         if (err < 0)
2783                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2784
2785         /* enable display to SOR clock and generate HDMI preamble */
2786         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2787
2788         if (!sor->soc->has_nvdisplay)
2789                 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2790         else
2791                 value |= SOR_ENABLE(sor->index);
2792
2793         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2794
2795         if (dc->soc->has_nvdisplay) {
2796                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2797                 value &= ~PROTOCOL_MASK;
2798                 value |= PROTOCOL_SINGLE_TMDS_A;
2799                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2800         }
2801
2802         tegra_dc_commit(dc);
2803
2804         err = tegra_sor_wakeup(sor);
2805         if (err < 0)
2806                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2807
2808         tegra_sor_hdmi_scdc_start(sor);
2809         tegra_sor_audio_prepare(sor);
2810 }
2811
2812 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2813         .disable = tegra_sor_hdmi_disable,
2814         .enable = tegra_sor_hdmi_enable,
2815         .atomic_check = tegra_sor_encoder_atomic_check,
2816 };
2817
2818 static int tegra_sor_init(struct host1x_client *client)
2819 {
2820         struct drm_device *drm = dev_get_drvdata(client->parent);
2821         const struct drm_encoder_helper_funcs *helpers = NULL;
2822         struct tegra_sor *sor = host1x_client_to_sor(client);
2823         int connector = DRM_MODE_CONNECTOR_Unknown;
2824         int encoder = DRM_MODE_ENCODER_NONE;
2825         int err;
2826
2827         if (!sor->aux) {
2828                 if (sor->soc->supports_hdmi) {
2829                         connector = DRM_MODE_CONNECTOR_HDMIA;
2830                         encoder = DRM_MODE_ENCODER_TMDS;
2831                         helpers = &tegra_sor_hdmi_helpers;
2832                 } else if (sor->soc->supports_lvds) {
2833                         connector = DRM_MODE_CONNECTOR_LVDS;
2834                         encoder = DRM_MODE_ENCODER_LVDS;
2835                 }
2836         } else {
2837                 if (sor->soc->supports_edp) {
2838                         connector = DRM_MODE_CONNECTOR_eDP;
2839                         encoder = DRM_MODE_ENCODER_TMDS;
2840                         helpers = &tegra_sor_edp_helpers;
2841                 } else if (sor->soc->supports_dp) {
2842                         connector = DRM_MODE_CONNECTOR_DisplayPort;
2843                         encoder = DRM_MODE_ENCODER_TMDS;
2844                 }
2845         }
2846
2847         sor->output.dev = sor->dev;
2848
2849         drm_connector_init(drm, &sor->output.connector,
2850                            &tegra_sor_connector_funcs,
2851                            connector);
2852         drm_connector_helper_add(&sor->output.connector,
2853                                  &tegra_sor_connector_helper_funcs);
2854         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2855
2856         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2857                          encoder, NULL);
2858         drm_encoder_helper_add(&sor->output.encoder, helpers);
2859
2860         drm_connector_attach_encoder(&sor->output.connector,
2861                                           &sor->output.encoder);
2862         drm_connector_register(&sor->output.connector);
2863
2864         err = tegra_output_init(drm, &sor->output);
2865         if (err < 0) {
2866                 dev_err(client->dev, "failed to initialize output: %d\n", err);
2867                 return err;
2868         }
2869
2870         tegra_output_find_possible_crtcs(&sor->output, drm);
2871
2872         if (sor->aux) {
2873                 err = drm_dp_aux_attach(sor->aux, &sor->output);
2874                 if (err < 0) {
2875                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
2876                         return err;
2877                 }
2878         }
2879
2880         /*
2881          * XXX: Remove this reset once proper hand-over from firmware to
2882          * kernel is possible.
2883          */
2884         if (sor->rst) {
2885                 err = reset_control_acquire(sor->rst);
2886                 if (err < 0) {
2887                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
2888                                 err);
2889                         return err;
2890                 }
2891
2892                 err = reset_control_assert(sor->rst);
2893                 if (err < 0) {
2894                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2895                                 err);
2896                         return err;
2897                 }
2898         }
2899
2900         err = clk_prepare_enable(sor->clk);
2901         if (err < 0) {
2902                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2903                 return err;
2904         }
2905
2906         usleep_range(1000, 3000);
2907
2908         if (sor->rst) {
2909                 err = reset_control_deassert(sor->rst);
2910                 if (err < 0) {
2911                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2912                                 err);
2913                         return err;
2914                 }
2915
2916                 reset_control_release(sor->rst);
2917         }
2918
2919         err = clk_prepare_enable(sor->clk_safe);
2920         if (err < 0)
2921                 return err;
2922
2923         err = clk_prepare_enable(sor->clk_dp);
2924         if (err < 0)
2925                 return err;
2926
2927         return 0;
2928 }
2929
2930 static int tegra_sor_exit(struct host1x_client *client)
2931 {
2932         struct tegra_sor *sor = host1x_client_to_sor(client);
2933         int err;
2934
2935         tegra_output_exit(&sor->output);
2936
2937         if (sor->aux) {
2938                 err = drm_dp_aux_detach(sor->aux);
2939                 if (err < 0) {
2940                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
2941                         return err;
2942                 }
2943         }
2944
2945         clk_disable_unprepare(sor->clk_safe);
2946         clk_disable_unprepare(sor->clk_dp);
2947         clk_disable_unprepare(sor->clk);
2948
2949         return 0;
2950 }
2951
2952 static const struct host1x_client_ops sor_client_ops = {
2953         .init = tegra_sor_init,
2954         .exit = tegra_sor_exit,
2955 };
2956
2957 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2958         .name = "eDP",
2959 };
2960
2961 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2962 {
2963         int err;
2964
2965         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2966         if (IS_ERR(sor->avdd_io_supply)) {
2967                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2968                         PTR_ERR(sor->avdd_io_supply));
2969                 return PTR_ERR(sor->avdd_io_supply);
2970         }
2971
2972         err = regulator_enable(sor->avdd_io_supply);
2973         if (err < 0) {
2974                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2975                         err);
2976                 return err;
2977         }
2978
2979         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2980         if (IS_ERR(sor->vdd_pll_supply)) {
2981                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2982                         PTR_ERR(sor->vdd_pll_supply));
2983                 return PTR_ERR(sor->vdd_pll_supply);
2984         }
2985
2986         err = regulator_enable(sor->vdd_pll_supply);
2987         if (err < 0) {
2988                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2989                         err);
2990                 return err;
2991         }
2992
2993         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2994         if (IS_ERR(sor->hdmi_supply)) {
2995                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2996                         PTR_ERR(sor->hdmi_supply));
2997                 return PTR_ERR(sor->hdmi_supply);
2998         }
2999
3000         err = regulator_enable(sor->hdmi_supply);
3001         if (err < 0) {
3002                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3003                 return err;
3004         }
3005
3006         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3007
3008         return 0;
3009 }
3010
3011 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3012 {
3013         regulator_disable(sor->hdmi_supply);
3014         regulator_disable(sor->vdd_pll_supply);
3015         regulator_disable(sor->avdd_io_supply);
3016
3017         return 0;
3018 }
3019
3020 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3021         .name = "HDMI",
3022         .probe = tegra_sor_hdmi_probe,
3023         .remove = tegra_sor_hdmi_remove,
3024 };
3025
3026 static const u8 tegra124_sor_xbar_cfg[5] = {
3027         0, 1, 2, 3, 4
3028 };
3029
3030 static const struct tegra_sor_regs tegra124_sor_regs = {
3031         .head_state0 = 0x05,
3032         .head_state1 = 0x07,
3033         .head_state2 = 0x09,
3034         .head_state3 = 0x0b,
3035         .head_state4 = 0x0d,
3036         .head_state5 = 0x0f,
3037         .pll0 = 0x17,
3038         .pll1 = 0x18,
3039         .pll2 = 0x19,
3040         .pll3 = 0x1a,
3041         .dp_padctl0 = 0x5c,
3042         .dp_padctl2 = 0x73,
3043 };
3044
3045 static const struct tegra_sor_soc tegra124_sor = {
3046         .supports_edp = true,
3047         .supports_lvds = true,
3048         .supports_hdmi = false,
3049         .supports_dp = false,
3050         .regs = &tegra124_sor_regs,
3051         .has_nvdisplay = false,
3052         .xbar_cfg = tegra124_sor_xbar_cfg,
3053 };
3054
3055 static const struct tegra_sor_regs tegra210_sor_regs = {
3056         .head_state0 = 0x05,
3057         .head_state1 = 0x07,
3058         .head_state2 = 0x09,
3059         .head_state3 = 0x0b,
3060         .head_state4 = 0x0d,
3061         .head_state5 = 0x0f,
3062         .pll0 = 0x17,
3063         .pll1 = 0x18,
3064         .pll2 = 0x19,
3065         .pll3 = 0x1a,
3066         .dp_padctl0 = 0x5c,
3067         .dp_padctl2 = 0x73,
3068 };
3069
3070 static const struct tegra_sor_soc tegra210_sor = {
3071         .supports_edp = true,
3072         .supports_lvds = false,
3073         .supports_hdmi = false,
3074         .supports_dp = false,
3075         .regs = &tegra210_sor_regs,
3076         .has_nvdisplay = false,
3077         .xbar_cfg = tegra124_sor_xbar_cfg,
3078 };
3079
3080 static const u8 tegra210_sor_xbar_cfg[5] = {
3081         2, 1, 0, 3, 4
3082 };
3083
3084 static const struct tegra_sor_soc tegra210_sor1 = {
3085         .supports_edp = false,
3086         .supports_lvds = false,
3087         .supports_hdmi = true,
3088         .supports_dp = true,
3089
3090         .regs = &tegra210_sor_regs,
3091         .has_nvdisplay = false,
3092
3093         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3094         .settings = tegra210_sor_hdmi_defaults,
3095
3096         .xbar_cfg = tegra210_sor_xbar_cfg,
3097 };
3098
3099 static const struct tegra_sor_regs tegra186_sor_regs = {
3100         .head_state0 = 0x151,
3101         .head_state1 = 0x154,
3102         .head_state2 = 0x157,
3103         .head_state3 = 0x15a,
3104         .head_state4 = 0x15d,
3105         .head_state5 = 0x160,
3106         .pll0 = 0x163,
3107         .pll1 = 0x164,
3108         .pll2 = 0x165,
3109         .pll3 = 0x166,
3110         .dp_padctl0 = 0x168,
3111         .dp_padctl2 = 0x16a,
3112 };
3113
3114 static const struct tegra_sor_soc tegra186_sor = {
3115         .supports_edp = false,
3116         .supports_lvds = false,
3117         .supports_hdmi = false,
3118         .supports_dp = true,
3119
3120         .regs = &tegra186_sor_regs,
3121         .has_nvdisplay = true,
3122
3123         .xbar_cfg = tegra124_sor_xbar_cfg,
3124 };
3125
3126 static const struct tegra_sor_soc tegra186_sor1 = {
3127         .supports_edp = false,
3128         .supports_lvds = false,
3129         .supports_hdmi = true,
3130         .supports_dp = true,
3131
3132         .regs = &tegra186_sor_regs,
3133         .has_nvdisplay = true,
3134
3135         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3136         .settings = tegra186_sor_hdmi_defaults,
3137
3138         .xbar_cfg = tegra124_sor_xbar_cfg,
3139 };
3140
3141 static const struct tegra_sor_regs tegra194_sor_regs = {
3142         .head_state0 = 0x151,
3143         .head_state1 = 0x155,
3144         .head_state2 = 0x159,
3145         .head_state3 = 0x15d,
3146         .head_state4 = 0x161,
3147         .head_state5 = 0x165,
3148         .pll0 = 0x169,
3149         .pll1 = 0x16a,
3150         .pll2 = 0x16b,
3151         .pll3 = 0x16c,
3152         .dp_padctl0 = 0x16e,
3153         .dp_padctl2 = 0x16f,
3154 };
3155
3156 static const struct tegra_sor_soc tegra194_sor = {
3157         .supports_edp = true,
3158         .supports_lvds = false,
3159         .supports_hdmi = true,
3160         .supports_dp = true,
3161
3162         .regs = &tegra194_sor_regs,
3163         .has_nvdisplay = true,
3164
3165         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3166         .settings = tegra194_sor_hdmi_defaults,
3167
3168         .xbar_cfg = tegra210_sor_xbar_cfg,
3169 };
3170
3171 static const struct of_device_id tegra_sor_of_match[] = {
3172         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3173         { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3174         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3175         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3176         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3177         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3178         { },
3179 };
3180 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3181
3182 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3183 {
3184         struct device_node *np = sor->dev->of_node;
3185         u32 xbar_cfg[5];
3186         unsigned int i;
3187         u32 value;
3188         int err;
3189
3190         if (sor->soc->has_nvdisplay) {
3191                 err = of_property_read_u32(np, "nvidia,interface", &value);
3192                 if (err < 0)
3193                         return err;
3194
3195                 sor->index = value;
3196
3197                 /*
3198                  * override the default that we already set for Tegra210 and
3199                  * earlier
3200                  */
3201                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3202         }
3203
3204         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3205         if (err < 0) {
3206                 /* fall back to default per-SoC XBAR configuration */
3207                 for (i = 0; i < 5; i++)
3208                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3209         } else {
3210                 /* copy cells to SOR XBAR configuration */
3211                 for (i = 0; i < 5; i++)
3212                         sor->xbar_cfg[i] = xbar_cfg[i];
3213         }
3214
3215         return 0;
3216 }
3217
3218 static irqreturn_t tegra_sor_irq(int irq, void *data)
3219 {
3220         struct tegra_sor *sor = data;
3221         u32 value;
3222
3223         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3224         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3225
3226         if (value & SOR_INT_CODEC_SCRATCH0) {
3227                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3228
3229                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3230                         unsigned int format;
3231
3232                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3233
3234                         tegra_hda_parse_format(format, &sor->format);
3235
3236                         tegra_sor_hdmi_audio_enable(sor);
3237                 } else {
3238                         tegra_sor_hdmi_audio_disable(sor);
3239                 }
3240         }
3241
3242         return IRQ_HANDLED;
3243 }
3244
3245 static int tegra_sor_probe(struct platform_device *pdev)
3246 {
3247         struct device_node *np;
3248         struct tegra_sor *sor;
3249         struct resource *regs;
3250         int err;
3251
3252         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3253         if (!sor)
3254                 return -ENOMEM;
3255
3256         sor->soc = of_device_get_match_data(&pdev->dev);
3257         sor->output.dev = sor->dev = &pdev->dev;
3258
3259         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3260                                      sor->soc->num_settings *
3261                                         sizeof(*sor->settings),
3262                                      GFP_KERNEL);
3263         if (!sor->settings)
3264                 return -ENOMEM;
3265
3266         sor->num_settings = sor->soc->num_settings;
3267
3268         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3269         if (np) {
3270                 sor->aux = drm_dp_aux_find_by_of_node(np);
3271                 of_node_put(np);
3272
3273                 if (!sor->aux)
3274                         return -EPROBE_DEFER;
3275         }
3276
3277         if (!sor->aux) {
3278                 if (sor->soc->supports_hdmi) {
3279                         sor->ops = &tegra_sor_hdmi_ops;
3280                         sor->pad = TEGRA_IO_PAD_HDMI;
3281                 } else if (sor->soc->supports_lvds) {
3282                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3283                         return -ENODEV;
3284                 } else {
3285                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3286                         return -ENODEV;
3287                 }
3288         } else {
3289                 if (sor->soc->supports_edp) {
3290                         sor->ops = &tegra_sor_edp_ops;
3291                         sor->pad = TEGRA_IO_PAD_LVDS;
3292                 } else if (sor->soc->supports_dp) {
3293                         dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3294                         return -ENODEV;
3295                 } else {
3296                         dev_err(&pdev->dev, "unknown (DP) support\n");
3297                         return -ENODEV;
3298                 }
3299         }
3300
3301         err = tegra_sor_parse_dt(sor);
3302         if (err < 0)
3303                 return err;
3304
3305         err = tegra_output_probe(&sor->output);
3306         if (err < 0) {
3307                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3308                 return err;
3309         }
3310
3311         if (sor->ops && sor->ops->probe) {
3312                 err = sor->ops->probe(sor);
3313                 if (err < 0) {
3314                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3315                                 sor->ops->name, err);
3316                         goto output;
3317                 }
3318         }
3319
3320         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3321         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3322         if (IS_ERR(sor->regs)) {
3323                 err = PTR_ERR(sor->regs);
3324                 goto remove;
3325         }
3326
3327         err = platform_get_irq(pdev, 0);
3328         if (err < 0) {
3329                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3330                 goto remove;
3331         }
3332
3333         sor->irq = err;
3334
3335         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3336                                dev_name(sor->dev), sor);
3337         if (err < 0) {
3338                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3339                 goto remove;
3340         }
3341
3342         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3343         if (IS_ERR(sor->rst)) {
3344                 err = PTR_ERR(sor->rst);
3345
3346                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3347                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3348                                 err);
3349                         goto remove;
3350                 }
3351
3352                 /*
3353                  * At this point, the reset control is most likely being used
3354                  * by the generic power domain implementation. With any luck
3355                  * the power domain will have taken care of resetting the SOR
3356                  * and we don't have to do anything.
3357                  */
3358                 sor->rst = NULL;
3359         }
3360
3361         sor->clk = devm_clk_get(&pdev->dev, NULL);
3362         if (IS_ERR(sor->clk)) {
3363                 err = PTR_ERR(sor->clk);
3364                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3365                 goto remove;
3366         }
3367
3368         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3369                 struct device_node *np = pdev->dev.of_node;
3370                 const char *name;
3371
3372                 /*
3373                  * For backwards compatibility with Tegra210 device trees,
3374                  * fall back to the old clock name "source" if the new "out"
3375                  * clock is not available.
3376                  */
3377                 if (of_property_match_string(np, "clock-names", "out") < 0)
3378                         name = "source";
3379                 else
3380                         name = "out";
3381
3382                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3383                 if (IS_ERR(sor->clk_out)) {
3384                         err = PTR_ERR(sor->clk_out);
3385                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3386                                 name, err);
3387                         goto remove;
3388                 }
3389         } else {
3390                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3391                 sor->clk_out = sor->clk;
3392         }
3393
3394         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3395         if (IS_ERR(sor->clk_parent)) {
3396                 err = PTR_ERR(sor->clk_parent);
3397                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3398                 goto remove;
3399         }
3400
3401         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3402         if (IS_ERR(sor->clk_safe)) {
3403                 err = PTR_ERR(sor->clk_safe);
3404                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3405                 goto remove;
3406         }
3407
3408         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3409         if (IS_ERR(sor->clk_dp)) {
3410                 err = PTR_ERR(sor->clk_dp);
3411                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3412                 goto remove;
3413         }
3414
3415         /*
3416          * Starting with Tegra186, the BPMP provides an implementation for
3417          * the pad output clock, so we have to look it up from device tree.
3418          */
3419         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3420         if (IS_ERR(sor->clk_pad)) {
3421                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3422                         err = PTR_ERR(sor->clk_pad);
3423                         goto remove;
3424                 }
3425
3426                 /*
3427                  * If the pad output clock is not available, then we assume
3428                  * we're on Tegra210 or earlier and have to provide our own
3429                  * implementation.
3430                  */
3431                 sor->clk_pad = NULL;
3432         }
3433
3434         /*
3435          * The bootloader may have set up the SOR such that it's module clock
3436          * is sourced by one of the display PLLs. However, that doesn't work
3437          * without properly having set up other bits of the SOR.
3438          */
3439         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3440         if (err < 0) {
3441                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3442                 goto remove;
3443         }
3444
3445         platform_set_drvdata(pdev, sor);
3446         pm_runtime_enable(&pdev->dev);
3447
3448         /*
3449          * On Tegra210 and earlier, provide our own implementation for the
3450          * pad output clock.
3451          */
3452         if (!sor->clk_pad) {
3453                 err = pm_runtime_get_sync(&pdev->dev);
3454                 if (err < 0) {
3455                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3456                                 err);
3457                         goto remove;
3458                 }
3459
3460                 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3461                                                           "sor1_pad_clkout");
3462                 pm_runtime_put(&pdev->dev);
3463         }
3464
3465         if (IS_ERR(sor->clk_pad)) {
3466                 err = PTR_ERR(sor->clk_pad);
3467                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3468                         err);
3469                 goto remove;
3470         }
3471
3472         INIT_LIST_HEAD(&sor->client.list);
3473         sor->client.ops = &sor_client_ops;
3474         sor->client.dev = &pdev->dev;
3475
3476         err = host1x_client_register(&sor->client);
3477         if (err < 0) {
3478                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3479                         err);
3480                 goto remove;
3481         }
3482
3483         return 0;
3484
3485 remove:
3486         if (sor->ops && sor->ops->remove)
3487                 sor->ops->remove(sor);
3488 output:
3489         tegra_output_remove(&sor->output);
3490         return err;
3491 }
3492
3493 static int tegra_sor_remove(struct platform_device *pdev)
3494 {
3495         struct tegra_sor *sor = platform_get_drvdata(pdev);
3496         int err;
3497
3498         pm_runtime_disable(&pdev->dev);
3499
3500         err = host1x_client_unregister(&sor->client);
3501         if (err < 0) {
3502                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3503                         err);
3504                 return err;
3505         }
3506
3507         if (sor->ops && sor->ops->remove) {
3508                 err = sor->ops->remove(sor);
3509                 if (err < 0)
3510                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3511         }
3512
3513         tegra_output_remove(&sor->output);
3514
3515         return 0;
3516 }
3517
3518 #ifdef CONFIG_PM
3519 static int tegra_sor_suspend(struct device *dev)
3520 {
3521         struct tegra_sor *sor = dev_get_drvdata(dev);
3522         int err;
3523
3524         if (sor->rst) {
3525                 err = reset_control_assert(sor->rst);
3526                 if (err < 0) {
3527                         dev_err(dev, "failed to assert reset: %d\n", err);
3528                         return err;
3529                 }
3530
3531                 reset_control_release(sor->rst);
3532         }
3533
3534         usleep_range(1000, 2000);
3535
3536         clk_disable_unprepare(sor->clk);
3537
3538         return 0;
3539 }
3540
3541 static int tegra_sor_resume(struct device *dev)
3542 {
3543         struct tegra_sor *sor = dev_get_drvdata(dev);
3544         int err;
3545
3546         err = clk_prepare_enable(sor->clk);
3547         if (err < 0) {
3548                 dev_err(dev, "failed to enable clock: %d\n", err);
3549                 return err;
3550         }
3551
3552         usleep_range(1000, 2000);
3553
3554         if (sor->rst) {
3555                 err = reset_control_acquire(sor->rst);
3556                 if (err < 0) {
3557                         dev_err(dev, "failed to acquire reset: %d\n", err);
3558                         clk_disable_unprepare(sor->clk);
3559                         return err;
3560                 }
3561
3562                 err = reset_control_deassert(sor->rst);
3563                 if (err < 0) {
3564                         dev_err(dev, "failed to deassert reset: %d\n", err);
3565                         reset_control_release(sor->rst);
3566                         clk_disable_unprepare(sor->clk);
3567                         return err;
3568                 }
3569         }
3570
3571         return 0;
3572 }
3573 #endif
3574
3575 static const struct dev_pm_ops tegra_sor_pm_ops = {
3576         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3577 };
3578
3579 struct platform_driver tegra_sor_driver = {
3580         .driver = {
3581                 .name = "tegra-sor",
3582                 .of_match_table = tegra_sor_of_match,
3583                 .pm = &tegra_sor_pm_ops,
3584         },
3585         .probe = tegra_sor_probe,
3586         .remove = tegra_sor_remove,
3587 };