drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/reset.h>
  17
  18 #include <soc/tegra/pmc.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_debugfs.h>
  22 #include <drm/drm_dp_helper.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_scdc_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_edp;
 375         bool supports_lvds;
 376         bool supports_hdmi;
 377         bool supports_dp;
 378
 379         const struct tegra_sor_regs *regs;
 380         bool has_nvdisplay;
 381
 382         const struct tegra_sor_hdmi_settings *settings;
 383         unsigned int num_settings;
 384
 385         const u8 *xbar_cfg;
 386         const u8 *lane_map;
 387
 388         const u8 (*voltage_swing)[4][4];
 389         const u8 (*pre_emphasis)[4][4];
 390         const u8 (*post_cursor)[4][4];
 391         const u8 (*tx_pu)[4][4];
 392 };
 393
 394 struct tegra_sor;
 395
 396 struct tegra_sor_ops {
 397         const char *name;
 398         int (*probe)(struct tegra_sor *sor);
 399         int (*remove)(struct tegra_sor *sor);
 400 };
 401
 402 struct tegra_sor {
 403         struct host1x_client client;
 404         struct tegra_output output;
 405         struct device *dev;
 406
 407         const struct tegra_sor_soc *soc;
 408         void __iomem *regs;
 409         unsigned int index;
 410         unsigned int irq;
 411
 412         struct reset_control *rst;
 413         struct clk *clk_parent;
 414         struct clk *clk_safe;
 415         struct clk *clk_out;
 416         struct clk *clk_pad;
 417         struct clk *clk_dp;
 418         struct clk *clk;
 419
 420         u8 xbar_cfg[5];
 421
 422         struct drm_dp_link link;
 423         struct drm_dp_aux *aux;
 424
 425         struct drm_info_list *debugfs_files;
 426
 427         const struct tegra_sor_ops *ops;
 428         enum tegra_io_pad pad;
 429
 430         /* for HDMI 2.0 */
 431         struct tegra_sor_hdmi_settings *settings;
 432         unsigned int num_settings;
 433
 434         struct regulator *avdd_io_supply;
 435         struct regulator *vdd_pll_supply;
 436         struct regulator *hdmi_supply;
 437
 438         struct delayed_work scdc;
 439         bool scdc_enabled;
 440
 441         struct tegra_hda_format format;
 442 };
 443
 444 struct tegra_sor_state {
 445         struct drm_connector_state base;
 446
 447         unsigned int link_speed;
 448         unsigned long pclk;
 449         unsigned int bpc;
 450 };
 451
 452 static inline struct tegra_sor_state *
 453 to_sor_state(struct drm_connector_state *state)
 454 {
 455         return container_of(state, struct tegra_sor_state, base);
 456 }
 457
 458 struct tegra_sor_config {
 459         u32 bits_per_pixel;
 460
 461         u32 active_polarity;
 462         u32 active_count;
 463         u32 tu_size;
 464         u32 active_frac;
 465         u32 watermark;
 466
 467         u32 hblank_symbols;
 468         u32 vblank_symbols;
 469 };
 470
 471 static inline struct tegra_sor *
 472 host1x_client_to_sor(struct host1x_client *client)
 473 {
 474         return container_of(client, struct tegra_sor, client);
 475 }
 476
 477 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 478 {
 479         return container_of(output, struct tegra_sor, output);
 480 }
 481
 482 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 483 {
 484         u32 value = readl(sor->regs + (offset << 2));
 485
 486         trace_sor_readl(sor->dev, offset, value);
 487
 488         return value;
 489 }
 490
 491 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 492                                     unsigned int offset)
 493 {
 494         trace_sor_writel(sor->dev, offset, value);
 495         writel(value, sor->regs + (offset << 2));
 496 }
 497
 498 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 499 {
 500         int err;
 501
 502         clk_disable_unprepare(sor->clk);
 503
 504         err = clk_set_parent(sor->clk_out, parent);
 505         if (err < 0)
 506                 return err;
 507
 508         err = clk_prepare_enable(sor->clk);
 509         if (err < 0)
 510                 return err;
 511
 512         return 0;
 513 }
 514
 515 struct tegra_clk_sor_pad {
 516         struct clk_hw hw;
 517         struct tegra_sor *sor;
 518 };
 519
 520 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 521 {
 522         return container_of(hw, struct tegra_clk_sor_pad, hw);
 523 }
 524
 525 static const char * const tegra_clk_sor_pad_parents[2][2] = {
 526         { "pll_d_out0", "pll_dp" },
 527         { "pll_d2_out0", "pll_dp" },
 528 };
 529
 530 /*
 531  * Implementing ->set_parent() here isn't really required because the parent
 532  * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 533  * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 534  * Tegra186 and later SoC generations where the BPMP implements this clock
 535  * and doesn't expose the mux via the common clock framework.
 536  */
 537
 538 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 539 {
 540         struct tegra_clk_sor_pad *pad = to_pad(hw);
 541         struct tegra_sor *sor = pad->sor;
 542         u32 value;
 543
 544         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 545         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 546
 547         switch (index) {
 548         case 0:
 549                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 550                 break;
 551
 552         case 1:
 553                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 554                 break;
 555         }
 556
 557         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 558
 559         return 0;
 560 }
 561
 562 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 563 {
 564         struct tegra_clk_sor_pad *pad = to_pad(hw);
 565         struct tegra_sor *sor = pad->sor;
 566         u8 parent = U8_MAX;
 567         u32 value;
 568
 569         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 570
 571         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 572         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 573         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 574                 parent = 0;
 575                 break;
 576
 577         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 578         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 579                 parent = 1;
 580                 break;
 581         }
 582
 583         return parent;
 584 }
 585
 586 static const struct clk_ops tegra_clk_sor_pad_ops = {
 587         .set_parent = tegra_clk_sor_pad_set_parent,
 588         .get_parent = tegra_clk_sor_pad_get_parent,
 589 };
 590
 591 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 592                                               const char *name)
 593 {
 594         struct tegra_clk_sor_pad *pad;
 595         struct clk_init_data init;
 596         struct clk *clk;
 597
 598         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 599         if (!pad)
 600                 return ERR_PTR(-ENOMEM);
 601
 602         pad->sor = sor;
 603
 604         init.name = name;
 605         init.flags = 0;
 606         init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 607         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 608         init.ops = &tegra_clk_sor_pad_ops;
 609
 610         pad->hw.init = &init;
 611
 612         clk = devm_clk_register(sor->dev, &pad->hw);
 613
 614         return clk;
 615 }
 616
 617 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 618 {
 619         struct drm_dp_link *link = &sor->link;
 620         unsigned int i;
 621
 622         /* Tegra only supports RBR, HBR and HBR2 */
 623         for (i = 0; i < link->num_rates; i++) {
 624                 switch (link->rates[i]) {
 625                 case 1620000:
 626                 case 2700000:
 627                 case 5400000:
 628                         break;
 629
 630                 default:
 631                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 632                                       link->rates[i]);
 633                         link->rates[i] = 0;
 634                         break;
 635                 }
 636         }
 637
 638         drm_dp_link_update_rates(link);
 639 }
 640
 641 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 642 {
 643         unsigned long timeout;
 644         u32 value;
 645
 646         /*
 647          * Clear or set the PD_TXD bit corresponding to each lane, depending
 648          * on whether it is used or not.
 649          */
 650         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 651
 652         if (lanes <= 2)
 653                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 654                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 655         else
 656                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 657                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 658
 659         if (lanes <= 1)
 660                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 661         else
 662                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 663
 664         if (lanes == 0)
 665                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 666         else
 667                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 668
 669         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 670
 671         /* start lane sequencer */
 672         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 673                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 674         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 675
 676         timeout = jiffies + msecs_to_jiffies(250);
 677
 678         while (time_before(jiffies, timeout)) {
 679                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 680                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 681                         break;
 682
 683                 usleep_range(250, 1000);
 684         }
 685
 686         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 687                 return -ETIMEDOUT;
 688
 689         return 0;
 690 }
 691
 692 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 693 {
 694         unsigned long timeout;
 695         u32 value;
 696
 697         /* power down all lanes */
 698         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 699         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 700                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 701         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 702
 703         /* start lane sequencer */
 704         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 705                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 706         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 707
 708         timeout = jiffies + msecs_to_jiffies(250);
 709
 710         while (time_before(jiffies, timeout)) {
 711                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 712                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 713                         break;
 714
 715                 usleep_range(25, 100);
 716         }
 717
 718         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 719                 return -ETIMEDOUT;
 720
 721         return 0;
 722 }
 723
 724 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 725 {
 726         u32 value;
 727
 728         /* pre-charge all used lanes */
 729         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 730
 731         if (lanes <= 2)
 732                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 733                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 734         else
 735                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 736                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 737
 738         if (lanes <= 1)
 739                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 740         else
 741                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 742
 743         if (lanes == 0)
 744                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 745         else
 746                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 747
 748         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 749
 750         usleep_range(15, 100);
 751
 752         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 753         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 754                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 755         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 756 }
 757
 758 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 759 {
 760         u32 mask = 0x08, adj = 0, value;
 761
 762         /* enable pad calibration logic */
 763         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 764         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 765         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 766
 767         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 768         value |= SOR_PLL1_TMDS_TERM;
 769         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 770
 771         while (mask) {
 772                 adj |= mask;
 773
 774                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 775                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 776                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 777                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 778
 779                 usleep_range(100, 200);
 780
 781                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 782                 if (value & SOR_PLL1_TERM_COMPOUT)
 783                         adj &= ~mask;
 784
 785                 mask >>= 1;
 786         }
 787
 788         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 789         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 790         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 791         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 792
 793         /* disable pad calibration logic */
 794         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 795         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 796         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 797 }
 798
 799 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 800 {
 801         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 802         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 803         const struct tegra_sor_soc *soc = sor->soc;
 804         u32 pattern = 0, tx_pu = 0, value;
 805         unsigned int i;
 806
 807         for (value = 0, i = 0; i < link->lanes; i++) {
 808                 u8 vs = link->train.request.voltage_swing[i];
 809                 u8 pe = link->train.request.pre_emphasis[i];
 810                 u8 pc = link->train.request.post_cursor[i];
 811                 u8 shift = sor->soc->lane_map[i] << 3;
 812
 813                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 814                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 815                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 816
 817                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 818                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 819
 820                 switch (link->train.pattern) {
 821                 case DP_TRAINING_PATTERN_DISABLE:
 822                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 823                                 SOR_DP_TPG_PATTERN_NONE;
 824                         break;
 825
 826                 case DP_TRAINING_PATTERN_1:
 827                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 828                                 SOR_DP_TPG_PATTERN_TRAIN1;
 829                         break;
 830
 831                 case DP_TRAINING_PATTERN_2:
 832                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 833                                 SOR_DP_TPG_PATTERN_TRAIN2;
 834                         break;
 835
 836                 case DP_TRAINING_PATTERN_3:
 837                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 838                                 SOR_DP_TPG_PATTERN_TRAIN3;
 839                         break;
 840
 841                 default:
 842                         return -EINVAL;
 843                 }
 844
 845                 if (link->caps.channel_coding)
 846                         value |= SOR_DP_TPG_CHANNEL_CODING;
 847
 848                 pattern = pattern << 8 | value;
 849         }
 850
 851         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 852         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 853
 854         if (link->caps.tps3_supported)
 855                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 856
 857         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 858
 859         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 860         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 861         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 862         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 863         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 864
 865         usleep_range(20, 100);
 866
 867         return 0;
 868 }
 869
 870 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 871 {
 872         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 873         unsigned int rate, lanes;
 874         u32 value;
 875         int err;
 876
 877         rate = drm_dp_link_rate_to_bw_code(link->rate);
 878         lanes = link->lanes;
 879
 880         /* configure link speed and lane count */
 881         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 882         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 883         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 884         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 885
 886         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 887         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 888         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 889
 890         if (link->caps.enhanced_framing)
 891                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 892
 893         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 894
 895         usleep_range(400, 1000);
 896
 897         /* configure load pulse position adjustment */
 898         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 899         value &= ~SOR_PLL1_LOADADJ_MASK;
 900
 901         switch (rate) {
 902         case DP_LINK_BW_1_62:
 903                 value |= SOR_PLL1_LOADADJ(0x3);
 904                 break;
 905
 906         case DP_LINK_BW_2_7:
 907                 value |= SOR_PLL1_LOADADJ(0x4);
 908                 break;
 909
 910         case DP_LINK_BW_5_4:
 911                 value |= SOR_PLL1_LOADADJ(0x6);
 912                 break;
 913         }
 914
 915         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 916
 917         /* use alternate scrambler reset for eDP */
 918         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 919
 920         if (link->edp == 0)
 921                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 922         else
 923                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 924
 925         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 926
 927         err = tegra_sor_power_down_lanes(sor);
 928         if (err < 0) {
 929                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 930                 return err;
 931         }
 932
 933         /* power up and pre-charge lanes */
 934         err = tegra_sor_power_up_lanes(sor, lanes);
 935         if (err < 0) {
 936                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 937                         lanes, (lanes != 1) ? "s" : "", err);
 938                 return err;
 939         }
 940
 941         tegra_sor_dp_precharge(sor, lanes);
 942
 943         return 0;
 944 }
 945
 946 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 947         .apply_training = tegra_sor_dp_link_apply_training,
 948         .configure = tegra_sor_dp_link_configure,
 949 };
 950
 951 static void tegra_sor_super_update(struct tegra_sor *sor)
 952 {
 953         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 954         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 955         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 956 }
 957
 958 static void tegra_sor_update(struct tegra_sor *sor)
 959 {
 960         tegra_sor_writel(sor, 0, SOR_STATE0);
 961         tegra_sor_writel(sor, 1, SOR_STATE0);
 962         tegra_sor_writel(sor, 0, SOR_STATE0);
 963 }
 964
 965 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 966 {
 967         u32 value;
 968
 969         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 970         value &= ~SOR_PWM_DIV_MASK;
 971         value |= 0x400; /* period */
 972         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 973
 974         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 975         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 976         value |= 0x400; /* duty cycle */
 977         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 978         value |= SOR_PWM_CTL_TRIGGER;
 979         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 980
 981         timeout = jiffies + msecs_to_jiffies(timeout);
 982
 983         while (time_before(jiffies, timeout)) {
 984                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 985                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 986                         return 0;
 987
 988                 usleep_range(25, 100);
 989         }
 990
 991         return -ETIMEDOUT;
 992 }
 993
 994 static int tegra_sor_attach(struct tegra_sor *sor)
 995 {
 996         unsigned long value, timeout;
 997
 998         /* wake up in normal mode */
 999         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1000         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1001         value |= SOR_SUPER_STATE_MODE_NORMAL;
1002         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1003         tegra_sor_super_update(sor);
1004
1005         /* attach */
1006         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1007         value |= SOR_SUPER_STATE_ATTACHED;
1008         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1009         tegra_sor_super_update(sor);
1010
1011         timeout = jiffies + msecs_to_jiffies(250);
1012
1013         while (time_before(jiffies, timeout)) {
1014                 value = tegra_sor_readl(sor, SOR_TEST);
1015                 if ((value & SOR_TEST_ATTACHED) != 0)
1016                         return 0;
1017
1018                 usleep_range(25, 100);
1019         }
1020
1021         return -ETIMEDOUT;
1022 }
1023
1024 static int tegra_sor_wakeup(struct tegra_sor *sor)
1025 {
1026         unsigned long value, timeout;
1027
1028         timeout = jiffies + msecs_to_jiffies(250);
1029
1030         /* wait for head to wake up */
1031         while (time_before(jiffies, timeout)) {
1032                 value = tegra_sor_readl(sor, SOR_TEST);
1033                 value &= SOR_TEST_HEAD_MODE_MASK;
1034
1035                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1036                         return 0;
1037
1038                 usleep_range(25, 100);
1039         }
1040
1041         return -ETIMEDOUT;
1042 }
1043
1044 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1045 {
1046         u32 value;
1047
1048         value = tegra_sor_readl(sor, SOR_PWR);
1049         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1050         tegra_sor_writel(sor, value, SOR_PWR);
1051
1052         timeout = jiffies + msecs_to_jiffies(timeout);
1053
1054         while (time_before(jiffies, timeout)) {
1055                 value = tegra_sor_readl(sor, SOR_PWR);
1056                 if ((value & SOR_PWR_TRIGGER) == 0)
1057                         return 0;
1058
1059                 usleep_range(25, 100);
1060         }
1061
1062         return -ETIMEDOUT;
1063 }
1064
1065 struct tegra_sor_params {
1066         /* number of link clocks per line */
1067         unsigned int num_clocks;
1068         /* ratio between input and output */
1069         u64 ratio;
1070         /* precision factor */
1071         u64 precision;
1072
1073         unsigned int active_polarity;
1074         unsigned int active_count;
1075         unsigned int active_frac;
1076         unsigned int tu_size;
1077         unsigned int error;
1078 };
1079
1080 static int tegra_sor_compute_params(struct tegra_sor *sor,
1081                                     struct tegra_sor_params *params,
1082                                     unsigned int tu_size)
1083 {
1084         u64 active_sym, active_count, frac, approx;
1085         u32 active_polarity, active_frac = 0;
1086         const u64 f = params->precision;
1087         s64 error;
1088
1089         active_sym = params->ratio * tu_size;
1090         active_count = div_u64(active_sym, f) * f;
1091         frac = active_sym - active_count;
1092
1093         /* fraction < 0.5 */
1094         if (frac >= (f / 2)) {
1095                 active_polarity = 1;
1096                 frac = f - frac;
1097         } else {
1098                 active_polarity = 0;
1099         }
1100
1101         if (frac != 0) {
1102                 frac = div_u64(f * f,  frac); /* 1/fraction */
1103                 if (frac <= (15 * f)) {
1104                         active_frac = div_u64(frac, f);
1105
1106                         /* round up */
1107                         if (active_polarity)
1108                                 active_frac++;
1109                 } else {
1110                         active_frac = active_polarity ? 1 : 15;
1111                 }
1112         }
1113
1114         if (active_frac == 1)
1115                 active_polarity = 0;
1116
1117         if (active_polarity == 1) {
1118                 if (active_frac) {
1119                         approx = active_count + (active_frac * (f - 1)) * f;
1120                         approx = div_u64(approx, active_frac * f);
1121                 } else {
1122                         approx = active_count + f;
1123                 }
1124         } else {
1125                 if (active_frac)
1126                         approx = active_count + div_u64(f, active_frac);
1127                 else
1128                         approx = active_count;
1129         }
1130
1131         error = div_s64(active_sym - approx, tu_size);
1132         error *= params->num_clocks;
1133
1134         if (error <= 0 && abs(error) < params->error) {
1135                 params->active_count = div_u64(active_count, f);
1136                 params->active_polarity = active_polarity;
1137                 params->active_frac = active_frac;
1138                 params->error = abs(error);
1139                 params->tu_size = tu_size;
1140
1141                 if (error == 0)
1142                         return true;
1143         }
1144
1145         return false;
1146 }
1147
1148 static int tegra_sor_compute_config(struct tegra_sor *sor,
1149                                     const struct drm_display_mode *mode,
1150                                     struct tegra_sor_config *config,
1151                                     struct drm_dp_link *link)
1152 {
1153         const u64 f = 100000, link_rate = link->rate * 1000;
1154         const u64 pclk = mode->clock * 1000;
1155         u64 input, output, watermark, num;
1156         struct tegra_sor_params params;
1157         u32 num_syms_per_line;
1158         unsigned int i;
1159
1160         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1161                 return -EINVAL;
1162
1163         input = pclk * config->bits_per_pixel;
1164         output = link_rate * 8 * link->lanes;
1165
1166         if (input >= output)
1167                 return -ERANGE;
1168
1169         memset(&params, 0, sizeof(params));
1170         params.ratio = div64_u64(input * f, output);
1171         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1172         params.precision = f;
1173         params.error = 64 * f;
1174         params.tu_size = 64;
1175
1176         for (i = params.tu_size; i >= 32; i--)
1177                 if (tegra_sor_compute_params(sor, &params, i))
1178                         break;
1179
1180         if (params.active_frac == 0) {
1181                 config->active_polarity = 0;
1182                 config->active_count = params.active_count;
1183
1184                 if (!params.active_polarity)
1185                         config->active_count--;
1186
1187                 config->tu_size = params.tu_size;
1188                 config->active_frac = 1;
1189         } else {
1190                 config->active_polarity = params.active_polarity;
1191                 config->active_count = params.active_count;
1192                 config->active_frac = params.active_frac;
1193                 config->tu_size = params.tu_size;
1194         }
1195
1196         dev_dbg(sor->dev,
1197                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1198                 config->active_polarity, config->active_count,
1199                 config->tu_size, config->active_frac);
1200
1201         watermark = params.ratio * config->tu_size * (f - params.ratio);
1202         watermark = div_u64(watermark, f);
1203
1204         watermark = div_u64(watermark + params.error, f);
1205         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1206         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1207                             (link->lanes * 8);
1208
1209         if (config->watermark > 30) {
1210                 config->watermark = 30;
1211                 dev_err(sor->dev,
1212                         "unable to compute TU size, forcing watermark to %u\n",
1213                         config->watermark);
1214         } else if (config->watermark > num_syms_per_line) {
1215                 config->watermark = num_syms_per_line;
1216                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1217                         config->watermark);
1218         }
1219
1220         /* compute the number of symbols per horizontal blanking interval */
1221         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1222         config->hblank_symbols = div_u64(num, pclk);
1223
1224         if (link->caps.enhanced_framing)
1225                 config->hblank_symbols -= 3;
1226
1227         config->hblank_symbols -= 12 / link->lanes;
1228
1229         /* compute the number of symbols per vertical blanking interval */
1230         num = (mode->hdisplay - 25) * link_rate;
1231         config->vblank_symbols = div_u64(num, pclk);
1232         config->vblank_symbols -= 36 / link->lanes + 4;
1233
1234         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1235                 config->vblank_symbols);
1236
1237         return 0;
1238 }
1239
1240 static void tegra_sor_apply_config(struct tegra_sor *sor,
1241                                    const struct tegra_sor_config *config)
1242 {
1243         u32 value;
1244
1245         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1246         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1247         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1248         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1249
1250         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1251         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1252         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1253
1254         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1255         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1256
1257         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1258         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1259
1260         if (config->active_polarity)
1261                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1262         else
1263                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1264
1265         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1266         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1267         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1268
1269         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1270         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1271         value |= config->hblank_symbols & 0xffff;
1272         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273
1274         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1275         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1276         value |= config->vblank_symbols & 0xffff;
1277         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278 }
1279
1280 static void tegra_sor_mode_set(struct tegra_sor *sor,
1281                                const struct drm_display_mode *mode,
1282                                struct tegra_sor_state *state)
1283 {
1284         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1285         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1286         u32 value;
1287
1288         value = tegra_sor_readl(sor, SOR_STATE1);
1289         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1290         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1291         value &= ~SOR_STATE_ASY_OWNER_MASK;
1292
1293         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1294                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1295
1296         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1297                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1298
1299         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1300                 value |= SOR_STATE_ASY_HSYNCPOL;
1301
1302         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1303                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1304
1305         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1306                 value |= SOR_STATE_ASY_VSYNCPOL;
1307
1308         switch (state->bpc) {
1309         case 16:
1310                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1311                 break;
1312
1313         case 12:
1314                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1315                 break;
1316
1317         case 10:
1318                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1319                 break;
1320
1321         case 8:
1322                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1323                 break;
1324
1325         case 6:
1326                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1327                 break;
1328
1329         default:
1330                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1331                 break;
1332         }
1333
1334         tegra_sor_writel(sor, value, SOR_STATE1);
1335
1336         /*
1337          * TODO: The video timing programming below doesn't seem to match the
1338          * register definitions.
1339          */
1340
1341         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1342         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1343
1344         /* sync end = sync width - 1 */
1345         vse = mode->vsync_end - mode->vsync_start - 1;
1346         hse = mode->hsync_end - mode->hsync_start - 1;
1347
1348         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1349         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1350
1351         /* blank end = sync end + back porch */
1352         vbe = vse + (mode->vtotal - mode->vsync_end);
1353         hbe = hse + (mode->htotal - mode->hsync_end);
1354
1355         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1356         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1357
1358         /* blank start = blank end + active */
1359         vbs = vbe + mode->vdisplay;
1360         hbs = hbe + mode->hdisplay;
1361
1362         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1363         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1364
1365         /* XXX interlacing support */
1366         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1367 }
1368
1369 static int tegra_sor_detach(struct tegra_sor *sor)
1370 {
1371         unsigned long value, timeout;
1372
1373         /* switch to safe mode */
1374         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1375         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1376         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1377         tegra_sor_super_update(sor);
1378
1379         timeout = jiffies + msecs_to_jiffies(250);
1380
1381         while (time_before(jiffies, timeout)) {
1382                 value = tegra_sor_readl(sor, SOR_PWR);
1383                 if (value & SOR_PWR_MODE_SAFE)
1384                         break;
1385         }
1386
1387         if ((value & SOR_PWR_MODE_SAFE) == 0)
1388                 return -ETIMEDOUT;
1389
1390         /* go to sleep */
1391         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1392         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1393         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1394         tegra_sor_super_update(sor);
1395
1396         /* detach */
1397         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1398         value &= ~SOR_SUPER_STATE_ATTACHED;
1399         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1400         tegra_sor_super_update(sor);
1401
1402         timeout = jiffies + msecs_to_jiffies(250);
1403
1404         while (time_before(jiffies, timeout)) {
1405                 value = tegra_sor_readl(sor, SOR_TEST);
1406                 if ((value & SOR_TEST_ATTACHED) == 0)
1407                         break;
1408
1409                 usleep_range(25, 100);
1410         }
1411
1412         if ((value & SOR_TEST_ATTACHED) != 0)
1413                 return -ETIMEDOUT;
1414
1415         return 0;
1416 }
1417
1418 static int tegra_sor_power_down(struct tegra_sor *sor)
1419 {
1420         unsigned long value, timeout;
1421         int err;
1422
1423         value = tegra_sor_readl(sor, SOR_PWR);
1424         value &= ~SOR_PWR_NORMAL_STATE_PU;
1425         value |= SOR_PWR_TRIGGER;
1426         tegra_sor_writel(sor, value, SOR_PWR);
1427
1428         timeout = jiffies + msecs_to_jiffies(250);
1429
1430         while (time_before(jiffies, timeout)) {
1431                 value = tegra_sor_readl(sor, SOR_PWR);
1432                 if ((value & SOR_PWR_TRIGGER) == 0)
1433                         return 0;
1434
1435                 usleep_range(25, 100);
1436         }
1437
1438         if ((value & SOR_PWR_TRIGGER) != 0)
1439                 return -ETIMEDOUT;
1440
1441         /* switch to safe parent clock */
1442         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1443         if (err < 0) {
1444                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1445                 return err;
1446         }
1447
1448         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1449         value |= SOR_PLL2_PORT_POWERDOWN;
1450         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1451
1452         usleep_range(20, 100);
1453
1454         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1455         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1456         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1457
1458         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1459         value |= SOR_PLL2_SEQ_PLLCAPPD;
1460         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1461         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1462
1463         usleep_range(20, 100);
1464
1465         return 0;
1466 }
1467
1468 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1469 {
1470         u32 value;
1471
1472         timeout = jiffies + msecs_to_jiffies(timeout);
1473
1474         while (time_before(jiffies, timeout)) {
1475                 value = tegra_sor_readl(sor, SOR_CRCA);
1476                 if (value & SOR_CRCA_VALID)
1477                         return 0;
1478
1479                 usleep_range(100, 200);
1480         }
1481
1482         return -ETIMEDOUT;
1483 }
1484
1485 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1486 {
1487         struct drm_info_node *node = s->private;
1488         struct tegra_sor *sor = node->info_ent->data;
1489         struct drm_crtc *crtc = sor->output.encoder.crtc;
1490         struct drm_device *drm = node->minor->dev;
1491         int err = 0;
1492         u32 value;
1493
1494         drm_modeset_lock_all(drm);
1495
1496         if (!crtc || !crtc->state->active) {
1497                 err = -EBUSY;
1498                 goto unlock;
1499         }
1500
1501         value = tegra_sor_readl(sor, SOR_STATE1);
1502         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1503         tegra_sor_writel(sor, value, SOR_STATE1);
1504
1505         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1506         value |= SOR_CRC_CNTRL_ENABLE;
1507         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1508
1509         value = tegra_sor_readl(sor, SOR_TEST);
1510         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1511         tegra_sor_writel(sor, value, SOR_TEST);
1512
1513         err = tegra_sor_crc_wait(sor, 100);
1514         if (err < 0)
1515                 goto unlock;
1516
1517         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1518         value = tegra_sor_readl(sor, SOR_CRCB);
1519
1520         seq_printf(s, "%08x\n", value);
1521
1522 unlock:
1523         drm_modeset_unlock_all(drm);
1524         return err;
1525 }
1526
1527 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1528
1529 static const struct debugfs_reg32 tegra_sor_regs[] = {
1530         DEBUGFS_REG32(SOR_CTXSW),
1531         DEBUGFS_REG32(SOR_SUPER_STATE0),
1532         DEBUGFS_REG32(SOR_SUPER_STATE1),
1533         DEBUGFS_REG32(SOR_STATE0),
1534         DEBUGFS_REG32(SOR_STATE1),
1535         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1536         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1537         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1538         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1539         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1540         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1541         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1542         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1543         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1544         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1545         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1546         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1547         DEBUGFS_REG32(SOR_CRC_CNTRL),
1548         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1549         DEBUGFS_REG32(SOR_CLK_CNTRL),
1550         DEBUGFS_REG32(SOR_CAP),
1551         DEBUGFS_REG32(SOR_PWR),
1552         DEBUGFS_REG32(SOR_TEST),
1553         DEBUGFS_REG32(SOR_PLL0),
1554         DEBUGFS_REG32(SOR_PLL1),
1555         DEBUGFS_REG32(SOR_PLL2),
1556         DEBUGFS_REG32(SOR_PLL3),
1557         DEBUGFS_REG32(SOR_CSTM),
1558         DEBUGFS_REG32(SOR_LVDS),
1559         DEBUGFS_REG32(SOR_CRCA),
1560         DEBUGFS_REG32(SOR_CRCB),
1561         DEBUGFS_REG32(SOR_BLANK),
1562         DEBUGFS_REG32(SOR_SEQ_CTL),
1563         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1564         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1565         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1566         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1567         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1568         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1571         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1572         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1573         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1574         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1575         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1576         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1577         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1578         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1579         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1580         DEBUGFS_REG32(SOR_PWM_DIV),
1581         DEBUGFS_REG32(SOR_PWM_CTL),
1582         DEBUGFS_REG32(SOR_VCRC_A0),
1583         DEBUGFS_REG32(SOR_VCRC_A1),
1584         DEBUGFS_REG32(SOR_VCRC_B0),
1585         DEBUGFS_REG32(SOR_VCRC_B1),
1586         DEBUGFS_REG32(SOR_CCRC_A0),
1587         DEBUGFS_REG32(SOR_CCRC_A1),
1588         DEBUGFS_REG32(SOR_CCRC_B0),
1589         DEBUGFS_REG32(SOR_CCRC_B1),
1590         DEBUGFS_REG32(SOR_EDATA_A0),
1591         DEBUGFS_REG32(SOR_EDATA_A1),
1592         DEBUGFS_REG32(SOR_EDATA_B0),
1593         DEBUGFS_REG32(SOR_EDATA_B1),
1594         DEBUGFS_REG32(SOR_COUNT_A0),
1595         DEBUGFS_REG32(SOR_COUNT_A1),
1596         DEBUGFS_REG32(SOR_COUNT_B0),
1597         DEBUGFS_REG32(SOR_COUNT_B1),
1598         DEBUGFS_REG32(SOR_DEBUG_A0),
1599         DEBUGFS_REG32(SOR_DEBUG_A1),
1600         DEBUGFS_REG32(SOR_DEBUG_B0),
1601         DEBUGFS_REG32(SOR_DEBUG_B1),
1602         DEBUGFS_REG32(SOR_TRIG),
1603         DEBUGFS_REG32(SOR_MSCHECK),
1604         DEBUGFS_REG32(SOR_XBAR_CTRL),
1605         DEBUGFS_REG32(SOR_XBAR_POL),
1606         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1607         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1608         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1609         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1610         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1611         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1612         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1613         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1614         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1615         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1616         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1617         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1618         DEBUGFS_REG32(SOR_DP_CONFIG0),
1619         DEBUGFS_REG32(SOR_DP_CONFIG1),
1620         DEBUGFS_REG32(SOR_DP_MN0),
1621         DEBUGFS_REG32(SOR_DP_MN1),
1622         DEBUGFS_REG32(SOR_DP_PADCTL0),
1623         DEBUGFS_REG32(SOR_DP_PADCTL1),
1624         DEBUGFS_REG32(SOR_DP_PADCTL2),
1625         DEBUGFS_REG32(SOR_DP_DEBUG0),
1626         DEBUGFS_REG32(SOR_DP_DEBUG1),
1627         DEBUGFS_REG32(SOR_DP_SPARE0),
1628         DEBUGFS_REG32(SOR_DP_SPARE1),
1629         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1630         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1631         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1632         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1633         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1634         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1635         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1636         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1637         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1638         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1639         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1640         DEBUGFS_REG32(SOR_DP_TPG),
1641         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1642         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1643         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1644         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1645 };
1646
1647 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1648 {
1649         struct drm_info_node *node = s->private;
1650         struct tegra_sor *sor = node->info_ent->data;
1651         struct drm_crtc *crtc = sor->output.encoder.crtc;
1652         struct drm_device *drm = node->minor->dev;
1653         unsigned int i;
1654         int err = 0;
1655
1656         drm_modeset_lock_all(drm);
1657
1658         if (!crtc || !crtc->state->active) {
1659                 err = -EBUSY;
1660                 goto unlock;
1661         }
1662
1663         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1664                 unsigned int offset = tegra_sor_regs[i].offset;
1665
1666                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1667                            offset, tegra_sor_readl(sor, offset));
1668         }
1669
1670 unlock:
1671         drm_modeset_unlock_all(drm);
1672         return err;
1673 }
1674
1675 static const struct drm_info_list debugfs_files[] = {
1676         { "crc", tegra_sor_show_crc, 0, NULL },
1677         { "regs", tegra_sor_show_regs, 0, NULL },
1678 };
1679
1680 static int tegra_sor_late_register(struct drm_connector *connector)
1681 {
1682         struct tegra_output *output = connector_to_output(connector);
1683         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1684         struct drm_minor *minor = connector->dev->primary;
1685         struct dentry *root = connector->debugfs_entry;
1686         struct tegra_sor *sor = to_sor(output);
1687         int err;
1688
1689         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1690                                      GFP_KERNEL);
1691         if (!sor->debugfs_files)
1692                 return -ENOMEM;
1693
1694         for (i = 0; i < count; i++)
1695                 sor->debugfs_files[i].data = sor;
1696
1697         err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1698         if (err < 0)
1699                 goto free;
1700
1701         return 0;
1702
1703 free:
1704         kfree(sor->debugfs_files);
1705         sor->debugfs_files = NULL;
1706
1707         return err;
1708 }
1709
1710 static void tegra_sor_early_unregister(struct drm_connector *connector)
1711 {
1712         struct tegra_output *output = connector_to_output(connector);
1713         unsigned int count = ARRAY_SIZE(debugfs_files);
1714         struct tegra_sor *sor = to_sor(output);
1715
1716         drm_debugfs_remove_files(sor->debugfs_files, count,
1717                                  connector->dev->primary);
1718         kfree(sor->debugfs_files);
1719         sor->debugfs_files = NULL;
1720 }
1721
1722 static void tegra_sor_connector_reset(struct drm_connector *connector)
1723 {
1724         struct tegra_sor_state *state;
1725
1726         state = kzalloc(sizeof(*state), GFP_KERNEL);
1727         if (!state)
1728                 return;
1729
1730         if (connector->state) {
1731                 __drm_atomic_helper_connector_destroy_state(connector->state);
1732                 kfree(connector->state);
1733         }
1734
1735         __drm_atomic_helper_connector_reset(connector, &state->base);
1736 }
1737
1738 static enum drm_connector_status
1739 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1740 {
1741         struct tegra_output *output = connector_to_output(connector);
1742         struct tegra_sor *sor = to_sor(output);
1743
1744         if (sor->aux)
1745                 return drm_dp_aux_detect(sor->aux);
1746
1747         return tegra_output_connector_detect(connector, force);
1748 }
1749
1750 static struct drm_connector_state *
1751 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1752 {
1753         struct tegra_sor_state *state = to_sor_state(connector->state);
1754         struct tegra_sor_state *copy;
1755
1756         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1757         if (!copy)
1758                 return NULL;
1759
1760         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1761
1762         return &copy->base;
1763 }
1764
1765 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1766         .reset = tegra_sor_connector_reset,
1767         .detect = tegra_sor_connector_detect,
1768         .fill_modes = drm_helper_probe_single_connector_modes,
1769         .destroy = tegra_output_connector_destroy,
1770         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1771         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1772         .late_register = tegra_sor_late_register,
1773         .early_unregister = tegra_sor_early_unregister,
1774 };
1775
1776 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1777 {
1778         struct tegra_output *output = connector_to_output(connector);
1779         struct tegra_sor *sor = to_sor(output);
1780         int err;
1781
1782         if (sor->aux)
1783                 drm_dp_aux_enable(sor->aux);
1784
1785         err = tegra_output_connector_get_modes(connector);
1786
1787         if (sor->aux)
1788                 drm_dp_aux_disable(sor->aux);
1789
1790         return err;
1791 }
1792
1793 static enum drm_mode_status
1794 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1795                                struct drm_display_mode *mode)
1796 {
1797         return MODE_OK;
1798 }
1799
1800 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1801         .get_modes = tegra_sor_connector_get_modes,
1802         .mode_valid = tegra_sor_connector_mode_valid,
1803 };
1804
1805 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1806         .destroy = tegra_output_encoder_destroy,
1807 };
1808
1809 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1810 {
1811         struct tegra_output *output = encoder_to_output(encoder);
1812         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1813         struct tegra_sor *sor = to_sor(output);
1814         u32 value;
1815         int err;
1816
1817         if (output->panel)
1818                 drm_panel_disable(output->panel);
1819
1820         err = tegra_sor_detach(sor);
1821         if (err < 0)
1822                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1823
1824         tegra_sor_writel(sor, 0, SOR_STATE1);
1825         tegra_sor_update(sor);
1826
1827         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1828         value &= ~SOR_ENABLE(0);
1829         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1830
1831         tegra_dc_commit(dc);
1832
1833         err = tegra_sor_power_down(sor);
1834         if (err < 0)
1835                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1836
1837         if (sor->aux) {
1838                 err = drm_dp_aux_disable(sor->aux);
1839                 if (err < 0)
1840                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1841         }
1842
1843         err = tegra_io_pad_power_disable(sor->pad);
1844         if (err < 0)
1845                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1846
1847         if (output->panel)
1848                 drm_panel_unprepare(output->panel);
1849
1850         pm_runtime_put(sor->dev);
1851 }
1852
1853 #if 0
1854 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1855                               unsigned int *value)
1856 {
1857         unsigned int hfp, hsw, hbp, a = 0, b;
1858
1859         hfp = mode->hsync_start - mode->hdisplay;
1860         hsw = mode->hsync_end - mode->hsync_start;
1861         hbp = mode->htotal - mode->hsync_end;
1862
1863         pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1864
1865         b = hfp - 1;
1866
1867         pr_info("a: %u, b: %u\n", a, b);
1868         pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1869
1870         if (a + hsw + hbp <= 11) {
1871                 a = 1 + 11 - hsw - hbp;
1872                 pr_info("a: %u\n", a);
1873         }
1874
1875         if (a > b)
1876                 return -EINVAL;
1877
1878         if (hsw < 1)
1879                 return -EINVAL;
1880
1881         if (mode->hdisplay < 16)
1882                 return -EINVAL;
1883
1884         if (value) {
1885                 if (b > a && a % 2)
1886                         *value = a + 1;
1887                 else
1888                         *value = a;
1889         }
1890
1891         return 0;
1892 }
1893 #endif
1894
1895 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1896 {
1897         struct tegra_output *output = encoder_to_output(encoder);
1898         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1899         struct tegra_sor *sor = to_sor(output);
1900         struct tegra_sor_config config;
1901         struct tegra_sor_state *state;
1902         struct drm_display_mode *mode;
1903         struct drm_display_info *info;
1904         unsigned int i;
1905         u32 value;
1906         int err;
1907
1908         state = to_sor_state(output->connector.state);
1909         mode = &encoder->crtc->state->adjusted_mode;
1910         info = &output->connector.display_info;
1911
1912         pm_runtime_get_sync(sor->dev);
1913
1914         /* switch to safe parent clock */
1915         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1916         if (err < 0)
1917                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1918
1919         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1920         if (err < 0)
1921                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
1922
1923         usleep_range(20, 100);
1924
1925         err = drm_dp_aux_enable(sor->aux);
1926         if (err < 0)
1927                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
1928
1929         err = drm_dp_link_probe(sor->aux, &sor->link);
1930         if (err < 0)
1931                 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1932
1933         tegra_sor_filter_rates(sor);
1934
1935         err = drm_dp_link_choose(&sor->link, mode, info);
1936         if (err < 0)
1937                 dev_err(sor->dev, "failed to choose link: %d\n", err);
1938
1939         if (output->panel)
1940                 drm_panel_prepare(output->panel);
1941
1942         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1943         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1944         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1945
1946         usleep_range(20, 40);
1947
1948         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1949         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1950         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1951
1952         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1953         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
1954         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1955
1956         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1957         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1958         value |= SOR_PLL2_SEQ_PLLCAPPD;
1959         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1960
1961         usleep_range(200, 400);
1962
1963         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1964         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1965         value &= ~SOR_PLL2_PORT_POWERDOWN;
1966         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1967
1968         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1969         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1970         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1971         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1972
1973         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
1974         /* XXX not in TRM */
1975         value |= SOR_DP_SPARE_PANEL_INTERNAL;
1976         value |= SOR_DP_SPARE_SEQ_ENABLE;
1977         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
1978
1979         /* XXX not in TRM */
1980         tegra_sor_writel(sor, 0, SOR_LVDS);
1981
1982         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1983         value &= ~SOR_PLL0_ICHPMP_MASK;
1984         value &= ~SOR_PLL0_VCOCAP_MASK;
1985         value |= SOR_PLL0_ICHPMP(0x1);
1986         value |= SOR_PLL0_VCOCAP(0x3);
1987         value |= SOR_PLL0_RESISTOR_EXT;
1988         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1989
1990         /* XXX not in TRM */
1991         for (value = 0, i = 0; i < 5; i++)
1992                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1993                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1994
1995         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1996         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1997
1998         /*
1999          * Switch the pad clock to the DP clock. Note that we cannot actually
2000          * do this because Tegra186 and later don't support clk_set_parent()
2001          * on the sorX_pad_clkout clocks. We already do the equivalent above
2002          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2003          */
2004 #if 0
2005         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2006         if (err < 0) {
2007                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2008                         err);
2009                 return;
2010         }
2011 #endif
2012
2013         /* switch the SOR clock to the pad clock */
2014         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2015         if (err < 0) {
2016                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2017                         err);
2018                 return;
2019         }
2020
2021         /* switch the output clock to the parent pixel clock */
2022         err = clk_set_parent(sor->clk, sor->clk_parent);
2023         if (err < 0) {
2024                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2025                         err);
2026                 return;
2027         }
2028
2029         /* use DP-A protocol */
2030         value = tegra_sor_readl(sor, SOR_STATE1);
2031         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2032         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2033         tegra_sor_writel(sor, value, SOR_STATE1);
2034
2035         /* enable port */
2036         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2037         value |= SOR_DP_LINKCTL_ENABLE;
2038         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2039
2040         tegra_sor_dp_term_calibrate(sor);
2041
2042         err = drm_dp_link_train(&sor->link);
2043         if (err < 0)
2044                 dev_err(sor->dev, "link training failed: %d\n", err);
2045         else
2046                 dev_dbg(sor->dev, "link training succeeded\n");
2047
2048         err = drm_dp_link_power_up(sor->aux, &sor->link);
2049         if (err < 0)
2050                 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
2051
2052         /* compute configuration */
2053         memset(&config, 0, sizeof(config));
2054         config.bits_per_pixel = state->bpc * 3;
2055
2056         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2057         if (err < 0)
2058                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2059
2060         tegra_sor_apply_config(sor, &config);
2061
2062         err = tegra_sor_power_up(sor, 250);
2063         if (err < 0)
2064                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2065
2066         /* CSTM (LVDS, link A/B, upper) */
2067         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2068                 SOR_CSTM_UPPER;
2069         tegra_sor_writel(sor, value, SOR_CSTM);
2070
2071         /* use DP-A protocol */
2072         value = tegra_sor_readl(sor, SOR_STATE1);
2073         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2074         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2075         tegra_sor_writel(sor, value, SOR_STATE1);
2076
2077         tegra_sor_mode_set(sor, mode, state);
2078
2079         /* PWM setup */
2080         err = tegra_sor_setup_pwm(sor, 250);
2081         if (err < 0)
2082                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2083
2084         tegra_sor_update(sor);
2085
2086         err = tegra_sor_power_up(sor, 250);
2087         if (err < 0)
2088                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2089
2090         /* attach and wake up */
2091         err = tegra_sor_attach(sor);
2092         if (err < 0)
2093                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2094
2095         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2096         value |= SOR_ENABLE(0);
2097         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2098
2099         tegra_dc_commit(dc);
2100
2101         err = tegra_sor_wakeup(sor);
2102         if (err < 0)
2103                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2104
2105         if (output->panel)
2106                 drm_panel_enable(output->panel);
2107 }
2108
2109 static int
2110 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
2111                                struct drm_crtc_state *crtc_state,
2112                                struct drm_connector_state *conn_state)
2113 {
2114         struct tegra_output *output = encoder_to_output(encoder);
2115         struct tegra_sor_state *state = to_sor_state(conn_state);
2116         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
2117         unsigned long pclk = crtc_state->mode.clock * 1000;
2118         struct tegra_sor *sor = to_sor(output);
2119         struct drm_display_info *info;
2120         int err;
2121
2122         info = &output->connector.display_info;
2123
2124         /*
2125          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2126          * the pixel clock must be corrected accordingly.
2127          */
2128         if (pclk >= 340000000) {
2129                 state->link_speed = 20;
2130                 state->pclk = pclk / 2;
2131         } else {
2132                 state->link_speed = 10;
2133                 state->pclk = pclk;
2134         }
2135
2136         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2137                                          pclk, 0);
2138         if (err < 0) {
2139                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2140                 return err;
2141         }
2142
2143         switch (info->bpc) {
2144         case 8:
2145         case 6:
2146                 state->bpc = info->bpc;
2147                 break;
2148
2149         default:
2150                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2151                 state->bpc = 8;
2152                 break;
2153         }
2154
2155         return 0;
2156 }
2157
2158 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2159         .disable = tegra_sor_edp_disable,
2160         .enable = tegra_sor_edp_enable,
2161         .atomic_check = tegra_sor_encoder_atomic_check,
2162 };
2163
2164 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2165 {
2166         u32 value = 0;
2167         size_t i;
2168
2169         for (i = size; i > 0; i--)
2170                 value = (value << 8) | ptr[i - 1];
2171
2172         return value;
2173 }
2174
2175 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2176                                           const void *data, size_t size)
2177 {
2178         const u8 *ptr = data;
2179         unsigned long offset;
2180         size_t i, j;
2181         u32 value;
2182
2183         switch (ptr[0]) {
2184         case HDMI_INFOFRAME_TYPE_AVI:
2185                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2186                 break;
2187
2188         case HDMI_INFOFRAME_TYPE_AUDIO:
2189                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2190                 break;
2191
2192         case HDMI_INFOFRAME_TYPE_VENDOR:
2193                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2194                 break;
2195
2196         default:
2197                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2198                         ptr[0]);
2199                 return;
2200         }
2201
2202         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2203                 INFOFRAME_HEADER_VERSION(ptr[1]) |
2204                 INFOFRAME_HEADER_LEN(ptr[2]);
2205         tegra_sor_writel(sor, value, offset);
2206         offset++;
2207
2208         /*
2209          * Each subpack contains 7 bytes, divided into:
2210          * - subpack_low: bytes 0 - 3
2211          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2212          */
2213         for (i = 3, j = 0; i < size; i += 7, j += 8) {
2214                 size_t rem = size - i, num = min_t(size_t, rem, 4);
2215
2216                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2217                 tegra_sor_writel(sor, value, offset++);
2218
2219                 num = min_t(size_t, rem - num, 3);
2220
2221                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2222                 tegra_sor_writel(sor, value, offset++);
2223         }
2224 }
2225
2226 static int
2227 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2228                                    const struct drm_display_mode *mode)
2229 {
2230         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2231         struct hdmi_avi_infoframe frame;
2232         u32 value;
2233         int err;
2234
2235         /* disable AVI infoframe */
2236         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2237         value &= ~INFOFRAME_CTRL_SINGLE;
2238         value &= ~INFOFRAME_CTRL_OTHER;
2239         value &= ~INFOFRAME_CTRL_ENABLE;
2240         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2241
2242         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2243                                                        &sor->output.connector, mode);
2244         if (err < 0) {
2245                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2246                 return err;
2247         }
2248
2249         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2250         if (err < 0) {
2251                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2252                 return err;
2253         }
2254
2255         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2256
2257         /* enable AVI infoframe */
2258         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2259         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2260         value |= INFOFRAME_CTRL_ENABLE;
2261         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2262
2263         return 0;
2264 }
2265
2266 static void tegra_sor_write_eld(struct tegra_sor *sor)
2267 {
2268         size_t length = drm_eld_size(sor->output.connector.eld), i;
2269
2270         for (i = 0; i < length; i++)
2271                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2272                                  SOR_AUDIO_HDA_ELD_BUFWR);
2273
2274         /*
2275          * The HDA codec will always report an ELD buffer size of 96 bytes and
2276          * the HDA codec driver will check that each byte read from the buffer
2277          * is valid. Therefore every byte must be written, even if no 96 bytes
2278          * were parsed from EDID.
2279          */
2280         for (i = length; i < 96; i++)
2281                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2282 }
2283
2284 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2285 {
2286         u32 value;
2287
2288         /*
2289          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2290          * is used for interoperability between the HDA codec driver and the
2291          * HDMI/DP driver.
2292          */
2293         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2294         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2295         tegra_sor_writel(sor, value, SOR_INT_MASK);
2296
2297         tegra_sor_write_eld(sor);
2298
2299         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2300         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2301 }
2302
2303 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2304 {
2305         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2306         tegra_sor_writel(sor, 0, SOR_INT_MASK);
2307         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2308 }
2309
2310 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2311 {
2312         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2313         struct hdmi_audio_infoframe frame;
2314         u32 value;
2315         int err;
2316
2317         err = hdmi_audio_infoframe_init(&frame);
2318         if (err < 0) {
2319                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2320                 return err;
2321         }
2322
2323         frame.channels = sor->format.channels;
2324
2325         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2326         if (err < 0) {
2327                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2328                 return err;
2329         }
2330
2331         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2332
2333         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2334         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2335         value |= INFOFRAME_CTRL_ENABLE;
2336         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2337
2338         return 0;
2339 }
2340
2341 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2342 {
2343         u32 value;
2344
2345         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2346
2347         /* select HDA audio input */
2348         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2349         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2350
2351         /* inject null samples */
2352         if (sor->format.channels != 2)
2353                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2354         else
2355                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2356
2357         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2358
2359         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2360
2361         /* enable advertising HBR capability */
2362         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2363
2364         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2365
2366         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2367                 SOR_HDMI_SPARE_CTS_RESET(1) |
2368                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2369         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2370
2371         /* enable HW CTS */
2372         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2373         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2374
2375         /* allow packet to be sent */
2376         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2377         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2378
2379         /* reset N counter and enable lookup */
2380         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2381         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2382
2383         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2384         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2385         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2386
2387         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2388         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2389
2390         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2391         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2392
2393         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2394         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2395
2396         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2397         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2398         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2399
2400         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2401         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2402         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2403
2404         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2405         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2406         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2407
2408         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2409         value &= ~SOR_HDMI_AUDIO_N_RESET;
2410         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2411
2412         tegra_sor_hdmi_enable_audio_infoframe(sor);
2413 }
2414
2415 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2416 {
2417         u32 value;
2418
2419         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2420         value &= ~INFOFRAME_CTRL_ENABLE;
2421         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2422 }
2423
2424 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2425 {
2426         tegra_sor_hdmi_disable_audio_infoframe(sor);
2427 }
2428
2429 static struct tegra_sor_hdmi_settings *
2430 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2431 {
2432         unsigned int i;
2433
2434         for (i = 0; i < sor->num_settings; i++)
2435                 if (frequency <= sor->settings[i].frequency)
2436                         return &sor->settings[i];
2437
2438         return NULL;
2439 }
2440
2441 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2442 {
2443         u32 value;
2444
2445         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2446         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2447         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2448         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2449 }
2450
2451 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2452 {
2453         struct i2c_adapter *ddc = sor->output.ddc;
2454
2455         drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2456         drm_scdc_set_scrambling(ddc, false);
2457
2458         tegra_sor_hdmi_disable_scrambling(sor);
2459 }
2460
2461 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2462 {
2463         if (sor->scdc_enabled) {
2464                 cancel_delayed_work_sync(&sor->scdc);
2465                 tegra_sor_hdmi_scdc_disable(sor);
2466         }
2467 }
2468
2469 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2470 {
2471         u32 value;
2472
2473         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2474         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2475         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2476         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2477 }
2478
2479 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2480 {
2481         struct i2c_adapter *ddc = sor->output.ddc;
2482
2483         drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2484         drm_scdc_set_scrambling(ddc, true);
2485
2486         tegra_sor_hdmi_enable_scrambling(sor);
2487 }
2488
2489 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2490 {
2491         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2492         struct i2c_adapter *ddc = sor->output.ddc;
2493
2494         if (!drm_scdc_get_scrambling_status(ddc)) {
2495                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2496                 tegra_sor_hdmi_scdc_enable(sor);
2497         }
2498
2499         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2500 }
2501
2502 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2503 {
2504         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2505         struct drm_display_mode *mode;
2506
2507         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2508
2509         if (mode->clock >= 340000 && scdc->supported) {
2510                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2511                 tegra_sor_hdmi_scdc_enable(sor);
2512                 sor->scdc_enabled = true;
2513         }
2514 }
2515
2516 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2517 {
2518         struct tegra_output *output = encoder_to_output(encoder);
2519         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2520         struct tegra_sor *sor = to_sor(output);
2521         u32 value;
2522         int err;
2523
2524         tegra_sor_audio_unprepare(sor);
2525         tegra_sor_hdmi_scdc_stop(sor);
2526
2527         err = tegra_sor_detach(sor);
2528         if (err < 0)
2529                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2530
2531         tegra_sor_writel(sor, 0, SOR_STATE1);
2532         tegra_sor_update(sor);
2533
2534         /* disable display to SOR clock */
2535         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2536
2537         if (!sor->soc->has_nvdisplay)
2538                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2539         else
2540                 value &= ~SOR_ENABLE(sor->index);
2541
2542         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2543
2544         tegra_dc_commit(dc);
2545
2546         err = tegra_sor_power_down(sor);
2547         if (err < 0)
2548                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2549
2550         err = tegra_io_pad_power_disable(sor->pad);
2551         if (err < 0)
2552                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2553
2554         pm_runtime_put(sor->dev);
2555 }
2556
2557 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2558 {
2559         struct tegra_output *output = encoder_to_output(encoder);
2560         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2561         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2562         struct tegra_sor_hdmi_settings *settings;
2563         struct tegra_sor *sor = to_sor(output);
2564         struct tegra_sor_state *state;
2565         struct drm_display_mode *mode;
2566         unsigned long rate, pclk;
2567         unsigned int div, i;
2568         u32 value;
2569         int err;
2570
2571         state = to_sor_state(output->connector.state);
2572         mode = &encoder->crtc->state->adjusted_mode;
2573         pclk = mode->clock * 1000;
2574
2575         pm_runtime_get_sync(sor->dev);
2576
2577         /* switch to safe parent clock */
2578         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2579         if (err < 0) {
2580                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2581                 return;
2582         }
2583
2584         div = clk_get_rate(sor->clk) / 1000000 * 4;
2585
2586         err = tegra_io_pad_power_enable(sor->pad);
2587         if (err < 0)
2588                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2589
2590         usleep_range(20, 100);
2591
2592         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2593         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2594         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2595
2596         usleep_range(20, 100);
2597
2598         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2599         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2600         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2601
2602         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2603         value &= ~SOR_PLL0_VCOPD;
2604         value &= ~SOR_PLL0_PWR;
2605         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2606
2607         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2608         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2609         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2610
2611         usleep_range(200, 400);
2612
2613         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2614         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2615         value &= ~SOR_PLL2_PORT_POWERDOWN;
2616         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2617
2618         usleep_range(20, 100);
2619
2620         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2621         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2622                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2623         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2624
2625         while (true) {
2626                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2627                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2628                         break;
2629
2630                 usleep_range(250, 1000);
2631         }
2632
2633         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2634                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2635         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2636
2637         while (true) {
2638                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2639                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2640                         break;
2641
2642                 usleep_range(250, 1000);
2643         }
2644
2645         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2646         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2647         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2648
2649         if (mode->clock < 340000) {
2650                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2651                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2652         } else {
2653                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2654                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2655         }
2656
2657         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2658         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2659
2660         /* SOR pad PLL stabilization time */
2661         usleep_range(250, 1000);
2662
2663         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2664         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2665         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2666         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2667
2668         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2669         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2670         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2671         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2672         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2673         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2674
2675         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2676                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2677         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2678
2679         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2680                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2681         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2682         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2683
2684         if (!sor->soc->has_nvdisplay) {
2685                 /* program the reference clock */
2686                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2687                 tegra_sor_writel(sor, value, SOR_REFCLK);
2688         }
2689
2690         /* XXX not in TRM */
2691         for (value = 0, i = 0; i < 5; i++)
2692                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2693                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2694
2695         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2696         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2697
2698         /*
2699          * Switch the pad clock to the DP clock. Note that we cannot actually
2700          * do this because Tegra186 and later don't support clk_set_parent()
2701          * on the sorX_pad_clkout clocks. We already do the equivalent above
2702          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2703          */
2704 #if 0
2705         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2706         if (err < 0) {
2707                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2708                         err);
2709                 return;
2710         }
2711 #endif
2712
2713         /* switch the SOR clock to the pad clock */
2714         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2715         if (err < 0) {
2716                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2717                         err);
2718                 return;
2719         }
2720
2721         /* switch the output clock to the parent pixel clock */
2722         err = clk_set_parent(sor->clk, sor->clk_parent);
2723         if (err < 0) {
2724                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2725                         err);
2726                 return;
2727         }
2728
2729         /* adjust clock rate for HDMI 2.0 modes */
2730         rate = clk_get_rate(sor->clk_parent);
2731
2732         if (mode->clock >= 340000)
2733                 rate /= 2;
2734
2735         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2736
2737         clk_set_rate(sor->clk, rate);
2738
2739         if (!sor->soc->has_nvdisplay) {
2740                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2741
2742                 /* XXX is this the proper check? */
2743                 if (mode->clock < 75000)
2744                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2745
2746                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2747         }
2748
2749         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2750
2751         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2752                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2753         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2754
2755         if (!dc->soc->has_nvdisplay) {
2756                 /* H_PULSE2 setup */
2757                 pulse_start = h_ref_to_sync +
2758                               (mode->hsync_end - mode->hsync_start) +
2759                               (mode->htotal - mode->hsync_end) - 10;
2760
2761                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2762                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2763                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2764
2765                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2766                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2767
2768                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2769                 value |= H_PULSE2_ENABLE;
2770                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2771         }
2772
2773         /* infoframe setup */
2774         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2775         if (err < 0)
2776                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2777
2778         /* XXX HDMI audio support not implemented yet */
2779         tegra_sor_hdmi_disable_audio_infoframe(sor);
2780
2781         /* use single TMDS protocol */
2782         value = tegra_sor_readl(sor, SOR_STATE1);
2783         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2784         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2785         tegra_sor_writel(sor, value, SOR_STATE1);
2786
2787         /* power up pad calibration */
2788         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2789         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2790         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2791
2792         /* production settings */
2793         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2794         if (!settings) {
2795                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2796                         mode->clock * 1000);
2797                 return;
2798         }
2799
2800         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2801         value &= ~SOR_PLL0_ICHPMP_MASK;
2802         value &= ~SOR_PLL0_FILTER_MASK;
2803         value &= ~SOR_PLL0_VCOCAP_MASK;
2804         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2805         value |= SOR_PLL0_FILTER(settings->filter);
2806         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2807         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2808
2809         /* XXX not in TRM */
2810         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2811         value &= ~SOR_PLL1_LOADADJ_MASK;
2812         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2813         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2814         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2815         value |= SOR_PLL1_TMDS_TERM;
2816         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2817
2818         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2819         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2820         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2821         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2822         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2823         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2824         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2825         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2826         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2827         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2828
2829         value = settings->drive_current[3] << 24 |
2830                 settings->drive_current[2] << 16 |
2831                 settings->drive_current[1] <<  8 |
2832                 settings->drive_current[0] <<  0;
2833         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2834
2835         value = settings->preemphasis[3] << 24 |
2836                 settings->preemphasis[2] << 16 |
2837                 settings->preemphasis[1] <<  8 |
2838                 settings->preemphasis[0] <<  0;
2839         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2840
2841         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2842         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2843         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2844         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2845         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2846
2847         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2848         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2849         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2850         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2851
2852         /* power down pad calibration */
2853         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2854         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2855         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2856
2857         if (!dc->soc->has_nvdisplay) {
2858                 /* miscellaneous display controller settings */
2859                 value = VSYNC_H_POSITION(1);
2860                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2861         }
2862
2863         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2864         value &= ~DITHER_CONTROL_MASK;
2865         value &= ~BASE_COLOR_SIZE_MASK;
2866
2867         switch (state->bpc) {
2868         case 6:
2869                 value |= BASE_COLOR_SIZE_666;
2870                 break;
2871
2872         case 8:
2873                 value |= BASE_COLOR_SIZE_888;
2874                 break;
2875
2876         case 10:
2877                 value |= BASE_COLOR_SIZE_101010;
2878                 break;
2879
2880         case 12:
2881                 value |= BASE_COLOR_SIZE_121212;
2882                 break;
2883
2884         default:
2885                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2886                 value |= BASE_COLOR_SIZE_888;
2887                 break;
2888         }
2889
2890         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2891
2892         /* XXX set display head owner */
2893         value = tegra_sor_readl(sor, SOR_STATE1);
2894         value &= ~SOR_STATE_ASY_OWNER_MASK;
2895         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2896         tegra_sor_writel(sor, value, SOR_STATE1);
2897
2898         err = tegra_sor_power_up(sor, 250);
2899         if (err < 0)
2900                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2901
2902         /* configure dynamic range of output */
2903         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2904         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2905         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2906         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2907
2908         /* configure colorspace */
2909         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2910         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2911         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2912         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2913
2914         tegra_sor_mode_set(sor, mode, state);
2915
2916         tegra_sor_update(sor);
2917
2918         /* program preamble timing in SOR (XXX) */
2919         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2920         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2921         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2922
2923         err = tegra_sor_attach(sor);
2924         if (err < 0)
2925                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2926
2927         /* enable display to SOR clock and generate HDMI preamble */
2928         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2929
2930         if (!sor->soc->has_nvdisplay)
2931                 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2932         else
2933                 value |= SOR_ENABLE(sor->index);
2934
2935         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2936
2937         if (dc->soc->has_nvdisplay) {
2938                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2939                 value &= ~PROTOCOL_MASK;
2940                 value |= PROTOCOL_SINGLE_TMDS_A;
2941                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2942         }
2943
2944         tegra_dc_commit(dc);
2945
2946         err = tegra_sor_wakeup(sor);
2947         if (err < 0)
2948                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2949
2950         tegra_sor_hdmi_scdc_start(sor);
2951         tegra_sor_audio_prepare(sor);
2952 }
2953
2954 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2955         .disable = tegra_sor_hdmi_disable,
2956         .enable = tegra_sor_hdmi_enable,
2957         .atomic_check = tegra_sor_encoder_atomic_check,
2958 };
2959
2960 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2961 {
2962         struct tegra_output *output = encoder_to_output(encoder);
2963         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2964         struct tegra_sor *sor = to_sor(output);
2965         u32 value;
2966         int err;
2967
2968         err = drm_dp_link_power_down(sor->aux, &sor->link);
2969         if (err < 0)
2970                 dev_err(sor->dev, "failed to power down link: %d\n", err);
2971
2972         err = tegra_sor_detach(sor);
2973         if (err < 0)
2974                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2975
2976         tegra_sor_writel(sor, 0, SOR_STATE1);
2977         tegra_sor_update(sor);
2978
2979         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2980
2981         if (!sor->soc->has_nvdisplay)
2982                 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2983         else
2984                 value &= ~SOR_ENABLE(sor->index);
2985
2986         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2987         tegra_dc_commit(dc);
2988
2989         value = tegra_sor_readl(sor, SOR_STATE1);
2990         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2991         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2992         value &= ~SOR_STATE_ASY_OWNER_MASK;
2993         tegra_sor_writel(sor, value, SOR_STATE1);
2994         tegra_sor_update(sor);
2995
2996         /* switch to safe parent clock */
2997         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2998         if (err < 0)
2999                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
3000
3001         err = tegra_sor_power_down(sor);
3002         if (err < 0)
3003                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
3004
3005         err = tegra_io_pad_power_disable(sor->pad);
3006         if (err < 0)
3007                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
3008
3009         err = drm_dp_aux_disable(sor->aux);
3010         if (err < 0)
3011                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
3012
3013         pm_runtime_put(sor->dev);
3014 }
3015
3016 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
3017 {
3018         struct tegra_output *output = encoder_to_output(encoder);
3019         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
3020         struct tegra_sor *sor = to_sor(output);
3021         struct tegra_sor_config config;
3022         struct tegra_sor_state *state;
3023         struct drm_display_mode *mode;
3024         struct drm_display_info *info;
3025         unsigned int i;
3026         u32 value;
3027         int err;
3028
3029         state = to_sor_state(output->connector.state);
3030         mode = &encoder->crtc->state->adjusted_mode;
3031         info = &output->connector.display_info;
3032
3033         pm_runtime_get_sync(sor->dev);
3034
3035         /* switch to safe parent clock */
3036         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
3037         if (err < 0)
3038                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
3039
3040         err = tegra_io_pad_power_enable(sor->pad);
3041         if (err < 0)
3042                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
3043
3044         usleep_range(20, 100);
3045
3046         err = drm_dp_aux_enable(sor->aux);
3047         if (err < 0)
3048                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
3049
3050         err = drm_dp_link_probe(sor->aux, &sor->link);
3051         if (err < 0)
3052                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
3053
3054         err = drm_dp_link_choose(&sor->link, mode, info);
3055         if (err < 0)
3056                 dev_err(sor->dev, "failed to choose link: %d\n", err);
3057
3058         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3059         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
3060         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3061
3062         usleep_range(20, 40);
3063
3064         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
3065         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
3066         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
3067
3068         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3069         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
3070         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3071
3072         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3073         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
3074         value |= SOR_PLL2_SEQ_PLLCAPPD;
3075         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3076
3077         usleep_range(200, 400);
3078
3079         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3080         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
3081         value &= ~SOR_PLL2_PORT_POWERDOWN;
3082         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3083
3084         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
3085         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
3086         value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
3087         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
3088
3089         usleep_range(200, 400);
3090
3091         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
3092         /* XXX not in TRM */
3093         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
3094         value |= SOR_DP_SPARE_SEQ_ENABLE;
3095         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
3096
3097         /* XXX not in TRM */
3098         tegra_sor_writel(sor, 0, SOR_LVDS);
3099
3100         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3101         value &= ~SOR_PLL0_ICHPMP_MASK;
3102         value &= ~SOR_PLL0_VCOCAP_MASK;
3103         value |= SOR_PLL0_ICHPMP(0x1);
3104         value |= SOR_PLL0_VCOCAP(0x3);
3105         value |= SOR_PLL0_RESISTOR_EXT;
3106         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3107
3108         /* XXX not in TRM */
3109         for (value = 0, i = 0; i < 5; i++)
3110                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
3111                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
3112
3113         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
3114         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
3115
3116         /*
3117          * Switch the pad clock to the DP clock. Note that we cannot actually
3118          * do this because Tegra186 and later don't support clk_set_parent()
3119          * on the sorX_pad_clkout clocks. We already do the equivalent above
3120          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
3121          */
3122 #if 0
3123         err = clk_set_parent(sor->clk_pad, sor->clk_parent);
3124         if (err < 0) {
3125                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
3126                         err);
3127                 return;
3128         }
3129 #endif
3130
3131         /* switch the SOR clock to the pad clock */
3132         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
3133         if (err < 0) {
3134                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
3135                         err);
3136                 return;
3137         }
3138
3139         /* switch the output clock to the parent pixel clock */
3140         err = clk_set_parent(sor->clk, sor->clk_parent);
3141         if (err < 0) {
3142                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
3143                         err);
3144                 return;
3145         }
3146
3147         /* use DP-A protocol */
3148         value = tegra_sor_readl(sor, SOR_STATE1);
3149         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
3150         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
3151         tegra_sor_writel(sor, value, SOR_STATE1);
3152
3153         /* enable port */
3154         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
3155         value |= SOR_DP_LINKCTL_ENABLE;
3156         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
3157
3158         tegra_sor_dp_term_calibrate(sor);
3159
3160         err = drm_dp_link_train(&sor->link);
3161         if (err < 0)
3162                 dev_err(sor->dev, "link training failed: %d\n", err);
3163         else
3164                 dev_dbg(sor->dev, "link training succeeded\n");
3165
3166         err = drm_dp_link_power_up(sor->aux, &sor->link);
3167         if (err < 0)
3168                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
3169
3170         /* compute configuration */
3171         memset(&config, 0, sizeof(config));
3172         config.bits_per_pixel = state->bpc * 3;
3173
3174         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
3175         if (err < 0)
3176                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
3177
3178         tegra_sor_apply_config(sor, &config);
3179         tegra_sor_mode_set(sor, mode, state);
3180         tegra_sor_update(sor);
3181
3182         err = tegra_sor_power_up(sor, 250);
3183         if (err < 0)
3184                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
3185
3186         /* attach and wake up */
3187         err = tegra_sor_attach(sor);
3188         if (err < 0)
3189                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
3190
3191         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
3192         value |= SOR_ENABLE(sor->index);
3193         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
3194
3195         tegra_dc_commit(dc);
3196
3197         err = tegra_sor_wakeup(sor);
3198         if (err < 0)
3199                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
3200 }
3201
3202 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
3203         .disable = tegra_sor_dp_disable,
3204         .enable = tegra_sor_dp_enable,
3205         .atomic_check = tegra_sor_encoder_atomic_check,
3206 };
3207
3208 static const struct tegra_sor_ops tegra_sor_edp_ops = {
3209         .name = "eDP",
3210 };
3211
3212 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
3213 {
3214         int err;
3215
3216         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
3217         if (IS_ERR(sor->avdd_io_supply)) {
3218                 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
3219                         PTR_ERR(sor->avdd_io_supply));
3220                 return PTR_ERR(sor->avdd_io_supply);
3221         }
3222
3223         err = regulator_enable(sor->avdd_io_supply);
3224         if (err < 0) {
3225                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
3226                         err);
3227                 return err;
3228         }
3229
3230         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
3231         if (IS_ERR(sor->vdd_pll_supply)) {
3232                 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
3233                         PTR_ERR(sor->vdd_pll_supply));
3234                 return PTR_ERR(sor->vdd_pll_supply);
3235         }
3236
3237         err = regulator_enable(sor->vdd_pll_supply);
3238         if (err < 0) {
3239                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
3240                         err);
3241                 return err;
3242         }
3243
3244         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
3245         if (IS_ERR(sor->hdmi_supply)) {
3246                 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
3247                         PTR_ERR(sor->hdmi_supply));
3248                 return PTR_ERR(sor->hdmi_supply);
3249         }
3250
3251         err = regulator_enable(sor->hdmi_supply);
3252         if (err < 0) {
3253                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3254                 return err;
3255         }
3256
3257         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3258
3259         return 0;
3260 }
3261
3262 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3263 {
3264         regulator_disable(sor->hdmi_supply);
3265         regulator_disable(sor->vdd_pll_supply);
3266         regulator_disable(sor->avdd_io_supply);
3267
3268         return 0;
3269 }
3270
3271 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3272         .name = "HDMI",
3273         .probe = tegra_sor_hdmi_probe,
3274         .remove = tegra_sor_hdmi_remove,
3275 };
3276
3277 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3278 {
3279         int err;
3280
3281         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3282         if (IS_ERR(sor->avdd_io_supply))
3283                 return PTR_ERR(sor->avdd_io_supply);
3284
3285         err = regulator_enable(sor->avdd_io_supply);
3286         if (err < 0)
3287                 return err;
3288
3289         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3290         if (IS_ERR(sor->vdd_pll_supply))
3291                 return PTR_ERR(sor->vdd_pll_supply);
3292
3293         err = regulator_enable(sor->vdd_pll_supply);
3294         if (err < 0)
3295                 return err;
3296
3297         return 0;
3298 }
3299
3300 static int tegra_sor_dp_remove(struct tegra_sor *sor)
3301 {
3302         regulator_disable(sor->vdd_pll_supply);
3303         regulator_disable(sor->avdd_io_supply);
3304
3305         return 0;
3306 }
3307
3308 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3309         .name = "DP",
3310         .probe = tegra_sor_dp_probe,
3311         .remove = tegra_sor_dp_remove,
3312 };
3313
3314 static int tegra_sor_init(struct host1x_client *client)
3315 {
3316         struct drm_device *drm = dev_get_drvdata(client->parent);
3317         const struct drm_encoder_helper_funcs *helpers = NULL;
3318         struct tegra_sor *sor = host1x_client_to_sor(client);
3319         int connector = DRM_MODE_CONNECTOR_Unknown;
3320         int encoder = DRM_MODE_ENCODER_NONE;
3321         int err;
3322
3323         if (!sor->aux) {
3324                 if (sor->ops == &tegra_sor_hdmi_ops) {
3325                         connector = DRM_MODE_CONNECTOR_HDMIA;
3326                         encoder = DRM_MODE_ENCODER_TMDS;
3327                         helpers = &tegra_sor_hdmi_helpers;
3328                 } else if (sor->soc->supports_lvds) {
3329                         connector = DRM_MODE_CONNECTOR_LVDS;
3330                         encoder = DRM_MODE_ENCODER_LVDS;
3331                 }
3332         } else {
3333                 if (sor->ops == &tegra_sor_edp_ops) {
3334                         connector = DRM_MODE_CONNECTOR_eDP;
3335                         encoder = DRM_MODE_ENCODER_TMDS;
3336                         helpers = &tegra_sor_edp_helpers;
3337                 } else {
3338                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3339                         encoder = DRM_MODE_ENCODER_TMDS;
3340                         helpers = &tegra_sor_dp_helpers;
3341                 }
3342
3343                 sor->link.ops = &tegra_sor_dp_link_ops;
3344                 sor->link.aux = sor->aux;
3345         }
3346
3347         sor->output.dev = sor->dev;
3348
3349         drm_connector_init(drm, &sor->output.connector,
3350                            &tegra_sor_connector_funcs,
3351                            connector);
3352         drm_connector_helper_add(&sor->output.connector,
3353                                  &tegra_sor_connector_helper_funcs);
3354         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3355
3356         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
3357                          encoder, NULL);
3358         drm_encoder_helper_add(&sor->output.encoder, helpers);
3359
3360         drm_connector_attach_encoder(&sor->output.connector,
3361                                           &sor->output.encoder);
3362         drm_connector_register(&sor->output.connector);
3363
3364         err = tegra_output_init(drm, &sor->output);
3365         if (err < 0) {
3366                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3367                 return err;
3368         }
3369
3370         tegra_output_find_possible_crtcs(&sor->output, drm);
3371
3372         if (sor->aux) {
3373                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3374                 if (err < 0) {
3375                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3376                         return err;
3377                 }
3378         }
3379
3380         /*
3381          * XXX: Remove this reset once proper hand-over from firmware to
3382          * kernel is possible.
3383          */
3384         if (sor->rst) {
3385                 err = reset_control_acquire(sor->rst);
3386                 if (err < 0) {
3387                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3388                                 err);
3389                         return err;
3390                 }
3391
3392                 err = reset_control_assert(sor->rst);
3393                 if (err < 0) {
3394                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3395                                 err);
3396                         return err;
3397                 }
3398         }
3399
3400         err = clk_prepare_enable(sor->clk);
3401         if (err < 0) {
3402                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3403                 return err;
3404         }
3405
3406         usleep_range(1000, 3000);
3407
3408         if (sor->rst) {
3409                 err = reset_control_deassert(sor->rst);
3410                 if (err < 0) {
3411                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3412                                 err);
3413                         return err;
3414                 }
3415
3416                 reset_control_release(sor->rst);
3417         }
3418
3419         err = clk_prepare_enable(sor->clk_safe);
3420         if (err < 0)
3421                 return err;
3422
3423         err = clk_prepare_enable(sor->clk_dp);
3424         if (err < 0)
3425                 return err;
3426
3427         return 0;
3428 }
3429
3430 static int tegra_sor_exit(struct host1x_client *client)
3431 {
3432         struct tegra_sor *sor = host1x_client_to_sor(client);
3433         int err;
3434
3435         tegra_output_exit(&sor->output);
3436
3437         if (sor->aux) {
3438                 err = drm_dp_aux_detach(sor->aux);
3439                 if (err < 0) {
3440                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3441                         return err;
3442                 }
3443         }
3444
3445         clk_disable_unprepare(sor->clk_safe);
3446         clk_disable_unprepare(sor->clk_dp);
3447         clk_disable_unprepare(sor->clk);
3448
3449         return 0;
3450 }
3451
3452 static const struct host1x_client_ops sor_client_ops = {
3453         .init = tegra_sor_init,
3454         .exit = tegra_sor_exit,
3455 };
3456
3457 static const u8 tegra124_sor_xbar_cfg[5] = {
3458         0, 1, 2, 3, 4
3459 };
3460
3461 static const struct tegra_sor_regs tegra124_sor_regs = {
3462         .head_state0 = 0x05,
3463         .head_state1 = 0x07,
3464         .head_state2 = 0x09,
3465         .head_state3 = 0x0b,
3466         .head_state4 = 0x0d,
3467         .head_state5 = 0x0f,
3468         .pll0 = 0x17,
3469         .pll1 = 0x18,
3470         .pll2 = 0x19,
3471         .pll3 = 0x1a,
3472         .dp_padctl0 = 0x5c,
3473         .dp_padctl2 = 0x73,
3474 };
3475
3476 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3477 static const u8 tegra124_sor_lane_map[4] = {
3478         2, 1, 0, 3,
3479 };
3480
3481 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3482         {
3483                 { 0x13, 0x19, 0x1e, 0x28 },
3484                 { 0x1e, 0x25, 0x2d, },
3485                 { 0x28, 0x32, },
3486                 { 0x3c, },
3487         }, {
3488                 { 0x12, 0x17, 0x1b, 0x25 },
3489                 { 0x1c, 0x23, 0x2a, },
3490                 { 0x25, 0x2f, },
3491                 { 0x39, }
3492         }, {
3493                 { 0x12, 0x16, 0x1a, 0x22 },
3494                 { 0x1b, 0x20, 0x27, },
3495                 { 0x24, 0x2d, },
3496                 { 0x36, },
3497         }, {
3498                 { 0x11, 0x14, 0x17, 0x1f },
3499                 { 0x19, 0x1e, 0x24, },
3500                 { 0x22, 0x2a, },
3501                 { 0x32, },
3502         },
3503 };
3504
3505 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3506         {
3507                 { 0x00, 0x09, 0x13, 0x25 },
3508                 { 0x00, 0x0f, 0x1e, },
3509                 { 0x00, 0x14, },
3510                 { 0x00, },
3511         }, {
3512                 { 0x00, 0x0a, 0x14, 0x28 },
3513                 { 0x00, 0x0f, 0x1e, },
3514                 { 0x00, 0x14, },
3515                 { 0x00 },
3516         }, {
3517                 { 0x00, 0x0a, 0x14, 0x28 },
3518                 { 0x00, 0x0f, 0x1e, },
3519                 { 0x00, 0x14, },
3520                 { 0x00, },
3521         }, {
3522                 { 0x00, 0x0a, 0x14, 0x28 },
3523                 { 0x00, 0x0f, 0x1e, },
3524                 { 0x00, 0x14, },
3525                 { 0x00, },
3526         },
3527 };
3528
3529 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3530         {
3531                 { 0x00, 0x00, 0x00, 0x00 },
3532                 { 0x00, 0x00, 0x00, },
3533                 { 0x00, 0x00, },
3534                 { 0x00, },
3535         }, {
3536                 { 0x02, 0x02, 0x04, 0x05 },
3537                 { 0x02, 0x04, 0x05, },
3538                 { 0x04, 0x05, },
3539                 { 0x05, },
3540         }, {
3541                 { 0x04, 0x05, 0x08, 0x0b },
3542                 { 0x05, 0x09, 0x0b, },
3543                 { 0x08, 0x0a, },
3544                 { 0x0b, },
3545         }, {
3546                 { 0x05, 0x09, 0x0b, 0x12 },
3547                 { 0x09, 0x0d, 0x12, },
3548                 { 0x0b, 0x0f, },
3549                 { 0x12, },
3550         },
3551 };
3552
3553 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3554         {
3555                 { 0x20, 0x30, 0x40, 0x60 },
3556                 { 0x30, 0x40, 0x60, },
3557                 { 0x40, 0x60, },
3558                 { 0x60, },
3559         }, {
3560                 { 0x20, 0x20, 0x30, 0x50 },
3561                 { 0x30, 0x40, 0x50, },
3562                 { 0x40, 0x50, },
3563                 { 0x60, },
3564         }, {
3565                 { 0x20, 0x20, 0x30, 0x40, },
3566                 { 0x30, 0x30, 0x40, },
3567                 { 0x40, 0x50, },
3568                 { 0x60, },
3569         }, {
3570                 { 0x20, 0x20, 0x20, 0x40, },
3571                 { 0x30, 0x30, 0x40, },
3572                 { 0x40, 0x40, },
3573                 { 0x60, },
3574         },
3575 };
3576
3577 static const struct tegra_sor_soc tegra124_sor = {
3578         .supports_edp = true,
3579         .supports_lvds = true,
3580         .supports_hdmi = false,
3581         .supports_dp = false,
3582         .regs = &tegra124_sor_regs,
3583         .has_nvdisplay = false,
3584         .xbar_cfg = tegra124_sor_xbar_cfg,
3585         .lane_map = tegra124_sor_lane_map,
3586         .voltage_swing = tegra124_sor_voltage_swing,
3587         .pre_emphasis = tegra124_sor_pre_emphasis,
3588         .post_cursor = tegra124_sor_post_cursor,
3589         .tx_pu = tegra124_sor_tx_pu,
3590 };
3591
3592 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3593         {
3594                 { 0x00, 0x08, 0x12, 0x24 },
3595                 { 0x01, 0x0e, 0x1d, },
3596                 { 0x01, 0x13, },
3597                 { 0x00, },
3598         }, {
3599                 { 0x00, 0x08, 0x12, 0x24 },
3600                 { 0x00, 0x0e, 0x1d, },
3601                 { 0x00, 0x13, },
3602                 { 0x00 },
3603         }, {
3604                 { 0x00, 0x08, 0x12, 0x24 },
3605                 { 0x00, 0x0e, 0x1d, },
3606                 { 0x00, 0x13, },
3607                 { 0x00, },
3608         }, {
3609                 { 0x00, 0x08, 0x12, 0x24 },
3610                 { 0x00, 0x0e, 0x1d, },
3611                 { 0x00, 0x13, },
3612                 { 0x00, },
3613         },
3614 };
3615
3616 static const struct tegra_sor_soc tegra132_sor = {
3617         .supports_edp = true,
3618         .supports_lvds = true,
3619         .supports_hdmi = false,
3620         .supports_dp = false,
3621         .regs = &tegra124_sor_regs,
3622         .has_nvdisplay = false,
3623         .xbar_cfg = tegra124_sor_xbar_cfg,
3624         .lane_map = tegra124_sor_lane_map,
3625         .voltage_swing = tegra124_sor_voltage_swing,
3626         .pre_emphasis = tegra132_sor_pre_emphasis,
3627         .post_cursor = tegra124_sor_post_cursor,
3628         .tx_pu = tegra124_sor_tx_pu,
3629 };
3630
3631 static const struct tegra_sor_regs tegra210_sor_regs = {
3632         .head_state0 = 0x05,
3633         .head_state1 = 0x07,
3634         .head_state2 = 0x09,
3635         .head_state3 = 0x0b,
3636         .head_state4 = 0x0d,
3637         .head_state5 = 0x0f,
3638         .pll0 = 0x17,
3639         .pll1 = 0x18,
3640         .pll2 = 0x19,
3641         .pll3 = 0x1a,
3642         .dp_padctl0 = 0x5c,
3643         .dp_padctl2 = 0x73,
3644 };
3645
3646 static const u8 tegra210_sor_xbar_cfg[5] = {
3647         2, 1, 0, 3, 4
3648 };
3649
3650 static const u8 tegra210_sor_lane_map[4] = {
3651         0, 1, 2, 3,
3652 };
3653
3654 static const struct tegra_sor_soc tegra210_sor = {
3655         .supports_edp = true,
3656         .supports_lvds = false,
3657         .supports_hdmi = false,
3658         .supports_dp = false,
3659
3660         .regs = &tegra210_sor_regs,
3661         .has_nvdisplay = false,
3662
3663         .xbar_cfg = tegra210_sor_xbar_cfg,
3664         .lane_map = tegra210_sor_lane_map,
3665         .voltage_swing = tegra124_sor_voltage_swing,
3666         .pre_emphasis = tegra124_sor_pre_emphasis,
3667         .post_cursor = tegra124_sor_post_cursor,
3668         .tx_pu = tegra124_sor_tx_pu,
3669 };
3670
3671 static const struct tegra_sor_soc tegra210_sor1 = {
3672         .supports_edp = false,
3673         .supports_lvds = false,
3674         .supports_hdmi = true,
3675         .supports_dp = true,
3676
3677         .regs = &tegra210_sor_regs,
3678         .has_nvdisplay = false,
3679
3680         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3681         .settings = tegra210_sor_hdmi_defaults,
3682         .xbar_cfg = tegra210_sor_xbar_cfg,
3683         .lane_map = tegra210_sor_lane_map,
3684         .voltage_swing = tegra124_sor_voltage_swing,
3685         .pre_emphasis = tegra124_sor_pre_emphasis,
3686         .post_cursor = tegra124_sor_post_cursor,
3687         .tx_pu = tegra124_sor_tx_pu,
3688 };
3689
3690 static const struct tegra_sor_regs tegra186_sor_regs = {
3691         .head_state0 = 0x151,
3692         .head_state1 = 0x154,
3693         .head_state2 = 0x157,
3694         .head_state3 = 0x15a,
3695         .head_state4 = 0x15d,
3696         .head_state5 = 0x160,
3697         .pll0 = 0x163,
3698         .pll1 = 0x164,
3699         .pll2 = 0x165,
3700         .pll3 = 0x166,
3701         .dp_padctl0 = 0x168,
3702         .dp_padctl2 = 0x16a,
3703 };
3704
3705 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3706         {
3707                 { 0x13, 0x19, 0x1e, 0x28 },
3708                 { 0x1e, 0x25, 0x2d, },
3709                 { 0x28, 0x32, },
3710                 { 0x39, },
3711         }, {
3712                 { 0x12, 0x16, 0x1b, 0x25 },
3713                 { 0x1c, 0x23, 0x2a, },
3714                 { 0x25, 0x2f, },
3715                 { 0x37, }
3716         }, {
3717                 { 0x12, 0x16, 0x1a, 0x22 },
3718                 { 0x1b, 0x20, 0x27, },
3719                 { 0x24, 0x2d, },
3720                 { 0x35, },
3721         }, {
3722                 { 0x11, 0x14, 0x17, 0x1f },
3723                 { 0x19, 0x1e, 0x24, },
3724                 { 0x22, 0x2a, },
3725                 { 0x32, },
3726         },
3727 };
3728
3729 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3730         {
3731                 { 0x00, 0x08, 0x12, 0x24 },
3732                 { 0x01, 0x0e, 0x1d, },
3733                 { 0x01, 0x13, },
3734                 { 0x00, },
3735         }, {
3736                 { 0x00, 0x08, 0x12, 0x24 },
3737                 { 0x00, 0x0e, 0x1d, },
3738                 { 0x00, 0x13, },
3739                 { 0x00 },
3740         }, {
3741                 { 0x00, 0x08, 0x14, 0x24 },
3742                 { 0x00, 0x0e, 0x1d, },
3743                 { 0x00, 0x13, },
3744                 { 0x00, },
3745         }, {
3746                 { 0x00, 0x08, 0x12, 0x24 },
3747                 { 0x00, 0x0e, 0x1d, },
3748                 { 0x00, 0x13, },
3749                 { 0x00, },
3750         },
3751 };
3752
3753 static const struct tegra_sor_soc tegra186_sor = {
3754         .supports_edp = false,
3755         .supports_lvds = false,
3756         .supports_hdmi = true,
3757         .supports_dp = true,
3758
3759         .regs = &tegra186_sor_regs,
3760         .has_nvdisplay = true,
3761
3762         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3763         .settings = tegra186_sor_hdmi_defaults,
3764         .xbar_cfg = tegra124_sor_xbar_cfg,
3765         .lane_map = tegra124_sor_lane_map,
3766         .voltage_swing = tegra186_sor_voltage_swing,
3767         .pre_emphasis = tegra186_sor_pre_emphasis,
3768         .post_cursor = tegra124_sor_post_cursor,
3769         .tx_pu = tegra124_sor_tx_pu,
3770 };
3771
3772 static const struct tegra_sor_regs tegra194_sor_regs = {
3773         .head_state0 = 0x151,
3774         .head_state1 = 0x155,
3775         .head_state2 = 0x159,
3776         .head_state3 = 0x15d,
3777         .head_state4 = 0x161,
3778         .head_state5 = 0x165,
3779         .pll0 = 0x169,
3780         .pll1 = 0x16a,
3781         .pll2 = 0x16b,
3782         .pll3 = 0x16c,
3783         .dp_padctl0 = 0x16e,
3784         .dp_padctl2 = 0x16f,
3785 };
3786
3787 static const struct tegra_sor_soc tegra194_sor = {
3788         .supports_edp = true,
3789         .supports_lvds = false,
3790         .supports_hdmi = true,
3791         .supports_dp = true,
3792
3793         .regs = &tegra194_sor_regs,
3794         .has_nvdisplay = true,
3795
3796         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3797         .settings = tegra194_sor_hdmi_defaults,
3798
3799         .xbar_cfg = tegra210_sor_xbar_cfg,
3800         .lane_map = tegra124_sor_lane_map,
3801         .voltage_swing = tegra186_sor_voltage_swing,
3802         .pre_emphasis = tegra186_sor_pre_emphasis,
3803         .post_cursor = tegra124_sor_post_cursor,
3804         .tx_pu = tegra124_sor_tx_pu,
3805 };
3806
3807 static const struct of_device_id tegra_sor_of_match[] = {
3808         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3809         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3810         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3811         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3812         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3813         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3814         { },
3815 };
3816 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3817
3818 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3819 {
3820         struct device_node *np = sor->dev->of_node;
3821         u32 xbar_cfg[5];
3822         unsigned int i;
3823         u32 value;
3824         int err;
3825
3826         if (sor->soc->has_nvdisplay) {
3827                 err = of_property_read_u32(np, "nvidia,interface", &value);
3828                 if (err < 0)
3829                         return err;
3830
3831                 sor->index = value;
3832
3833                 /*
3834                  * override the default that we already set for Tegra210 and
3835                  * earlier
3836                  */
3837                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3838         } else {
3839                 if (sor->soc->supports_edp)
3840                         sor->index = 0;
3841                 else
3842                         sor->index = 1;
3843         }
3844
3845         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3846         if (err < 0) {
3847                 /* fall back to default per-SoC XBAR configuration */
3848                 for (i = 0; i < 5; i++)
3849                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3850         } else {
3851                 /* copy cells to SOR XBAR configuration */
3852                 for (i = 0; i < 5; i++)
3853                         sor->xbar_cfg[i] = xbar_cfg[i];
3854         }
3855
3856         return 0;
3857 }
3858
3859 static irqreturn_t tegra_sor_irq(int irq, void *data)
3860 {
3861         struct tegra_sor *sor = data;
3862         u32 value;
3863
3864         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3865         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3866
3867         if (value & SOR_INT_CODEC_SCRATCH0) {
3868                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3869
3870                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3871                         unsigned int format;
3872
3873                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3874
3875                         tegra_hda_parse_format(format, &sor->format);
3876
3877                         tegra_sor_hdmi_audio_enable(sor);
3878                 } else {
3879                         tegra_sor_hdmi_audio_disable(sor);
3880                 }
3881         }
3882
3883         return IRQ_HANDLED;
3884 }
3885
3886 static int tegra_sor_probe(struct platform_device *pdev)
3887 {
3888         struct device_node *np;
3889         struct tegra_sor *sor;
3890         struct resource *regs;
3891         int err;
3892
3893         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3894         if (!sor)
3895                 return -ENOMEM;
3896
3897         sor->soc = of_device_get_match_data(&pdev->dev);
3898         sor->output.dev = sor->dev = &pdev->dev;
3899
3900         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3901                                      sor->soc->num_settings *
3902                                         sizeof(*sor->settings),
3903                                      GFP_KERNEL);
3904         if (!sor->settings)
3905                 return -ENOMEM;
3906
3907         sor->num_settings = sor->soc->num_settings;
3908
3909         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3910         if (np) {
3911                 sor->aux = drm_dp_aux_find_by_of_node(np);
3912                 of_node_put(np);
3913
3914                 if (!sor->aux)
3915                         return -EPROBE_DEFER;
3916
3917                 sor->output.ddc = &sor->aux->ddc;
3918         }
3919
3920         if (!sor->aux) {
3921                 if (sor->soc->supports_hdmi) {
3922                         sor->ops = &tegra_sor_hdmi_ops;
3923                         sor->pad = TEGRA_IO_PAD_HDMI;
3924                 } else if (sor->soc->supports_lvds) {
3925                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3926                         return -ENODEV;
3927                 } else {
3928                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3929                         return -ENODEV;
3930                 }
3931         } else {
3932                 if (sor->soc->supports_edp) {
3933                         sor->ops = &tegra_sor_edp_ops;
3934                         sor->pad = TEGRA_IO_PAD_LVDS;
3935                 } else if (sor->soc->supports_dp) {
3936                         sor->ops = &tegra_sor_dp_ops;
3937                         sor->pad = TEGRA_IO_PAD_LVDS;
3938                 } else {
3939                         dev_err(&pdev->dev, "unknown (DP) support\n");
3940                         return -ENODEV;
3941                 }
3942         }
3943
3944         err = tegra_sor_parse_dt(sor);
3945         if (err < 0)
3946                 return err;
3947
3948         err = tegra_output_probe(&sor->output);
3949         if (err < 0) {
3950                 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3951                 return err;
3952         }
3953
3954         if (sor->ops && sor->ops->probe) {
3955                 err = sor->ops->probe(sor);
3956                 if (err < 0) {
3957                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3958                                 sor->ops->name, err);
3959                         goto output;
3960                 }
3961         }
3962
3963         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3964         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3965         if (IS_ERR(sor->regs)) {
3966                 err = PTR_ERR(sor->regs);
3967                 goto remove;
3968         }
3969
3970         err = platform_get_irq(pdev, 0);
3971         if (err < 0) {
3972                 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3973                 goto remove;
3974         }
3975
3976         sor->irq = err;
3977
3978         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3979                                dev_name(sor->dev), sor);
3980         if (err < 0) {
3981                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3982                 goto remove;
3983         }
3984
3985         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3986         if (IS_ERR(sor->rst)) {
3987                 err = PTR_ERR(sor->rst);
3988
3989                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3990                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3991                                 err);
3992                         goto remove;
3993                 }
3994
3995                 /*
3996                  * At this point, the reset control is most likely being used
3997                  * by the generic power domain implementation. With any luck
3998                  * the power domain will have taken care of resetting the SOR
3999                  * and we don't have to do anything.
4000                  */
4001                 sor->rst = NULL;
4002         }
4003
4004         sor->clk = devm_clk_get(&pdev->dev, NULL);
4005         if (IS_ERR(sor->clk)) {
4006                 err = PTR_ERR(sor->clk);
4007                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
4008                 goto remove;
4009         }
4010
4011         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
4012                 struct device_node *np = pdev->dev.of_node;
4013                 const char *name;
4014
4015                 /*
4016                  * For backwards compatibility with Tegra210 device trees,
4017                  * fall back to the old clock name "source" if the new "out"
4018                  * clock is not available.
4019                  */
4020                 if (of_property_match_string(np, "clock-names", "out") < 0)
4021                         name = "source";
4022                 else
4023                         name = "out";
4024
4025                 sor->clk_out = devm_clk_get(&pdev->dev, name);
4026                 if (IS_ERR(sor->clk_out)) {
4027                         err = PTR_ERR(sor->clk_out);
4028                         dev_err(sor->dev, "failed to get %s clock: %d\n",
4029                                 name, err);
4030                         goto remove;
4031                 }
4032         } else {
4033                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
4034                 sor->clk_out = sor->clk;
4035         }
4036
4037         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
4038         if (IS_ERR(sor->clk_parent)) {
4039                 err = PTR_ERR(sor->clk_parent);
4040                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
4041                 goto remove;
4042         }
4043
4044         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
4045         if (IS_ERR(sor->clk_safe)) {
4046                 err = PTR_ERR(sor->clk_safe);
4047                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
4048                 goto remove;
4049         }
4050
4051         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
4052         if (IS_ERR(sor->clk_dp)) {
4053                 err = PTR_ERR(sor->clk_dp);
4054                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
4055                 goto remove;
4056         }
4057
4058         /*
4059          * Starting with Tegra186, the BPMP provides an implementation for
4060          * the pad output clock, so we have to look it up from device tree.
4061          */
4062         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
4063         if (IS_ERR(sor->clk_pad)) {
4064                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
4065                         err = PTR_ERR(sor->clk_pad);
4066                         goto remove;
4067                 }
4068
4069                 /*
4070                  * If the pad output clock is not available, then we assume
4071                  * we're on Tegra210 or earlier and have to provide our own
4072                  * implementation.
4073                  */
4074                 sor->clk_pad = NULL;
4075         }
4076
4077         /*
4078          * The bootloader may have set up the SOR such that it's module clock
4079          * is sourced by one of the display PLLs. However, that doesn't work
4080          * without properly having set up other bits of the SOR.
4081          */
4082         err = clk_set_parent(sor->clk_out, sor->clk_safe);
4083         if (err < 0) {
4084                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
4085                 goto remove;
4086         }
4087
4088         platform_set_drvdata(pdev, sor);
4089         pm_runtime_enable(&pdev->dev);
4090
4091         /*
4092          * On Tegra210 and earlier, provide our own implementation for the
4093          * pad output clock.
4094          */
4095         if (!sor->clk_pad) {
4096                 char *name;
4097
4098                 err = pm_runtime_get_sync(&pdev->dev);
4099                 if (err < 0) {
4100                         dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
4101                                 err);
4102                         goto remove;
4103                 }
4104
4105                 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "sor%u_pad_clkout", sor->index);
4106                 if (!name) {
4107                         err = -ENOMEM;
4108                         goto remove;
4109                 }
4110
4111                 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
4112                 pm_runtime_put(&pdev->dev);
4113         }
4114
4115         if (IS_ERR(sor->clk_pad)) {
4116                 err = PTR_ERR(sor->clk_pad);
4117                 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
4118                         err);
4119                 goto remove;
4120         }
4121
4122         INIT_LIST_HEAD(&sor->client.list);
4123         sor->client.ops = &sor_client_ops;
4124         sor->client.dev = &pdev->dev;
4125
4126         err = host1x_client_register(&sor->client);
4127         if (err < 0) {
4128                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
4129                         err);
4130                 goto remove;
4131         }
4132
4133         return 0;
4134
4135 remove:
4136         if (sor->ops && sor->ops->remove)
4137                 sor->ops->remove(sor);
4138 output:
4139         tegra_output_remove(&sor->output);
4140         return err;
4141 }
4142
4143 static int tegra_sor_remove(struct platform_device *pdev)
4144 {
4145         struct tegra_sor *sor = platform_get_drvdata(pdev);
4146         int err;
4147
4148         pm_runtime_disable(&pdev->dev);
4149
4150         err = host1x_client_unregister(&sor->client);
4151         if (err < 0) {
4152                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
4153                         err);
4154                 return err;
4155         }
4156
4157         if (sor->ops && sor->ops->remove) {
4158                 err = sor->ops->remove(sor);
4159                 if (err < 0)
4160                         dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
4161         }
4162
4163         tegra_output_remove(&sor->output);
4164
4165         return 0;
4166 }
4167
4168 #ifdef CONFIG_PM
4169 static int tegra_sor_suspend(struct device *dev)
4170 {
4171         struct tegra_sor *sor = dev_get_drvdata(dev);
4172         int err;
4173
4174         if (sor->rst) {
4175                 err = reset_control_assert(sor->rst);
4176                 if (err < 0) {
4177                         dev_err(dev, "failed to assert reset: %d\n", err);
4178                         return err;
4179                 }
4180
4181                 reset_control_release(sor->rst);
4182         }
4183
4184         usleep_range(1000, 2000);
4185
4186         clk_disable_unprepare(sor->clk);
4187
4188         return 0;
4189 }
4190
4191 static int tegra_sor_resume(struct device *dev)
4192 {
4193         struct tegra_sor *sor = dev_get_drvdata(dev);
4194         int err;
4195
4196         err = clk_prepare_enable(sor->clk);
4197         if (err < 0) {
4198                 dev_err(dev, "failed to enable clock: %d\n", err);
4199                 return err;
4200         }
4201
4202         usleep_range(1000, 2000);
4203
4204         if (sor->rst) {
4205                 err = reset_control_acquire(sor->rst);
4206                 if (err < 0) {
4207                         dev_err(dev, "failed to acquire reset: %d\n", err);
4208                         clk_disable_unprepare(sor->clk);
4209                         return err;
4210                 }
4211
4212                 err = reset_control_deassert(sor->rst);
4213                 if (err < 0) {
4214                         dev_err(dev, "failed to deassert reset: %d\n", err);
4215                         reset_control_release(sor->rst);
4216                         clk_disable_unprepare(sor->clk);
4217                         return err;
4218                 }
4219         }
4220
4221         return 0;
4222 }
4223 #endif
4224
4225 static const struct dev_pm_ops tegra_sor_pm_ops = {
4226         SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
4227 };
4228
4229 struct platform_driver tegra_sor_driver = {
4230         .driver = {
4231                 .name = "tegra-sor",
4232                 .of_match_table = tegra_sor_of_match,
4233                 .pm = &tegra_sor_pm_ops,
4234         },
4235         .probe = tegra_sor_probe,
4236         .remove = tegra_sor_remove,
4237 };