1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/clk-provider.h>
8 #include <linux/debugfs.h>
9 #include <linux/gpio.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
18 #include <soc/tegra/pmc.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_debugfs.h>
22 #include <drm/drm_dp_helper.h>
23 #include <drm/drm_file.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_scdc_helper.h>
34 #define SOR_REKEY 0x38
36 struct tegra_sor_hdmi_settings {
37 unsigned long frequency;
56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
58 .frequency = 54000000,
70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
73 .frequency = 75000000,
85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
88 .frequency = 150000000,
100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
103 .frequency = 300000000,
111 .bg_vref_level = 0xa,
115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
118 .frequency = 600000000,
126 .bg_vref_level = 0x8,
130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
137 .frequency = 75000000,
145 .bg_vref_level = 0x8,
149 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
152 .frequency = 150000000,
160 .bg_vref_level = 0x8,
164 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
167 .frequency = 300000000,
175 .bg_vref_level = 0xf,
179 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
182 .frequency = 600000000,
190 .bg_vref_level = 0xe,
194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
202 .frequency = 54000000,
214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
217 .frequency = 75000000,
229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
232 .frequency = 150000000,
238 .tx_pu_value = 0x66 /* 0 */,
243 .sparepll = 0x00, /* 0x34 */
244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
247 .frequency = 300000000,
259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
262 .frequency = 600000000,
274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
281 .frequency = 54000000,
293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
296 .frequency = 75000000,
308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
311 .frequency = 150000000,
317 .tx_pu_value = 0x66 /* 0 */,
322 .sparepll = 0x00, /* 0x34 */
323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
326 .frequency = 300000000,
338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
341 .frequency = 600000000,
353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
358 struct tegra_sor_regs {
359 unsigned int head_state0;
360 unsigned int head_state1;
361 unsigned int head_state2;
362 unsigned int head_state3;
363 unsigned int head_state4;
364 unsigned int head_state5;
369 unsigned int dp_padctl0;
370 unsigned int dp_padctl2;
373 struct tegra_sor_soc {
379 const struct tegra_sor_regs *regs;
382 const struct tegra_sor_hdmi_settings *settings;
383 unsigned int num_settings;
390 struct tegra_sor_ops {
392 int (*probe)(struct tegra_sor *sor);
393 int (*remove)(struct tegra_sor *sor);
397 struct host1x_client client;
398 struct tegra_output output;
401 const struct tegra_sor_soc *soc;
406 struct reset_control *rst;
407 struct clk *clk_parent;
408 struct clk *clk_safe;
416 struct drm_dp_aux *aux;
418 struct drm_info_list *debugfs_files;
420 const struct tegra_sor_ops *ops;
421 enum tegra_io_pad pad;
424 struct tegra_sor_hdmi_settings *settings;
425 unsigned int num_settings;
427 struct regulator *avdd_io_supply;
428 struct regulator *vdd_pll_supply;
429 struct regulator *hdmi_supply;
431 struct delayed_work scdc;
434 struct tegra_hda_format format;
437 struct tegra_sor_state {
438 struct drm_connector_state base;
440 unsigned int link_speed;
445 static inline struct tegra_sor_state *
446 to_sor_state(struct drm_connector_state *state)
448 return container_of(state, struct tegra_sor_state, base);
451 struct tegra_sor_config {
464 static inline struct tegra_sor *
465 host1x_client_to_sor(struct host1x_client *client)
467 return container_of(client, struct tegra_sor, client);
470 static inline struct tegra_sor *to_sor(struct tegra_output *output)
472 return container_of(output, struct tegra_sor, output);
475 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
477 u32 value = readl(sor->regs + (offset << 2));
479 trace_sor_readl(sor->dev, offset, value);
484 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
487 trace_sor_writel(sor->dev, offset, value);
488 writel(value, sor->regs + (offset << 2));
491 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
495 clk_disable_unprepare(sor->clk);
497 err = clk_set_parent(sor->clk_out, parent);
501 err = clk_prepare_enable(sor->clk);
508 struct tegra_clk_sor_pad {
510 struct tegra_sor *sor;
513 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
515 return container_of(hw, struct tegra_clk_sor_pad, hw);
518 static const char * const tegra_clk_sor_pad_parents[] = {
519 "pll_d2_out0", "pll_dp"
522 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
524 struct tegra_clk_sor_pad *pad = to_pad(hw);
525 struct tegra_sor *sor = pad->sor;
528 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
529 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
533 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
537 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
541 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
546 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
548 struct tegra_clk_sor_pad *pad = to_pad(hw);
549 struct tegra_sor *sor = pad->sor;
553 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
555 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
556 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
557 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
561 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
562 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
570 static const struct clk_ops tegra_clk_sor_pad_ops = {
571 .set_parent = tegra_clk_sor_pad_set_parent,
572 .get_parent = tegra_clk_sor_pad_get_parent,
575 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
578 struct tegra_clk_sor_pad *pad;
579 struct clk_init_data init;
582 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
584 return ERR_PTR(-ENOMEM);
590 init.parent_names = tegra_clk_sor_pad_parents;
591 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents);
592 init.ops = &tegra_clk_sor_pad_ops;
594 pad->hw.init = &init;
596 clk = devm_clk_register(sor->dev, &pad->hw);
601 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
602 struct drm_dp_link *link)
609 /* setup lane parameters */
610 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
611 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
612 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
613 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
614 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
616 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
617 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
618 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
619 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
620 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
622 value = SOR_LANE_POSTCURSOR_LANE3(0x00) |
623 SOR_LANE_POSTCURSOR_LANE2(0x00) |
624 SOR_LANE_POSTCURSOR_LANE1(0x00) |
625 SOR_LANE_POSTCURSOR_LANE0(0x00);
626 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0);
628 /* disable LVDS mode */
629 tegra_sor_writel(sor, 0, SOR_LVDS);
631 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
632 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
633 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
634 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
635 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
637 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
638 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
639 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
640 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
642 usleep_range(10, 100);
644 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
645 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
646 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
647 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
649 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B);
653 for (i = 0, value = 0; i < link->lanes; i++) {
654 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
655 SOR_DP_TPG_SCRAMBLER_NONE |
656 SOR_DP_TPG_PATTERN_TRAIN1;
657 value = (value << 8) | lane;
660 tegra_sor_writel(sor, value, SOR_DP_TPG);
662 pattern = DP_TRAINING_PATTERN_1;
664 err = drm_dp_aux_train(sor->aux, link, pattern);
668 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
669 value |= SOR_DP_SPARE_SEQ_ENABLE;
670 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
671 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
672 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
674 for (i = 0, value = 0; i < link->lanes; i++) {
675 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
676 SOR_DP_TPG_SCRAMBLER_NONE |
677 SOR_DP_TPG_PATTERN_TRAIN2;
678 value = (value << 8) | lane;
681 tegra_sor_writel(sor, value, SOR_DP_TPG);
683 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
685 err = drm_dp_aux_train(sor->aux, link, pattern);
689 for (i = 0, value = 0; i < link->lanes; i++) {
690 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
691 SOR_DP_TPG_SCRAMBLER_GALIOS |
692 SOR_DP_TPG_PATTERN_NONE;
693 value = (value << 8) | lane;
696 tegra_sor_writel(sor, value, SOR_DP_TPG);
698 pattern = DP_TRAINING_PATTERN_DISABLE;
700 err = drm_dp_aux_train(sor->aux, link, pattern);
707 static void tegra_sor_super_update(struct tegra_sor *sor)
709 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
710 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
711 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
714 static void tegra_sor_update(struct tegra_sor *sor)
716 tegra_sor_writel(sor, 0, SOR_STATE0);
717 tegra_sor_writel(sor, 1, SOR_STATE0);
718 tegra_sor_writel(sor, 0, SOR_STATE0);
721 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
725 value = tegra_sor_readl(sor, SOR_PWM_DIV);
726 value &= ~SOR_PWM_DIV_MASK;
727 value |= 0x400; /* period */
728 tegra_sor_writel(sor, value, SOR_PWM_DIV);
730 value = tegra_sor_readl(sor, SOR_PWM_CTL);
731 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
732 value |= 0x400; /* duty cycle */
733 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
734 value |= SOR_PWM_CTL_TRIGGER;
735 tegra_sor_writel(sor, value, SOR_PWM_CTL);
737 timeout = jiffies + msecs_to_jiffies(timeout);
739 while (time_before(jiffies, timeout)) {
740 value = tegra_sor_readl(sor, SOR_PWM_CTL);
741 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
744 usleep_range(25, 100);
750 static int tegra_sor_attach(struct tegra_sor *sor)
752 unsigned long value, timeout;
754 /* wake up in normal mode */
755 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
756 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
757 value |= SOR_SUPER_STATE_MODE_NORMAL;
758 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
759 tegra_sor_super_update(sor);
762 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
763 value |= SOR_SUPER_STATE_ATTACHED;
764 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
765 tegra_sor_super_update(sor);
767 timeout = jiffies + msecs_to_jiffies(250);
769 while (time_before(jiffies, timeout)) {
770 value = tegra_sor_readl(sor, SOR_TEST);
771 if ((value & SOR_TEST_ATTACHED) != 0)
774 usleep_range(25, 100);
780 static int tegra_sor_wakeup(struct tegra_sor *sor)
782 unsigned long value, timeout;
784 timeout = jiffies + msecs_to_jiffies(250);
786 /* wait for head to wake up */
787 while (time_before(jiffies, timeout)) {
788 value = tegra_sor_readl(sor, SOR_TEST);
789 value &= SOR_TEST_HEAD_MODE_MASK;
791 if (value == SOR_TEST_HEAD_MODE_AWAKE)
794 usleep_range(25, 100);
800 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
804 value = tegra_sor_readl(sor, SOR_PWR);
805 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
806 tegra_sor_writel(sor, value, SOR_PWR);
808 timeout = jiffies + msecs_to_jiffies(timeout);
810 while (time_before(jiffies, timeout)) {
811 value = tegra_sor_readl(sor, SOR_PWR);
812 if ((value & SOR_PWR_TRIGGER) == 0)
815 usleep_range(25, 100);
821 struct tegra_sor_params {
822 /* number of link clocks per line */
823 unsigned int num_clocks;
824 /* ratio between input and output */
826 /* precision factor */
829 unsigned int active_polarity;
830 unsigned int active_count;
831 unsigned int active_frac;
832 unsigned int tu_size;
836 static int tegra_sor_compute_params(struct tegra_sor *sor,
837 struct tegra_sor_params *params,
838 unsigned int tu_size)
840 u64 active_sym, active_count, frac, approx;
841 u32 active_polarity, active_frac = 0;
842 const u64 f = params->precision;
845 active_sym = params->ratio * tu_size;
846 active_count = div_u64(active_sym, f) * f;
847 frac = active_sym - active_count;
850 if (frac >= (f / 2)) {
858 frac = div_u64(f * f, frac); /* 1/fraction */
859 if (frac <= (15 * f)) {
860 active_frac = div_u64(frac, f);
866 active_frac = active_polarity ? 1 : 15;
870 if (active_frac == 1)
873 if (active_polarity == 1) {
875 approx = active_count + (active_frac * (f - 1)) * f;
876 approx = div_u64(approx, active_frac * f);
878 approx = active_count + f;
882 approx = active_count + div_u64(f, active_frac);
884 approx = active_count;
887 error = div_s64(active_sym - approx, tu_size);
888 error *= params->num_clocks;
890 if (error <= 0 && abs(error) < params->error) {
891 params->active_count = div_u64(active_count, f);
892 params->active_polarity = active_polarity;
893 params->active_frac = active_frac;
894 params->error = abs(error);
895 params->tu_size = tu_size;
904 static int tegra_sor_compute_config(struct tegra_sor *sor,
905 const struct drm_display_mode *mode,
906 struct tegra_sor_config *config,
907 struct drm_dp_link *link)
909 const u64 f = 100000, link_rate = link->rate * 1000;
910 const u64 pclk = mode->clock * 1000;
911 u64 input, output, watermark, num;
912 struct tegra_sor_params params;
913 u32 num_syms_per_line;
916 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
919 input = pclk * config->bits_per_pixel;
920 output = link_rate * 8 * link->lanes;
925 memset(¶ms, 0, sizeof(params));
926 params.ratio = div64_u64(input * f, output);
927 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
928 params.precision = f;
929 params.error = 64 * f;
932 for (i = params.tu_size; i >= 32; i--)
933 if (tegra_sor_compute_params(sor, ¶ms, i))
936 if (params.active_frac == 0) {
937 config->active_polarity = 0;
938 config->active_count = params.active_count;
940 if (!params.active_polarity)
941 config->active_count--;
943 config->tu_size = params.tu_size;
944 config->active_frac = 1;
946 config->active_polarity = params.active_polarity;
947 config->active_count = params.active_count;
948 config->active_frac = params.active_frac;
949 config->tu_size = params.tu_size;
953 "polarity: %d active count: %d tu size: %d active frac: %d\n",
954 config->active_polarity, config->active_count,
955 config->tu_size, config->active_frac);
957 watermark = params.ratio * config->tu_size * (f - params.ratio);
958 watermark = div_u64(watermark, f);
960 watermark = div_u64(watermark + params.error, f);
961 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
962 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
965 if (config->watermark > 30) {
966 config->watermark = 30;
968 "unable to compute TU size, forcing watermark to %u\n",
970 } else if (config->watermark > num_syms_per_line) {
971 config->watermark = num_syms_per_line;
972 dev_err(sor->dev, "watermark too high, forcing to %u\n",
976 /* compute the number of symbols per horizontal blanking interval */
977 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
978 config->hblank_symbols = div_u64(num, pclk);
980 if (link->caps.enhanced_framing)
981 config->hblank_symbols -= 3;
983 config->hblank_symbols -= 12 / link->lanes;
985 /* compute the number of symbols per vertical blanking interval */
986 num = (mode->hdisplay - 25) * link_rate;
987 config->vblank_symbols = div_u64(num, pclk);
988 config->vblank_symbols -= 36 / link->lanes + 4;
990 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
991 config->vblank_symbols);
996 static void tegra_sor_apply_config(struct tegra_sor *sor,
997 const struct tegra_sor_config *config)
1001 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1002 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1003 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1004 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1006 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1007 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1008 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1010 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1011 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1013 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1014 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1016 if (config->active_polarity)
1017 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1019 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1021 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1022 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1023 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1025 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1026 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1027 value |= config->hblank_symbols & 0xffff;
1028 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1030 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1031 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1032 value |= config->vblank_symbols & 0xffff;
1033 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1036 static void tegra_sor_mode_set(struct tegra_sor *sor,
1037 const struct drm_display_mode *mode,
1038 struct tegra_sor_state *state)
1040 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1041 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1044 value = tegra_sor_readl(sor, SOR_STATE1);
1045 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1046 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1047 value &= ~SOR_STATE_ASY_OWNER_MASK;
1049 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1050 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1052 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1053 value &= ~SOR_STATE_ASY_HSYNCPOL;
1055 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1056 value |= SOR_STATE_ASY_HSYNCPOL;
1058 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1059 value &= ~SOR_STATE_ASY_VSYNCPOL;
1061 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1062 value |= SOR_STATE_ASY_VSYNCPOL;
1064 switch (state->bpc) {
1066 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1070 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1074 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1078 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1082 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1086 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1090 tegra_sor_writel(sor, value, SOR_STATE1);
1093 * TODO: The video timing programming below doesn't seem to match the
1094 * register definitions.
1097 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1098 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1100 /* sync end = sync width - 1 */
1101 vse = mode->vsync_end - mode->vsync_start - 1;
1102 hse = mode->hsync_end - mode->hsync_start - 1;
1104 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1105 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1107 /* blank end = sync end + back porch */
1108 vbe = vse + (mode->vtotal - mode->vsync_end);
1109 hbe = hse + (mode->htotal - mode->hsync_end);
1111 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1112 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1114 /* blank start = blank end + active */
1115 vbs = vbe + mode->vdisplay;
1116 hbs = hbe + mode->hdisplay;
1118 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1119 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1121 /* XXX interlacing support */
1122 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1125 static int tegra_sor_detach(struct tegra_sor *sor)
1127 unsigned long value, timeout;
1129 /* switch to safe mode */
1130 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1131 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1132 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1133 tegra_sor_super_update(sor);
1135 timeout = jiffies + msecs_to_jiffies(250);
1137 while (time_before(jiffies, timeout)) {
1138 value = tegra_sor_readl(sor, SOR_PWR);
1139 if (value & SOR_PWR_MODE_SAFE)
1143 if ((value & SOR_PWR_MODE_SAFE) == 0)
1147 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1148 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1149 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1150 tegra_sor_super_update(sor);
1153 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1154 value &= ~SOR_SUPER_STATE_ATTACHED;
1155 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1156 tegra_sor_super_update(sor);
1158 timeout = jiffies + msecs_to_jiffies(250);
1160 while (time_before(jiffies, timeout)) {
1161 value = tegra_sor_readl(sor, SOR_TEST);
1162 if ((value & SOR_TEST_ATTACHED) == 0)
1165 usleep_range(25, 100);
1168 if ((value & SOR_TEST_ATTACHED) != 0)
1174 static int tegra_sor_power_down(struct tegra_sor *sor)
1176 unsigned long value, timeout;
1179 value = tegra_sor_readl(sor, SOR_PWR);
1180 value &= ~SOR_PWR_NORMAL_STATE_PU;
1181 value |= SOR_PWR_TRIGGER;
1182 tegra_sor_writel(sor, value, SOR_PWR);
1184 timeout = jiffies + msecs_to_jiffies(250);
1186 while (time_before(jiffies, timeout)) {
1187 value = tegra_sor_readl(sor, SOR_PWR);
1188 if ((value & SOR_PWR_TRIGGER) == 0)
1191 usleep_range(25, 100);
1194 if ((value & SOR_PWR_TRIGGER) != 0)
1197 /* switch to safe parent clock */
1198 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1200 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1204 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1205 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
1206 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
1207 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1209 /* stop lane sequencer */
1210 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
1211 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
1212 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1214 timeout = jiffies + msecs_to_jiffies(250);
1216 while (time_before(jiffies, timeout)) {
1217 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1218 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1221 usleep_range(25, 100);
1224 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
1227 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1228 value |= SOR_PLL2_PORT_POWERDOWN;
1229 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1231 usleep_range(20, 100);
1233 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1234 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1235 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1237 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1238 value |= SOR_PLL2_SEQ_PLLCAPPD;
1239 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1240 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1242 usleep_range(20, 100);
1247 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1251 timeout = jiffies + msecs_to_jiffies(timeout);
1253 while (time_before(jiffies, timeout)) {
1254 value = tegra_sor_readl(sor, SOR_CRCA);
1255 if (value & SOR_CRCA_VALID)
1258 usleep_range(100, 200);
1264 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1266 struct drm_info_node *node = s->private;
1267 struct tegra_sor *sor = node->info_ent->data;
1268 struct drm_crtc *crtc = sor->output.encoder.crtc;
1269 struct drm_device *drm = node->minor->dev;
1273 drm_modeset_lock_all(drm);
1275 if (!crtc || !crtc->state->active) {
1280 value = tegra_sor_readl(sor, SOR_STATE1);
1281 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1282 tegra_sor_writel(sor, value, SOR_STATE1);
1284 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1285 value |= SOR_CRC_CNTRL_ENABLE;
1286 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1288 value = tegra_sor_readl(sor, SOR_TEST);
1289 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1290 tegra_sor_writel(sor, value, SOR_TEST);
1292 err = tegra_sor_crc_wait(sor, 100);
1296 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1297 value = tegra_sor_readl(sor, SOR_CRCB);
1299 seq_printf(s, "%08x\n", value);
1302 drm_modeset_unlock_all(drm);
1306 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1308 static const struct debugfs_reg32 tegra_sor_regs[] = {
1309 DEBUGFS_REG32(SOR_CTXSW),
1310 DEBUGFS_REG32(SOR_SUPER_STATE0),
1311 DEBUGFS_REG32(SOR_SUPER_STATE1),
1312 DEBUGFS_REG32(SOR_STATE0),
1313 DEBUGFS_REG32(SOR_STATE1),
1314 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1315 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1316 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1317 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1318 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1319 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1320 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1321 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1322 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1323 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1324 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1325 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1326 DEBUGFS_REG32(SOR_CRC_CNTRL),
1327 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1328 DEBUGFS_REG32(SOR_CLK_CNTRL),
1329 DEBUGFS_REG32(SOR_CAP),
1330 DEBUGFS_REG32(SOR_PWR),
1331 DEBUGFS_REG32(SOR_TEST),
1332 DEBUGFS_REG32(SOR_PLL0),
1333 DEBUGFS_REG32(SOR_PLL1),
1334 DEBUGFS_REG32(SOR_PLL2),
1335 DEBUGFS_REG32(SOR_PLL3),
1336 DEBUGFS_REG32(SOR_CSTM),
1337 DEBUGFS_REG32(SOR_LVDS),
1338 DEBUGFS_REG32(SOR_CRCA),
1339 DEBUGFS_REG32(SOR_CRCB),
1340 DEBUGFS_REG32(SOR_BLANK),
1341 DEBUGFS_REG32(SOR_SEQ_CTL),
1342 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1343 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1344 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1345 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1346 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1347 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1348 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1349 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1350 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1351 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1352 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1353 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1354 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1355 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1356 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1357 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1358 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1359 DEBUGFS_REG32(SOR_PWM_DIV),
1360 DEBUGFS_REG32(SOR_PWM_CTL),
1361 DEBUGFS_REG32(SOR_VCRC_A0),
1362 DEBUGFS_REG32(SOR_VCRC_A1),
1363 DEBUGFS_REG32(SOR_VCRC_B0),
1364 DEBUGFS_REG32(SOR_VCRC_B1),
1365 DEBUGFS_REG32(SOR_CCRC_A0),
1366 DEBUGFS_REG32(SOR_CCRC_A1),
1367 DEBUGFS_REG32(SOR_CCRC_B0),
1368 DEBUGFS_REG32(SOR_CCRC_B1),
1369 DEBUGFS_REG32(SOR_EDATA_A0),
1370 DEBUGFS_REG32(SOR_EDATA_A1),
1371 DEBUGFS_REG32(SOR_EDATA_B0),
1372 DEBUGFS_REG32(SOR_EDATA_B1),
1373 DEBUGFS_REG32(SOR_COUNT_A0),
1374 DEBUGFS_REG32(SOR_COUNT_A1),
1375 DEBUGFS_REG32(SOR_COUNT_B0),
1376 DEBUGFS_REG32(SOR_COUNT_B1),
1377 DEBUGFS_REG32(SOR_DEBUG_A0),
1378 DEBUGFS_REG32(SOR_DEBUG_A1),
1379 DEBUGFS_REG32(SOR_DEBUG_B0),
1380 DEBUGFS_REG32(SOR_DEBUG_B1),
1381 DEBUGFS_REG32(SOR_TRIG),
1382 DEBUGFS_REG32(SOR_MSCHECK),
1383 DEBUGFS_REG32(SOR_XBAR_CTRL),
1384 DEBUGFS_REG32(SOR_XBAR_POL),
1385 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1386 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1387 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1388 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1389 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1390 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1391 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1392 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1393 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1394 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1395 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1396 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1397 DEBUGFS_REG32(SOR_DP_CONFIG0),
1398 DEBUGFS_REG32(SOR_DP_CONFIG1),
1399 DEBUGFS_REG32(SOR_DP_MN0),
1400 DEBUGFS_REG32(SOR_DP_MN1),
1401 DEBUGFS_REG32(SOR_DP_PADCTL0),
1402 DEBUGFS_REG32(SOR_DP_PADCTL1),
1403 DEBUGFS_REG32(SOR_DP_PADCTL2),
1404 DEBUGFS_REG32(SOR_DP_DEBUG0),
1405 DEBUGFS_REG32(SOR_DP_DEBUG1),
1406 DEBUGFS_REG32(SOR_DP_SPARE0),
1407 DEBUGFS_REG32(SOR_DP_SPARE1),
1408 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1409 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1410 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1411 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1415 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1416 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1417 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1418 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1419 DEBUGFS_REG32(SOR_DP_TPG),
1420 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1421 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1422 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1423 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1426 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1428 struct drm_info_node *node = s->private;
1429 struct tegra_sor *sor = node->info_ent->data;
1430 struct drm_crtc *crtc = sor->output.encoder.crtc;
1431 struct drm_device *drm = node->minor->dev;
1435 drm_modeset_lock_all(drm);
1437 if (!crtc || !crtc->state->active) {
1442 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1443 unsigned int offset = tegra_sor_regs[i].offset;
1445 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1446 offset, tegra_sor_readl(sor, offset));
1450 drm_modeset_unlock_all(drm);
1454 static const struct drm_info_list debugfs_files[] = {
1455 { "crc", tegra_sor_show_crc, 0, NULL },
1456 { "regs", tegra_sor_show_regs, 0, NULL },
1459 static int tegra_sor_late_register(struct drm_connector *connector)
1461 struct tegra_output *output = connector_to_output(connector);
1462 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1463 struct drm_minor *minor = connector->dev->primary;
1464 struct dentry *root = connector->debugfs_entry;
1465 struct tegra_sor *sor = to_sor(output);
1468 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1470 if (!sor->debugfs_files)
1473 for (i = 0; i < count; i++)
1474 sor->debugfs_files[i].data = sor;
1476 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1483 kfree(sor->debugfs_files);
1484 sor->debugfs_files = NULL;
1489 static void tegra_sor_early_unregister(struct drm_connector *connector)
1491 struct tegra_output *output = connector_to_output(connector);
1492 unsigned int count = ARRAY_SIZE(debugfs_files);
1493 struct tegra_sor *sor = to_sor(output);
1495 drm_debugfs_remove_files(sor->debugfs_files, count,
1496 connector->dev->primary);
1497 kfree(sor->debugfs_files);
1498 sor->debugfs_files = NULL;
1501 static void tegra_sor_connector_reset(struct drm_connector *connector)
1503 struct tegra_sor_state *state;
1505 state = kzalloc(sizeof(*state), GFP_KERNEL);
1509 if (connector->state) {
1510 __drm_atomic_helper_connector_destroy_state(connector->state);
1511 kfree(connector->state);
1514 __drm_atomic_helper_connector_reset(connector, &state->base);
1517 static enum drm_connector_status
1518 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1520 struct tegra_output *output = connector_to_output(connector);
1521 struct tegra_sor *sor = to_sor(output);
1524 return drm_dp_aux_detect(sor->aux);
1526 return tegra_output_connector_detect(connector, force);
1529 static struct drm_connector_state *
1530 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1532 struct tegra_sor_state *state = to_sor_state(connector->state);
1533 struct tegra_sor_state *copy;
1535 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1539 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1544 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1545 .reset = tegra_sor_connector_reset,
1546 .detect = tegra_sor_connector_detect,
1547 .fill_modes = drm_helper_probe_single_connector_modes,
1548 .destroy = tegra_output_connector_destroy,
1549 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1550 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1551 .late_register = tegra_sor_late_register,
1552 .early_unregister = tegra_sor_early_unregister,
1555 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1557 struct tegra_output *output = connector_to_output(connector);
1558 struct tegra_sor *sor = to_sor(output);
1562 drm_dp_aux_enable(sor->aux);
1564 err = tegra_output_connector_get_modes(connector);
1567 drm_dp_aux_disable(sor->aux);
1572 static enum drm_mode_status
1573 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1574 struct drm_display_mode *mode)
1579 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1580 .get_modes = tegra_sor_connector_get_modes,
1581 .mode_valid = tegra_sor_connector_mode_valid,
1584 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1585 .destroy = tegra_output_encoder_destroy,
1588 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1590 struct tegra_output *output = encoder_to_output(encoder);
1591 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1592 struct tegra_sor *sor = to_sor(output);
1597 drm_panel_disable(output->panel);
1599 err = tegra_sor_detach(sor);
1601 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1603 tegra_sor_writel(sor, 0, SOR_STATE1);
1604 tegra_sor_update(sor);
1607 * The following accesses registers of the display controller, so make
1608 * sure it's only executed when the output is attached to one.
1611 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1612 value &= ~SOR_ENABLE(0);
1613 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1615 tegra_dc_commit(dc);
1618 err = tegra_sor_power_down(sor);
1620 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1623 err = drm_dp_aux_disable(sor->aux);
1625 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1628 err = tegra_io_pad_power_disable(sor->pad);
1630 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1633 drm_panel_unprepare(output->panel);
1635 pm_runtime_put(sor->dev);
1639 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1640 unsigned int *value)
1642 unsigned int hfp, hsw, hbp, a = 0, b;
1644 hfp = mode->hsync_start - mode->hdisplay;
1645 hsw = mode->hsync_end - mode->hsync_start;
1646 hbp = mode->htotal - mode->hsync_end;
1648 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1652 pr_info("a: %u, b: %u\n", a, b);
1653 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1655 if (a + hsw + hbp <= 11) {
1656 a = 1 + 11 - hsw - hbp;
1657 pr_info("a: %u\n", a);
1666 if (mode->hdisplay < 16)
1680 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1682 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1683 struct tegra_output *output = encoder_to_output(encoder);
1684 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1685 struct tegra_sor *sor = to_sor(output);
1686 struct tegra_sor_config config;
1687 struct tegra_sor_state *state;
1688 struct drm_dp_link link;
1694 state = to_sor_state(output->connector.state);
1696 pm_runtime_get_sync(sor->dev);
1699 drm_panel_prepare(output->panel);
1701 err = drm_dp_aux_enable(sor->aux);
1703 dev_err(sor->dev, "failed to enable DP: %d\n", err);
1705 err = drm_dp_link_probe(sor->aux, &link);
1707 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1711 /* switch to safe parent clock */
1712 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1714 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1716 memset(&config, 0, sizeof(config));
1717 config.bits_per_pixel = state->bpc * 3;
1719 err = tegra_sor_compute_config(sor, mode, &config, &link);
1721 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
1723 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1724 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1725 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1726 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1728 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1729 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1730 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1731 usleep_range(20, 100);
1733 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1734 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1735 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1737 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST |
1738 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT;
1739 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1741 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1742 value |= SOR_PLL2_SEQ_PLLCAPPD;
1743 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1744 value |= SOR_PLL2_LVDS_ENABLE;
1745 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1747 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM;
1748 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
1751 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1752 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0)
1755 usleep_range(250, 1000);
1758 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1759 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1760 value &= ~SOR_PLL2_PORT_POWERDOWN;
1761 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1767 /* set safe link bandwidth (1.62 Gbps) */
1768 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1769 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1770 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
1771 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1774 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1775 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN |
1776 SOR_PLL2_BANDGAP_POWERDOWN;
1777 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1779 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1780 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1781 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1783 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1784 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
1785 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1788 err = tegra_io_pad_power_enable(sor->pad);
1790 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
1792 usleep_range(5, 100);
1795 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1796 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1797 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1799 usleep_range(20, 100);
1802 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1803 value &= ~SOR_PLL0_VCOPD;
1804 value &= ~SOR_PLL0_PWR;
1805 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1807 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1808 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1809 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1811 usleep_range(200, 1000);
1814 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1815 value &= ~SOR_PLL2_PORT_POWERDOWN;
1816 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1818 /* XXX not in TRM */
1819 for (value = 0, i = 0; i < 5; i++)
1820 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1821 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1823 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1824 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1826 /* switch to DP parent clock */
1827 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1829 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1831 /* power DP lanes */
1832 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1834 if (link.lanes <= 2)
1835 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
1837 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
1839 if (link.lanes <= 1)
1840 value &= ~SOR_DP_PADCTL_PD_TXD_1;
1842 value |= SOR_DP_PADCTL_PD_TXD_1;
1844 if (link.lanes == 0)
1845 value &= ~SOR_DP_PADCTL_PD_TXD_0;
1847 value |= SOR_DP_PADCTL_PD_TXD_0;
1849 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1851 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1852 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1853 value |= SOR_DP_LINKCTL_LANE_COUNT(link.lanes);
1854 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1856 /* start lane sequencer */
1857 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
1858 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1859 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1862 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1863 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1866 usleep_range(250, 1000);
1869 /* set link bandwidth */
1870 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1871 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1872 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1873 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1875 tegra_sor_apply_config(sor, &config);
1878 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1879 value |= SOR_DP_LINKCTL_ENABLE;
1880 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1881 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1883 for (i = 0, value = 0; i < 4; i++) {
1884 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1885 SOR_DP_TPG_SCRAMBLER_GALIOS |
1886 SOR_DP_TPG_PATTERN_NONE;
1887 value = (value << 8) | lane;
1890 tegra_sor_writel(sor, value, SOR_DP_TPG);
1892 /* enable pad calibration logic */
1893 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
1894 value |= SOR_DP_PADCTL_PAD_CAL_PD;
1895 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
1897 err = drm_dp_link_probe(sor->aux, &link);
1899 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1901 err = drm_dp_link_power_up(sor->aux, &link);
1903 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
1905 err = drm_dp_link_configure(sor->aux, &link);
1907 dev_err(sor->dev, "failed to configure eDP link: %d\n", err);
1909 rate = drm_dp_link_rate_to_bw_code(link.rate);
1912 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1913 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1914 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1915 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1917 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1918 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1919 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1921 if (link.caps.enhanced_framing)
1922 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1924 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1926 /* disable training pattern generator */
1928 for (i = 0; i < link.lanes; i++) {
1929 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1930 SOR_DP_TPG_SCRAMBLER_GALIOS |
1931 SOR_DP_TPG_PATTERN_NONE;
1932 value = (value << 8) | lane;
1935 tegra_sor_writel(sor, value, SOR_DP_TPG);
1937 err = tegra_sor_dp_train_fast(sor, &link);
1939 dev_err(sor->dev, "DP fast link training failed: %d\n", err);
1941 dev_dbg(sor->dev, "fast link training succeeded\n");
1943 err = tegra_sor_power_up(sor, 250);
1945 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1947 /* CSTM (LVDS, link A/B, upper) */
1948 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1950 tegra_sor_writel(sor, value, SOR_CSTM);
1952 /* use DP-A protocol */
1953 value = tegra_sor_readl(sor, SOR_STATE1);
1954 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1955 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1956 tegra_sor_writel(sor, value, SOR_STATE1);
1958 tegra_sor_mode_set(sor, mode, state);
1961 err = tegra_sor_setup_pwm(sor, 250);
1963 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1965 tegra_sor_update(sor);
1967 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1968 value |= SOR_ENABLE(0);
1969 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1971 tegra_dc_commit(dc);
1973 err = tegra_sor_attach(sor);
1975 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1977 err = tegra_sor_wakeup(sor);
1979 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1982 drm_panel_enable(output->panel);
1986 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1987 struct drm_crtc_state *crtc_state,
1988 struct drm_connector_state *conn_state)
1990 struct tegra_output *output = encoder_to_output(encoder);
1991 struct tegra_sor_state *state = to_sor_state(conn_state);
1992 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1993 unsigned long pclk = crtc_state->mode.clock * 1000;
1994 struct tegra_sor *sor = to_sor(output);
1995 struct drm_display_info *info;
1998 info = &output->connector.display_info;
2001 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2002 * the pixel clock must be corrected accordingly.
2004 if (pclk >= 340000000) {
2005 state->link_speed = 20;
2006 state->pclk = pclk / 2;
2008 state->link_speed = 10;
2012 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2015 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2019 switch (info->bpc) {
2022 state->bpc = info->bpc;
2026 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2034 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2035 .disable = tegra_sor_edp_disable,
2036 .enable = tegra_sor_edp_enable,
2037 .atomic_check = tegra_sor_encoder_atomic_check,
2040 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2045 for (i = size; i > 0; i--)
2046 value = (value << 8) | ptr[i - 1];
2051 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2052 const void *data, size_t size)
2054 const u8 *ptr = data;
2055 unsigned long offset;
2060 case HDMI_INFOFRAME_TYPE_AVI:
2061 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2064 case HDMI_INFOFRAME_TYPE_AUDIO:
2065 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2068 case HDMI_INFOFRAME_TYPE_VENDOR:
2069 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2073 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2078 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2079 INFOFRAME_HEADER_VERSION(ptr[1]) |
2080 INFOFRAME_HEADER_LEN(ptr[2]);
2081 tegra_sor_writel(sor, value, offset);
2085 * Each subpack contains 7 bytes, divided into:
2086 * - subpack_low: bytes 0 - 3
2087 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2089 for (i = 3, j = 0; i < size; i += 7, j += 8) {
2090 size_t rem = size - i, num = min_t(size_t, rem, 4);
2092 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2093 tegra_sor_writel(sor, value, offset++);
2095 num = min_t(size_t, rem - num, 3);
2097 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2098 tegra_sor_writel(sor, value, offset++);
2103 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2104 const struct drm_display_mode *mode)
2106 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2107 struct hdmi_avi_infoframe frame;
2111 /* disable AVI infoframe */
2112 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2113 value &= ~INFOFRAME_CTRL_SINGLE;
2114 value &= ~INFOFRAME_CTRL_OTHER;
2115 value &= ~INFOFRAME_CTRL_ENABLE;
2116 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2118 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2119 &sor->output.connector, mode);
2121 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2125 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2127 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2131 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2133 /* enable AVI infoframe */
2134 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2135 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2136 value |= INFOFRAME_CTRL_ENABLE;
2137 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2142 static void tegra_sor_write_eld(struct tegra_sor *sor)
2144 size_t length = drm_eld_size(sor->output.connector.eld), i;
2146 for (i = 0; i < length; i++)
2147 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2148 SOR_AUDIO_HDA_ELD_BUFWR);
2151 * The HDA codec will always report an ELD buffer size of 96 bytes and
2152 * the HDA codec driver will check that each byte read from the buffer
2153 * is valid. Therefore every byte must be written, even if no 96 bytes
2154 * were parsed from EDID.
2156 for (i = length; i < 96; i++)
2157 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2160 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2165 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2166 * is used for interoperability between the HDA codec driver and the
2169 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2170 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2171 tegra_sor_writel(sor, value, SOR_INT_MASK);
2173 tegra_sor_write_eld(sor);
2175 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2176 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2179 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2181 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2182 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2183 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2186 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2188 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2189 struct hdmi_audio_infoframe frame;
2193 err = hdmi_audio_infoframe_init(&frame);
2195 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2199 frame.channels = sor->format.channels;
2201 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2203 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2207 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2209 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2210 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2211 value |= INFOFRAME_CTRL_ENABLE;
2212 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2217 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2221 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2223 /* select HDA audio input */
2224 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2225 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2227 /* inject null samples */
2228 if (sor->format.channels != 2)
2229 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2231 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2233 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2235 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2237 /* enable advertising HBR capability */
2238 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2240 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2242 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2243 SOR_HDMI_SPARE_CTS_RESET(1) |
2244 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2245 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2248 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2249 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2251 /* allow packet to be sent */
2252 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2253 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2255 /* reset N counter and enable lookup */
2256 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2257 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2259 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2260 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2261 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2263 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2264 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2266 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2267 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2269 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2270 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2272 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2273 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2274 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2276 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2277 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2278 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2280 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2281 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2282 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2284 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2285 value &= ~SOR_HDMI_AUDIO_N_RESET;
2286 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2288 tegra_sor_hdmi_enable_audio_infoframe(sor);
2291 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2295 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2296 value &= ~INFOFRAME_CTRL_ENABLE;
2297 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2300 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2302 tegra_sor_hdmi_disable_audio_infoframe(sor);
2305 static struct tegra_sor_hdmi_settings *
2306 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2310 for (i = 0; i < sor->num_settings; i++)
2311 if (frequency <= sor->settings[i].frequency)
2312 return &sor->settings[i];
2317 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2321 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2322 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2323 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2324 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2327 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2329 struct i2c_adapter *ddc = sor->output.ddc;
2331 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2332 drm_scdc_set_scrambling(ddc, false);
2334 tegra_sor_hdmi_disable_scrambling(sor);
2337 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2339 if (sor->scdc_enabled) {
2340 cancel_delayed_work_sync(&sor->scdc);
2341 tegra_sor_hdmi_scdc_disable(sor);
2345 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2349 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2350 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2351 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2352 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2355 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2357 struct i2c_adapter *ddc = sor->output.ddc;
2359 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2360 drm_scdc_set_scrambling(ddc, true);
2362 tegra_sor_hdmi_enable_scrambling(sor);
2365 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2367 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2368 struct i2c_adapter *ddc = sor->output.ddc;
2370 if (!drm_scdc_get_scrambling_status(ddc)) {
2371 DRM_DEBUG_KMS("SCDC not scrambled\n");
2372 tegra_sor_hdmi_scdc_enable(sor);
2375 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2378 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2380 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2381 struct drm_display_mode *mode;
2383 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2385 if (mode->clock >= 340000 && scdc->supported) {
2386 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2387 tegra_sor_hdmi_scdc_enable(sor);
2388 sor->scdc_enabled = true;
2392 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2394 struct tegra_output *output = encoder_to_output(encoder);
2395 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2396 struct tegra_sor *sor = to_sor(output);
2400 tegra_sor_audio_unprepare(sor);
2401 tegra_sor_hdmi_scdc_stop(sor);
2403 err = tegra_sor_detach(sor);
2405 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2407 tegra_sor_writel(sor, 0, SOR_STATE1);
2408 tegra_sor_update(sor);
2410 /* disable display to SOR clock */
2411 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2413 if (!sor->soc->has_nvdisplay)
2414 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2416 value &= ~SOR_ENABLE(sor->index);
2418 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2420 tegra_dc_commit(dc);
2422 err = tegra_sor_power_down(sor);
2424 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2426 err = tegra_io_pad_power_disable(sor->pad);
2428 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2430 pm_runtime_put(sor->dev);
2433 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2435 struct tegra_output *output = encoder_to_output(encoder);
2436 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2437 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2438 struct tegra_sor_hdmi_settings *settings;
2439 struct tegra_sor *sor = to_sor(output);
2440 struct tegra_sor_state *state;
2441 struct drm_display_mode *mode;
2442 unsigned long rate, pclk;
2443 unsigned int div, i;
2447 state = to_sor_state(output->connector.state);
2448 mode = &encoder->crtc->state->adjusted_mode;
2449 pclk = mode->clock * 1000;
2451 pm_runtime_get_sync(sor->dev);
2453 /* switch to safe parent clock */
2454 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2456 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2460 div = clk_get_rate(sor->clk) / 1000000 * 4;
2462 err = tegra_io_pad_power_enable(sor->pad);
2464 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2466 usleep_range(20, 100);
2468 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2469 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2470 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2472 usleep_range(20, 100);
2474 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2475 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2476 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2478 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2479 value &= ~SOR_PLL0_VCOPD;
2480 value &= ~SOR_PLL0_PWR;
2481 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2483 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2484 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2485 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2487 usleep_range(200, 400);
2489 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2490 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2491 value &= ~SOR_PLL2_PORT_POWERDOWN;
2492 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2494 usleep_range(20, 100);
2496 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2497 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2498 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2499 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2502 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2503 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2506 usleep_range(250, 1000);
2509 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2510 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2511 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2514 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2515 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2518 usleep_range(250, 1000);
2521 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2522 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2523 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2525 if (mode->clock < 340000) {
2526 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2527 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2529 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2530 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2533 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2534 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2536 /* SOR pad PLL stabilization time */
2537 usleep_range(250, 1000);
2539 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2540 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2541 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2542 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2544 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2545 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2546 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2547 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2548 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2549 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2551 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2552 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2553 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2555 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2556 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2557 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2558 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2560 if (!sor->soc->has_nvdisplay) {
2561 /* program the reference clock */
2562 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2563 tegra_sor_writel(sor, value, SOR_REFCLK);
2566 /* XXX not in TRM */
2567 for (value = 0, i = 0; i < 5; i++)
2568 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2569 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2571 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2572 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2574 /* switch to parent clock */
2575 err = clk_set_parent(sor->clk, sor->clk_parent);
2577 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2581 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2583 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2587 /* adjust clock rate for HDMI 2.0 modes */
2588 rate = clk_get_rate(sor->clk_parent);
2590 if (mode->clock >= 340000)
2593 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2595 clk_set_rate(sor->clk, rate);
2597 if (!sor->soc->has_nvdisplay) {
2598 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2600 /* XXX is this the proper check? */
2601 if (mode->clock < 75000)
2602 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2604 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2607 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2609 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2610 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2611 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2613 if (!dc->soc->has_nvdisplay) {
2614 /* H_PULSE2 setup */
2615 pulse_start = h_ref_to_sync +
2616 (mode->hsync_end - mode->hsync_start) +
2617 (mode->htotal - mode->hsync_end) - 10;
2619 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2620 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2621 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2623 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2624 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2626 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2627 value |= H_PULSE2_ENABLE;
2628 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2631 /* infoframe setup */
2632 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2634 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2636 /* XXX HDMI audio support not implemented yet */
2637 tegra_sor_hdmi_disable_audio_infoframe(sor);
2639 /* use single TMDS protocol */
2640 value = tegra_sor_readl(sor, SOR_STATE1);
2641 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2642 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2643 tegra_sor_writel(sor, value, SOR_STATE1);
2645 /* power up pad calibration */
2646 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2647 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2648 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2650 /* production settings */
2651 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2653 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2654 mode->clock * 1000);
2658 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2659 value &= ~SOR_PLL0_ICHPMP_MASK;
2660 value &= ~SOR_PLL0_FILTER_MASK;
2661 value &= ~SOR_PLL0_VCOCAP_MASK;
2662 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2663 value |= SOR_PLL0_FILTER(settings->filter);
2664 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2665 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2667 /* XXX not in TRM */
2668 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2669 value &= ~SOR_PLL1_LOADADJ_MASK;
2670 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2671 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2672 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2673 value |= SOR_PLL1_TMDS_TERM;
2674 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2676 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2677 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2678 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2679 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2680 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2681 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2682 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2683 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2684 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2685 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2687 value = settings->drive_current[3] << 24 |
2688 settings->drive_current[2] << 16 |
2689 settings->drive_current[1] << 8 |
2690 settings->drive_current[0] << 0;
2691 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2693 value = settings->preemphasis[3] << 24 |
2694 settings->preemphasis[2] << 16 |
2695 settings->preemphasis[1] << 8 |
2696 settings->preemphasis[0] << 0;
2697 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2699 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2700 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2701 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2702 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2703 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2706 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2707 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2708 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2710 /* power down pad calibration */
2711 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2712 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2713 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2715 if (!dc->soc->has_nvdisplay) {
2716 /* miscellaneous display controller settings */
2717 value = VSYNC_H_POSITION(1);
2718 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2721 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2722 value &= ~DITHER_CONTROL_MASK;
2723 value &= ~BASE_COLOR_SIZE_MASK;
2725 switch (state->bpc) {
2727 value |= BASE_COLOR_SIZE_666;
2731 value |= BASE_COLOR_SIZE_888;
2735 value |= BASE_COLOR_SIZE_101010;
2739 value |= BASE_COLOR_SIZE_121212;
2743 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2744 value |= BASE_COLOR_SIZE_888;
2748 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2750 /* XXX set display head owner */
2751 value = tegra_sor_readl(sor, SOR_STATE1);
2752 value &= ~SOR_STATE_ASY_OWNER_MASK;
2753 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2754 tegra_sor_writel(sor, value, SOR_STATE1);
2756 err = tegra_sor_power_up(sor, 250);
2758 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2760 /* configure dynamic range of output */
2761 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2762 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2763 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2764 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2766 /* configure colorspace */
2767 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2768 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2769 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2770 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2772 tegra_sor_mode_set(sor, mode, state);
2774 tegra_sor_update(sor);
2776 /* program preamble timing in SOR (XXX) */
2777 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2778 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2779 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2781 err = tegra_sor_attach(sor);
2783 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2785 /* enable display to SOR clock and generate HDMI preamble */
2786 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2788 if (!sor->soc->has_nvdisplay)
2789 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2791 value |= SOR_ENABLE(sor->index);
2793 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2795 if (dc->soc->has_nvdisplay) {
2796 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2797 value &= ~PROTOCOL_MASK;
2798 value |= PROTOCOL_SINGLE_TMDS_A;
2799 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2802 tegra_dc_commit(dc);
2804 err = tegra_sor_wakeup(sor);
2806 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2808 tegra_sor_hdmi_scdc_start(sor);
2809 tegra_sor_audio_prepare(sor);
2812 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2813 .disable = tegra_sor_hdmi_disable,
2814 .enable = tegra_sor_hdmi_enable,
2815 .atomic_check = tegra_sor_encoder_atomic_check,
2818 static int tegra_sor_init(struct host1x_client *client)
2820 struct drm_device *drm = dev_get_drvdata(client->parent);
2821 const struct drm_encoder_helper_funcs *helpers = NULL;
2822 struct tegra_sor *sor = host1x_client_to_sor(client);
2823 int connector = DRM_MODE_CONNECTOR_Unknown;
2824 int encoder = DRM_MODE_ENCODER_NONE;
2828 if (sor->soc->supports_hdmi) {
2829 connector = DRM_MODE_CONNECTOR_HDMIA;
2830 encoder = DRM_MODE_ENCODER_TMDS;
2831 helpers = &tegra_sor_hdmi_helpers;
2832 } else if (sor->soc->supports_lvds) {
2833 connector = DRM_MODE_CONNECTOR_LVDS;
2834 encoder = DRM_MODE_ENCODER_LVDS;
2837 if (sor->soc->supports_edp) {
2838 connector = DRM_MODE_CONNECTOR_eDP;
2839 encoder = DRM_MODE_ENCODER_TMDS;
2840 helpers = &tegra_sor_edp_helpers;
2841 } else if (sor->soc->supports_dp) {
2842 connector = DRM_MODE_CONNECTOR_DisplayPort;
2843 encoder = DRM_MODE_ENCODER_TMDS;
2847 sor->output.dev = sor->dev;
2849 drm_connector_init(drm, &sor->output.connector,
2850 &tegra_sor_connector_funcs,
2852 drm_connector_helper_add(&sor->output.connector,
2853 &tegra_sor_connector_helper_funcs);
2854 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
2856 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
2858 drm_encoder_helper_add(&sor->output.encoder, helpers);
2860 drm_connector_attach_encoder(&sor->output.connector,
2861 &sor->output.encoder);
2862 drm_connector_register(&sor->output.connector);
2864 err = tegra_output_init(drm, &sor->output);
2866 dev_err(client->dev, "failed to initialize output: %d\n", err);
2870 tegra_output_find_possible_crtcs(&sor->output, drm);
2873 err = drm_dp_aux_attach(sor->aux, &sor->output);
2875 dev_err(sor->dev, "failed to attach DP: %d\n", err);
2881 * XXX: Remove this reset once proper hand-over from firmware to
2882 * kernel is possible.
2885 err = reset_control_acquire(sor->rst);
2887 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
2892 err = reset_control_assert(sor->rst);
2894 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
2900 err = clk_prepare_enable(sor->clk);
2902 dev_err(sor->dev, "failed to enable clock: %d\n", err);
2906 usleep_range(1000, 3000);
2909 err = reset_control_deassert(sor->rst);
2911 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
2916 reset_control_release(sor->rst);
2919 err = clk_prepare_enable(sor->clk_safe);
2923 err = clk_prepare_enable(sor->clk_dp);
2930 static int tegra_sor_exit(struct host1x_client *client)
2932 struct tegra_sor *sor = host1x_client_to_sor(client);
2935 tegra_output_exit(&sor->output);
2938 err = drm_dp_aux_detach(sor->aux);
2940 dev_err(sor->dev, "failed to detach DP: %d\n", err);
2945 clk_disable_unprepare(sor->clk_safe);
2946 clk_disable_unprepare(sor->clk_dp);
2947 clk_disable_unprepare(sor->clk);
2952 static const struct host1x_client_ops sor_client_ops = {
2953 .init = tegra_sor_init,
2954 .exit = tegra_sor_exit,
2957 static const struct tegra_sor_ops tegra_sor_edp_ops = {
2961 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2965 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
2966 if (IS_ERR(sor->avdd_io_supply)) {
2967 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2968 PTR_ERR(sor->avdd_io_supply));
2969 return PTR_ERR(sor->avdd_io_supply);
2972 err = regulator_enable(sor->avdd_io_supply);
2974 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2979 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
2980 if (IS_ERR(sor->vdd_pll_supply)) {
2981 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2982 PTR_ERR(sor->vdd_pll_supply));
2983 return PTR_ERR(sor->vdd_pll_supply);
2986 err = regulator_enable(sor->vdd_pll_supply);
2988 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2993 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2994 if (IS_ERR(sor->hdmi_supply)) {
2995 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2996 PTR_ERR(sor->hdmi_supply));
2997 return PTR_ERR(sor->hdmi_supply);
3000 err = regulator_enable(sor->hdmi_supply);
3002 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3006 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3011 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3013 regulator_disable(sor->hdmi_supply);
3014 regulator_disable(sor->vdd_pll_supply);
3015 regulator_disable(sor->avdd_io_supply);
3020 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3022 .probe = tegra_sor_hdmi_probe,
3023 .remove = tegra_sor_hdmi_remove,
3026 static const u8 tegra124_sor_xbar_cfg[5] = {
3030 static const struct tegra_sor_regs tegra124_sor_regs = {
3031 .head_state0 = 0x05,
3032 .head_state1 = 0x07,
3033 .head_state2 = 0x09,
3034 .head_state3 = 0x0b,
3035 .head_state4 = 0x0d,
3036 .head_state5 = 0x0f,
3045 static const struct tegra_sor_soc tegra124_sor = {
3046 .supports_edp = true,
3047 .supports_lvds = true,
3048 .supports_hdmi = false,
3049 .supports_dp = false,
3050 .regs = &tegra124_sor_regs,
3051 .has_nvdisplay = false,
3052 .xbar_cfg = tegra124_sor_xbar_cfg,
3055 static const struct tegra_sor_regs tegra210_sor_regs = {
3056 .head_state0 = 0x05,
3057 .head_state1 = 0x07,
3058 .head_state2 = 0x09,
3059 .head_state3 = 0x0b,
3060 .head_state4 = 0x0d,
3061 .head_state5 = 0x0f,
3070 static const struct tegra_sor_soc tegra210_sor = {
3071 .supports_edp = true,
3072 .supports_lvds = false,
3073 .supports_hdmi = false,
3074 .supports_dp = false,
3075 .regs = &tegra210_sor_regs,
3076 .has_nvdisplay = false,
3077 .xbar_cfg = tegra124_sor_xbar_cfg,
3080 static const u8 tegra210_sor_xbar_cfg[5] = {
3084 static const struct tegra_sor_soc tegra210_sor1 = {
3085 .supports_edp = false,
3086 .supports_lvds = false,
3087 .supports_hdmi = true,
3088 .supports_dp = true,
3090 .regs = &tegra210_sor_regs,
3091 .has_nvdisplay = false,
3093 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3094 .settings = tegra210_sor_hdmi_defaults,
3096 .xbar_cfg = tegra210_sor_xbar_cfg,
3099 static const struct tegra_sor_regs tegra186_sor_regs = {
3100 .head_state0 = 0x151,
3101 .head_state1 = 0x154,
3102 .head_state2 = 0x157,
3103 .head_state3 = 0x15a,
3104 .head_state4 = 0x15d,
3105 .head_state5 = 0x160,
3110 .dp_padctl0 = 0x168,
3111 .dp_padctl2 = 0x16a,
3114 static const struct tegra_sor_soc tegra186_sor = {
3115 .supports_edp = false,
3116 .supports_lvds = false,
3117 .supports_hdmi = false,
3118 .supports_dp = true,
3120 .regs = &tegra186_sor_regs,
3121 .has_nvdisplay = true,
3123 .xbar_cfg = tegra124_sor_xbar_cfg,
3126 static const struct tegra_sor_soc tegra186_sor1 = {
3127 .supports_edp = false,
3128 .supports_lvds = false,
3129 .supports_hdmi = true,
3130 .supports_dp = true,
3132 .regs = &tegra186_sor_regs,
3133 .has_nvdisplay = true,
3135 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3136 .settings = tegra186_sor_hdmi_defaults,
3138 .xbar_cfg = tegra124_sor_xbar_cfg,
3141 static const struct tegra_sor_regs tegra194_sor_regs = {
3142 .head_state0 = 0x151,
3143 .head_state1 = 0x155,
3144 .head_state2 = 0x159,
3145 .head_state3 = 0x15d,
3146 .head_state4 = 0x161,
3147 .head_state5 = 0x165,
3152 .dp_padctl0 = 0x16e,
3153 .dp_padctl2 = 0x16f,
3156 static const struct tegra_sor_soc tegra194_sor = {
3157 .supports_edp = true,
3158 .supports_lvds = false,
3159 .supports_hdmi = true,
3160 .supports_dp = true,
3162 .regs = &tegra194_sor_regs,
3163 .has_nvdisplay = true,
3165 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3166 .settings = tegra194_sor_hdmi_defaults,
3168 .xbar_cfg = tegra210_sor_xbar_cfg,
3171 static const struct of_device_id tegra_sor_of_match[] = {
3172 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3173 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
3174 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3175 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3176 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3177 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3180 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3182 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3184 struct device_node *np = sor->dev->of_node;
3190 if (sor->soc->has_nvdisplay) {
3191 err = of_property_read_u32(np, "nvidia,interface", &value);
3198 * override the default that we already set for Tegra210 and
3201 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3204 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3206 /* fall back to default per-SoC XBAR configuration */
3207 for (i = 0; i < 5; i++)
3208 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3210 /* copy cells to SOR XBAR configuration */
3211 for (i = 0; i < 5; i++)
3212 sor->xbar_cfg[i] = xbar_cfg[i];
3218 static irqreturn_t tegra_sor_irq(int irq, void *data)
3220 struct tegra_sor *sor = data;
3223 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3224 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3226 if (value & SOR_INT_CODEC_SCRATCH0) {
3227 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3229 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3230 unsigned int format;
3232 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3234 tegra_hda_parse_format(format, &sor->format);
3236 tegra_sor_hdmi_audio_enable(sor);
3238 tegra_sor_hdmi_audio_disable(sor);
3245 static int tegra_sor_probe(struct platform_device *pdev)
3247 struct device_node *np;
3248 struct tegra_sor *sor;
3249 struct resource *regs;
3252 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3256 sor->soc = of_device_get_match_data(&pdev->dev);
3257 sor->output.dev = sor->dev = &pdev->dev;
3259 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3260 sor->soc->num_settings *
3261 sizeof(*sor->settings),
3266 sor->num_settings = sor->soc->num_settings;
3268 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3270 sor->aux = drm_dp_aux_find_by_of_node(np);
3274 return -EPROBE_DEFER;
3278 if (sor->soc->supports_hdmi) {
3279 sor->ops = &tegra_sor_hdmi_ops;
3280 sor->pad = TEGRA_IO_PAD_HDMI;
3281 } else if (sor->soc->supports_lvds) {
3282 dev_err(&pdev->dev, "LVDS not supported yet\n");
3285 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3289 if (sor->soc->supports_edp) {
3290 sor->ops = &tegra_sor_edp_ops;
3291 sor->pad = TEGRA_IO_PAD_LVDS;
3292 } else if (sor->soc->supports_dp) {
3293 dev_err(&pdev->dev, "DisplayPort not supported yet\n");
3296 dev_err(&pdev->dev, "unknown (DP) support\n");
3301 err = tegra_sor_parse_dt(sor);
3305 err = tegra_output_probe(&sor->output);
3307 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3311 if (sor->ops && sor->ops->probe) {
3312 err = sor->ops->probe(sor);
3314 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3315 sor->ops->name, err);
3320 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3321 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3322 if (IS_ERR(sor->regs)) {
3323 err = PTR_ERR(sor->regs);
3327 err = platform_get_irq(pdev, 0);
3329 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3335 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3336 dev_name(sor->dev), sor);
3338 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3342 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3343 if (IS_ERR(sor->rst)) {
3344 err = PTR_ERR(sor->rst);
3346 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3347 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3353 * At this point, the reset control is most likely being used
3354 * by the generic power domain implementation. With any luck
3355 * the power domain will have taken care of resetting the SOR
3356 * and we don't have to do anything.
3361 sor->clk = devm_clk_get(&pdev->dev, NULL);
3362 if (IS_ERR(sor->clk)) {
3363 err = PTR_ERR(sor->clk);
3364 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3368 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3369 struct device_node *np = pdev->dev.of_node;
3373 * For backwards compatibility with Tegra210 device trees,
3374 * fall back to the old clock name "source" if the new "out"
3375 * clock is not available.
3377 if (of_property_match_string(np, "clock-names", "out") < 0)
3382 sor->clk_out = devm_clk_get(&pdev->dev, name);
3383 if (IS_ERR(sor->clk_out)) {
3384 err = PTR_ERR(sor->clk_out);
3385 dev_err(sor->dev, "failed to get %s clock: %d\n",
3390 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3391 sor->clk_out = sor->clk;
3394 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3395 if (IS_ERR(sor->clk_parent)) {
3396 err = PTR_ERR(sor->clk_parent);
3397 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3401 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3402 if (IS_ERR(sor->clk_safe)) {
3403 err = PTR_ERR(sor->clk_safe);
3404 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3408 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3409 if (IS_ERR(sor->clk_dp)) {
3410 err = PTR_ERR(sor->clk_dp);
3411 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3416 * Starting with Tegra186, the BPMP provides an implementation for
3417 * the pad output clock, so we have to look it up from device tree.
3419 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3420 if (IS_ERR(sor->clk_pad)) {
3421 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3422 err = PTR_ERR(sor->clk_pad);
3427 * If the pad output clock is not available, then we assume
3428 * we're on Tegra210 or earlier and have to provide our own
3431 sor->clk_pad = NULL;
3435 * The bootloader may have set up the SOR such that it's module clock
3436 * is sourced by one of the display PLLs. However, that doesn't work
3437 * without properly having set up other bits of the SOR.
3439 err = clk_set_parent(sor->clk_out, sor->clk_safe);
3441 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3445 platform_set_drvdata(pdev, sor);
3446 pm_runtime_enable(&pdev->dev);
3449 * On Tegra210 and earlier, provide our own implementation for the
3452 if (!sor->clk_pad) {
3453 err = pm_runtime_get_sync(&pdev->dev);
3455 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
3460 sor->clk_pad = tegra_clk_sor_pad_register(sor,
3462 pm_runtime_put(&pdev->dev);
3465 if (IS_ERR(sor->clk_pad)) {
3466 err = PTR_ERR(sor->clk_pad);
3467 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
3472 INIT_LIST_HEAD(&sor->client.list);
3473 sor->client.ops = &sor_client_ops;
3474 sor->client.dev = &pdev->dev;
3476 err = host1x_client_register(&sor->client);
3478 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3486 if (sor->ops && sor->ops->remove)
3487 sor->ops->remove(sor);
3489 tegra_output_remove(&sor->output);
3493 static int tegra_sor_remove(struct platform_device *pdev)
3495 struct tegra_sor *sor = platform_get_drvdata(pdev);
3498 pm_runtime_disable(&pdev->dev);
3500 err = host1x_client_unregister(&sor->client);
3502 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3507 if (sor->ops && sor->ops->remove) {
3508 err = sor->ops->remove(sor);
3510 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3513 tegra_output_remove(&sor->output);
3519 static int tegra_sor_suspend(struct device *dev)
3521 struct tegra_sor *sor = dev_get_drvdata(dev);
3525 err = reset_control_assert(sor->rst);
3527 dev_err(dev, "failed to assert reset: %d\n", err);
3531 reset_control_release(sor->rst);
3534 usleep_range(1000, 2000);
3536 clk_disable_unprepare(sor->clk);
3541 static int tegra_sor_resume(struct device *dev)
3543 struct tegra_sor *sor = dev_get_drvdata(dev);
3546 err = clk_prepare_enable(sor->clk);
3548 dev_err(dev, "failed to enable clock: %d\n", err);
3552 usleep_range(1000, 2000);
3555 err = reset_control_acquire(sor->rst);
3557 dev_err(dev, "failed to acquire reset: %d\n", err);
3558 clk_disable_unprepare(sor->clk);
3562 err = reset_control_deassert(sor->rst);
3564 dev_err(dev, "failed to deassert reset: %d\n", err);
3565 reset_control_release(sor->rst);
3566 clk_disable_unprepare(sor->clk);
3575 static const struct dev_pm_ops tegra_sor_pm_ops = {
3576 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
3579 struct platform_driver tegra_sor_driver = {
3581 .name = "tegra-sor",
3582 .of_match_table = tegra_sor_of_match,
3583 .pm = &tegra_sor_pm_ops,
3585 .probe = tegra_sor_probe,
3586 .remove = tegra_sor_remove,