1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 NVIDIA Corporation
7 #include <linux/clk-provider.h>
8 #include <linux/debugfs.h>
9 #include <linux/gpio.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset.h>
18 #include <soc/tegra/pmc.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_debugfs.h>
22 #include <drm/drm_dp_helper.h>
23 #include <drm/drm_file.h>
24 #include <drm/drm_panel.h>
25 #include <drm/drm_scdc_helper.h>
34 #define SOR_REKEY 0x38
36 struct tegra_sor_hdmi_settings {
37 unsigned long frequency;
56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
58 .frequency = 54000000,
70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
73 .frequency = 75000000,
85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
88 .frequency = 150000000,
100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
103 .frequency = 300000000,
111 .bg_vref_level = 0xa,
115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
118 .frequency = 600000000,
126 .bg_vref_level = 0x8,
130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
137 .frequency = 75000000,
145 .bg_vref_level = 0x8,
149 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
152 .frequency = 150000000,
160 .bg_vref_level = 0x8,
164 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
167 .frequency = 300000000,
175 .bg_vref_level = 0xf,
179 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
182 .frequency = 600000000,
190 .bg_vref_level = 0xe,
194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
202 .frequency = 54000000,
214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
217 .frequency = 75000000,
229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
232 .frequency = 150000000,
238 .tx_pu_value = 0x66 /* 0 */,
243 .sparepll = 0x00, /* 0x34 */
244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
247 .frequency = 300000000,
259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
262 .frequency = 600000000,
274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
281 .frequency = 54000000,
293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
296 .frequency = 75000000,
308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
311 .frequency = 150000000,
317 .tx_pu_value = 0x66 /* 0 */,
322 .sparepll = 0x00, /* 0x34 */
323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
326 .frequency = 300000000,
338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
341 .frequency = 600000000,
353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
358 struct tegra_sor_regs {
359 unsigned int head_state0;
360 unsigned int head_state1;
361 unsigned int head_state2;
362 unsigned int head_state3;
363 unsigned int head_state4;
364 unsigned int head_state5;
369 unsigned int dp_padctl0;
370 unsigned int dp_padctl2;
373 struct tegra_sor_soc {
379 const struct tegra_sor_regs *regs;
382 const struct tegra_sor_hdmi_settings *settings;
383 unsigned int num_settings;
388 const u8 (*voltage_swing)[4][4];
389 const u8 (*pre_emphasis)[4][4];
390 const u8 (*post_cursor)[4][4];
391 const u8 (*tx_pu)[4][4];
396 struct tegra_sor_ops {
398 int (*probe)(struct tegra_sor *sor);
399 int (*remove)(struct tegra_sor *sor);
403 struct host1x_client client;
404 struct tegra_output output;
407 const struct tegra_sor_soc *soc;
412 struct reset_control *rst;
413 struct clk *clk_parent;
414 struct clk *clk_safe;
422 struct drm_dp_link link;
423 struct drm_dp_aux *aux;
425 struct drm_info_list *debugfs_files;
427 const struct tegra_sor_ops *ops;
428 enum tegra_io_pad pad;
431 struct tegra_sor_hdmi_settings *settings;
432 unsigned int num_settings;
434 struct regulator *avdd_io_supply;
435 struct regulator *vdd_pll_supply;
436 struct regulator *hdmi_supply;
438 struct delayed_work scdc;
441 struct tegra_hda_format format;
444 struct tegra_sor_state {
445 struct drm_connector_state base;
447 unsigned int link_speed;
452 static inline struct tegra_sor_state *
453 to_sor_state(struct drm_connector_state *state)
455 return container_of(state, struct tegra_sor_state, base);
458 struct tegra_sor_config {
471 static inline struct tegra_sor *
472 host1x_client_to_sor(struct host1x_client *client)
474 return container_of(client, struct tegra_sor, client);
477 static inline struct tegra_sor *to_sor(struct tegra_output *output)
479 return container_of(output, struct tegra_sor, output);
482 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
484 u32 value = readl(sor->regs + (offset << 2));
486 trace_sor_readl(sor->dev, offset, value);
491 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
494 trace_sor_writel(sor->dev, offset, value);
495 writel(value, sor->regs + (offset << 2));
498 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
502 clk_disable_unprepare(sor->clk);
504 err = clk_set_parent(sor->clk_out, parent);
508 err = clk_prepare_enable(sor->clk);
515 struct tegra_clk_sor_pad {
517 struct tegra_sor *sor;
520 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
522 return container_of(hw, struct tegra_clk_sor_pad, hw);
525 static const char * const tegra_clk_sor_pad_parents[2][2] = {
526 { "pll_d_out0", "pll_dp" },
527 { "pll_d2_out0", "pll_dp" },
530 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
532 struct tegra_clk_sor_pad *pad = to_pad(hw);
533 struct tegra_sor *sor = pad->sor;
536 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
537 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
541 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
545 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
549 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
554 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
556 struct tegra_clk_sor_pad *pad = to_pad(hw);
557 struct tegra_sor *sor = pad->sor;
561 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
563 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
564 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
565 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
569 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
570 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
578 static const struct clk_ops tegra_clk_sor_pad_ops = {
579 .set_parent = tegra_clk_sor_pad_set_parent,
580 .get_parent = tegra_clk_sor_pad_get_parent,
583 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
586 struct tegra_clk_sor_pad *pad;
587 struct clk_init_data init;
590 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
592 return ERR_PTR(-ENOMEM);
598 init.parent_names = tegra_clk_sor_pad_parents[sor->index];
599 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
600 init.ops = &tegra_clk_sor_pad_ops;
602 pad->hw.init = &init;
604 clk = devm_clk_register(sor->dev, &pad->hw);
609 static void tegra_sor_filter_rates(struct tegra_sor *sor)
611 struct drm_dp_link *link = &sor->link;
614 /* Tegra only supports RBR, HBR and HBR2 */
615 for (i = 0; i < link->num_rates; i++) {
616 switch (link->rates[i]) {
623 DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
630 drm_dp_link_update_rates(link);
633 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
635 unsigned long timeout;
639 * Clear or set the PD_TXD bit corresponding to each lane, depending
640 * on whether it is used or not.
642 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
645 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
646 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
648 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
649 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
652 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
654 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
657 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
661 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
663 /* start lane sequencer */
664 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
665 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
666 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
668 timeout = jiffies + msecs_to_jiffies(250);
670 while (time_before(jiffies, timeout)) {
671 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
672 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
675 usleep_range(250, 1000);
678 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
684 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
686 unsigned long timeout;
689 /* power down all lanes */
690 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
691 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
692 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
693 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
695 /* start lane sequencer */
696 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
697 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
698 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
700 timeout = jiffies + msecs_to_jiffies(250);
702 while (time_before(jiffies, timeout)) {
703 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
704 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
707 usleep_range(25, 100);
710 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
716 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
720 /* pre-charge all used lanes */
721 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
724 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
725 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
727 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
728 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
731 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
733 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
736 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
740 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
742 usleep_range(15, 100);
744 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
745 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
746 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
747 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
750 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
752 u32 mask = 0x08, adj = 0, value;
754 /* enable pad calibration logic */
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
756 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
759 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
760 value |= SOR_PLL1_TMDS_TERM;
761 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
766 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
767 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
768 value |= SOR_PLL1_TMDS_TERMADJ(adj);
769 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
771 usleep_range(100, 200);
773 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
774 if (value & SOR_PLL1_TERM_COMPOUT)
780 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
781 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
782 value |= SOR_PLL1_TMDS_TERMADJ(adj);
783 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
785 /* disable pad calibration logic */
786 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
787 value |= SOR_DP_PADCTL_PAD_CAL_PD;
788 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
791 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
793 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
794 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
795 const struct tegra_sor_soc *soc = sor->soc;
796 u32 pattern = 0, tx_pu = 0, value;
799 for (value = 0, i = 0; i < link->lanes; i++) {
800 u8 vs = link->train.request.voltage_swing[i];
801 u8 pe = link->train.request.pre_emphasis[i];
802 u8 pc = link->train.request.post_cursor[i];
803 u8 shift = sor->soc->lane_map[i] << 3;
805 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
806 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
807 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
809 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
810 tx_pu = sor->soc->tx_pu[pc][vs][pe];
812 switch (link->train.pattern) {
813 case DP_TRAINING_PATTERN_DISABLE:
814 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
815 SOR_DP_TPG_PATTERN_NONE;
818 case DP_TRAINING_PATTERN_1:
819 value = SOR_DP_TPG_SCRAMBLER_NONE |
820 SOR_DP_TPG_PATTERN_TRAIN1;
823 case DP_TRAINING_PATTERN_2:
824 value = SOR_DP_TPG_SCRAMBLER_NONE |
825 SOR_DP_TPG_PATTERN_TRAIN2;
828 case DP_TRAINING_PATTERN_3:
829 value = SOR_DP_TPG_SCRAMBLER_NONE |
830 SOR_DP_TPG_PATTERN_TRAIN3;
837 if (link->caps.channel_coding)
838 value |= SOR_DP_TPG_CHANNEL_CODING;
840 pattern = pattern << 8 | value;
843 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
844 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
846 if (link->caps.tps3_supported)
847 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
849 tegra_sor_writel(sor, pattern, SOR_DP_TPG);
851 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
852 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
853 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
854 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
855 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
857 usleep_range(20, 100);
862 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
864 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
865 unsigned int rate, lanes;
869 rate = drm_dp_link_rate_to_bw_code(link->rate);
872 /* configure link speed and lane count */
873 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
874 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
875 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
876 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
878 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
879 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
880 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
882 if (link->caps.enhanced_framing)
883 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
885 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
887 usleep_range(400, 1000);
889 /* configure load pulse position adjustment */
890 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
891 value &= ~SOR_PLL1_LOADADJ_MASK;
894 case DP_LINK_BW_1_62:
895 value |= SOR_PLL1_LOADADJ(0x3);
899 value |= SOR_PLL1_LOADADJ(0x4);
903 value |= SOR_PLL1_LOADADJ(0x6);
907 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
909 /* use alternate scrambler reset for eDP */
910 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
913 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
915 value |= SOR_DP_SPARE_PANEL_INTERNAL;
917 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
919 err = tegra_sor_power_down_lanes(sor);
921 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
925 /* power up and pre-charge lanes */
926 err = tegra_sor_power_up_lanes(sor, lanes);
928 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
929 lanes, (lanes != 1) ? "s" : "", err);
933 tegra_sor_dp_precharge(sor, lanes);
938 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
939 .apply_training = tegra_sor_dp_link_apply_training,
940 .configure = tegra_sor_dp_link_configure,
943 static void tegra_sor_super_update(struct tegra_sor *sor)
945 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
946 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
947 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
950 static void tegra_sor_update(struct tegra_sor *sor)
952 tegra_sor_writel(sor, 0, SOR_STATE0);
953 tegra_sor_writel(sor, 1, SOR_STATE0);
954 tegra_sor_writel(sor, 0, SOR_STATE0);
957 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
961 value = tegra_sor_readl(sor, SOR_PWM_DIV);
962 value &= ~SOR_PWM_DIV_MASK;
963 value |= 0x400; /* period */
964 tegra_sor_writel(sor, value, SOR_PWM_DIV);
966 value = tegra_sor_readl(sor, SOR_PWM_CTL);
967 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
968 value |= 0x400; /* duty cycle */
969 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
970 value |= SOR_PWM_CTL_TRIGGER;
971 tegra_sor_writel(sor, value, SOR_PWM_CTL);
973 timeout = jiffies + msecs_to_jiffies(timeout);
975 while (time_before(jiffies, timeout)) {
976 value = tegra_sor_readl(sor, SOR_PWM_CTL);
977 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
980 usleep_range(25, 100);
986 static int tegra_sor_attach(struct tegra_sor *sor)
988 unsigned long value, timeout;
990 /* wake up in normal mode */
991 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
992 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
993 value |= SOR_SUPER_STATE_MODE_NORMAL;
994 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
995 tegra_sor_super_update(sor);
998 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
999 value |= SOR_SUPER_STATE_ATTACHED;
1000 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1001 tegra_sor_super_update(sor);
1003 timeout = jiffies + msecs_to_jiffies(250);
1005 while (time_before(jiffies, timeout)) {
1006 value = tegra_sor_readl(sor, SOR_TEST);
1007 if ((value & SOR_TEST_ATTACHED) != 0)
1010 usleep_range(25, 100);
1016 static int tegra_sor_wakeup(struct tegra_sor *sor)
1018 unsigned long value, timeout;
1020 timeout = jiffies + msecs_to_jiffies(250);
1022 /* wait for head to wake up */
1023 while (time_before(jiffies, timeout)) {
1024 value = tegra_sor_readl(sor, SOR_TEST);
1025 value &= SOR_TEST_HEAD_MODE_MASK;
1027 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1030 usleep_range(25, 100);
1036 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1040 value = tegra_sor_readl(sor, SOR_PWR);
1041 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1042 tegra_sor_writel(sor, value, SOR_PWR);
1044 timeout = jiffies + msecs_to_jiffies(timeout);
1046 while (time_before(jiffies, timeout)) {
1047 value = tegra_sor_readl(sor, SOR_PWR);
1048 if ((value & SOR_PWR_TRIGGER) == 0)
1051 usleep_range(25, 100);
1057 struct tegra_sor_params {
1058 /* number of link clocks per line */
1059 unsigned int num_clocks;
1060 /* ratio between input and output */
1062 /* precision factor */
1065 unsigned int active_polarity;
1066 unsigned int active_count;
1067 unsigned int active_frac;
1068 unsigned int tu_size;
1072 static int tegra_sor_compute_params(struct tegra_sor *sor,
1073 struct tegra_sor_params *params,
1074 unsigned int tu_size)
1076 u64 active_sym, active_count, frac, approx;
1077 u32 active_polarity, active_frac = 0;
1078 const u64 f = params->precision;
1081 active_sym = params->ratio * tu_size;
1082 active_count = div_u64(active_sym, f) * f;
1083 frac = active_sym - active_count;
1085 /* fraction < 0.5 */
1086 if (frac >= (f / 2)) {
1087 active_polarity = 1;
1090 active_polarity = 0;
1094 frac = div_u64(f * f, frac); /* 1/fraction */
1095 if (frac <= (15 * f)) {
1096 active_frac = div_u64(frac, f);
1099 if (active_polarity)
1102 active_frac = active_polarity ? 1 : 15;
1106 if (active_frac == 1)
1107 active_polarity = 0;
1109 if (active_polarity == 1) {
1111 approx = active_count + (active_frac * (f - 1)) * f;
1112 approx = div_u64(approx, active_frac * f);
1114 approx = active_count + f;
1118 approx = active_count + div_u64(f, active_frac);
1120 approx = active_count;
1123 error = div_s64(active_sym - approx, tu_size);
1124 error *= params->num_clocks;
1126 if (error <= 0 && abs(error) < params->error) {
1127 params->active_count = div_u64(active_count, f);
1128 params->active_polarity = active_polarity;
1129 params->active_frac = active_frac;
1130 params->error = abs(error);
1131 params->tu_size = tu_size;
1140 static int tegra_sor_compute_config(struct tegra_sor *sor,
1141 const struct drm_display_mode *mode,
1142 struct tegra_sor_config *config,
1143 struct drm_dp_link *link)
1145 const u64 f = 100000, link_rate = link->rate * 1000;
1146 const u64 pclk = mode->clock * 1000;
1147 u64 input, output, watermark, num;
1148 struct tegra_sor_params params;
1149 u32 num_syms_per_line;
1152 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1155 input = pclk * config->bits_per_pixel;
1156 output = link_rate * 8 * link->lanes;
1158 if (input >= output)
1161 memset(¶ms, 0, sizeof(params));
1162 params.ratio = div64_u64(input * f, output);
1163 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1164 params.precision = f;
1165 params.error = 64 * f;
1166 params.tu_size = 64;
1168 for (i = params.tu_size; i >= 32; i--)
1169 if (tegra_sor_compute_params(sor, ¶ms, i))
1172 if (params.active_frac == 0) {
1173 config->active_polarity = 0;
1174 config->active_count = params.active_count;
1176 if (!params.active_polarity)
1177 config->active_count--;
1179 config->tu_size = params.tu_size;
1180 config->active_frac = 1;
1182 config->active_polarity = params.active_polarity;
1183 config->active_count = params.active_count;
1184 config->active_frac = params.active_frac;
1185 config->tu_size = params.tu_size;
1189 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1190 config->active_polarity, config->active_count,
1191 config->tu_size, config->active_frac);
1193 watermark = params.ratio * config->tu_size * (f - params.ratio);
1194 watermark = div_u64(watermark, f);
1196 watermark = div_u64(watermark + params.error, f);
1197 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1198 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1201 if (config->watermark > 30) {
1202 config->watermark = 30;
1204 "unable to compute TU size, forcing watermark to %u\n",
1206 } else if (config->watermark > num_syms_per_line) {
1207 config->watermark = num_syms_per_line;
1208 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1212 /* compute the number of symbols per horizontal blanking interval */
1213 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1214 config->hblank_symbols = div_u64(num, pclk);
1216 if (link->caps.enhanced_framing)
1217 config->hblank_symbols -= 3;
1219 config->hblank_symbols -= 12 / link->lanes;
1221 /* compute the number of symbols per vertical blanking interval */
1222 num = (mode->hdisplay - 25) * link_rate;
1223 config->vblank_symbols = div_u64(num, pclk);
1224 config->vblank_symbols -= 36 / link->lanes + 4;
1226 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1227 config->vblank_symbols);
1232 static void tegra_sor_apply_config(struct tegra_sor *sor,
1233 const struct tegra_sor_config *config)
1237 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1238 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1239 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1240 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1242 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1243 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1244 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1246 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1247 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1249 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1250 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1252 if (config->active_polarity)
1253 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1255 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1257 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1258 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1259 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1261 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1262 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1263 value |= config->hblank_symbols & 0xffff;
1264 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1266 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1267 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1268 value |= config->vblank_symbols & 0xffff;
1269 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1272 static void tegra_sor_mode_set(struct tegra_sor *sor,
1273 const struct drm_display_mode *mode,
1274 struct tegra_sor_state *state)
1276 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1277 unsigned int vbe, vse, hbe, hse, vbs, hbs;
1280 value = tegra_sor_readl(sor, SOR_STATE1);
1281 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1282 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1283 value &= ~SOR_STATE_ASY_OWNER_MASK;
1285 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1286 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1288 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1289 value &= ~SOR_STATE_ASY_HSYNCPOL;
1291 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1292 value |= SOR_STATE_ASY_HSYNCPOL;
1294 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1295 value &= ~SOR_STATE_ASY_VSYNCPOL;
1297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1298 value |= SOR_STATE_ASY_VSYNCPOL;
1300 switch (state->bpc) {
1302 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1306 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1310 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1314 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1318 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1322 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1326 tegra_sor_writel(sor, value, SOR_STATE1);
1329 * TODO: The video timing programming below doesn't seem to match the
1330 * register definitions.
1333 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1334 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1336 /* sync end = sync width - 1 */
1337 vse = mode->vsync_end - mode->vsync_start - 1;
1338 hse = mode->hsync_end - mode->hsync_start - 1;
1340 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1341 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1343 /* blank end = sync end + back porch */
1344 vbe = vse + (mode->vtotal - mode->vsync_end);
1345 hbe = hse + (mode->htotal - mode->hsync_end);
1347 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1348 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1350 /* blank start = blank end + active */
1351 vbs = vbe + mode->vdisplay;
1352 hbs = hbe + mode->hdisplay;
1354 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1355 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1357 /* XXX interlacing support */
1358 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1361 static int tegra_sor_detach(struct tegra_sor *sor)
1363 unsigned long value, timeout;
1365 /* switch to safe mode */
1366 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1367 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1368 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1369 tegra_sor_super_update(sor);
1371 timeout = jiffies + msecs_to_jiffies(250);
1373 while (time_before(jiffies, timeout)) {
1374 value = tegra_sor_readl(sor, SOR_PWR);
1375 if (value & SOR_PWR_MODE_SAFE)
1379 if ((value & SOR_PWR_MODE_SAFE) == 0)
1383 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1384 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1385 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1386 tegra_sor_super_update(sor);
1389 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1390 value &= ~SOR_SUPER_STATE_ATTACHED;
1391 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1392 tegra_sor_super_update(sor);
1394 timeout = jiffies + msecs_to_jiffies(250);
1396 while (time_before(jiffies, timeout)) {
1397 value = tegra_sor_readl(sor, SOR_TEST);
1398 if ((value & SOR_TEST_ATTACHED) == 0)
1401 usleep_range(25, 100);
1404 if ((value & SOR_TEST_ATTACHED) != 0)
1410 static int tegra_sor_power_down(struct tegra_sor *sor)
1412 unsigned long value, timeout;
1415 value = tegra_sor_readl(sor, SOR_PWR);
1416 value &= ~SOR_PWR_NORMAL_STATE_PU;
1417 value |= SOR_PWR_TRIGGER;
1418 tegra_sor_writel(sor, value, SOR_PWR);
1420 timeout = jiffies + msecs_to_jiffies(250);
1422 while (time_before(jiffies, timeout)) {
1423 value = tegra_sor_readl(sor, SOR_PWR);
1424 if ((value & SOR_PWR_TRIGGER) == 0)
1427 usleep_range(25, 100);
1430 if ((value & SOR_PWR_TRIGGER) != 0)
1433 /* switch to safe parent clock */
1434 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1436 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1440 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1441 value |= SOR_PLL2_PORT_POWERDOWN;
1442 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1444 usleep_range(20, 100);
1446 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1447 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1448 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1450 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1451 value |= SOR_PLL2_SEQ_PLLCAPPD;
1452 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1455 usleep_range(20, 100);
1460 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1464 timeout = jiffies + msecs_to_jiffies(timeout);
1466 while (time_before(jiffies, timeout)) {
1467 value = tegra_sor_readl(sor, SOR_CRCA);
1468 if (value & SOR_CRCA_VALID)
1471 usleep_range(100, 200);
1477 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1479 struct drm_info_node *node = s->private;
1480 struct tegra_sor *sor = node->info_ent->data;
1481 struct drm_crtc *crtc = sor->output.encoder.crtc;
1482 struct drm_device *drm = node->minor->dev;
1486 drm_modeset_lock_all(drm);
1488 if (!crtc || !crtc->state->active) {
1493 value = tegra_sor_readl(sor, SOR_STATE1);
1494 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1495 tegra_sor_writel(sor, value, SOR_STATE1);
1497 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1498 value |= SOR_CRC_CNTRL_ENABLE;
1499 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1501 value = tegra_sor_readl(sor, SOR_TEST);
1502 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1503 tegra_sor_writel(sor, value, SOR_TEST);
1505 err = tegra_sor_crc_wait(sor, 100);
1509 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1510 value = tegra_sor_readl(sor, SOR_CRCB);
1512 seq_printf(s, "%08x\n", value);
1515 drm_modeset_unlock_all(drm);
1519 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1521 static const struct debugfs_reg32 tegra_sor_regs[] = {
1522 DEBUGFS_REG32(SOR_CTXSW),
1523 DEBUGFS_REG32(SOR_SUPER_STATE0),
1524 DEBUGFS_REG32(SOR_SUPER_STATE1),
1525 DEBUGFS_REG32(SOR_STATE0),
1526 DEBUGFS_REG32(SOR_STATE1),
1527 DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1528 DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1529 DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1530 DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1531 DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1532 DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1533 DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1534 DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1535 DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1536 DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1537 DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1538 DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1539 DEBUGFS_REG32(SOR_CRC_CNTRL),
1540 DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1541 DEBUGFS_REG32(SOR_CLK_CNTRL),
1542 DEBUGFS_REG32(SOR_CAP),
1543 DEBUGFS_REG32(SOR_PWR),
1544 DEBUGFS_REG32(SOR_TEST),
1545 DEBUGFS_REG32(SOR_PLL0),
1546 DEBUGFS_REG32(SOR_PLL1),
1547 DEBUGFS_REG32(SOR_PLL2),
1548 DEBUGFS_REG32(SOR_PLL3),
1549 DEBUGFS_REG32(SOR_CSTM),
1550 DEBUGFS_REG32(SOR_LVDS),
1551 DEBUGFS_REG32(SOR_CRCA),
1552 DEBUGFS_REG32(SOR_CRCB),
1553 DEBUGFS_REG32(SOR_BLANK),
1554 DEBUGFS_REG32(SOR_SEQ_CTL),
1555 DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1556 DEBUGFS_REG32(SOR_SEQ_INST(0)),
1557 DEBUGFS_REG32(SOR_SEQ_INST(1)),
1558 DEBUGFS_REG32(SOR_SEQ_INST(2)),
1559 DEBUGFS_REG32(SOR_SEQ_INST(3)),
1560 DEBUGFS_REG32(SOR_SEQ_INST(4)),
1561 DEBUGFS_REG32(SOR_SEQ_INST(5)),
1562 DEBUGFS_REG32(SOR_SEQ_INST(6)),
1563 DEBUGFS_REG32(SOR_SEQ_INST(7)),
1564 DEBUGFS_REG32(SOR_SEQ_INST(8)),
1565 DEBUGFS_REG32(SOR_SEQ_INST(9)),
1566 DEBUGFS_REG32(SOR_SEQ_INST(10)),
1567 DEBUGFS_REG32(SOR_SEQ_INST(11)),
1568 DEBUGFS_REG32(SOR_SEQ_INST(12)),
1569 DEBUGFS_REG32(SOR_SEQ_INST(13)),
1570 DEBUGFS_REG32(SOR_SEQ_INST(14)),
1571 DEBUGFS_REG32(SOR_SEQ_INST(15)),
1572 DEBUGFS_REG32(SOR_PWM_DIV),
1573 DEBUGFS_REG32(SOR_PWM_CTL),
1574 DEBUGFS_REG32(SOR_VCRC_A0),
1575 DEBUGFS_REG32(SOR_VCRC_A1),
1576 DEBUGFS_REG32(SOR_VCRC_B0),
1577 DEBUGFS_REG32(SOR_VCRC_B1),
1578 DEBUGFS_REG32(SOR_CCRC_A0),
1579 DEBUGFS_REG32(SOR_CCRC_A1),
1580 DEBUGFS_REG32(SOR_CCRC_B0),
1581 DEBUGFS_REG32(SOR_CCRC_B1),
1582 DEBUGFS_REG32(SOR_EDATA_A0),
1583 DEBUGFS_REG32(SOR_EDATA_A1),
1584 DEBUGFS_REG32(SOR_EDATA_B0),
1585 DEBUGFS_REG32(SOR_EDATA_B1),
1586 DEBUGFS_REG32(SOR_COUNT_A0),
1587 DEBUGFS_REG32(SOR_COUNT_A1),
1588 DEBUGFS_REG32(SOR_COUNT_B0),
1589 DEBUGFS_REG32(SOR_COUNT_B1),
1590 DEBUGFS_REG32(SOR_DEBUG_A0),
1591 DEBUGFS_REG32(SOR_DEBUG_A1),
1592 DEBUGFS_REG32(SOR_DEBUG_B0),
1593 DEBUGFS_REG32(SOR_DEBUG_B1),
1594 DEBUGFS_REG32(SOR_TRIG),
1595 DEBUGFS_REG32(SOR_MSCHECK),
1596 DEBUGFS_REG32(SOR_XBAR_CTRL),
1597 DEBUGFS_REG32(SOR_XBAR_POL),
1598 DEBUGFS_REG32(SOR_DP_LINKCTL0),
1599 DEBUGFS_REG32(SOR_DP_LINKCTL1),
1600 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1601 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1602 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1603 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1604 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1605 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1606 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1607 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1608 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1609 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1610 DEBUGFS_REG32(SOR_DP_CONFIG0),
1611 DEBUGFS_REG32(SOR_DP_CONFIG1),
1612 DEBUGFS_REG32(SOR_DP_MN0),
1613 DEBUGFS_REG32(SOR_DP_MN1),
1614 DEBUGFS_REG32(SOR_DP_PADCTL0),
1615 DEBUGFS_REG32(SOR_DP_PADCTL1),
1616 DEBUGFS_REG32(SOR_DP_PADCTL2),
1617 DEBUGFS_REG32(SOR_DP_DEBUG0),
1618 DEBUGFS_REG32(SOR_DP_DEBUG1),
1619 DEBUGFS_REG32(SOR_DP_SPARE0),
1620 DEBUGFS_REG32(SOR_DP_SPARE1),
1621 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1622 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1623 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1624 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1625 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1626 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1627 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1628 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1629 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1630 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1631 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1632 DEBUGFS_REG32(SOR_DP_TPG),
1633 DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1634 DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1635 DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1636 DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1639 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1641 struct drm_info_node *node = s->private;
1642 struct tegra_sor *sor = node->info_ent->data;
1643 struct drm_crtc *crtc = sor->output.encoder.crtc;
1644 struct drm_device *drm = node->minor->dev;
1648 drm_modeset_lock_all(drm);
1650 if (!crtc || !crtc->state->active) {
1655 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1656 unsigned int offset = tegra_sor_regs[i].offset;
1658 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1659 offset, tegra_sor_readl(sor, offset));
1663 drm_modeset_unlock_all(drm);
1667 static const struct drm_info_list debugfs_files[] = {
1668 { "crc", tegra_sor_show_crc, 0, NULL },
1669 { "regs", tegra_sor_show_regs, 0, NULL },
1672 static int tegra_sor_late_register(struct drm_connector *connector)
1674 struct tegra_output *output = connector_to_output(connector);
1675 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1676 struct drm_minor *minor = connector->dev->primary;
1677 struct dentry *root = connector->debugfs_entry;
1678 struct tegra_sor *sor = to_sor(output);
1681 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1683 if (!sor->debugfs_files)
1686 for (i = 0; i < count; i++)
1687 sor->debugfs_files[i].data = sor;
1689 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1696 kfree(sor->debugfs_files);
1697 sor->debugfs_files = NULL;
1702 static void tegra_sor_early_unregister(struct drm_connector *connector)
1704 struct tegra_output *output = connector_to_output(connector);
1705 unsigned int count = ARRAY_SIZE(debugfs_files);
1706 struct tegra_sor *sor = to_sor(output);
1708 drm_debugfs_remove_files(sor->debugfs_files, count,
1709 connector->dev->primary);
1710 kfree(sor->debugfs_files);
1711 sor->debugfs_files = NULL;
1714 static void tegra_sor_connector_reset(struct drm_connector *connector)
1716 struct tegra_sor_state *state;
1718 state = kzalloc(sizeof(*state), GFP_KERNEL);
1722 if (connector->state) {
1723 __drm_atomic_helper_connector_destroy_state(connector->state);
1724 kfree(connector->state);
1727 __drm_atomic_helper_connector_reset(connector, &state->base);
1730 static enum drm_connector_status
1731 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1733 struct tegra_output *output = connector_to_output(connector);
1734 struct tegra_sor *sor = to_sor(output);
1737 return drm_dp_aux_detect(sor->aux);
1739 return tegra_output_connector_detect(connector, force);
1742 static struct drm_connector_state *
1743 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1745 struct tegra_sor_state *state = to_sor_state(connector->state);
1746 struct tegra_sor_state *copy;
1748 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1752 __drm_atomic_helper_connector_duplicate_state(connector, ©->base);
1757 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1758 .reset = tegra_sor_connector_reset,
1759 .detect = tegra_sor_connector_detect,
1760 .fill_modes = drm_helper_probe_single_connector_modes,
1761 .destroy = tegra_output_connector_destroy,
1762 .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1763 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1764 .late_register = tegra_sor_late_register,
1765 .early_unregister = tegra_sor_early_unregister,
1768 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1770 struct tegra_output *output = connector_to_output(connector);
1771 struct tegra_sor *sor = to_sor(output);
1775 drm_dp_aux_enable(sor->aux);
1777 err = tegra_output_connector_get_modes(connector);
1780 drm_dp_aux_disable(sor->aux);
1785 static enum drm_mode_status
1786 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1787 struct drm_display_mode *mode)
1792 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1793 .get_modes = tegra_sor_connector_get_modes,
1794 .mode_valid = tegra_sor_connector_mode_valid,
1797 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
1798 .destroy = tegra_output_encoder_destroy,
1801 static void tegra_sor_edp_disable(struct drm_encoder *encoder)
1803 struct tegra_output *output = encoder_to_output(encoder);
1804 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1805 struct tegra_sor *sor = to_sor(output);
1810 drm_panel_disable(output->panel);
1812 err = tegra_sor_detach(sor);
1814 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1816 tegra_sor_writel(sor, 0, SOR_STATE1);
1817 tegra_sor_update(sor);
1819 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1820 value &= ~SOR_ENABLE(0);
1821 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1823 tegra_dc_commit(dc);
1825 err = tegra_sor_power_down(sor);
1827 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1830 err = drm_dp_aux_disable(sor->aux);
1832 dev_err(sor->dev, "failed to disable DP: %d\n", err);
1835 err = tegra_io_pad_power_disable(sor->pad);
1837 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
1840 drm_panel_unprepare(output->panel);
1842 pm_runtime_put(sor->dev);
1846 static int calc_h_ref_to_sync(const struct drm_display_mode *mode,
1847 unsigned int *value)
1849 unsigned int hfp, hsw, hbp, a = 0, b;
1851 hfp = mode->hsync_start - mode->hdisplay;
1852 hsw = mode->hsync_end - mode->hsync_start;
1853 hbp = mode->htotal - mode->hsync_end;
1855 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp);
1859 pr_info("a: %u, b: %u\n", a, b);
1860 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp);
1862 if (a + hsw + hbp <= 11) {
1863 a = 1 + 11 - hsw - hbp;
1864 pr_info("a: %u\n", a);
1873 if (mode->hdisplay < 16)
1887 static void tegra_sor_edp_enable(struct drm_encoder *encoder)
1889 struct tegra_output *output = encoder_to_output(encoder);
1890 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1891 struct tegra_sor *sor = to_sor(output);
1892 struct tegra_sor_config config;
1893 struct tegra_sor_state *state;
1894 struct drm_display_mode *mode;
1895 struct drm_display_info *info;
1900 state = to_sor_state(output->connector.state);
1901 mode = &encoder->crtc->state->adjusted_mode;
1902 info = &output->connector.display_info;
1904 pm_runtime_get_sync(sor->dev);
1906 /* switch to safe parent clock */
1907 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1909 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1911 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
1913 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
1915 usleep_range(20, 100);
1917 err = drm_dp_aux_enable(sor->aux);
1919 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
1921 err = drm_dp_link_probe(sor->aux, &sor->link);
1923 dev_err(sor->dev, "failed to probe eDP link: %d\n", err);
1925 tegra_sor_filter_rates(sor);
1927 err = drm_dp_link_choose(&sor->link, mode, info);
1929 dev_err(sor->dev, "failed to choose link: %d\n", err);
1932 drm_panel_prepare(output->panel);
1934 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1935 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
1936 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1938 usleep_range(20, 40);
1940 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
1941 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
1942 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
1944 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1945 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
1946 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1948 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1949 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1950 value |= SOR_PLL2_SEQ_PLLCAPPD;
1951 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1953 usleep_range(200, 400);
1955 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1956 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
1957 value &= ~SOR_PLL2_PORT_POWERDOWN;
1958 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1960 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1961 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
1962 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
1963 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1965 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
1966 /* XXX not in TRM */
1967 value |= SOR_DP_SPARE_PANEL_INTERNAL;
1968 value |= SOR_DP_SPARE_SEQ_ENABLE;
1969 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
1971 /* XXX not in TRM */
1972 tegra_sor_writel(sor, 0, SOR_LVDS);
1974 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1975 value &= ~SOR_PLL0_ICHPMP_MASK;
1976 value &= ~SOR_PLL0_VCOCAP_MASK;
1977 value |= SOR_PLL0_ICHPMP(0x1);
1978 value |= SOR_PLL0_VCOCAP(0x3);
1979 value |= SOR_PLL0_RESISTOR_EXT;
1980 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1982 /* XXX not in TRM */
1983 for (value = 0, i = 0; i < 5; i++)
1984 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
1985 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
1987 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
1988 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
1990 /* switch to DP parent clock */
1991 err = tegra_sor_set_parent_clock(sor, sor->clk_dp);
1993 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1995 /* use DP-A protocol */
1996 value = tegra_sor_readl(sor, SOR_STATE1);
1997 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
1998 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
1999 tegra_sor_writel(sor, value, SOR_STATE1);
2002 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2003 value |= SOR_DP_LINKCTL_ENABLE;
2004 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2006 tegra_sor_dp_term_calibrate(sor);
2008 err = drm_dp_link_train(&sor->link);
2010 dev_err(sor->dev, "link training failed: %d\n", err);
2012 dev_dbg(sor->dev, "link training succeeded\n");
2014 err = drm_dp_link_power_up(sor->aux, &sor->link);
2016 dev_err(sor->dev, "failed to power up eDP link: %d\n", err);
2018 /* compute configuration */
2019 memset(&config, 0, sizeof(config));
2020 config.bits_per_pixel = state->bpc * 3;
2022 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2024 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2026 tegra_sor_apply_config(sor, &config);
2028 err = tegra_sor_power_up(sor, 250);
2030 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2032 /* CSTM (LVDS, link A/B, upper) */
2033 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2035 tegra_sor_writel(sor, value, SOR_CSTM);
2037 /* use DP-A protocol */
2038 value = tegra_sor_readl(sor, SOR_STATE1);
2039 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2040 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2041 tegra_sor_writel(sor, value, SOR_STATE1);
2043 tegra_sor_mode_set(sor, mode, state);
2046 err = tegra_sor_setup_pwm(sor, 250);
2048 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2050 tegra_sor_update(sor);
2052 err = tegra_sor_power_up(sor, 250);
2054 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2056 /* attach and wake up */
2057 err = tegra_sor_attach(sor);
2059 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2061 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2062 value |= SOR_ENABLE(0);
2063 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2065 tegra_dc_commit(dc);
2067 err = tegra_sor_wakeup(sor);
2069 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2072 drm_panel_enable(output->panel);
2076 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
2077 struct drm_crtc_state *crtc_state,
2078 struct drm_connector_state *conn_state)
2080 struct tegra_output *output = encoder_to_output(encoder);
2081 struct tegra_sor_state *state = to_sor_state(conn_state);
2082 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
2083 unsigned long pclk = crtc_state->mode.clock * 1000;
2084 struct tegra_sor *sor = to_sor(output);
2085 struct drm_display_info *info;
2088 info = &output->connector.display_info;
2091 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
2092 * the pixel clock must be corrected accordingly.
2094 if (pclk >= 340000000) {
2095 state->link_speed = 20;
2096 state->pclk = pclk / 2;
2098 state->link_speed = 10;
2102 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
2105 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
2109 switch (info->bpc) {
2112 state->bpc = info->bpc;
2116 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
2124 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = {
2125 .disable = tegra_sor_edp_disable,
2126 .enable = tegra_sor_edp_enable,
2127 .atomic_check = tegra_sor_encoder_atomic_check,
2130 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
2135 for (i = size; i > 0; i--)
2136 value = (value << 8) | ptr[i - 1];
2141 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
2142 const void *data, size_t size)
2144 const u8 *ptr = data;
2145 unsigned long offset;
2150 case HDMI_INFOFRAME_TYPE_AVI:
2151 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
2154 case HDMI_INFOFRAME_TYPE_AUDIO:
2155 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
2158 case HDMI_INFOFRAME_TYPE_VENDOR:
2159 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
2163 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
2168 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
2169 INFOFRAME_HEADER_VERSION(ptr[1]) |
2170 INFOFRAME_HEADER_LEN(ptr[2]);
2171 tegra_sor_writel(sor, value, offset);
2175 * Each subpack contains 7 bytes, divided into:
2176 * - subpack_low: bytes 0 - 3
2177 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
2179 for (i = 3, j = 0; i < size; i += 7, j += 8) {
2180 size_t rem = size - i, num = min_t(size_t, rem, 4);
2182 value = tegra_sor_hdmi_subpack(&ptr[i], num);
2183 tegra_sor_writel(sor, value, offset++);
2185 num = min_t(size_t, rem - num, 3);
2187 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
2188 tegra_sor_writel(sor, value, offset++);
2193 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
2194 const struct drm_display_mode *mode)
2196 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
2197 struct hdmi_avi_infoframe frame;
2201 /* disable AVI infoframe */
2202 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2203 value &= ~INFOFRAME_CTRL_SINGLE;
2204 value &= ~INFOFRAME_CTRL_OTHER;
2205 value &= ~INFOFRAME_CTRL_ENABLE;
2206 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2208 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2209 &sor->output.connector, mode);
2211 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2215 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
2217 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
2221 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2223 /* enable AVI infoframe */
2224 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
2225 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2226 value |= INFOFRAME_CTRL_ENABLE;
2227 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
2232 static void tegra_sor_write_eld(struct tegra_sor *sor)
2234 size_t length = drm_eld_size(sor->output.connector.eld), i;
2236 for (i = 0; i < length; i++)
2237 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
2238 SOR_AUDIO_HDA_ELD_BUFWR);
2241 * The HDA codec will always report an ELD buffer size of 96 bytes and
2242 * the HDA codec driver will check that each byte read from the buffer
2243 * is valid. Therefore every byte must be written, even if no 96 bytes
2244 * were parsed from EDID.
2246 for (i = length; i < 96; i++)
2247 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
2250 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
2255 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
2256 * is used for interoperability between the HDA codec driver and the
2259 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
2260 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
2261 tegra_sor_writel(sor, value, SOR_INT_MASK);
2263 tegra_sor_write_eld(sor);
2265 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
2266 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
2269 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
2271 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
2272 tegra_sor_writel(sor, 0, SOR_INT_MASK);
2273 tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
2276 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2278 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2279 struct hdmi_audio_infoframe frame;
2283 err = hdmi_audio_infoframe_init(&frame);
2285 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2289 frame.channels = sor->format.channels;
2291 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2293 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2297 tegra_sor_hdmi_write_infopack(sor, buffer, err);
2299 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2300 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2301 value |= INFOFRAME_CTRL_ENABLE;
2302 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2307 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2311 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2313 /* select HDA audio input */
2314 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2315 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2317 /* inject null samples */
2318 if (sor->format.channels != 2)
2319 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2321 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2323 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2325 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2327 /* enable advertising HBR capability */
2328 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2330 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2332 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2333 SOR_HDMI_SPARE_CTS_RESET(1) |
2334 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2335 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2338 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2339 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2341 /* allow packet to be sent */
2342 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2343 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2345 /* reset N counter and enable lookup */
2346 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2347 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2349 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2350 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2351 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2353 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2354 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2356 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2357 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2359 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2360 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2362 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2363 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2364 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2366 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2367 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2368 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2370 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2371 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2372 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2374 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2375 value &= ~SOR_HDMI_AUDIO_N_RESET;
2376 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2378 tegra_sor_hdmi_enable_audio_infoframe(sor);
2381 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2385 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2386 value &= ~INFOFRAME_CTRL_ENABLE;
2387 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2390 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2392 tegra_sor_hdmi_disable_audio_infoframe(sor);
2395 static struct tegra_sor_hdmi_settings *
2396 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2400 for (i = 0; i < sor->num_settings; i++)
2401 if (frequency <= sor->settings[i].frequency)
2402 return &sor->settings[i];
2407 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2411 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2412 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2413 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2414 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2417 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2419 struct i2c_adapter *ddc = sor->output.ddc;
2421 drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2422 drm_scdc_set_scrambling(ddc, false);
2424 tegra_sor_hdmi_disable_scrambling(sor);
2427 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2429 if (sor->scdc_enabled) {
2430 cancel_delayed_work_sync(&sor->scdc);
2431 tegra_sor_hdmi_scdc_disable(sor);
2435 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2439 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2440 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2441 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2442 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2445 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2447 struct i2c_adapter *ddc = sor->output.ddc;
2449 drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2450 drm_scdc_set_scrambling(ddc, true);
2452 tegra_sor_hdmi_enable_scrambling(sor);
2455 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2457 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2458 struct i2c_adapter *ddc = sor->output.ddc;
2460 if (!drm_scdc_get_scrambling_status(ddc)) {
2461 DRM_DEBUG_KMS("SCDC not scrambled\n");
2462 tegra_sor_hdmi_scdc_enable(sor);
2465 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2468 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2470 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2471 struct drm_display_mode *mode;
2473 mode = &sor->output.encoder.crtc->state->adjusted_mode;
2475 if (mode->clock >= 340000 && scdc->supported) {
2476 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2477 tegra_sor_hdmi_scdc_enable(sor);
2478 sor->scdc_enabled = true;
2482 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2484 struct tegra_output *output = encoder_to_output(encoder);
2485 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2486 struct tegra_sor *sor = to_sor(output);
2490 tegra_sor_audio_unprepare(sor);
2491 tegra_sor_hdmi_scdc_stop(sor);
2493 err = tegra_sor_detach(sor);
2495 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2497 tegra_sor_writel(sor, 0, SOR_STATE1);
2498 tegra_sor_update(sor);
2500 /* disable display to SOR clock */
2501 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2503 if (!sor->soc->has_nvdisplay)
2504 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2506 value &= ~SOR_ENABLE(sor->index);
2508 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2510 tegra_dc_commit(dc);
2512 err = tegra_sor_power_down(sor);
2514 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2516 err = tegra_io_pad_power_disable(sor->pad);
2518 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2520 pm_runtime_put(sor->dev);
2523 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2525 struct tegra_output *output = encoder_to_output(encoder);
2526 unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2527 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2528 struct tegra_sor_hdmi_settings *settings;
2529 struct tegra_sor *sor = to_sor(output);
2530 struct tegra_sor_state *state;
2531 struct drm_display_mode *mode;
2532 unsigned long rate, pclk;
2533 unsigned int div, i;
2537 state = to_sor_state(output->connector.state);
2538 mode = &encoder->crtc->state->adjusted_mode;
2539 pclk = mode->clock * 1000;
2541 pm_runtime_get_sync(sor->dev);
2543 /* switch to safe parent clock */
2544 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2546 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2550 div = clk_get_rate(sor->clk) / 1000000 * 4;
2552 err = tegra_io_pad_power_enable(sor->pad);
2554 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2556 usleep_range(20, 100);
2558 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2559 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2560 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2562 usleep_range(20, 100);
2564 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2565 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2566 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2568 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2569 value &= ~SOR_PLL0_VCOPD;
2570 value &= ~SOR_PLL0_PWR;
2571 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2573 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2574 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2575 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2577 usleep_range(200, 400);
2579 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2580 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2581 value &= ~SOR_PLL2_PORT_POWERDOWN;
2582 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2584 usleep_range(20, 100);
2586 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2587 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2588 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2589 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2592 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2593 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2596 usleep_range(250, 1000);
2599 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2600 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2601 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2604 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2605 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2608 usleep_range(250, 1000);
2611 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2612 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2613 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2615 if (mode->clock < 340000) {
2616 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2617 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2619 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2620 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2623 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2624 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2626 /* SOR pad PLL stabilization time */
2627 usleep_range(250, 1000);
2629 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2630 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2631 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2632 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2634 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2635 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2636 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2637 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2638 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2639 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2641 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2642 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2643 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2645 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2646 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2647 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2648 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2650 if (!sor->soc->has_nvdisplay) {
2651 /* program the reference clock */
2652 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2653 tegra_sor_writel(sor, value, SOR_REFCLK);
2656 /* XXX not in TRM */
2657 for (value = 0, i = 0; i < 5; i++)
2658 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2659 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2661 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2662 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2664 /* switch to parent clock */
2665 err = clk_set_parent(sor->clk, sor->clk_parent);
2667 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
2671 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2673 dev_err(sor->dev, "failed to set pad clock: %d\n", err);
2677 /* adjust clock rate for HDMI 2.0 modes */
2678 rate = clk_get_rate(sor->clk_parent);
2680 if (mode->clock >= 340000)
2683 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2685 clk_set_rate(sor->clk, rate);
2687 if (!sor->soc->has_nvdisplay) {
2688 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2690 /* XXX is this the proper check? */
2691 if (mode->clock < 75000)
2692 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2694 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2697 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2699 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2700 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2701 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2703 if (!dc->soc->has_nvdisplay) {
2704 /* H_PULSE2 setup */
2705 pulse_start = h_ref_to_sync +
2706 (mode->hsync_end - mode->hsync_start) +
2707 (mode->htotal - mode->hsync_end) - 10;
2709 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2710 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2711 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2713 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2714 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2716 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2717 value |= H_PULSE2_ENABLE;
2718 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2721 /* infoframe setup */
2722 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2724 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2726 /* XXX HDMI audio support not implemented yet */
2727 tegra_sor_hdmi_disable_audio_infoframe(sor);
2729 /* use single TMDS protocol */
2730 value = tegra_sor_readl(sor, SOR_STATE1);
2731 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2732 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2733 tegra_sor_writel(sor, value, SOR_STATE1);
2735 /* power up pad calibration */
2736 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2737 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2738 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2740 /* production settings */
2741 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2743 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2744 mode->clock * 1000);
2748 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2749 value &= ~SOR_PLL0_ICHPMP_MASK;
2750 value &= ~SOR_PLL0_FILTER_MASK;
2751 value &= ~SOR_PLL0_VCOCAP_MASK;
2752 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2753 value |= SOR_PLL0_FILTER(settings->filter);
2754 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2755 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2757 /* XXX not in TRM */
2758 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2759 value &= ~SOR_PLL1_LOADADJ_MASK;
2760 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2761 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2762 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2763 value |= SOR_PLL1_TMDS_TERM;
2764 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2766 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2767 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2768 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2769 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2770 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2771 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2772 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2773 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2774 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2775 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2777 value = settings->drive_current[3] << 24 |
2778 settings->drive_current[2] << 16 |
2779 settings->drive_current[1] << 8 |
2780 settings->drive_current[0] << 0;
2781 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2783 value = settings->preemphasis[3] << 24 |
2784 settings->preemphasis[2] << 16 |
2785 settings->preemphasis[1] << 8 |
2786 settings->preemphasis[0] << 0;
2787 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2789 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2790 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2791 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2792 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2793 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2795 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2796 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2797 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2798 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2800 /* power down pad calibration */
2801 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2802 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2803 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2805 if (!dc->soc->has_nvdisplay) {
2806 /* miscellaneous display controller settings */
2807 value = VSYNC_H_POSITION(1);
2808 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2811 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2812 value &= ~DITHER_CONTROL_MASK;
2813 value &= ~BASE_COLOR_SIZE_MASK;
2815 switch (state->bpc) {
2817 value |= BASE_COLOR_SIZE_666;
2821 value |= BASE_COLOR_SIZE_888;
2825 value |= BASE_COLOR_SIZE_101010;
2829 value |= BASE_COLOR_SIZE_121212;
2833 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2834 value |= BASE_COLOR_SIZE_888;
2838 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2840 /* XXX set display head owner */
2841 value = tegra_sor_readl(sor, SOR_STATE1);
2842 value &= ~SOR_STATE_ASY_OWNER_MASK;
2843 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2844 tegra_sor_writel(sor, value, SOR_STATE1);
2846 err = tegra_sor_power_up(sor, 250);
2848 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2850 /* configure dynamic range of output */
2851 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2852 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2853 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2854 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2856 /* configure colorspace */
2857 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2858 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2859 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2860 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2862 tegra_sor_mode_set(sor, mode, state);
2864 tegra_sor_update(sor);
2866 /* program preamble timing in SOR (XXX) */
2867 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2868 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2869 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2871 err = tegra_sor_attach(sor);
2873 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2875 /* enable display to SOR clock and generate HDMI preamble */
2876 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2878 if (!sor->soc->has_nvdisplay)
2879 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA;
2881 value |= SOR_ENABLE(sor->index);
2883 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2885 if (dc->soc->has_nvdisplay) {
2886 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2887 value &= ~PROTOCOL_MASK;
2888 value |= PROTOCOL_SINGLE_TMDS_A;
2889 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2892 tegra_dc_commit(dc);
2894 err = tegra_sor_wakeup(sor);
2896 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2898 tegra_sor_hdmi_scdc_start(sor);
2899 tegra_sor_audio_prepare(sor);
2902 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2903 .disable = tegra_sor_hdmi_disable,
2904 .enable = tegra_sor_hdmi_enable,
2905 .atomic_check = tegra_sor_encoder_atomic_check,
2908 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2910 struct tegra_output *output = encoder_to_output(encoder);
2911 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2912 struct tegra_sor *sor = to_sor(output);
2916 err = drm_dp_link_power_down(sor->aux, &sor->link);
2918 dev_err(sor->dev, "failed to power down link: %d\n", err);
2920 err = tegra_sor_detach(sor);
2922 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2924 tegra_sor_writel(sor, 0, SOR_STATE1);
2925 tegra_sor_update(sor);
2927 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2929 if (!sor->soc->has_nvdisplay)
2930 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1));
2932 value &= ~SOR_ENABLE(sor->index);
2934 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2935 tegra_dc_commit(dc);
2937 value = tegra_sor_readl(sor, SOR_STATE1);
2938 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2939 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2940 value &= ~SOR_STATE_ASY_OWNER_MASK;
2941 tegra_sor_writel(sor, value, SOR_STATE1);
2942 tegra_sor_update(sor);
2944 /* switch to safe parent clock */
2945 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2947 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2949 err = tegra_sor_power_down(sor);
2951 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2953 err = tegra_io_pad_power_disable(sor->pad);
2955 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2957 err = drm_dp_aux_disable(sor->aux);
2959 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2961 pm_runtime_put(sor->dev);
2964 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2966 struct tegra_output *output = encoder_to_output(encoder);
2967 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2968 struct tegra_sor *sor = to_sor(output);
2969 struct tegra_sor_config config;
2970 struct tegra_sor_state *state;
2971 struct drm_display_mode *mode;
2972 struct drm_display_info *info;
2977 state = to_sor_state(output->connector.state);
2978 mode = &encoder->crtc->state->adjusted_mode;
2979 info = &output->connector.display_info;
2981 pm_runtime_get_sync(sor->dev);
2983 /* switch to safe parent clock */
2984 err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2986 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2988 err = tegra_io_pad_power_enable(sor->pad);
2990 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2992 usleep_range(20, 100);
2994 err = drm_dp_aux_enable(sor->aux);
2996 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2998 err = drm_dp_link_probe(sor->aux, &sor->link);
3000 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
3002 err = drm_dp_link_choose(&sor->link, mode, info);
3004 dev_err(sor->dev, "failed to choose link: %d\n", err);
3006 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3007 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
3008 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3010 usleep_range(20, 40);
3012 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
3013 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
3014 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
3016 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3017 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
3018 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3020 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3021 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
3022 value |= SOR_PLL2_SEQ_PLLCAPPD;
3023 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3025 usleep_range(200, 400);
3027 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
3028 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
3029 value &= ~SOR_PLL2_PORT_POWERDOWN;
3030 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
3032 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
3033 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
3034 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
3035 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
3037 usleep_range(200, 400);
3039 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
3040 /* XXX not in TRM */
3041 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
3042 value |= SOR_DP_SPARE_SEQ_ENABLE;
3043 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
3045 /* XXX not in TRM */
3046 tegra_sor_writel(sor, 0, SOR_LVDS);
3048 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
3049 value &= ~SOR_PLL0_ICHPMP_MASK;
3050 value &= ~SOR_PLL0_VCOCAP_MASK;
3051 value |= SOR_PLL0_ICHPMP(0x1);
3052 value |= SOR_PLL0_VCOCAP(0x3);
3053 value |= SOR_PLL0_RESISTOR_EXT;
3054 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
3056 /* XXX not in TRM */
3057 for (value = 0, i = 0; i < 5; i++)
3058 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
3059 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
3061 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
3062 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
3064 /* switch to DP parent clock */
3065 err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
3067 dev_err(sor->dev, "failed to switch to pad clock: %d\n", err);
3071 err = clk_set_parent(sor->clk, sor->clk_parent);
3073 dev_err(sor->dev, "failed to switch to parent clock: %d\n", err);
3077 /* use DP-A protocol */
3078 value = tegra_sor_readl(sor, SOR_STATE1);
3079 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
3080 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
3081 tegra_sor_writel(sor, value, SOR_STATE1);
3084 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
3085 value |= SOR_DP_LINKCTL_ENABLE;
3086 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
3088 tegra_sor_dp_term_calibrate(sor);
3090 err = drm_dp_link_train(&sor->link);
3092 dev_err(sor->dev, "link training failed: %d\n", err);
3094 dev_dbg(sor->dev, "link training succeeded\n");
3096 err = drm_dp_link_power_up(sor->aux, &sor->link);
3098 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
3100 /* compute configuration */
3101 memset(&config, 0, sizeof(config));
3102 config.bits_per_pixel = state->bpc * 3;
3104 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
3106 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
3108 tegra_sor_apply_config(sor, &config);
3109 tegra_sor_mode_set(sor, mode, state);
3110 tegra_sor_update(sor);
3112 err = tegra_sor_power_up(sor, 250);
3114 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
3116 /* attach and wake up */
3117 err = tegra_sor_attach(sor);
3119 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
3121 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
3122 value |= SOR_ENABLE(sor->index);
3123 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
3125 tegra_dc_commit(dc);
3127 err = tegra_sor_wakeup(sor);
3129 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
3132 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
3133 .disable = tegra_sor_dp_disable,
3134 .enable = tegra_sor_dp_enable,
3135 .atomic_check = tegra_sor_encoder_atomic_check,
3138 static const struct tegra_sor_ops tegra_sor_edp_ops = {
3142 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
3146 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io");
3147 if (IS_ERR(sor->avdd_io_supply)) {
3148 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
3149 PTR_ERR(sor->avdd_io_supply));
3150 return PTR_ERR(sor->avdd_io_supply);
3153 err = regulator_enable(sor->avdd_io_supply);
3155 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
3160 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll");
3161 if (IS_ERR(sor->vdd_pll_supply)) {
3162 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
3163 PTR_ERR(sor->vdd_pll_supply));
3164 return PTR_ERR(sor->vdd_pll_supply);
3167 err = regulator_enable(sor->vdd_pll_supply);
3169 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
3174 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
3175 if (IS_ERR(sor->hdmi_supply)) {
3176 dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
3177 PTR_ERR(sor->hdmi_supply));
3178 return PTR_ERR(sor->hdmi_supply);
3181 err = regulator_enable(sor->hdmi_supply);
3183 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
3187 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
3192 static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
3194 regulator_disable(sor->hdmi_supply);
3195 regulator_disable(sor->vdd_pll_supply);
3196 regulator_disable(sor->avdd_io_supply);
3201 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3203 .probe = tegra_sor_hdmi_probe,
3204 .remove = tegra_sor_hdmi_remove,
3207 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3211 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3212 if (IS_ERR(sor->avdd_io_supply))
3213 return PTR_ERR(sor->avdd_io_supply);
3215 err = regulator_enable(sor->avdd_io_supply);
3219 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3220 if (IS_ERR(sor->vdd_pll_supply))
3221 return PTR_ERR(sor->vdd_pll_supply);
3223 err = regulator_enable(sor->vdd_pll_supply);
3230 static int tegra_sor_dp_remove(struct tegra_sor *sor)
3232 regulator_disable(sor->vdd_pll_supply);
3233 regulator_disable(sor->avdd_io_supply);
3238 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3240 .probe = tegra_sor_dp_probe,
3241 .remove = tegra_sor_dp_remove,
3244 static int tegra_sor_init(struct host1x_client *client)
3246 struct drm_device *drm = dev_get_drvdata(client->parent);
3247 const struct drm_encoder_helper_funcs *helpers = NULL;
3248 struct tegra_sor *sor = host1x_client_to_sor(client);
3249 int connector = DRM_MODE_CONNECTOR_Unknown;
3250 int encoder = DRM_MODE_ENCODER_NONE;
3254 if (sor->ops == &tegra_sor_hdmi_ops) {
3255 connector = DRM_MODE_CONNECTOR_HDMIA;
3256 encoder = DRM_MODE_ENCODER_TMDS;
3257 helpers = &tegra_sor_hdmi_helpers;
3258 } else if (sor->soc->supports_lvds) {
3259 connector = DRM_MODE_CONNECTOR_LVDS;
3260 encoder = DRM_MODE_ENCODER_LVDS;
3263 if (sor->ops == &tegra_sor_edp_ops) {
3264 connector = DRM_MODE_CONNECTOR_eDP;
3265 encoder = DRM_MODE_ENCODER_TMDS;
3266 helpers = &tegra_sor_edp_helpers;
3268 connector = DRM_MODE_CONNECTOR_DisplayPort;
3269 encoder = DRM_MODE_ENCODER_TMDS;
3270 helpers = &tegra_sor_dp_helpers;
3273 sor->link.ops = &tegra_sor_dp_link_ops;
3274 sor->link.aux = sor->aux;
3277 sor->output.dev = sor->dev;
3279 drm_connector_init(drm, &sor->output.connector,
3280 &tegra_sor_connector_funcs,
3282 drm_connector_helper_add(&sor->output.connector,
3283 &tegra_sor_connector_helper_funcs);
3284 sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3286 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
3288 drm_encoder_helper_add(&sor->output.encoder, helpers);
3290 drm_connector_attach_encoder(&sor->output.connector,
3291 &sor->output.encoder);
3292 drm_connector_register(&sor->output.connector);
3294 err = tegra_output_init(drm, &sor->output);
3296 dev_err(client->dev, "failed to initialize output: %d\n", err);
3300 tegra_output_find_possible_crtcs(&sor->output, drm);
3303 err = drm_dp_aux_attach(sor->aux, &sor->output);
3305 dev_err(sor->dev, "failed to attach DP: %d\n", err);
3311 * XXX: Remove this reset once proper hand-over from firmware to
3312 * kernel is possible.
3315 err = reset_control_acquire(sor->rst);
3317 dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3322 err = reset_control_assert(sor->rst);
3324 dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3330 err = clk_prepare_enable(sor->clk);
3332 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3336 usleep_range(1000, 3000);
3339 err = reset_control_deassert(sor->rst);
3341 dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3346 reset_control_release(sor->rst);
3349 err = clk_prepare_enable(sor->clk_safe);
3353 err = clk_prepare_enable(sor->clk_dp);
3360 static int tegra_sor_exit(struct host1x_client *client)
3362 struct tegra_sor *sor = host1x_client_to_sor(client);
3365 tegra_output_exit(&sor->output);
3368 err = drm_dp_aux_detach(sor->aux);
3370 dev_err(sor->dev, "failed to detach DP: %d\n", err);
3375 clk_disable_unprepare(sor->clk_safe);
3376 clk_disable_unprepare(sor->clk_dp);
3377 clk_disable_unprepare(sor->clk);
3382 static const struct host1x_client_ops sor_client_ops = {
3383 .init = tegra_sor_init,
3384 .exit = tegra_sor_exit,
3387 static const u8 tegra124_sor_xbar_cfg[5] = {
3391 static const struct tegra_sor_regs tegra124_sor_regs = {
3392 .head_state0 = 0x05,
3393 .head_state1 = 0x07,
3394 .head_state2 = 0x09,
3395 .head_state3 = 0x0b,
3396 .head_state4 = 0x0d,
3397 .head_state5 = 0x0f,
3406 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3407 static const u8 tegra124_sor_lane_map[4] = {
3411 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3413 { 0x13, 0x19, 0x1e, 0x28 },
3414 { 0x1e, 0x25, 0x2d, },
3418 { 0x12, 0x17, 0x1b, 0x25 },
3419 { 0x1c, 0x23, 0x2a, },
3423 { 0x12, 0x16, 0x1a, 0x22 },
3424 { 0x1b, 0x20, 0x27, },
3428 { 0x11, 0x14, 0x17, 0x1f },
3429 { 0x19, 0x1e, 0x24, },
3435 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3437 { 0x00, 0x09, 0x13, 0x25 },
3438 { 0x00, 0x0f, 0x1e, },
3442 { 0x00, 0x0a, 0x14, 0x28 },
3443 { 0x00, 0x0f, 0x1e, },
3447 { 0x00, 0x0a, 0x14, 0x28 },
3448 { 0x00, 0x0f, 0x1e, },
3452 { 0x00, 0x0a, 0x14, 0x28 },
3453 { 0x00, 0x0f, 0x1e, },
3459 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3461 { 0x00, 0x00, 0x00, 0x00 },
3462 { 0x00, 0x00, 0x00, },
3466 { 0x02, 0x02, 0x04, 0x05 },
3467 { 0x02, 0x04, 0x05, },
3471 { 0x04, 0x05, 0x08, 0x0b },
3472 { 0x05, 0x09, 0x0b, },
3476 { 0x05, 0x09, 0x0b, 0x12 },
3477 { 0x09, 0x0d, 0x12, },
3483 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3485 { 0x20, 0x30, 0x40, 0x60 },
3486 { 0x30, 0x40, 0x60, },
3490 { 0x20, 0x20, 0x30, 0x50 },
3491 { 0x30, 0x40, 0x50, },
3495 { 0x20, 0x20, 0x30, 0x40, },
3496 { 0x30, 0x30, 0x40, },
3500 { 0x20, 0x20, 0x20, 0x40, },
3501 { 0x30, 0x30, 0x40, },
3507 static const struct tegra_sor_soc tegra124_sor = {
3508 .supports_edp = true,
3509 .supports_lvds = true,
3510 .supports_hdmi = false,
3511 .supports_dp = false,
3512 .regs = &tegra124_sor_regs,
3513 .has_nvdisplay = false,
3514 .xbar_cfg = tegra124_sor_xbar_cfg,
3515 .lane_map = tegra124_sor_lane_map,
3516 .voltage_swing = tegra124_sor_voltage_swing,
3517 .pre_emphasis = tegra124_sor_pre_emphasis,
3518 .post_cursor = tegra124_sor_post_cursor,
3519 .tx_pu = tegra124_sor_tx_pu,
3522 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3524 { 0x00, 0x08, 0x12, 0x24 },
3525 { 0x01, 0x0e, 0x1d, },
3529 { 0x00, 0x08, 0x12, 0x24 },
3530 { 0x00, 0x0e, 0x1d, },
3534 { 0x00, 0x08, 0x12, 0x24 },
3535 { 0x00, 0x0e, 0x1d, },
3539 { 0x00, 0x08, 0x12, 0x24 },
3540 { 0x00, 0x0e, 0x1d, },
3546 static const struct tegra_sor_soc tegra132_sor = {
3547 .supports_edp = true,
3548 .supports_lvds = true,
3549 .supports_hdmi = false,
3550 .supports_dp = false,
3551 .regs = &tegra124_sor_regs,
3552 .has_nvdisplay = false,
3553 .xbar_cfg = tegra124_sor_xbar_cfg,
3554 .lane_map = tegra124_sor_lane_map,
3555 .voltage_swing = tegra124_sor_voltage_swing,
3556 .pre_emphasis = tegra132_sor_pre_emphasis,
3557 .post_cursor = tegra124_sor_post_cursor,
3558 .tx_pu = tegra124_sor_tx_pu,
3561 static const struct tegra_sor_regs tegra210_sor_regs = {
3562 .head_state0 = 0x05,
3563 .head_state1 = 0x07,
3564 .head_state2 = 0x09,
3565 .head_state3 = 0x0b,
3566 .head_state4 = 0x0d,
3567 .head_state5 = 0x0f,
3576 static const u8 tegra210_sor_xbar_cfg[5] = {
3580 static const u8 tegra210_sor_lane_map[4] = {
3584 static const struct tegra_sor_soc tegra210_sor = {
3585 .supports_edp = true,
3586 .supports_lvds = false,
3587 .supports_hdmi = false,
3588 .supports_dp = false,
3590 .regs = &tegra210_sor_regs,
3591 .has_nvdisplay = false,
3593 .xbar_cfg = tegra210_sor_xbar_cfg,
3594 .lane_map = tegra210_sor_lane_map,
3595 .voltage_swing = tegra124_sor_voltage_swing,
3596 .pre_emphasis = tegra124_sor_pre_emphasis,
3597 .post_cursor = tegra124_sor_post_cursor,
3598 .tx_pu = tegra124_sor_tx_pu,
3601 static const struct tegra_sor_soc tegra210_sor1 = {
3602 .supports_edp = false,
3603 .supports_lvds = false,
3604 .supports_hdmi = true,
3605 .supports_dp = true,
3607 .regs = &tegra210_sor_regs,
3608 .has_nvdisplay = false,
3610 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3611 .settings = tegra210_sor_hdmi_defaults,
3612 .xbar_cfg = tegra210_sor_xbar_cfg,
3613 .lane_map = tegra210_sor_lane_map,
3614 .voltage_swing = tegra124_sor_voltage_swing,
3615 .pre_emphasis = tegra124_sor_pre_emphasis,
3616 .post_cursor = tegra124_sor_post_cursor,
3617 .tx_pu = tegra124_sor_tx_pu,
3620 static const struct tegra_sor_regs tegra186_sor_regs = {
3621 .head_state0 = 0x151,
3622 .head_state1 = 0x154,
3623 .head_state2 = 0x157,
3624 .head_state3 = 0x15a,
3625 .head_state4 = 0x15d,
3626 .head_state5 = 0x160,
3631 .dp_padctl0 = 0x168,
3632 .dp_padctl2 = 0x16a,
3635 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3637 { 0x13, 0x19, 0x1e, 0x28 },
3638 { 0x1e, 0x25, 0x2d, },
3642 { 0x12, 0x16, 0x1b, 0x25 },
3643 { 0x1c, 0x23, 0x2a, },
3647 { 0x12, 0x16, 0x1a, 0x22 },
3648 { 0x1b, 0x20, 0x27, },
3652 { 0x11, 0x14, 0x17, 0x1f },
3653 { 0x19, 0x1e, 0x24, },
3659 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3661 { 0x00, 0x08, 0x12, 0x24 },
3662 { 0x01, 0x0e, 0x1d, },
3666 { 0x00, 0x08, 0x12, 0x24 },
3667 { 0x00, 0x0e, 0x1d, },
3671 { 0x00, 0x08, 0x14, 0x24 },
3672 { 0x00, 0x0e, 0x1d, },
3676 { 0x00, 0x08, 0x12, 0x24 },
3677 { 0x00, 0x0e, 0x1d, },
3683 static const struct tegra_sor_soc tegra186_sor = {
3684 .supports_edp = false,
3685 .supports_lvds = false,
3686 .supports_hdmi = true,
3687 .supports_dp = true,
3689 .regs = &tegra186_sor_regs,
3690 .has_nvdisplay = true,
3692 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3693 .settings = tegra186_sor_hdmi_defaults,
3694 .xbar_cfg = tegra124_sor_xbar_cfg,
3695 .lane_map = tegra124_sor_lane_map,
3696 .voltage_swing = tegra186_sor_voltage_swing,
3697 .pre_emphasis = tegra186_sor_pre_emphasis,
3698 .post_cursor = tegra124_sor_post_cursor,
3699 .tx_pu = tegra124_sor_tx_pu,
3702 static const struct tegra_sor_regs tegra194_sor_regs = {
3703 .head_state0 = 0x151,
3704 .head_state1 = 0x155,
3705 .head_state2 = 0x159,
3706 .head_state3 = 0x15d,
3707 .head_state4 = 0x161,
3708 .head_state5 = 0x165,
3713 .dp_padctl0 = 0x16e,
3714 .dp_padctl2 = 0x16f,
3717 static const struct tegra_sor_soc tegra194_sor = {
3718 .supports_edp = true,
3719 .supports_lvds = false,
3720 .supports_hdmi = true,
3721 .supports_dp = true,
3723 .regs = &tegra194_sor_regs,
3724 .has_nvdisplay = true,
3726 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3727 .settings = tegra194_sor_hdmi_defaults,
3729 .xbar_cfg = tegra210_sor_xbar_cfg,
3730 .lane_map = tegra124_sor_lane_map,
3731 .voltage_swing = tegra186_sor_voltage_swing,
3732 .pre_emphasis = tegra186_sor_pre_emphasis,
3733 .post_cursor = tegra124_sor_post_cursor,
3734 .tx_pu = tegra124_sor_tx_pu,
3737 static const struct of_device_id tegra_sor_of_match[] = {
3738 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3739 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3740 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3741 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3742 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3743 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3746 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3748 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3750 struct device_node *np = sor->dev->of_node;
3756 if (sor->soc->has_nvdisplay) {
3757 err = of_property_read_u32(np, "nvidia,interface", &value);
3764 * override the default that we already set for Tegra210 and
3767 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3769 if (sor->soc->supports_edp)
3775 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3777 /* fall back to default per-SoC XBAR configuration */
3778 for (i = 0; i < 5; i++)
3779 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3781 /* copy cells to SOR XBAR configuration */
3782 for (i = 0; i < 5; i++)
3783 sor->xbar_cfg[i] = xbar_cfg[i];
3789 static irqreturn_t tegra_sor_irq(int irq, void *data)
3791 struct tegra_sor *sor = data;
3794 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3795 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3797 if (value & SOR_INT_CODEC_SCRATCH0) {
3798 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3800 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3801 unsigned int format;
3803 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3805 tegra_hda_parse_format(format, &sor->format);
3807 tegra_sor_hdmi_audio_enable(sor);
3809 tegra_sor_hdmi_audio_disable(sor);
3816 static int tegra_sor_probe(struct platform_device *pdev)
3818 struct device_node *np;
3819 struct tegra_sor *sor;
3820 struct resource *regs;
3823 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3827 sor->soc = of_device_get_match_data(&pdev->dev);
3828 sor->output.dev = sor->dev = &pdev->dev;
3830 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3831 sor->soc->num_settings *
3832 sizeof(*sor->settings),
3837 sor->num_settings = sor->soc->num_settings;
3839 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3841 sor->aux = drm_dp_aux_find_by_of_node(np);
3845 return -EPROBE_DEFER;
3847 sor->output.ddc = &sor->aux->ddc;
3851 if (sor->soc->supports_hdmi) {
3852 sor->ops = &tegra_sor_hdmi_ops;
3853 sor->pad = TEGRA_IO_PAD_HDMI;
3854 } else if (sor->soc->supports_lvds) {
3855 dev_err(&pdev->dev, "LVDS not supported yet\n");
3858 dev_err(&pdev->dev, "unknown (non-DP) support\n");
3862 if (sor->soc->supports_edp) {
3863 sor->ops = &tegra_sor_edp_ops;
3864 sor->pad = TEGRA_IO_PAD_LVDS;
3865 } else if (sor->soc->supports_dp) {
3866 sor->ops = &tegra_sor_dp_ops;
3868 dev_err(&pdev->dev, "unknown (DP) support\n");
3873 err = tegra_sor_parse_dt(sor);
3877 err = tegra_output_probe(&sor->output);
3879 dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3883 if (sor->ops && sor->ops->probe) {
3884 err = sor->ops->probe(sor);
3886 dev_err(&pdev->dev, "failed to probe %s: %d\n",
3887 sor->ops->name, err);
3892 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3893 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3894 if (IS_ERR(sor->regs)) {
3895 err = PTR_ERR(sor->regs);
3899 err = platform_get_irq(pdev, 0);
3901 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3907 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3908 dev_name(sor->dev), sor);
3910 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3914 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3915 if (IS_ERR(sor->rst)) {
3916 err = PTR_ERR(sor->rst);
3918 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3919 dev_err(&pdev->dev, "failed to get reset control: %d\n",
3925 * At this point, the reset control is most likely being used
3926 * by the generic power domain implementation. With any luck
3927 * the power domain will have taken care of resetting the SOR
3928 * and we don't have to do anything.
3933 sor->clk = devm_clk_get(&pdev->dev, NULL);
3934 if (IS_ERR(sor->clk)) {
3935 err = PTR_ERR(sor->clk);
3936 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3940 if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3941 struct device_node *np = pdev->dev.of_node;
3945 * For backwards compatibility with Tegra210 device trees,
3946 * fall back to the old clock name "source" if the new "out"
3947 * clock is not available.
3949 if (of_property_match_string(np, "clock-names", "out") < 0)
3954 sor->clk_out = devm_clk_get(&pdev->dev, name);
3955 if (IS_ERR(sor->clk_out)) {
3956 err = PTR_ERR(sor->clk_out);
3957 dev_err(sor->dev, "failed to get %s clock: %d\n",
3962 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3963 sor->clk_out = sor->clk;
3966 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3967 if (IS_ERR(sor->clk_parent)) {
3968 err = PTR_ERR(sor->clk_parent);
3969 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3973 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3974 if (IS_ERR(sor->clk_safe)) {
3975 err = PTR_ERR(sor->clk_safe);
3976 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3980 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3981 if (IS_ERR(sor->clk_dp)) {
3982 err = PTR_ERR(sor->clk_dp);
3983 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3988 * Starting with Tegra186, the BPMP provides an implementation for
3989 * the pad output clock, so we have to look it up from device tree.
3991 sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3992 if (IS_ERR(sor->clk_pad)) {
3993 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3994 err = PTR_ERR(sor->clk_pad);
3999 * If the pad output clock is not available, then we assume
4000 * we're on Tegra210 or earlier and have to provide our own
4003 sor->clk_pad = NULL;
4007 * The bootloader may have set up the SOR such that it's module clock
4008 * is sourced by one of the display PLLs. However, that doesn't work
4009 * without properly having set up other bits of the SOR.
4011 err = clk_set_parent(sor->clk_out, sor->clk_safe);
4013 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
4017 platform_set_drvdata(pdev, sor);
4018 pm_runtime_enable(&pdev->dev);
4021 * On Tegra210 and earlier, provide our own implementation for the
4024 if (!sor->clk_pad) {
4027 err = pm_runtime_get_sync(&pdev->dev);
4029 dev_err(&pdev->dev, "failed to get runtime PM: %d\n",
4034 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "sor%u_pad_clkout", sor->index);
4040 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
4041 pm_runtime_put(&pdev->dev);
4044 if (IS_ERR(sor->clk_pad)) {
4045 err = PTR_ERR(sor->clk_pad);
4046 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n",
4051 INIT_LIST_HEAD(&sor->client.list);
4052 sor->client.ops = &sor_client_ops;
4053 sor->client.dev = &pdev->dev;
4055 err = host1x_client_register(&sor->client);
4057 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
4065 if (sor->ops && sor->ops->remove)
4066 sor->ops->remove(sor);
4068 tegra_output_remove(&sor->output);
4072 static int tegra_sor_remove(struct platform_device *pdev)
4074 struct tegra_sor *sor = platform_get_drvdata(pdev);
4077 pm_runtime_disable(&pdev->dev);
4079 err = host1x_client_unregister(&sor->client);
4081 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
4086 if (sor->ops && sor->ops->remove) {
4087 err = sor->ops->remove(sor);
4089 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
4092 tegra_output_remove(&sor->output);
4098 static int tegra_sor_suspend(struct device *dev)
4100 struct tegra_sor *sor = dev_get_drvdata(dev);
4104 err = reset_control_assert(sor->rst);
4106 dev_err(dev, "failed to assert reset: %d\n", err);
4110 reset_control_release(sor->rst);
4113 usleep_range(1000, 2000);
4115 clk_disable_unprepare(sor->clk);
4120 static int tegra_sor_resume(struct device *dev)
4122 struct tegra_sor *sor = dev_get_drvdata(dev);
4125 err = clk_prepare_enable(sor->clk);
4127 dev_err(dev, "failed to enable clock: %d\n", err);
4131 usleep_range(1000, 2000);
4134 err = reset_control_acquire(sor->rst);
4136 dev_err(dev, "failed to acquire reset: %d\n", err);
4137 clk_disable_unprepare(sor->clk);
4141 err = reset_control_deassert(sor->rst);
4143 dev_err(dev, "failed to deassert reset: %d\n", err);
4144 reset_control_release(sor->rst);
4145 clk_disable_unprepare(sor->clk);
4154 static const struct dev_pm_ops tegra_sor_pm_ops = {
4155 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL)
4158 struct platform_driver tegra_sor_driver = {
4160 .name = "tegra-sor",
4161 .of_match_table = tegra_sor_of_match,
4162 .pm = &tegra_sor_pm_ops,
4164 .probe = tegra_sor_probe,
4165 .remove = tegra_sor_remove,