1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, NVIDIA Corporation.
7 #include <linux/delay.h>
8 #include <linux/host1x.h>
9 #include <linux/iommu.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
18 #include <soc/tegra/pmc.h>
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
39 struct reset_control *rst;
41 /* Platform configuration */
42 const struct vic_config *config;
45 static inline struct vic *to_vic(struct tegra_drm_client *client)
47 return container_of(client, struct vic, client);
50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
52 writel(value, vic->regs + offset);
55 static int vic_runtime_resume(struct device *dev)
57 struct vic *vic = dev_get_drvdata(dev);
60 err = clk_prepare_enable(vic->clk);
66 err = reset_control_deassert(vic->rst);
75 clk_disable_unprepare(vic->clk);
79 static int vic_runtime_suspend(struct device *dev)
81 struct vic *vic = dev_get_drvdata(dev);
84 err = reset_control_assert(vic->rst);
88 usleep_range(2000, 4000);
90 clk_disable_unprepare(vic->clk);
97 static int vic_boot(struct vic *vic)
99 #ifdef CONFIG_IOMMU_API
100 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
102 u32 fce_ucode_size, fce_bin_data_offset;
109 #ifdef CONFIG_IOMMU_API
110 if (vic->config->supports_sid && spec) {
113 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
114 TRANSCFG_ATT(0, TRANSCFG_SID_HW);
115 vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
117 if (spec->num_ids > 0) {
118 value = spec->ids[0] & 0xffff;
120 vic_writel(vic, value, VIC_THI_STREAMID0);
121 vic_writel(vic, value, VIC_THI_STREAMID1);
126 /* setup clockgating registers */
127 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
129 CG_WAKEUP_DLY_CNT(4),
130 NV_PVIC_MISC_PRI_VIC_CG);
132 err = falcon_boot(&vic->falcon);
136 hdr = vic->falcon.firmware.vaddr;
137 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
138 hdr = vic->falcon.firmware.vaddr +
139 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
140 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
142 falcon_execute_method(&vic->falcon, VIC_SET_APPLICATION_ID, 1);
143 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
145 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
146 (vic->falcon.firmware.paddr + fce_bin_data_offset)
149 err = falcon_wait_idle(&vic->falcon);
152 "failed to set application ID and FCE base\n");
161 static int vic_init(struct host1x_client *client)
163 struct tegra_drm_client *drm = host1x_to_drm_client(client);
164 struct drm_device *dev = dev_get_drvdata(client->parent);
165 struct tegra_drm *tegra = dev->dev_private;
166 struct vic *vic = to_vic(drm);
169 err = host1x_client_iommu_attach(client);
171 dev_err(vic->dev, "failed to attach to domain: %d\n", err);
175 vic->channel = host1x_channel_request(client);
181 client->syncpts[0] = host1x_syncpt_request(client, 0);
182 if (!client->syncpts[0]) {
187 err = tegra_drm_register_client(tegra, drm);
192 * Inherit the DMA parameters (such as maximum segment size) from the
195 client->dev->dma_parms = client->parent->dma_parms;
200 host1x_syncpt_free(client->syncpts[0]);
202 host1x_channel_put(vic->channel);
204 host1x_client_iommu_detach(client);
209 static int vic_exit(struct host1x_client *client)
211 struct tegra_drm_client *drm = host1x_to_drm_client(client);
212 struct drm_device *dev = dev_get_drvdata(client->parent);
213 struct tegra_drm *tegra = dev->dev_private;
214 struct vic *vic = to_vic(drm);
217 /* avoid a dangling pointer just in case this disappears */
218 client->dev->dma_parms = NULL;
220 err = tegra_drm_unregister_client(tegra, drm);
224 host1x_syncpt_free(client->syncpts[0]);
225 host1x_channel_put(vic->channel);
226 host1x_client_iommu_detach(client);
229 tegra_drm_free(tegra, vic->falcon.firmware.size,
230 vic->falcon.firmware.vaddr,
231 vic->falcon.firmware.paddr);
233 dma_free_coherent(vic->dev, vic->falcon.firmware.size,
234 vic->falcon.firmware.vaddr,
235 vic->falcon.firmware.paddr);
240 static const struct host1x_client_ops vic_client_ops = {
245 static int vic_load_firmware(struct vic *vic)
247 struct host1x_client *client = &vic->client.base;
248 struct tegra_drm *tegra = vic->client.drm;
254 if (vic->falcon.firmware.vaddr)
257 err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
261 size = vic->falcon.firmware.size;
263 if (!client->group) {
264 virt = dma_alloc_coherent(vic->dev, size, &phys, GFP_KERNEL);
266 err = dma_mapping_error(vic->dev, phys);
270 virt = tegra_drm_alloc(tegra, size, &phys);
273 vic->falcon.firmware.vaddr = virt;
274 vic->falcon.firmware.paddr = phys;
276 err = falcon_load_firmware(&vic->falcon);
281 * In this case we have received an IOVA from the shared domain, so we
282 * need to make sure to get the physical address so that the DMA API
283 * knows what memory pages to flush the cache for.
286 phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
288 err = dma_mapping_error(vic->dev, phys);
293 * If the DMA API mapped this through a bounce buffer, the
294 * dma_sync_single_for_device() call below will not be able
295 * to flush the caches for the right memory pages. Output a
296 * big warning in that case so that the DMA mask can be set
297 * properly and the bounce buffer avoided.
299 WARN(phys != vic->falcon.firmware.paddr,
300 "check DMA mask setting for %s\n", dev_name(vic->dev));
303 dma_sync_single_for_device(vic->dev, phys, size, DMA_TO_DEVICE);
306 dma_unmap_single(vic->dev, phys, size, DMA_TO_DEVICE);
312 dma_free_coherent(vic->dev, size, virt, phys);
314 tegra_drm_free(tegra, size, virt, phys);
319 static int vic_open_channel(struct tegra_drm_client *client,
320 struct tegra_drm_context *context)
322 struct vic *vic = to_vic(client);
325 err = pm_runtime_get_sync(vic->dev);
329 err = vic_load_firmware(vic);
337 context->channel = host1x_channel_get(vic->channel);
338 if (!context->channel) {
346 pm_runtime_put(vic->dev);
350 static void vic_close_channel(struct tegra_drm_context *context)
352 struct vic *vic = to_vic(context->client);
354 host1x_channel_put(context->channel);
356 pm_runtime_put(vic->dev);
359 static const struct tegra_drm_client_ops vic_ops = {
360 .open_channel = vic_open_channel,
361 .close_channel = vic_close_channel,
362 .submit = tegra_drm_submit,
365 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
367 static const struct vic_config vic_t124_config = {
368 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
370 .supports_sid = false,
373 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
375 static const struct vic_config vic_t210_config = {
376 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
378 .supports_sid = false,
381 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
383 static const struct vic_config vic_t186_config = {
384 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
386 .supports_sid = true,
389 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
391 static const struct vic_config vic_t194_config = {
392 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
394 .supports_sid = true,
397 static const struct of_device_id vic_match[] = {
398 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
399 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
400 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
401 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
405 static int vic_probe(struct platform_device *pdev)
407 struct device *dev = &pdev->dev;
408 struct host1x_syncpt **syncpts;
409 struct resource *regs;
413 /* inherit DMA mask from host1x parent */
414 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
416 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
420 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
424 vic->config = of_device_get_match_data(dev);
426 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
430 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432 dev_err(&pdev->dev, "failed to get registers\n");
436 vic->regs = devm_ioremap_resource(dev, regs);
437 if (IS_ERR(vic->regs))
438 return PTR_ERR(vic->regs);
440 vic->clk = devm_clk_get(dev, NULL);
441 if (IS_ERR(vic->clk)) {
442 dev_err(&pdev->dev, "failed to get clock\n");
443 return PTR_ERR(vic->clk);
446 if (!dev->pm_domain) {
447 vic->rst = devm_reset_control_get(dev, "vic");
448 if (IS_ERR(vic->rst)) {
449 dev_err(&pdev->dev, "failed to get reset\n");
450 return PTR_ERR(vic->rst);
454 vic->falcon.dev = dev;
455 vic->falcon.regs = vic->regs;
457 err = falcon_init(&vic->falcon);
461 platform_set_drvdata(pdev, vic);
463 INIT_LIST_HEAD(&vic->client.base.list);
464 vic->client.base.ops = &vic_client_ops;
465 vic->client.base.dev = dev;
466 vic->client.base.class = HOST1X_CLASS_VIC;
467 vic->client.base.syncpts = syncpts;
468 vic->client.base.num_syncpts = 1;
471 INIT_LIST_HEAD(&vic->client.list);
472 vic->client.version = vic->config->version;
473 vic->client.ops = &vic_ops;
475 err = host1x_client_register(&vic->client.base);
477 dev_err(dev, "failed to register host1x client: %d\n", err);
481 pm_runtime_enable(&pdev->dev);
482 if (!pm_runtime_enabled(&pdev->dev)) {
483 err = vic_runtime_resume(&pdev->dev);
485 goto unregister_client;
491 host1x_client_unregister(&vic->client.base);
493 falcon_exit(&vic->falcon);
498 static int vic_remove(struct platform_device *pdev)
500 struct vic *vic = platform_get_drvdata(pdev);
503 err = host1x_client_unregister(&vic->client.base);
505 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
510 if (pm_runtime_enabled(&pdev->dev))
511 pm_runtime_disable(&pdev->dev);
513 vic_runtime_suspend(&pdev->dev);
515 falcon_exit(&vic->falcon);
520 static const struct dev_pm_ops vic_pm_ops = {
521 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
524 struct platform_driver tegra_vic_driver = {
527 .of_match_table = vic_match,
531 .remove = vic_remove,
534 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
535 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
537 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
538 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
540 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
541 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
543 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
544 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);