1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2015-2018 Broadcom */
4 #include <linux/mm_types.h>
6 #include <drm/drm_encoder.h>
7 #include <drm/drm_gem.h>
8 #include <drm/drm_gem_shmem_helper.h>
9 #include <drm/gpu_scheduler.h>
10 #include "uapi/drm/v3d_drm.h"
12 #define GMP_GRANULARITY (128 * 1024)
14 /* Enum for each of the V3D queues. */
21 #define V3D_MAX_QUEUES (V3D_TFU + 1)
23 struct v3d_queue_state {
24 struct drm_gpu_scheduler sched;
31 struct drm_device drm;
33 /* Short representation (e.g. 33, 41) of the V3D tech version
40 struct platform_device *pdev;
41 void __iomem *hub_regs;
42 void __iomem *core_regs[3];
43 void __iomem *bridge_regs;
44 void __iomem *gca_regs;
46 struct reset_control *reset;
48 /* Virtual and DMA addresses of the single shared page table. */
52 /* Virtual and DMA addresses of the MMU's scratch page. When
53 * a read or write is invalid in the MMU, it will be
57 dma_addr_t mmu_scratch_paddr;
59 /* Number of V3D cores. */
62 /* Allocator managing the address space. All units are in
68 struct work_struct overflow_mem_work;
70 struct v3d_exec_info *bin_job;
71 struct v3d_exec_info *render_job;
72 struct v3d_tfu_job *tfu_job;
74 struct v3d_queue_state queue[V3D_MAX_QUEUES];
76 /* Spinlock used to synchronize the overflow memory
77 * management against bin job submission.
81 /* Protects bo_stats */
84 /* Lock taken when resetting the GPU, to keep multiple
85 * processes from trying to park the scheduler threads and
88 struct mutex reset_lock;
90 /* Lock taken when creating and pushing the GPU scheduler
91 * jobs, to keep the sched-fence seqnos in order.
93 struct mutex sched_lock;
101 static inline struct v3d_dev *
102 to_v3d_dev(struct drm_device *dev)
104 return (struct v3d_dev *)dev->dev_private;
107 /* The per-fd struct, which tracks the MMU mappings. */
108 struct v3d_file_priv {
111 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
115 struct drm_gem_shmem_object base;
117 struct drm_mm_node node;
119 /* List entry for the BO's position in
120 * v3d_exec_info->unref_list
122 struct list_head unref_head;
125 static inline struct v3d_bo *
126 to_v3d_bo(struct drm_gem_object *bo)
128 return (struct v3d_bo *)bo;
132 struct dma_fence base;
133 struct drm_device *dev;
134 /* v3d seqno for signaled() test */
136 enum v3d_queue queue;
139 static inline struct v3d_fence *
140 to_v3d_fence(struct dma_fence *fence)
142 return (struct v3d_fence *)fence;
145 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
146 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
148 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
149 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
151 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
152 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
154 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
155 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
158 struct drm_sched_job base;
160 struct v3d_exec_info *exec;
162 /* An optional fence userspace can pass in for the job to depend on. */
163 struct dma_fence *in_fence;
165 /* v3d fence to be signaled by IRQ handler when the job is complete. */
166 struct dma_fence *done_fence;
168 /* GPU virtual addresses of the start/end of the CL job. */
171 u32 timedout_ctca, timedout_ctra;
174 struct v3d_exec_info {
177 struct v3d_job bin, render;
179 /* Fence for when the scheduler considers the binner to be
180 * done, for render to depend on.
182 struct dma_fence *bin_done_fence;
184 /* Fence for when the scheduler considers the render to be
185 * done, for when the BOs reservations should be complete.
187 struct dma_fence *render_done_fence;
189 struct kref refcount;
191 /* This is the array of BOs that were looked up at the start of exec. */
195 /* List of overflow BOs used in the job that need to be
196 * released once the job is complete.
198 struct list_head unref_list;
200 /* Submitted tile memory allocation start/size, tile state. */
205 struct drm_sched_job base;
207 struct drm_v3d_submit_tfu args;
209 /* An optional fence userspace can pass in for the job to depend on. */
210 struct dma_fence *in_fence;
212 /* v3d fence to be signaled by IRQ handler when the job is complete. */
213 struct dma_fence *done_fence;
217 struct kref refcount;
219 /* This is the array of BOs that were looked up at the start of exec. */
220 struct v3d_bo *bo[4];
224 * _wait_for - magic (register) wait macro
226 * Does the right thing for modeset paths when run under kdgb or similar atomic
227 * contexts. Note that it's important that we check the condition again after
228 * having timed out, since the timeout could be due to preemption or similar and
229 * we've never had a chance to check the condition before the timeout.
231 #define wait_for(COND, MS) ({ \
232 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
235 if (time_after(jiffies, timeout__)) { \
237 ret__ = -ETIMEDOUT; \
245 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
247 /* nsecs_to_jiffies64() does not guard against overflow */
248 if (NSEC_PER_SEC % HZ &&
249 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
250 return MAX_JIFFY_OFFSET;
252 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
256 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
257 void v3d_free_object(struct drm_gem_object *gem_obj);
258 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
260 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
261 struct drm_file *file_priv);
262 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
263 struct drm_file *file_priv);
264 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
265 struct drm_file *file_priv);
266 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
267 struct dma_buf_attachment *attach,
268 struct sg_table *sgt);
271 int v3d_debugfs_init(struct drm_minor *minor);
274 extern const struct dma_fence_ops v3d_fence_ops;
275 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
278 int v3d_gem_init(struct drm_device *dev);
279 void v3d_gem_destroy(struct drm_device *dev);
280 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
281 struct drm_file *file_priv);
282 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
283 struct drm_file *file_priv);
284 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
285 struct drm_file *file_priv);
286 void v3d_exec_put(struct v3d_exec_info *exec);
287 void v3d_tfu_job_put(struct v3d_tfu_job *exec);
288 void v3d_reset(struct v3d_dev *v3d);
289 void v3d_invalidate_caches(struct v3d_dev *v3d);
292 int v3d_irq_init(struct v3d_dev *v3d);
293 void v3d_irq_enable(struct v3d_dev *v3d);
294 void v3d_irq_disable(struct v3d_dev *v3d);
295 void v3d_irq_reset(struct v3d_dev *v3d);
298 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
300 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
301 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
302 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
305 int v3d_sched_init(struct v3d_dev *v3d);
306 void v3d_sched_fini(struct v3d_dev *v3d);