drivers/gpu/drm/vc4/vc4_crtc.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 CRTC module
  11  *
  12  * In VC4, the Pixel Valve is what most closely corresponds to the
  13  * DRM's concept of a CRTC.  The PV generates video timings from the
  14  * encoder's clock plus its configuration.  It pulls scaled pixels from
  15  * the HVS at that timing, and feeds it to the encoder.
  16  *
  17  * However, the DRM CRTC also collects the configuration of all the
  18  * DRM planes attached to it.  As a result, the CRTC is also
  19  * responsible for writing the display list for the HVS channel that
  20  * the CRTC will use.
  21  *
  22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  24  * image domain can feed either HDMI or the SDTV controller.  The
  25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  26  * SDTV, etc.) according to which output type is chosen in the mux.
  27  *
  28  * For power management, the pixel valve's registers are all clocked
  29  * by the AXI clock, while the timings and FIFOs make use of the
  30  * output-specific clock.  Since the encoders also directly consume
  31  * the CPRMAN clocks, and know what timings they need, they are the
  32  * ones that set the clock.
  33  */
  34
  35 #include <linux/clk.h>
  36 #include <linux/component.h>
  37 #include <linux/of_device.h>
  38
  39 #include <drm/drm_atomic.h>
  40 #include <drm/drm_atomic_helper.h>
  41 #include <drm/drm_atomic_uapi.h>
  42 #include <drm/drm_fb_cma_helper.h>
  43 #include <drm/drm_print.h>
  44 #include <drm/drm_probe_helper.h>
  45 #include <drm/drm_vblank.h>
  46
  47 #include "vc4_drv.h"
  48 #include "vc4_regs.h"
  49
  50 struct vc4_crtc_state {
  51         struct drm_crtc_state base;
  52         /* Dlist area for this CRTC configuration. */
  53         struct drm_mm_node mm;
  54         bool feed_txp;
  55         bool txp_armed;
  56
  57         struct {
  58                 unsigned int left;
  59                 unsigned int right;
  60                 unsigned int top;
  61                 unsigned int bottom;
  62         } margins;
  63 };
  64
  65 static inline struct vc4_crtc_state *
  66 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  67 {
  68         return (struct vc4_crtc_state *)crtc_state;
  69 }
  70
  71 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  72 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  73
  74 static const struct debugfs_reg32 crtc_regs[] = {
  75         VC4_REG32(PV_CONTROL),
  76         VC4_REG32(PV_V_CONTROL),
  77         VC4_REG32(PV_VSYNCD_EVEN),
  78         VC4_REG32(PV_HORZA),
  79         VC4_REG32(PV_HORZB),
  80         VC4_REG32(PV_VERTA),
  81         VC4_REG32(PV_VERTB),
  82         VC4_REG32(PV_VERTA_EVEN),
  83         VC4_REG32(PV_VERTB_EVEN),
  84         VC4_REG32(PV_INTEN),
  85         VC4_REG32(PV_INTSTAT),
  86         VC4_REG32(PV_STAT),
  87         VC4_REG32(PV_HACT_ACT),
  88 };
  89
  90 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
  91                              bool in_vblank_irq, int *vpos, int *hpos,
  92                              ktime_t *stime, ktime_t *etime,
  93                              const struct drm_display_mode *mode)
  94 {
  95         struct vc4_dev *vc4 = to_vc4_dev(dev);
  96         struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
  97         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  98         u32 val;
  99         int fifo_lines;
 100         int vblank_lines;
 101         bool ret = false;
 102
 103         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 104
 105         /* Get optional system timestamp before query. */
 106         if (stime)
 107                 *stime = ktime_get();
 108
 109         /*
 110          * Read vertical scanline which is currently composed for our
 111          * pixelvalve by the HVS, and also the scaler status.
 112          */
 113         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 114
 115         /* Get optional system timestamp after query. */
 116         if (etime)
 117                 *etime = ktime_get();
 118
 119         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 120
 121         /* Vertical position of hvs composed scanline. */
 122         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 123         *hpos = 0;
 124
 125         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 126                 *vpos /= 2;
 127
 128                 /* Use hpos to correct for field offset in interlaced mode. */
 129                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 130                         *hpos += mode->crtc_htotal / 2;
 131         }
 132
 133         /* This is the offset we need for translating hvs -> pv scanout pos. */
 134         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 135
 136         if (fifo_lines > 0)
 137                 ret = true;
 138
 139         /* HVS more than fifo_lines into frame for compositing? */
 140         if (*vpos > fifo_lines) {
 141                 /*
 142                  * We are in active scanout and can get some meaningful results
 143                  * from HVS. The actual PV scanout can not trail behind more
 144                  * than fifo_lines as that is the fifo's capacity. Assume that
 145                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 146                  * refilling the fifo and PV consuming from the fifo, ie.
 147                  * whenever the PV consumes and frees up a scanline in the
 148                  * fifo, the HVS will immediately refill it, therefore
 149                  * incrementing vpos. Therefore we choose HVS read position -
 150                  * fifo size in scanlines as a estimate of the real scanout
 151                  * position of the PV.
 152                  */
 153                 *vpos -= fifo_lines + 1;
 154
 155                 return ret;
 156         }
 157
 158         /*
 159          * Less: This happens when we are in vblank and the HVS, after getting
 160          * the VSTART restart signal from the PV, just started refilling its
 161          * fifo with new lines from the top-most lines of the new framebuffers.
 162          * The PV does not scan out in vblank, so does not remove lines from
 163          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 164          * We can't get meaningful readings wrt. scanline position of the PV
 165          * and need to make things up in a approximative but consistent way.
 166          */
 167         vblank_lines = mode->vtotal - mode->vdisplay;
 168
 169         if (in_vblank_irq) {
 170                 /*
 171                  * Assume the irq handler got called close to first
 172                  * line of vblank, so PV has about a full vblank
 173                  * scanlines to go, and as a base timestamp use the
 174                  * one taken at entry into vblank irq handler, so it
 175                  * is not affected by random delays due to lock
 176                  * contention on event_lock or vblank_time lock in
 177                  * the core.
 178                  */
 179                 *vpos = -vblank_lines;
 180
 181                 if (stime)
 182                         *stime = vc4_crtc->t_vblank;
 183                 if (etime)
 184                         *etime = vc4_crtc->t_vblank;
 185
 186                 /*
 187                  * If the HVS fifo is not yet full then we know for certain
 188                  * we are at the very beginning of vblank, as the hvs just
 189                  * started refilling, and the stime and etime timestamps
 190                  * truly correspond to start of vblank.
 191                  *
 192                  * Unfortunately there's no way to report this to upper levels
 193                  * and make it more useful.
 194                  */
 195         } else {
 196                 /*
 197                  * No clue where we are inside vblank. Return a vpos of zero,
 198                  * which will cause calling code to just return the etime
 199                  * timestamp uncorrected. At least this is no worse than the
 200                  * standard fallback.
 201                  */
 202                 *vpos = 0;
 203         }
 204
 205         return ret;
 206 }
 207
 208 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 209 {
 210         drm_crtc_cleanup(crtc);
 211 }
 212
 213 static void
 214 vc4_crtc_lut_load(struct drm_crtc *crtc)
 215 {
 216         struct drm_device *dev = crtc->dev;
 217         struct vc4_dev *vc4 = to_vc4_dev(dev);
 218         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 219         u32 i;
 220
 221         /* The LUT memory is laid out with each HVS channel in order,
 222          * each of which takes 256 writes for R, 256 for G, then 256
 223          * for B.
 224          */
 225         HVS_WRITE(SCALER_GAMADDR,
 226                   SCALER_GAMADDR_AUTOINC |
 227                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 228
 229         for (i = 0; i < crtc->gamma_size; i++)
 230                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 231         for (i = 0; i < crtc->gamma_size; i++)
 232                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 233         for (i = 0; i < crtc->gamma_size; i++)
 234                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 235 }
 236
 237 static void
 238 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 239 {
 240         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 241         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 242         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 243         u32 i;
 244
 245         for (i = 0; i < length; i++) {
 246                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 247                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 248                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 249         }
 250
 251         vc4_crtc_lut_load(crtc);
 252 }
 253
 254 static u32 vc4_get_fifo_full_level(u32 format)
 255 {
 256         static const u32 fifo_len_bytes = 64;
 257         static const u32 hvs_latency_pix = 6;
 258
 259         switch (format) {
 260         case PV_CONTROL_FORMAT_DSIV_16:
 261         case PV_CONTROL_FORMAT_DSIC_16:
 262                 return fifo_len_bytes - 2 * hvs_latency_pix;
 263         case PV_CONTROL_FORMAT_DSIV_18:
 264                 return fifo_len_bytes - 14;
 265         case PV_CONTROL_FORMAT_24:
 266         case PV_CONTROL_FORMAT_DSIV_24:
 267         default:
 268                 return fifo_len_bytes - 3 * hvs_latency_pix;
 269         }
 270 }
 271
 272 /*
 273  * Returns the encoder attached to the CRTC.
 274  *
 275  * VC4 can only scan out to one encoder at a time, while the DRM core
 276  * allows drivers to push pixels to more than one encoder from the
 277  * same CRTC.
 278  */
 279 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 280 {
 281         struct drm_connector *connector;
 282         struct drm_connector_list_iter conn_iter;
 283
 284         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 285         drm_for_each_connector_iter(connector, &conn_iter) {
 286                 if (connector->state->crtc == crtc) {
 287                         drm_connector_list_iter_end(&conn_iter);
 288                         return connector->encoder;
 289                 }
 290         }
 291         drm_connector_list_iter_end(&conn_iter);
 292
 293         return NULL;
 294 }
 295
 296 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 297 {
 298         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 299         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 300         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 301         struct drm_crtc_state *state = crtc->state;
 302         struct drm_display_mode *mode = &state->adjusted_mode;
 303         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 304         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 305         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 306                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 307         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 308
 309         /* Reset the PV fifo. */
 310         CRTC_WRITE(PV_CONTROL, 0);
 311         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 312         CRTC_WRITE(PV_CONTROL, 0);
 313
 314         CRTC_WRITE(PV_HORZA,
 315                    VC4_SET_FIELD((mode->htotal -
 316                                   mode->hsync_end) * pixel_rep,
 317                                  PV_HORZA_HBP) |
 318                    VC4_SET_FIELD((mode->hsync_end -
 319                                   mode->hsync_start) * pixel_rep,
 320                                  PV_HORZA_HSYNC));
 321         CRTC_WRITE(PV_HORZB,
 322                    VC4_SET_FIELD((mode->hsync_start -
 323                                   mode->hdisplay) * pixel_rep,
 324                                  PV_HORZB_HFP) |
 325                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 326
 327         CRTC_WRITE(PV_VERTA,
 328                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 329                                  PV_VERTA_VBP) |
 330                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 331                                  PV_VERTA_VSYNC));
 332         CRTC_WRITE(PV_VERTB,
 333                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 334                                  PV_VERTB_VFP) |
 335                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 336
 337         if (interlace) {
 338                 CRTC_WRITE(PV_VERTA_EVEN,
 339                            VC4_SET_FIELD(mode->crtc_vtotal -
 340                                          mode->crtc_vsync_end - 1,
 341                                          PV_VERTA_VBP) |
 342                            VC4_SET_FIELD(mode->crtc_vsync_end -
 343                                          mode->crtc_vsync_start,
 344                                          PV_VERTA_VSYNC));
 345                 CRTC_WRITE(PV_VERTB_EVEN,
 346                            VC4_SET_FIELD(mode->crtc_vsync_start -
 347                                          mode->crtc_vdisplay,
 348                                          PV_VERTB_VFP) |
 349                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 350
 351                 /* We set up first field even mode for HDMI.  VEC's
 352                  * NTSC mode would want first field odd instead, once
 353                  * we support it (to do so, set ODD_FIRST and put the
 354                  * delay in VSYNCD_EVEN instead).
 355                  */
 356                 CRTC_WRITE(PV_V_CONTROL,
 357                            PV_VCONTROL_CONTINUOUS |
 358                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 359                            PV_VCONTROL_INTERLACE |
 360                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 361                                          PV_VCONTROL_ODD_DELAY));
 362                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 363         } else {
 364                 CRTC_WRITE(PV_V_CONTROL,
 365                            PV_VCONTROL_CONTINUOUS |
 366                            (is_dsi ? PV_VCONTROL_DSI : 0));
 367         }
 368
 369         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 370
 371         CRTC_WRITE(PV_CONTROL,
 372                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 373                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 374                                  PV_CONTROL_FIFO_LEVEL) |
 375                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 376                    PV_CONTROL_CLR_AT_START |
 377                    PV_CONTROL_TRIGGER_UNDERFLOW |
 378                    PV_CONTROL_WAIT_HSTART |
 379                    VC4_SET_FIELD(vc4_encoder->clock_select,
 380                                  PV_CONTROL_CLK_SELECT) |
 381                    PV_CONTROL_FIFO_CLR |
 382                    PV_CONTROL_EN);
 383 }
 384
 385 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 386 {
 387         struct drm_device *dev = crtc->dev;
 388         struct vc4_dev *vc4 = to_vc4_dev(dev);
 389         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 390         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 391         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 392         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 393         bool debug_dump_regs = false;
 394
 395         if (debug_dump_regs) {
 396                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 397                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 398                          drm_crtc_index(crtc));
 399                 drm_print_regset32(&p, &vc4_crtc->regset);
 400         }
 401
 402         if (vc4_crtc->channel == 2) {
 403                 u32 dispctrl;
 404                 u32 dsp3_mux;
 405
 406                 /*
 407                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 408                  * FIFO X'.
 409                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 410                  *
 411                  * DSP3 is connected to FIFO2 unless the transposer is
 412                  * enabled. In this case, FIFO 2 is directly accessed by the
 413                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 414                  * route.
 415                  */
 416                 if (vc4_state->feed_txp)
 417                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 418                 else
 419                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 420
 421                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 422                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 423                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 424         }
 425
 426         if (!vc4_state->feed_txp)
 427                 vc4_crtc_config_pv(crtc);
 428
 429         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 430                   SCALER_DISPBKGND_AUTOHS |
 431                   SCALER_DISPBKGND_GAMMA |
 432                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 433
 434         /* Reload the LUT, since the SRAMs would have been disabled if
 435          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 436          */
 437         vc4_crtc_lut_load(crtc);
 438
 439         if (debug_dump_regs) {
 440                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 441                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 442                          drm_crtc_index(crtc));
 443                 drm_print_regset32(&p, &vc4_crtc->regset);
 444         }
 445 }
 446
 447 static void require_hvs_enabled(struct drm_device *dev)
 448 {
 449         struct vc4_dev *vc4 = to_vc4_dev(dev);
 450
 451         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 452                      SCALER_DISPCTRL_ENABLE);
 453 }
 454
 455 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 456                                     struct drm_crtc_state *old_state)
 457 {
 458         struct drm_device *dev = crtc->dev;
 459         struct vc4_dev *vc4 = to_vc4_dev(dev);
 460         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 461         u32 chan = vc4_crtc->channel;
 462         int ret;
 463         require_hvs_enabled(dev);
 464
 465         /* Disable vblank irq handling before crtc is disabled. */
 466         drm_crtc_vblank_off(crtc);
 467
 468         CRTC_WRITE(PV_V_CONTROL,
 469                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 470         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 471         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 472
 473         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 474             SCALER_DISPCTRLX_ENABLE) {
 475                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 476                           SCALER_DISPCTRLX_RESET);
 477
 478                 /* While the docs say that reset is self-clearing, it
 479                  * seems it doesn't actually.
 480                  */
 481                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 482         }
 483
 484         /* Once we leave, the scaler should be disabled and its fifo empty. */
 485
 486         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 487
 488         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 489                                    SCALER_DISPSTATX_MODE) !=
 490                      SCALER_DISPSTATX_MODE_DISABLED);
 491
 492         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 493                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 494                      SCALER_DISPSTATX_EMPTY);
 495
 496         /*
 497          * Make sure we issue a vblank event after disabling the CRTC if
 498          * someone was waiting it.
 499          */
 500         if (crtc->state->event) {
 501                 unsigned long flags;
 502
 503                 spin_lock_irqsave(&dev->event_lock, flags);
 504                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 505                 crtc->state->event = NULL;
 506                 spin_unlock_irqrestore(&dev->event_lock, flags);
 507         }
 508 }
 509
 510 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 511 {
 512         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 513
 514         vc4_state->txp_armed = true;
 515 }
 516
 517 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 518 {
 519         struct drm_device *dev = crtc->dev;
 520         struct vc4_dev *vc4 = to_vc4_dev(dev);
 521         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 522         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 523
 524         if (crtc->state->event) {
 525                 unsigned long flags;
 526
 527                 crtc->state->event->pipe = drm_crtc_index(crtc);
 528
 529                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 530
 531                 spin_lock_irqsave(&dev->event_lock, flags);
 532
 533                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 534                         vc4_crtc->event = crtc->state->event;
 535                         crtc->state->event = NULL;
 536                 }
 537
 538                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 539                           vc4_state->mm.start);
 540
 541                 spin_unlock_irqrestore(&dev->event_lock, flags);
 542         } else {
 543                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 544                           vc4_state->mm.start);
 545         }
 546 }
 547
 548 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 549                                    struct drm_crtc_state *old_state)
 550 {
 551         struct drm_device *dev = crtc->dev;
 552         struct vc4_dev *vc4 = to_vc4_dev(dev);
 553         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 554         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 555         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 556
 557         require_hvs_enabled(dev);
 558
 559         /* Enable vblank irq handling before crtc is started otherwise
 560          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 561          */
 562         drm_crtc_vblank_on(crtc);
 563         vc4_crtc_update_dlist(crtc);
 564
 565         /* Turn on the scaler, which will wait for vstart to start
 566          * compositing.
 567          * When feeding the transposer, we should operate in oneshot
 568          * mode.
 569          */
 570         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 571                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 572                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 573                   SCALER_DISPCTRLX_ENABLE |
 574                   (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
 575
 576         /* When feeding the transposer block the pixelvalve is unneeded and
 577          * should not be enabled.
 578          */
 579         if (!vc4_state->feed_txp)
 580                 CRTC_WRITE(PV_V_CONTROL,
 581                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 582 }
 583
 584 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 585                                                 const struct drm_display_mode *mode)
 586 {
 587         /* Do not allow doublescan modes from user space */
 588         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 589                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 590                               crtc->base.id);
 591                 return MODE_NO_DBLESCAN;
 592         }
 593
 594         return MODE_OK;
 595 }
 596
 597 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 598                           unsigned int *left, unsigned int *right,
 599                           unsigned int *top, unsigned int *bottom)
 600 {
 601         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 602         struct drm_connector_state *conn_state;
 603         struct drm_connector *conn;
 604         int i;
 605
 606         *left = vc4_state->margins.left;
 607         *right = vc4_state->margins.right;
 608         *top = vc4_state->margins.top;
 609         *bottom = vc4_state->margins.bottom;
 610
 611         /* We have to interate over all new connector states because
 612          * vc4_crtc_get_margins() might be called before
 613          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 614          * might be outdated.
 615          */
 616         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 617                 if (conn_state->crtc != state->crtc)
 618                         continue;
 619
 620                 *left = conn_state->tv.margins.left;
 621                 *right = conn_state->tv.margins.right;
 622                 *top = conn_state->tv.margins.top;
 623                 *bottom = conn_state->tv.margins.bottom;
 624                 break;
 625         }
 626 }
 627
 628 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 629                                  struct drm_crtc_state *state)
 630 {
 631         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 632         struct drm_device *dev = crtc->dev;
 633         struct vc4_dev *vc4 = to_vc4_dev(dev);
 634         struct drm_plane *plane;
 635         unsigned long flags;
 636         const struct drm_plane_state *plane_state;
 637         struct drm_connector *conn;
 638         struct drm_connector_state *conn_state;
 639         u32 dlist_count = 0;
 640         int ret, i;
 641
 642         /* The pixelvalve can only feed one encoder (and encoders are
 643          * 1:1 with connectors.)
 644          */
 645         if (hweight32(state->connector_mask) > 1)
 646                 return -EINVAL;
 647
 648         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 649                 dlist_count += vc4_plane_dlist_size(plane_state);
 650
 651         dlist_count++; /* Account for SCALER_CTL0_END. */
 652
 653         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 654         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 655                                  dlist_count);
 656         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 657         if (ret)
 658                 return ret;
 659
 660         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 661                 if (conn_state->crtc != crtc)
 662                         continue;
 663
 664                 /* The writeback connector is implemented using the transposer
 665                  * block which is directly taking its data from the HVS FIFO.
 666                  */
 667                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 668                         state->no_vblank = true;
 669                         vc4_state->feed_txp = true;
 670                 } else {
 671                         state->no_vblank = false;
 672                         vc4_state->feed_txp = false;
 673                 }
 674
 675                 vc4_state->margins.left = conn_state->tv.margins.left;
 676                 vc4_state->margins.right = conn_state->tv.margins.right;
 677                 vc4_state->margins.top = conn_state->tv.margins.top;
 678                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 679                 break;
 680         }
 681
 682         return 0;
 683 }
 684
 685 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 686                                   struct drm_crtc_state *old_state)
 687 {
 688         struct drm_device *dev = crtc->dev;
 689         struct vc4_dev *vc4 = to_vc4_dev(dev);
 690         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 691         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 692         struct drm_plane *plane;
 693         struct vc4_plane_state *vc4_plane_state;
 694         bool debug_dump_regs = false;
 695         bool enable_bg_fill = false;
 696         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 697         u32 __iomem *dlist_next = dlist_start;
 698
 699         if (debug_dump_regs) {
 700                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 701                 vc4_hvs_dump_state(dev);
 702         }
 703
 704         /* Copy all the active planes' dlist contents to the hardware dlist. */
 705         drm_atomic_crtc_for_each_plane(plane, crtc) {
 706                 /* Is this the first active plane? */
 707                 if (dlist_next == dlist_start) {
 708                         /* We need to enable background fill when a plane
 709                          * could be alpha blending from the background, i.e.
 710                          * where no other plane is underneath. It suffices to
 711                          * consider the first active plane here since we set
 712                          * needs_bg_fill such that either the first plane
 713                          * already needs it or all planes on top blend from
 714                          * the first or a lower plane.
 715                          */
 716                         vc4_plane_state = to_vc4_plane_state(plane->state);
 717                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 718                 }
 719
 720                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 721         }
 722
 723         writel(SCALER_CTL0_END, dlist_next);
 724         dlist_next++;
 725
 726         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 727
 728         if (enable_bg_fill)
 729                 /* This sets a black background color fill, as is the case
 730                  * with other DRM drivers.
 731                  */
 732                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 733                           HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
 734                           SCALER_DISPBKGND_FILL);
 735
 736         /* Only update DISPLIST if the CRTC was already running and is not
 737          * being disabled.
 738          * vc4_crtc_enable() takes care of updating the dlist just after
 739          * re-enabling VBLANK interrupts and before enabling the engine.
 740          * If the CRTC is being disabled, there's no point in updating this
 741          * information.
 742          */
 743         if (crtc->state->active && old_state->active)
 744                 vc4_crtc_update_dlist(crtc);
 745
 746         if (crtc->state->color_mgmt_changed) {
 747                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
 748
 749                 if (crtc->state->gamma_lut) {
 750                         vc4_crtc_update_gamma_lut(crtc);
 751                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 752                 } else {
 753                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 754                          * in hardware, which is the same as a linear lut that
 755                          * DRM expects us to use in absence of a user lut.
 756                          */
 757                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 758                 }
 759                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
 760         }
 761
 762         if (debug_dump_regs) {
 763                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 764                 vc4_hvs_dump_state(dev);
 765         }
 766 }
 767
 768 static int vc4_enable_vblank(struct drm_crtc *crtc)
 769 {
 770         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 771
 772         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 773
 774         return 0;
 775 }
 776
 777 static void vc4_disable_vblank(struct drm_crtc *crtc)
 778 {
 779         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 780
 781         CRTC_WRITE(PV_INTEN, 0);
 782 }
 783
 784 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 785 {
 786         struct drm_crtc *crtc = &vc4_crtc->base;
 787         struct drm_device *dev = crtc->dev;
 788         struct vc4_dev *vc4 = to_vc4_dev(dev);
 789         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 790         u32 chan = vc4_crtc->channel;
 791         unsigned long flags;
 792
 793         spin_lock_irqsave(&dev->event_lock, flags);
 794         if (vc4_crtc->event &&
 795             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 796              vc4_state->feed_txp)) {
 797                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 798                 vc4_crtc->event = NULL;
 799                 drm_crtc_vblank_put(crtc);
 800
 801                 /* Wait for the page flip to unmask the underrun to ensure that
 802                  * the display list was updated by the hardware. Before that
 803                  * happens, the HVS will be using the previous display list with
 804                  * the CRTC and encoder already reconfigured, leading to
 805                  * underruns. This can be seen when reconfiguring the CRTC.
 806                  */
 807                 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
 808         }
 809         spin_unlock_irqrestore(&dev->event_lock, flags);
 810 }
 811
 812 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 813 {
 814         crtc->t_vblank = ktime_get();
 815         drm_crtc_handle_vblank(&crtc->base);
 816         vc4_crtc_handle_page_flip(crtc);
 817 }
 818
 819 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 820 {
 821         struct vc4_crtc *vc4_crtc = data;
 822         u32 stat = CRTC_READ(PV_INTSTAT);
 823         irqreturn_t ret = IRQ_NONE;
 824
 825         if (stat & PV_INT_VFP_START) {
 826                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 827                 vc4_crtc_handle_vblank(vc4_crtc);
 828                 ret = IRQ_HANDLED;
 829         }
 830
 831         return ret;
 832 }
 833
 834 struct vc4_async_flip_state {
 835         struct drm_crtc *crtc;
 836         struct drm_framebuffer *fb;
 837         struct drm_framebuffer *old_fb;
 838         struct drm_pending_vblank_event *event;
 839
 840         struct vc4_seqno_cb cb;
 841 };
 842
 843 /* Called when the V3D execution for the BO being flipped to is done, so that
 844  * we can actually update the plane's address to point to it.
 845  */
 846 static void
 847 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 848 {
 849         struct vc4_async_flip_state *flip_state =
 850                 container_of(cb, struct vc4_async_flip_state, cb);
 851         struct drm_crtc *crtc = flip_state->crtc;
 852         struct drm_device *dev = crtc->dev;
 853         struct vc4_dev *vc4 = to_vc4_dev(dev);
 854         struct drm_plane *plane = crtc->primary;
 855
 856         vc4_plane_async_set_fb(plane, flip_state->fb);
 857         if (flip_state->event) {
 858                 unsigned long flags;
 859
 860                 spin_lock_irqsave(&dev->event_lock, flags);
 861                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 862                 spin_unlock_irqrestore(&dev->event_lock, flags);
 863         }
 864
 865         drm_crtc_vblank_put(crtc);
 866         drm_framebuffer_put(flip_state->fb);
 867
 868         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 869          * when the planes are updated through the async update path.
 870          * FIXME: we should move to generic async-page-flip when it's
 871          * available, so that we can get rid of this hand-made cleanup_fb()
 872          * logic.
 873          */
 874         if (flip_state->old_fb) {
 875                 struct drm_gem_cma_object *cma_bo;
 876                 struct vc4_bo *bo;
 877
 878                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 879                 bo = to_vc4_bo(&cma_bo->base);
 880                 vc4_bo_dec_usecnt(bo);
 881                 drm_framebuffer_put(flip_state->old_fb);
 882         }
 883
 884         kfree(flip_state);
 885
 886         up(&vc4->async_modeset);
 887 }
 888
 889 /* Implements async (non-vblank-synced) page flips.
 890  *
 891  * The page flip ioctl needs to return immediately, so we grab the
 892  * modeset semaphore on the pipe, and queue the address update for
 893  * when V3D is done with the BO being flipped to.
 894  */
 895 static int vc4_async_page_flip(struct drm_crtc *crtc,
 896                                struct drm_framebuffer *fb,
 897                                struct drm_pending_vblank_event *event,
 898                                uint32_t flags)
 899 {
 900         struct drm_device *dev = crtc->dev;
 901         struct vc4_dev *vc4 = to_vc4_dev(dev);
 902         struct drm_plane *plane = crtc->primary;
 903         int ret = 0;
 904         struct vc4_async_flip_state *flip_state;
 905         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 906         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 907
 908         /* Increment the BO usecnt here, so that we never end up with an
 909          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 910          * plane is later updated through the non-async path.
 911          * FIXME: we should move to generic async-page-flip when it's
 912          * available, so that we can get rid of this hand-made prepare_fb()
 913          * logic.
 914          */
 915         ret = vc4_bo_inc_usecnt(bo);
 916         if (ret)
 917                 return ret;
 918
 919         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 920         if (!flip_state) {
 921                 vc4_bo_dec_usecnt(bo);
 922                 return -ENOMEM;
 923         }
 924
 925         drm_framebuffer_get(fb);
 926         flip_state->fb = fb;
 927         flip_state->crtc = crtc;
 928         flip_state->event = event;
 929
 930         /* Make sure all other async modesetes have landed. */
 931         ret = down_interruptible(&vc4->async_modeset);
 932         if (ret) {
 933                 drm_framebuffer_put(fb);
 934                 vc4_bo_dec_usecnt(bo);
 935                 kfree(flip_state);
 936                 return ret;
 937         }
 938
 939         /* Save the current FB before it's replaced by the new one in
 940          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 941          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 942          * it consistent.
 943          * FIXME: we should move to generic async-page-flip when it's
 944          * available, so that we can get rid of this hand-made cleanup_fb()
 945          * logic.
 946          */
 947         flip_state->old_fb = plane->state->fb;
 948         if (flip_state->old_fb)
 949                 drm_framebuffer_get(flip_state->old_fb);
 950
 951         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 952
 953         /* Immediately update the plane's legacy fb pointer, so that later
 954          * modeset prep sees the state that will be present when the semaphore
 955          * is released.
 956          */
 957         drm_atomic_set_fb_for_plane(plane->state, fb);
 958
 959         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 960                            vc4_async_page_flip_complete);
 961
 962         /* Driver takes ownership of state on successful async commit. */
 963         return 0;
 964 }
 965
 966 static int vc4_page_flip(struct drm_crtc *crtc,
 967                          struct drm_framebuffer *fb,
 968                          struct drm_pending_vblank_event *event,
 969                          uint32_t flags,
 970                          struct drm_modeset_acquire_ctx *ctx)
 971 {
 972         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 973                 return vc4_async_page_flip(crtc, fb, event, flags);
 974         else
 975                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 976 }
 977
 978 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 979 {
 980         struct vc4_crtc_state *vc4_state, *old_vc4_state;
 981
 982         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 983         if (!vc4_state)
 984                 return NULL;
 985
 986         old_vc4_state = to_vc4_crtc_state(crtc->state);
 987         vc4_state->feed_txp = old_vc4_state->feed_txp;
 988         vc4_state->margins = old_vc4_state->margins;
 989
 990         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 991         return &vc4_state->base;
 992 }
 993
 994 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 995                                    struct drm_crtc_state *state)
 996 {
 997         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 998         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 999
1000         if (vc4_state->mm.allocated) {
1001                 unsigned long flags;
1002
1003                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1004                 drm_mm_remove_node(&vc4_state->mm);
1005                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1006
1007         }
1008
1009         drm_atomic_helper_crtc_destroy_state(crtc, state);
1010 }
1011
1012 static void
1013 vc4_crtc_reset(struct drm_crtc *crtc)
1014 {
1015         if (crtc->state)
1016                 vc4_crtc_destroy_state(crtc, crtc->state);
1017
1018         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1019         if (crtc->state)
1020                 crtc->state->crtc = crtc;
1021 }
1022
1023 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1024         .set_config = drm_atomic_helper_set_config,
1025         .destroy = vc4_crtc_destroy,
1026         .page_flip = vc4_page_flip,
1027         .set_property = NULL,
1028         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1029         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1030         .reset = vc4_crtc_reset,
1031         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1032         .atomic_destroy_state = vc4_crtc_destroy_state,
1033         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1034         .enable_vblank = vc4_enable_vblank,
1035         .disable_vblank = vc4_disable_vblank,
1036 };
1037
1038 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1039         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1040         .mode_valid = vc4_crtc_mode_valid,
1041         .atomic_check = vc4_crtc_atomic_check,
1042         .atomic_flush = vc4_crtc_atomic_flush,
1043         .atomic_enable = vc4_crtc_atomic_enable,
1044         .atomic_disable = vc4_crtc_atomic_disable,
1045 };
1046
1047 static const struct vc4_crtc_data pv0_data = {
1048         .hvs_channel = 0,
1049         .debugfs_name = "crtc0_regs",
1050         .encoder_types = {
1051                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1052                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1053         },
1054 };
1055
1056 static const struct vc4_crtc_data pv1_data = {
1057         .hvs_channel = 2,
1058         .debugfs_name = "crtc1_regs",
1059         .encoder_types = {
1060                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1061                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1062         },
1063 };
1064
1065 static const struct vc4_crtc_data pv2_data = {
1066         .hvs_channel = 1,
1067         .debugfs_name = "crtc2_regs",
1068         .encoder_types = {
1069                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1070                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1071         },
1072 };
1073
1074 static const struct of_device_id vc4_crtc_dt_match[] = {
1075         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1076         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1077         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1078         {}
1079 };
1080
1081 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1082                                         struct drm_crtc *crtc)
1083 {
1084         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1085         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1086         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1087         struct drm_encoder *encoder;
1088
1089         drm_for_each_encoder(encoder, drm) {
1090                 struct vc4_encoder *vc4_encoder;
1091                 int i;
1092
1093                 /* HVS FIFO2 can feed the TXP IP. */
1094                 if (crtc_data->hvs_channel == 2 &&
1095                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1096                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1097                         continue;
1098                 }
1099
1100                 vc4_encoder = to_vc4_encoder(encoder);
1101                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1102                         if (vc4_encoder->type == encoder_types[i]) {
1103                                 vc4_encoder->clock_select = i;
1104                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1105                                 break;
1106                         }
1107                 }
1108         }
1109 }
1110
1111 static void
1112 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1113 {
1114         struct drm_device *drm = vc4_crtc->base.dev;
1115         struct vc4_dev *vc4 = to_vc4_dev(drm);
1116         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1117         /* Top/base are supposed to be 4-pixel aligned, but the
1118          * Raspberry Pi firmware fills the low bits (which are
1119          * presumably ignored).
1120          */
1121         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1122         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1123
1124         vc4_crtc->cob_size = top - base + 4;
1125 }
1126
1127 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1128 {
1129         struct platform_device *pdev = to_platform_device(dev);
1130         struct drm_device *drm = dev_get_drvdata(master);
1131         struct vc4_crtc *vc4_crtc;
1132         struct drm_crtc *crtc;
1133         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1134         const struct of_device_id *match;
1135         int ret, i;
1136
1137         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1138         if (!vc4_crtc)
1139                 return -ENOMEM;
1140         crtc = &vc4_crtc->base;
1141
1142         match = of_match_device(vc4_crtc_dt_match, dev);
1143         if (!match)
1144                 return -ENODEV;
1145         vc4_crtc->data = match->data;
1146         vc4_crtc->pdev = pdev;
1147
1148         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1149         if (IS_ERR(vc4_crtc->regs))
1150                 return PTR_ERR(vc4_crtc->regs);
1151
1152         vc4_crtc->regset.base = vc4_crtc->regs;
1153         vc4_crtc->regset.regs = crtc_regs;
1154         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1155
1156         /* For now, we create just the primary and the legacy cursor
1157          * planes.  We should be able to stack more planes on easily,
1158          * but to do that we would need to compute the bandwidth
1159          * requirement of the plane configuration, and reject ones
1160          * that will take too much.
1161          */
1162         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1163         if (IS_ERR(primary_plane)) {
1164                 dev_err(dev, "failed to construct primary plane\n");
1165                 ret = PTR_ERR(primary_plane);
1166                 goto err;
1167         }
1168
1169         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1170                                   &vc4_crtc_funcs, NULL);
1171         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1172         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1173         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1174         drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1175
1176         /* We support CTM, but only for one CRTC at a time. It's therefore
1177          * implemented as private driver state in vc4_kms, not here.
1178          */
1179         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1180
1181         /* Set up some arbitrary number of planes.  We're not limited
1182          * by a set number of physical registers, just the space in
1183          * the HVS (16k) and how small an plane can be (28 bytes).
1184          * However, each plane we set up takes up some memory, and
1185          * increases the cost of looping over planes, which atomic
1186          * modesetting does quite a bit.  As a result, we pick a
1187          * modest number of planes to expose, that should hopefully
1188          * still cover any sane usecase.
1189          */
1190         for (i = 0; i < 8; i++) {
1191                 struct drm_plane *plane =
1192                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1193
1194                 if (IS_ERR(plane))
1195                         continue;
1196
1197                 plane->possible_crtcs = drm_crtc_mask(crtc);
1198         }
1199
1200         /* Set up the legacy cursor after overlay initialization,
1201          * since we overlay planes on the CRTC in the order they were
1202          * initialized.
1203          */
1204         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1205         if (!IS_ERR(cursor_plane)) {
1206                 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1207                 crtc->cursor = cursor_plane;
1208         }
1209
1210         vc4_crtc_get_cob_allocation(vc4_crtc);
1211
1212         CRTC_WRITE(PV_INTEN, 0);
1213         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1214         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1215                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1216         if (ret)
1217                 goto err_destroy_planes;
1218
1219         vc4_set_crtc_possible_masks(drm, crtc);
1220
1221         for (i = 0; i < crtc->gamma_size; i++) {
1222                 vc4_crtc->lut_r[i] = i;
1223                 vc4_crtc->lut_g[i] = i;
1224                 vc4_crtc->lut_b[i] = i;
1225         }
1226
1227         platform_set_drvdata(pdev, vc4_crtc);
1228
1229         vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1230                                  &vc4_crtc->regset);
1231
1232         return 0;
1233
1234 err_destroy_planes:
1235         list_for_each_entry_safe(destroy_plane, temp,
1236                                  &drm->mode_config.plane_list, head) {
1237                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1238                     destroy_plane->funcs->destroy(destroy_plane);
1239         }
1240 err:
1241         return ret;
1242 }
1243
1244 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1245                             void *data)
1246 {
1247         struct platform_device *pdev = to_platform_device(dev);
1248         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1249
1250         vc4_crtc_destroy(&vc4_crtc->base);
1251
1252         CRTC_WRITE(PV_INTEN, 0);
1253
1254         platform_set_drvdata(pdev, NULL);
1255 }
1256
1257 static const struct component_ops vc4_crtc_ops = {
1258         .bind   = vc4_crtc_bind,
1259         .unbind = vc4_crtc_unbind,
1260 };
1261
1262 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1263 {
1264         return component_add(&pdev->dev, &vc4_crtc_ops);
1265 }
1266
1267 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1268 {
1269         component_del(&pdev->dev, &vc4_crtc_ops);
1270         return 0;
1271 }
1272
1273 struct platform_driver vc4_crtc_driver = {
1274         .probe = vc4_crtc_dev_probe,
1275         .remove = vc4_crtc_dev_remove,
1276         .driver = {
1277                 .name = "vc4_crtc",
1278                 .of_match_table = vc4_crtc_dt_match,
1279         },
1280 };