2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
34 #include "drm_atomic.h"
35 #include "drm_atomic_helper.h"
36 #include "drm_crtc_helper.h"
37 #include "linux/clk.h"
38 #include "drm_fb_cma_helper.h"
39 #include "linux/component.h"
40 #include "linux/of_device.h"
46 const struct vc4_crtc_data *data;
49 /* Timestamp at start of vblank irq - unaffected by lock delays. */
52 /* Which HVS channel we're using for our CRTC. */
58 /* Size in pixels of the COB memory allocated to this CRTC. */
61 struct drm_pending_vblank_event *event;
64 struct vc4_crtc_state {
65 struct drm_crtc_state base;
66 /* Dlist area for this CRTC configuration. */
67 struct drm_mm_node mm;
70 static inline struct vc4_crtc *
71 to_vc4_crtc(struct drm_crtc *crtc)
73 return (struct vc4_crtc *)crtc;
76 static inline struct vc4_crtc_state *
77 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
79 return (struct vc4_crtc_state *)crtc_state;
82 struct vc4_crtc_data {
83 /* Which channel of the HVS this pixelvalve sources from. */
86 enum vc4_encoder_type encoder_types[4];
89 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
90 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92 #define CRTC_REG(reg) { reg, #reg }
98 CRTC_REG(PV_V_CONTROL),
99 CRTC_REG(PV_VSYNCD_EVEN),
104 CRTC_REG(PV_VERTA_EVEN),
105 CRTC_REG(PV_VERTB_EVEN),
107 CRTC_REG(PV_INTSTAT),
109 CRTC_REG(PV_HACT_ACT),
112 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
116 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
117 DRM_INFO("0x%04x (%s): 0x%08x\n",
118 crtc_regs[i].reg, crtc_regs[i].name,
119 CRTC_READ(crtc_regs[i].reg));
123 #ifdef CONFIG_DEBUG_FS
124 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
126 struct drm_info_node *node = (struct drm_info_node *)m->private;
127 struct drm_device *dev = node->minor->dev;
128 int crtc_index = (uintptr_t)node->info_ent->data;
129 struct drm_crtc *crtc;
130 struct vc4_crtc *vc4_crtc;
134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
141 vc4_crtc = to_vc4_crtc(crtc);
143 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
144 seq_printf(m, "%s (0x%04x): 0x%08x\n",
145 crtc_regs[i].name, crtc_regs[i].reg,
146 CRTC_READ(crtc_regs[i].reg));
153 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
154 unsigned int flags, int *vpos, int *hpos,
155 ktime_t *stime, ktime_t *etime,
156 const struct drm_display_mode *mode)
158 struct vc4_dev *vc4 = to_vc4_dev(dev);
159 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
165 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
167 /* Get optional system timestamp before query. */
169 *stime = ktime_get();
172 * Read vertical scanline which is currently composed for our
173 * pixelvalve by the HVS, and also the scaler status.
175 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
177 /* Get optional system timestamp after query. */
179 *etime = ktime_get();
181 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
183 /* Vertical position of hvs composed scanline. */
184 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
187 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
190 /* Use hpos to correct for field offset in interlaced mode. */
191 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
192 *hpos += mode->crtc_htotal / 2;
195 /* This is the offset we need for translating hvs -> pv scanout pos. */
196 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
199 ret |= DRM_SCANOUTPOS_VALID;
201 /* HVS more than fifo_lines into frame for compositing? */
202 if (*vpos > fifo_lines) {
204 * We are in active scanout and can get some meaningful results
205 * from HVS. The actual PV scanout can not trail behind more
206 * than fifo_lines as that is the fifo's capacity. Assume that
207 * in active scanout the HVS and PV work in lockstep wrt. HVS
208 * refilling the fifo and PV consuming from the fifo, ie.
209 * whenever the PV consumes and frees up a scanline in the
210 * fifo, the HVS will immediately refill it, therefore
211 * incrementing vpos. Therefore we choose HVS read position -
212 * fifo size in scanlines as a estimate of the real scanout
213 * position of the PV.
215 *vpos -= fifo_lines + 1;
217 ret |= DRM_SCANOUTPOS_ACCURATE;
222 * Less: This happens when we are in vblank and the HVS, after getting
223 * the VSTART restart signal from the PV, just started refilling its
224 * fifo with new lines from the top-most lines of the new framebuffers.
225 * The PV does not scan out in vblank, so does not remove lines from
226 * the fifo, so the fifo will be full quickly and the HVS has to pause.
227 * We can't get meaningful readings wrt. scanline position of the PV
228 * and need to make things up in a approximative but consistent way.
230 ret |= DRM_SCANOUTPOS_IN_VBLANK;
231 vblank_lines = mode->vtotal - mode->vdisplay;
233 if (flags & DRM_CALLED_FROM_VBLIRQ) {
235 * Assume the irq handler got called close to first
236 * line of vblank, so PV has about a full vblank
237 * scanlines to go, and as a base timestamp use the
238 * one taken at entry into vblank irq handler, so it
239 * is not affected by random delays due to lock
240 * contention on event_lock or vblank_time lock in
243 *vpos = -vblank_lines;
246 *stime = vc4_crtc->t_vblank;
248 *etime = vc4_crtc->t_vblank;
251 * If the HVS fifo is not yet full then we know for certain
252 * we are at the very beginning of vblank, as the hvs just
253 * started refilling, and the stime and etime timestamps
254 * truly correspond to start of vblank.
256 if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
257 ret |= DRM_SCANOUTPOS_ACCURATE;
260 * No clue where we are inside vblank. Return a vpos of zero,
261 * which will cause calling code to just return the etime
262 * timestamp uncorrected. At least this is no worse than the
271 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
272 int *max_error, struct timeval *vblank_time,
275 struct vc4_dev *vc4 = to_vc4_dev(dev);
276 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
277 struct drm_crtc *crtc = &vc4_crtc->base;
278 struct drm_crtc_state *state = crtc->state;
280 /* Helper routine in DRM core does all the work: */
281 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
283 &state->adjusted_mode);
286 static void vc4_crtc_destroy(struct drm_crtc *crtc)
288 drm_crtc_cleanup(crtc);
292 vc4_crtc_lut_load(struct drm_crtc *crtc)
294 struct drm_device *dev = crtc->dev;
295 struct vc4_dev *vc4 = to_vc4_dev(dev);
296 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
299 /* The LUT memory is laid out with each HVS channel in order,
300 * each of which takes 256 writes for R, 256 for G, then 256
303 HVS_WRITE(SCALER_GAMADDR,
304 SCALER_GAMADDR_AUTOINC |
305 (vc4_crtc->channel * 3 * crtc->gamma_size));
307 for (i = 0; i < crtc->gamma_size; i++)
308 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
309 for (i = 0; i < crtc->gamma_size; i++)
310 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
311 for (i = 0; i < crtc->gamma_size; i++)
312 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
316 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
319 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
322 for (i = 0; i < size; i++) {
323 vc4_crtc->lut_r[i] = r[i] >> 8;
324 vc4_crtc->lut_g[i] = g[i] >> 8;
325 vc4_crtc->lut_b[i] = b[i] >> 8;
328 vc4_crtc_lut_load(crtc);
333 static u32 vc4_get_fifo_full_level(u32 format)
335 static const u32 fifo_len_bytes = 64;
336 static const u32 hvs_latency_pix = 6;
339 case PV_CONTROL_FORMAT_DSIV_16:
340 case PV_CONTROL_FORMAT_DSIC_16:
341 return fifo_len_bytes - 2 * hvs_latency_pix;
342 case PV_CONTROL_FORMAT_DSIV_18:
343 return fifo_len_bytes - 14;
344 case PV_CONTROL_FORMAT_24:
345 case PV_CONTROL_FORMAT_DSIV_24:
347 return fifo_len_bytes - 3 * hvs_latency_pix;
352 * Returns the clock select bit for the connector attached to the
355 static int vc4_get_clock_select(struct drm_crtc *crtc)
357 struct drm_connector *connector;
359 drm_for_each_connector(connector, crtc->dev) {
360 if (connector->state->crtc == crtc) {
361 struct drm_encoder *encoder = connector->encoder;
362 struct vc4_encoder *vc4_encoder =
363 to_vc4_encoder(encoder);
365 return vc4_encoder->clock_select;
372 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
374 struct drm_device *dev = crtc->dev;
375 struct vc4_dev *vc4 = to_vc4_dev(dev);
376 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
377 struct drm_crtc_state *state = crtc->state;
378 struct drm_display_mode *mode = &state->adjusted_mode;
379 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
380 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
381 u32 format = PV_CONTROL_FORMAT_24;
382 bool debug_dump_regs = false;
383 int clock_select = vc4_get_clock_select(crtc);
385 if (debug_dump_regs) {
386 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
387 vc4_crtc_dump_regs(vc4_crtc);
390 /* Reset the PV fifo. */
391 CRTC_WRITE(PV_CONTROL, 0);
392 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
393 CRTC_WRITE(PV_CONTROL, 0);
396 VC4_SET_FIELD((mode->htotal -
397 mode->hsync_end) * pixel_rep,
399 VC4_SET_FIELD((mode->hsync_end -
400 mode->hsync_start) * pixel_rep,
403 VC4_SET_FIELD((mode->hsync_start -
404 mode->hdisplay) * pixel_rep,
406 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
409 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
411 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
414 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
416 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
419 CRTC_WRITE(PV_VERTA_EVEN,
420 VC4_SET_FIELD(mode->crtc_vtotal -
421 mode->crtc_vsync_end - 1,
423 VC4_SET_FIELD(mode->crtc_vsync_end -
424 mode->crtc_vsync_start,
426 CRTC_WRITE(PV_VERTB_EVEN,
427 VC4_SET_FIELD(mode->crtc_vsync_start -
430 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
432 /* We set up first field even mode for HDMI. VEC's
433 * NTSC mode would want first field odd instead, once
434 * we support it (to do so, set ODD_FIRST and put the
435 * delay in VSYNCD_EVEN instead).
437 CRTC_WRITE(PV_V_CONTROL,
438 PV_VCONTROL_CONTINUOUS |
439 PV_VCONTROL_INTERLACE |
440 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
441 PV_VCONTROL_ODD_DELAY));
442 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
444 CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
447 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
450 CRTC_WRITE(PV_CONTROL,
451 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
452 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
453 PV_CONTROL_FIFO_LEVEL) |
454 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
455 PV_CONTROL_CLR_AT_START |
456 PV_CONTROL_TRIGGER_UNDERFLOW |
457 PV_CONTROL_WAIT_HSTART |
458 VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
459 PV_CONTROL_FIFO_CLR |
462 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
463 SCALER_DISPBKGND_AUTOHS |
464 SCALER_DISPBKGND_GAMMA |
465 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
467 /* Reload the LUT, since the SRAMs would have been disabled if
468 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
470 vc4_crtc_lut_load(crtc);
472 if (debug_dump_regs) {
473 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
474 vc4_crtc_dump_regs(vc4_crtc);
478 static void require_hvs_enabled(struct drm_device *dev)
480 struct vc4_dev *vc4 = to_vc4_dev(dev);
482 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
483 SCALER_DISPCTRL_ENABLE);
486 static void vc4_crtc_disable(struct drm_crtc *crtc)
488 struct drm_device *dev = crtc->dev;
489 struct vc4_dev *vc4 = to_vc4_dev(dev);
490 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
491 u32 chan = vc4_crtc->channel;
493 require_hvs_enabled(dev);
495 /* Disable vblank irq handling before crtc is disabled. */
496 drm_crtc_vblank_off(crtc);
498 CRTC_WRITE(PV_V_CONTROL,
499 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
500 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
501 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
503 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
504 SCALER_DISPCTRLX_ENABLE) {
505 HVS_WRITE(SCALER_DISPCTRLX(chan),
506 SCALER_DISPCTRLX_RESET);
508 /* While the docs say that reset is self-clearing, it
509 * seems it doesn't actually.
511 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
514 /* Once we leave, the scaler should be disabled and its fifo empty. */
516 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
518 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
519 SCALER_DISPSTATX_MODE) !=
520 SCALER_DISPSTATX_MODE_DISABLED);
522 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
523 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
524 SCALER_DISPSTATX_EMPTY);
527 static void vc4_crtc_enable(struct drm_crtc *crtc)
529 struct drm_device *dev = crtc->dev;
530 struct vc4_dev *vc4 = to_vc4_dev(dev);
531 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
532 struct drm_crtc_state *state = crtc->state;
533 struct drm_display_mode *mode = &state->adjusted_mode;
535 require_hvs_enabled(dev);
537 /* Turn on the scaler, which will wait for vstart to start
540 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
541 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
542 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
543 SCALER_DISPCTRLX_ENABLE);
545 /* Turn on the pixel valve, which will emit the vstart signal. */
546 CRTC_WRITE(PV_V_CONTROL,
547 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
549 /* Enable vblank irq handling after crtc is started. */
550 drm_crtc_vblank_on(crtc);
553 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
554 const struct drm_display_mode *mode,
555 struct drm_display_mode *adjusted_mode)
557 /* Do not allow doublescan modes from user space */
558 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
559 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
567 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
568 struct drm_crtc_state *state)
570 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
571 struct drm_device *dev = crtc->dev;
572 struct vc4_dev *vc4 = to_vc4_dev(dev);
573 struct drm_plane *plane;
575 const struct drm_plane_state *plane_state;
579 /* The pixelvalve can only feed one encoder (and encoders are
580 * 1:1 with connectors.)
582 if (hweight32(state->connector_mask) > 1)
585 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
586 dlist_count += vc4_plane_dlist_size(plane_state);
588 dlist_count++; /* Account for SCALER_CTL0_END. */
590 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
591 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
593 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
600 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
601 struct drm_crtc_state *old_state)
603 struct drm_device *dev = crtc->dev;
604 struct vc4_dev *vc4 = to_vc4_dev(dev);
605 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
606 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
607 struct drm_plane *plane;
608 bool debug_dump_regs = false;
609 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
610 u32 __iomem *dlist_next = dlist_start;
612 if (debug_dump_regs) {
613 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
614 vc4_hvs_dump_state(dev);
617 /* Copy all the active planes' dlist contents to the hardware dlist. */
618 drm_atomic_crtc_for_each_plane(plane, crtc) {
619 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
622 writel(SCALER_CTL0_END, dlist_next);
625 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
627 if (crtc->state->event) {
630 crtc->state->event->pipe = drm_crtc_index(crtc);
632 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
634 spin_lock_irqsave(&dev->event_lock, flags);
635 vc4_crtc->event = crtc->state->event;
636 crtc->state->event = NULL;
638 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
639 vc4_state->mm.start);
641 spin_unlock_irqrestore(&dev->event_lock, flags);
643 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
644 vc4_state->mm.start);
647 if (debug_dump_regs) {
648 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
649 vc4_hvs_dump_state(dev);
653 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
655 struct vc4_dev *vc4 = to_vc4_dev(dev);
656 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
658 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
663 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
665 struct vc4_dev *vc4 = to_vc4_dev(dev);
666 struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
668 CRTC_WRITE(PV_INTEN, 0);
671 /* Must be called with the event lock held */
672 bool vc4_event_pending(struct drm_crtc *crtc)
674 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
676 return !!vc4_crtc->event;
679 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
681 struct drm_crtc *crtc = &vc4_crtc->base;
682 struct drm_device *dev = crtc->dev;
683 struct vc4_dev *vc4 = to_vc4_dev(dev);
684 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
685 u32 chan = vc4_crtc->channel;
688 spin_lock_irqsave(&dev->event_lock, flags);
689 if (vc4_crtc->event &&
690 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
691 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
692 vc4_crtc->event = NULL;
693 drm_crtc_vblank_put(crtc);
695 spin_unlock_irqrestore(&dev->event_lock, flags);
698 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
700 struct vc4_crtc *vc4_crtc = data;
701 u32 stat = CRTC_READ(PV_INTSTAT);
702 irqreturn_t ret = IRQ_NONE;
704 if (stat & PV_INT_VFP_START) {
705 vc4_crtc->t_vblank = ktime_get();
706 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
707 drm_crtc_handle_vblank(&vc4_crtc->base);
708 vc4_crtc_handle_page_flip(vc4_crtc);
715 struct vc4_async_flip_state {
716 struct drm_crtc *crtc;
717 struct drm_framebuffer *fb;
718 struct drm_pending_vblank_event *event;
720 struct vc4_seqno_cb cb;
723 /* Called when the V3D execution for the BO being flipped to is done, so that
724 * we can actually update the plane's address to point to it.
727 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
729 struct vc4_async_flip_state *flip_state =
730 container_of(cb, struct vc4_async_flip_state, cb);
731 struct drm_crtc *crtc = flip_state->crtc;
732 struct drm_device *dev = crtc->dev;
733 struct vc4_dev *vc4 = to_vc4_dev(dev);
734 struct drm_plane *plane = crtc->primary;
736 vc4_plane_async_set_fb(plane, flip_state->fb);
737 if (flip_state->event) {
740 spin_lock_irqsave(&dev->event_lock, flags);
741 drm_crtc_send_vblank_event(crtc, flip_state->event);
742 spin_unlock_irqrestore(&dev->event_lock, flags);
745 drm_crtc_vblank_put(crtc);
746 drm_framebuffer_unreference(flip_state->fb);
749 up(&vc4->async_modeset);
752 /* Implements async (non-vblank-synced) page flips.
754 * The page flip ioctl needs to return immediately, so we grab the
755 * modeset semaphore on the pipe, and queue the address update for
756 * when V3D is done with the BO being flipped to.
758 static int vc4_async_page_flip(struct drm_crtc *crtc,
759 struct drm_framebuffer *fb,
760 struct drm_pending_vblank_event *event,
763 struct drm_device *dev = crtc->dev;
764 struct vc4_dev *vc4 = to_vc4_dev(dev);
765 struct drm_plane *plane = crtc->primary;
767 struct vc4_async_flip_state *flip_state;
768 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
769 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
771 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
775 drm_framebuffer_reference(fb);
777 flip_state->crtc = crtc;
778 flip_state->event = event;
780 /* Make sure all other async modesetes have landed. */
781 ret = down_interruptible(&vc4->async_modeset);
783 drm_framebuffer_unreference(fb);
788 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
790 /* Immediately update the plane's legacy fb pointer, so that later
791 * modeset prep sees the state that will be present when the semaphore
794 drm_atomic_set_fb_for_plane(plane->state, fb);
797 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
798 vc4_async_page_flip_complete);
800 /* Driver takes ownership of state on successful async commit. */
804 static int vc4_page_flip(struct drm_crtc *crtc,
805 struct drm_framebuffer *fb,
806 struct drm_pending_vblank_event *event,
809 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
810 return vc4_async_page_flip(crtc, fb, event, flags);
812 return drm_atomic_helper_page_flip(crtc, fb, event, flags);
815 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
817 struct vc4_crtc_state *vc4_state;
819 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
823 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
824 return &vc4_state->base;
827 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
828 struct drm_crtc_state *state)
830 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
831 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
833 if (vc4_state->mm.allocated) {
836 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
837 drm_mm_remove_node(&vc4_state->mm);
838 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
842 drm_atomic_helper_crtc_destroy_state(crtc, state);
845 static const struct drm_crtc_funcs vc4_crtc_funcs = {
846 .set_config = drm_atomic_helper_set_config,
847 .destroy = vc4_crtc_destroy,
848 .page_flip = vc4_page_flip,
849 .set_property = NULL,
850 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
851 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
852 .reset = drm_atomic_helper_crtc_reset,
853 .atomic_duplicate_state = vc4_crtc_duplicate_state,
854 .atomic_destroy_state = vc4_crtc_destroy_state,
855 .gamma_set = vc4_crtc_gamma_set,
858 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
859 .mode_set_nofb = vc4_crtc_mode_set_nofb,
860 .disable = vc4_crtc_disable,
861 .enable = vc4_crtc_enable,
862 .mode_fixup = vc4_crtc_mode_fixup,
863 .atomic_check = vc4_crtc_atomic_check,
864 .atomic_flush = vc4_crtc_atomic_flush,
867 static const struct vc4_crtc_data pv0_data = {
870 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
871 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
875 static const struct vc4_crtc_data pv1_data = {
878 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
879 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
883 static const struct vc4_crtc_data pv2_data = {
886 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
887 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
891 static const struct of_device_id vc4_crtc_dt_match[] = {
892 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
893 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
894 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
898 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
899 struct drm_crtc *crtc)
901 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
902 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
903 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
904 struct drm_encoder *encoder;
906 drm_for_each_encoder(encoder, drm) {
907 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
910 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
911 if (vc4_encoder->type == encoder_types[i]) {
912 vc4_encoder->clock_select = i;
913 encoder->possible_crtcs |= drm_crtc_mask(crtc);
921 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
923 struct drm_device *drm = vc4_crtc->base.dev;
924 struct vc4_dev *vc4 = to_vc4_dev(drm);
925 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
926 /* Top/base are supposed to be 4-pixel aligned, but the
927 * Raspberry Pi firmware fills the low bits (which are
928 * presumably ignored).
930 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
931 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
933 vc4_crtc->cob_size = top - base + 4;
936 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
938 struct platform_device *pdev = to_platform_device(dev);
939 struct drm_device *drm = dev_get_drvdata(master);
940 struct vc4_dev *vc4 = to_vc4_dev(drm);
941 struct vc4_crtc *vc4_crtc;
942 struct drm_crtc *crtc;
943 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
944 const struct of_device_id *match;
947 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
950 crtc = &vc4_crtc->base;
952 match = of_match_device(vc4_crtc_dt_match, dev);
955 vc4_crtc->data = match->data;
957 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
958 if (IS_ERR(vc4_crtc->regs))
959 return PTR_ERR(vc4_crtc->regs);
961 /* For now, we create just the primary and the legacy cursor
962 * planes. We should be able to stack more planes on easily,
963 * but to do that we would need to compute the bandwidth
964 * requirement of the plane configuration, and reject ones
965 * that will take too much.
967 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
968 if (IS_ERR(primary_plane)) {
969 dev_err(dev, "failed to construct primary plane\n");
970 ret = PTR_ERR(primary_plane);
974 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
975 &vc4_crtc_funcs, NULL);
976 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
977 primary_plane->crtc = crtc;
978 vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
979 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
980 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
982 /* Set up some arbitrary number of planes. We're not limited
983 * by a set number of physical registers, just the space in
984 * the HVS (16k) and how small an plane can be (28 bytes).
985 * However, each plane we set up takes up some memory, and
986 * increases the cost of looping over planes, which atomic
987 * modesetting does quite a bit. As a result, we pick a
988 * modest number of planes to expose, that should hopefully
989 * still cover any sane usecase.
991 for (i = 0; i < 8; i++) {
992 struct drm_plane *plane =
993 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
998 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1001 /* Set up the legacy cursor after overlay initialization,
1002 * since we overlay planes on the CRTC in the order they were
1005 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1006 if (!IS_ERR(cursor_plane)) {
1007 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1008 cursor_plane->crtc = crtc;
1009 crtc->cursor = cursor_plane;
1012 vc4_crtc_get_cob_allocation(vc4_crtc);
1014 CRTC_WRITE(PV_INTEN, 0);
1015 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1016 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1017 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1019 goto err_destroy_planes;
1021 vc4_set_crtc_possible_masks(drm, crtc);
1023 for (i = 0; i < crtc->gamma_size; i++) {
1024 vc4_crtc->lut_r[i] = i;
1025 vc4_crtc->lut_g[i] = i;
1026 vc4_crtc->lut_b[i] = i;
1029 platform_set_drvdata(pdev, vc4_crtc);
1034 list_for_each_entry_safe(destroy_plane, temp,
1035 &drm->mode_config.plane_list, head) {
1036 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1037 destroy_plane->funcs->destroy(destroy_plane);
1043 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1046 struct platform_device *pdev = to_platform_device(dev);
1047 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1049 vc4_crtc_destroy(&vc4_crtc->base);
1051 CRTC_WRITE(PV_INTEN, 0);
1053 platform_set_drvdata(pdev, NULL);
1056 static const struct component_ops vc4_crtc_ops = {
1057 .bind = vc4_crtc_bind,
1058 .unbind = vc4_crtc_unbind,
1061 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1063 return component_add(&pdev->dev, &vc4_crtc_ops);
1066 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1068 component_del(&pdev->dev, &vc4_crtc_ops);
1072 struct platform_driver vc4_crtc_driver = {
1073 .probe = vc4_crtc_dev_probe,
1074 .remove = vc4_crtc_dev_remove,
1077 .of_match_table = vc4_crtc_dt_match,