2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/mm_types.h>
11 #include <drm/drm_util.h>
12 #include <drm/drm_encoder.h>
13 #include <drm/drm_gem_cma_helper.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_syncobj.h>
17 #include "uapi/drm/vc4_drm.h"
19 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
22 enum vc4_kernel_bo_type {
23 /* Any kernel allocation (gem_create_object hook) before it
24 * gets another type set.
28 VC4_BO_TYPE_V3D_SHADER,
33 VC4_BO_TYPE_KERNEL_CACHE,
37 /* Performance monitor object. The perform lifetime is controlled by userspace
38 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
39 * request, and when this is the case, HW perf counters will be activated just
40 * before the submit_cl is submitted to the GPU and disabled when the job is
41 * done. This way, only events related to a specific job will be counted.
44 /* Tracks the number of users of the perfmon, when this counter reaches
45 * zero the perfmon is destroyed.
49 /* Number of counters activated in this perfmon instance
50 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
54 /* Events counted by the HW perf counters. */
55 u8 events[DRM_VC4_MAX_PERF_COUNTERS];
57 /* Storage for counter values. Counters are incremented by the HW
58 * perf counter values every time the perfmon is attached to a GPU job.
59 * This way, perfmon users don't have to retrieve the results after
60 * each job if they want to track events covering several submissions.
61 * Note that counter values can't be reset, but you can fake a reset by
62 * destroying the perfmon and creating a new one.
68 struct drm_device *dev;
70 struct vc4_hdmi *hdmi;
78 struct vc4_hang_state *hang_state;
80 /* The kernel-space BO cache. Tracks buffers that have been
81 * unreferenced by all other users (refcounts of 0!) but not
82 * yet freed, so we can do cheap allocations.
85 /* Array of list heads for entries in the BO cache,
86 * based on number of pages, so we can do O(1) lookups
87 * in the cache when allocating.
89 struct list_head *size_list;
90 uint32_t size_list_size;
92 /* List of all BOs in the cache, ordered by age, so we
93 * can do O(1) lookups when trying to free old
96 struct list_head time_list;
97 struct work_struct time_work;
98 struct timer_list time_timer;
108 /* Protects bo_cache and bo_labels. */
109 struct mutex bo_lock;
111 /* Purgeable BO pool. All BOs in this pool can have their memory
112 * reclaimed if the driver is unable to allocate new BOs. We also
113 * keep stats related to the purge mechanism here.
116 struct list_head list;
119 unsigned int purged_num;
124 uint64_t dma_fence_context;
126 /* Sequence number for the last job queued in bin_job_list.
127 * Starts at 0 (no jobs emitted).
131 /* Sequence number for the last completed job on the GPU.
132 * Starts at 0 (no jobs completed).
134 uint64_t finished_seqno;
136 /* List of all struct vc4_exec_info for jobs to be executed in
137 * the binner. The first job in the list is the one currently
138 * programmed into ct0ca for execution.
140 struct list_head bin_job_list;
142 /* List of all struct vc4_exec_info for jobs that have
143 * completed binning and are ready for rendering. The first
144 * job in the list is the one currently programmed into ct1ca
147 struct list_head render_job_list;
149 /* List of the finished vc4_exec_infos waiting to be freed by
152 struct list_head job_done_list;
153 /* Spinlock used to synchronize the job_list and seqno
154 * accesses between the IRQ handler and GEM ioctls.
157 wait_queue_head_t job_wait_queue;
158 struct work_struct job_done_work;
160 /* Used to track the active perfmon if any. Access to this field is
161 * protected by job_lock.
163 struct vc4_perfmon *active_perfmon;
165 /* List of struct vc4_seqno_cb for callbacks to be made from a
166 * workqueue when the given seqno is passed.
168 struct list_head seqno_cb_list;
170 /* The memory used for storing binner tile alloc, tile state,
171 * and overflow memory allocations. This is freed when V3D
174 struct vc4_bo *bin_bo;
176 /* Size of blocks allocated within bin_bo. */
177 uint32_t bin_alloc_size;
179 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
182 uint32_t bin_alloc_used;
184 /* Bitmask of the current bin_alloc used for overflow memory. */
185 uint32_t bin_alloc_overflow;
187 /* Incremented when an underrun error happened after an atomic commit.
188 * This is particularly useful to detect when a specific modeset is too
189 * demanding in term of memory or HVS bandwidth which is hard to guess
190 * at atomic check time.
194 struct work_struct overflow_mem_work;
198 /* Set to true when the load tracker is active. */
199 bool load_tracker_enabled;
201 /* Mutex controlling the power refcount. */
202 struct mutex power_lock;
205 struct timer_list timer;
206 struct work_struct reset_work;
209 struct semaphore async_modeset;
211 struct drm_modeset_lock ctm_state_lock;
212 struct drm_private_obj ctm_manager;
213 struct drm_private_obj load_tracker;
216 static inline struct vc4_dev *
217 to_vc4_dev(struct drm_device *dev)
219 return (struct vc4_dev *)dev->dev_private;
223 struct drm_gem_cma_object base;
225 /* seqno of the last job to render using this BO. */
228 /* seqno of the last job to use the RCL to write to this BO.
230 * Note that this doesn't include binner overflow memory
233 uint64_t write_seqno;
237 /* List entry for the BO's position in either
238 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
240 struct list_head unref_head;
242 /* Time in jiffies when the BO was put in vc4->bo_cache. */
243 unsigned long free_time;
245 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
246 struct list_head size_head;
248 /* Struct for shader validation state, if created by
249 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
251 struct vc4_validated_shader_info *validated_shader;
253 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
254 * for user-allocated labels.
258 /* Count the number of active users. This is needed to determine
259 * whether we can move the BO to the purgeable list or not (when the BO
260 * is used by the GPU or the display engine we can't purge it).
264 /* Store purgeable/purged state here */
266 struct mutex madv_lock;
269 static inline struct vc4_bo *
270 to_vc4_bo(struct drm_gem_object *bo)
272 return (struct vc4_bo *)bo;
276 struct dma_fence base;
277 struct drm_device *dev;
278 /* vc4 seqno for signaled() test */
282 static inline struct vc4_fence *
283 to_vc4_fence(struct dma_fence *fence)
285 return (struct vc4_fence *)fence;
288 struct vc4_seqno_cb {
289 struct work_struct work;
291 void (*func)(struct vc4_seqno_cb *cb);
296 struct platform_device *pdev;
299 struct debugfs_regset32 regset;
303 struct platform_device *pdev;
307 /* Memory manager for CRTCs to allocate space in the display
308 * list. Units are dwords.
310 struct drm_mm dlist_mm;
311 /* Memory manager for the LBM memory used by HVS scaling. */
312 struct drm_mm lbm_mm;
315 struct drm_mm_node mitchell_netravali_filter;
316 struct debugfs_regset32 regset;
320 struct drm_plane base;
323 static inline struct vc4_plane *
324 to_vc4_plane(struct drm_plane *plane)
326 return (struct vc4_plane *)plane;
329 enum vc4_scaling_mode {
335 struct vc4_plane_state {
336 struct drm_plane_state base;
337 /* System memory copy of the display list for this element, computed
338 * at atomic_check time.
341 u32 dlist_size; /* Number of dwords allocated for the display list */
342 u32 dlist_count; /* Number of used dwords in the display list. */
344 /* Offset in the dlist to various words, for pageflip or
352 /* Offset where the plane's dlist was last stored in the
353 * hardware at vc4_crtc_atomic_flush() time.
355 u32 __iomem *hw_dlist;
357 /* Clipped coordinates of the plane on the display. */
358 int crtc_x, crtc_y, crtc_w, crtc_h;
359 /* Clipped area being scanned from in the FB. */
362 u32 src_w[2], src_h[2];
364 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
365 enum vc4_scaling_mode x_scaling[2], y_scaling[2];
369 /* Offset to start scanning out from the start of the plane's
374 /* Our allocation in LBM for temporary storage during scaling. */
375 struct drm_mm_node lbm;
377 /* Set when the plane has per-pixel alpha content or does not cover
378 * the entire screen. This is a hint to the CRTC that it might need
379 * to enable background color fill.
383 /* Mark the dlist as initialized. Useful to avoid initializing it twice
384 * when async update is not possible.
386 bool dlist_initialized;
388 /* Load of this plane on the HVS block. The load is expressed in HVS
393 /* Memory bandwidth needed for this plane. This is expressed in
399 static inline struct vc4_plane_state *
400 to_vc4_plane_state(struct drm_plane_state *state)
402 return (struct vc4_plane_state *)state;
405 enum vc4_encoder_type {
406 VC4_ENCODER_TYPE_NONE,
407 VC4_ENCODER_TYPE_HDMI,
408 VC4_ENCODER_TYPE_VEC,
409 VC4_ENCODER_TYPE_DSI0,
410 VC4_ENCODER_TYPE_DSI1,
411 VC4_ENCODER_TYPE_SMI,
412 VC4_ENCODER_TYPE_DPI,
416 struct drm_encoder base;
417 enum vc4_encoder_type type;
421 static inline struct vc4_encoder *
422 to_vc4_encoder(struct drm_encoder *encoder)
424 return container_of(encoder, struct vc4_encoder, base);
427 struct vc4_crtc_data {
428 /* Which channel of the HVS this pixelvalve sources from. */
431 enum vc4_encoder_type encoder_types[4];
435 struct drm_crtc base;
436 struct platform_device *pdev;
437 const struct vc4_crtc_data *data;
440 /* Timestamp at start of vblank irq - unaffected by lock delays. */
443 /* Which HVS channel we're using for our CRTC. */
449 /* Size in pixels of the COB memory allocated to this CRTC. */
452 struct drm_pending_vblank_event *event;
454 struct debugfs_regset32 regset;
457 static inline struct vc4_crtc *
458 to_vc4_crtc(struct drm_crtc *crtc)
460 return (struct vc4_crtc *)crtc;
463 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
464 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
465 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
466 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
468 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
470 struct vc4_exec_info {
471 /* Sequence number for this bin/render job. */
474 /* Latest write_seqno of any BO that binning depends on. */
475 uint64_t bin_dep_seqno;
477 struct dma_fence *fence;
479 /* Last current addresses the hardware was processing when the
480 * hangcheck timer checked on us.
482 uint32_t last_ct0ca, last_ct1ca;
484 /* Kernel-space copy of the ioctl arguments */
485 struct drm_vc4_submit_cl *args;
487 /* This is the array of BOs that were looked up at the start of exec.
488 * Command validation will use indices into this array.
490 struct drm_gem_cma_object **bo;
493 /* List of BOs that are being written by the RCL. Other than
494 * the binner temporary storage, this is all the BOs written
497 struct drm_gem_cma_object *rcl_write_bo[4];
498 uint32_t rcl_write_bo_count;
500 /* Pointers for our position in vc4->job_list */
501 struct list_head head;
503 /* List of other BOs used in the job that need to be released
504 * once the job is complete.
506 struct list_head unref_list;
508 /* Current unvalidated indices into @bo loaded by the non-hardware
509 * VC4_PACKET_GEM_HANDLES.
511 uint32_t bo_index[2];
513 /* This is the BO where we store the validated command lists, shader
514 * records, and uniforms.
516 struct drm_gem_cma_object *exec_bo;
519 * This tracks the per-shader-record state (packet 64) that
520 * determines the length of the shader record and the offset
521 * it's expected to be found at. It gets read in from the
524 struct vc4_shader_state {
526 /* Maximum vertex index referenced by any primitive using this
532 /** How many shader states the user declared they were using. */
533 uint32_t shader_state_size;
534 /** How many shader state records the validator has seen. */
535 uint32_t shader_state_count;
537 bool found_tile_binning_mode_config_packet;
538 bool found_start_tile_binning_packet;
539 bool found_increment_semaphore_packet;
541 uint8_t bin_tiles_x, bin_tiles_y;
542 /* Physical address of the start of the tile alloc array
543 * (where each tile's binned CL will start)
545 uint32_t tile_alloc_offset;
546 /* Bitmask of which binner slots are freed when this job completes. */
550 * Computed addresses pointing into exec_bo where we start the
551 * bin thread (ct0) and render thread (ct1).
553 uint32_t ct0ca, ct0ea;
554 uint32_t ct1ca, ct1ea;
556 /* Pointer to the unvalidated bin CL (if present). */
559 /* Pointers to the shader recs. These paddr gets incremented as CL
560 * packets are relocated in validate_gl_shader_state, and the vaddrs
561 * (u and v) get incremented and size decremented as the shader recs
562 * themselves are validated.
566 uint32_t shader_rec_p;
567 uint32_t shader_rec_size;
569 /* Pointers to the uniform data. These pointers are incremented, and
570 * size decremented, as each batch of uniforms is uploaded.
575 uint32_t uniforms_size;
577 /* Pointer to a performance monitor object if the user requested it,
580 struct vc4_perfmon *perfmon;
583 /* Per-open file private data. Any driver-specific resource that has to be
584 * released when the DRM file is closed should be placed here.
593 static inline struct vc4_exec_info *
594 vc4_first_bin_job(struct vc4_dev *vc4)
596 return list_first_entry_or_null(&vc4->bin_job_list,
597 struct vc4_exec_info, head);
600 static inline struct vc4_exec_info *
601 vc4_first_render_job(struct vc4_dev *vc4)
603 return list_first_entry_or_null(&vc4->render_job_list,
604 struct vc4_exec_info, head);
607 static inline struct vc4_exec_info *
608 vc4_last_render_job(struct vc4_dev *vc4)
610 if (list_empty(&vc4->render_job_list))
612 return list_last_entry(&vc4->render_job_list,
613 struct vc4_exec_info, head);
617 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
620 * This will be used at draw time to relocate the reference to the texture
621 * contents in p0, and validate that the offset combined with
622 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
623 * Note that the hardware treats unprovided config parameters as 0, so not all
624 * of them need to be set up for every texure sample, and we'll store ~0 as
625 * the offset to mark the unused ones.
627 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
628 * Setup") for definitions of the texture parameters.
630 struct vc4_texture_sample_info {
632 uint32_t p_offset[4];
636 * struct vc4_validated_shader_info - information about validated shaders that
637 * needs to be used from command list validation.
639 * For a given shader, each time a shader state record references it, we need
640 * to verify that the shader doesn't read more uniforms than the shader state
641 * record's uniform BO pointer can provide, and we need to apply relocations
642 * and validate the shader state record's uniforms that define the texture
645 struct vc4_validated_shader_info {
646 uint32_t uniforms_size;
647 uint32_t uniforms_src_size;
648 uint32_t num_texture_samples;
649 struct vc4_texture_sample_info *texture_samples;
651 uint32_t num_uniform_addr_offsets;
652 uint32_t *uniform_addr_offsets;
658 * _wait_for - magic (register) wait macro
660 * Does the right thing for modeset paths when run under kdgb or similar atomic
661 * contexts. Note that it's important that we check the condition again after
662 * having timed out, since the timeout could be due to preemption or similar and
663 * we've never had a chance to check the condition before the timeout.
665 #define _wait_for(COND, MS, W) ({ \
666 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
669 if (time_after(jiffies, timeout__)) { \
671 ret__ = -ETIMEDOUT; \
674 if (W && drm_can_sleep()) { \
683 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
686 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size);
687 void vc4_free_object(struct drm_gem_object *gem_obj);
688 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size,
689 bool from_cache, enum vc4_kernel_bo_type type);
690 int vc4_dumb_create(struct drm_file *file_priv,
691 struct drm_device *dev,
692 struct drm_mode_create_dumb *args);
693 struct dma_buf *vc4_prime_export(struct drm_device *dev,
694 struct drm_gem_object *obj, int flags);
695 int vc4_create_bo_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
701 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
702 struct drm_file *file_priv);
703 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
704 struct drm_file *file_priv);
705 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data,
706 struct drm_file *file_priv);
707 int vc4_label_bo_ioctl(struct drm_device *dev, void *data,
708 struct drm_file *file_priv);
709 vm_fault_t vc4_fault(struct vm_fault *vmf);
710 int vc4_mmap(struct file *filp, struct vm_area_struct *vma);
711 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
712 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev,
713 struct dma_buf_attachment *attach,
714 struct sg_table *sgt);
715 void *vc4_prime_vmap(struct drm_gem_object *obj);
716 int vc4_bo_cache_init(struct drm_device *dev);
717 void vc4_bo_cache_destroy(struct drm_device *dev);
718 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg);
719 int vc4_bo_inc_usecnt(struct vc4_bo *bo);
720 void vc4_bo_dec_usecnt(struct vc4_bo *bo);
721 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo);
722 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo);
725 extern struct platform_driver vc4_crtc_driver;
726 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
727 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
728 bool in_vblank_irq, int *vpos, int *hpos,
729 ktime_t *stime, ktime_t *etime,
730 const struct drm_display_mode *mode);
731 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc);
732 void vc4_crtc_txp_armed(struct drm_crtc_state *state);
733 void vc4_crtc_get_margins(struct drm_crtc_state *state,
734 unsigned int *right, unsigned int *left,
735 unsigned int *top, unsigned int *bottom);
738 int vc4_debugfs_init(struct drm_minor *minor);
741 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index);
744 extern struct platform_driver vc4_dpi_driver;
745 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
748 extern struct platform_driver vc4_dsi_driver;
749 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
752 extern const struct dma_fence_ops vc4_fence_ops;
755 void vc4_gem_init(struct drm_device *dev);
756 void vc4_gem_destroy(struct drm_device *dev);
757 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
758 struct drm_file *file_priv);
759 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
760 struct drm_file *file_priv);
761 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
762 struct drm_file *file_priv);
763 void vc4_submit_next_bin_job(struct drm_device *dev);
764 void vc4_submit_next_render_job(struct drm_device *dev);
765 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec);
766 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno,
767 uint64_t timeout_ns, bool interruptible);
768 void vc4_job_handle_completed(struct vc4_dev *vc4);
769 int vc4_queue_seqno_cb(struct drm_device *dev,
770 struct vc4_seqno_cb *cb, uint64_t seqno,
771 void (*func)(struct vc4_seqno_cb *cb));
772 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
773 struct drm_file *file_priv);
776 extern struct platform_driver vc4_hdmi_driver;
777 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused);
780 extern struct platform_driver vc4_vec_driver;
781 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused);
784 extern struct platform_driver vc4_txp_driver;
785 int vc4_txp_debugfs_regs(struct seq_file *m, void *unused);
788 irqreturn_t vc4_irq(int irq, void *arg);
789 void vc4_irq_preinstall(struct drm_device *dev);
790 int vc4_irq_postinstall(struct drm_device *dev);
791 void vc4_irq_uninstall(struct drm_device *dev);
792 void vc4_irq_reset(struct drm_device *dev);
795 extern struct platform_driver vc4_hvs_driver;
796 void vc4_hvs_dump_state(struct drm_device *dev);
797 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);
798 int vc4_hvs_debugfs_underrun(struct seq_file *m, void *unused);
799 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
800 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);
803 int vc4_kms_load(struct drm_device *dev);
806 struct drm_plane *vc4_plane_init(struct drm_device *dev,
807 enum drm_plane_type type);
808 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist);
809 u32 vc4_plane_dlist_size(const struct drm_plane_state *state);
810 void vc4_plane_async_set_fb(struct drm_plane *plane,
811 struct drm_framebuffer *fb);
814 extern struct platform_driver vc4_v3d_driver;
815 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused);
816 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused);
817 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4);
818 int vc4_v3d_pm_get(struct vc4_dev *vc4);
819 void vc4_v3d_pm_put(struct vc4_dev *vc4);
823 vc4_validate_bin_cl(struct drm_device *dev,
826 struct vc4_exec_info *exec);
829 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec);
831 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec,
834 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec);
836 bool vc4_check_tex_size(struct vc4_exec_info *exec,
837 struct drm_gem_cma_object *fbo,
838 uint32_t offset, uint8_t tiling_format,
839 uint32_t width, uint32_t height, uint8_t cpp);
841 /* vc4_validate_shader.c */
842 struct vc4_validated_shader_info *
843 vc4_validate_shader(struct drm_gem_cma_object *shader_obj);
846 void vc4_perfmon_get(struct vc4_perfmon *perfmon);
847 void vc4_perfmon_put(struct vc4_perfmon *perfmon);
848 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon);
849 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon,
851 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id);
852 void vc4_perfmon_open_file(struct vc4_file *vc4file);
853 void vc4_perfmon_close_file(struct vc4_file *vc4file);
854 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data,
855 struct drm_file *file_priv);
856 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
857 struct drm_file *file_priv);
858 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
859 struct drm_file *file_priv);