drivers/gpu/drm/vc4/vc4_hvs.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 HVS module.
  11  *
  12  * The Hardware Video Scaler (HVS) is the piece of hardware that does
  13  * translation, scaling, colorspace conversion, and compositing of
  14  * pixels stored in framebuffers into a FIFO of pixels going out to
  15  * the Pixel Valve (CRTC).  It operates at the system clock rate (the
  16  * system audio clock gate, specifically), which is much higher than
  17  * the pixel clock rate.
  18  *
  19  * There is a single global HVS, with multiple output FIFOs that can
  20  * be consumed by the PVs.  This file just manages the resources for
  21  * the HVS, while the vc4_crtc.c code actually drives HVS setup for
  22  * each CRTC.
  23  */
  24
  25 #include <drm/drm_atomic_helper.h>
  26 #include <linux/component.h>
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 static const struct debugfs_reg32 hvs_regs[] = {
  31         VC4_REG32(SCALER_DISPCTRL),
  32         VC4_REG32(SCALER_DISPSTAT),
  33         VC4_REG32(SCALER_DISPID),
  34         VC4_REG32(SCALER_DISPECTRL),
  35         VC4_REG32(SCALER_DISPPROF),
  36         VC4_REG32(SCALER_DISPDITHER),
  37         VC4_REG32(SCALER_DISPEOLN),
  38         VC4_REG32(SCALER_DISPLIST0),
  39         VC4_REG32(SCALER_DISPLIST1),
  40         VC4_REG32(SCALER_DISPLIST2),
  41         VC4_REG32(SCALER_DISPLSTAT),
  42         VC4_REG32(SCALER_DISPLACT0),
  43         VC4_REG32(SCALER_DISPLACT1),
  44         VC4_REG32(SCALER_DISPLACT2),
  45         VC4_REG32(SCALER_DISPCTRL0),
  46         VC4_REG32(SCALER_DISPBKGND0),
  47         VC4_REG32(SCALER_DISPSTAT0),
  48         VC4_REG32(SCALER_DISPBASE0),
  49         VC4_REG32(SCALER_DISPCTRL1),
  50         VC4_REG32(SCALER_DISPBKGND1),
  51         VC4_REG32(SCALER_DISPSTAT1),
  52         VC4_REG32(SCALER_DISPBASE1),
  53         VC4_REG32(SCALER_DISPCTRL2),
  54         VC4_REG32(SCALER_DISPBKGND2),
  55         VC4_REG32(SCALER_DISPSTAT2),
  56         VC4_REG32(SCALER_DISPBASE2),
  57         VC4_REG32(SCALER_DISPALPHA2),
  58         VC4_REG32(SCALER_OLEDOFFS),
  59         VC4_REG32(SCALER_OLEDCOEF0),
  60         VC4_REG32(SCALER_OLEDCOEF1),
  61         VC4_REG32(SCALER_OLEDCOEF2),
  62 };
  63
  64 void vc4_hvs_dump_state(struct drm_device *dev)
  65 {
  66         struct vc4_dev *vc4 = to_vc4_dev(dev);
  67         struct drm_printer p = drm_info_printer(&vc4->hvs->pdev->dev);
  68         int i;
  69
  70         drm_print_regset32(&p, &vc4->hvs->regset);
  71
  72         DRM_INFO("HVS ctx:\n");
  73         for (i = 0; i < 64; i += 4) {
  74                 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n",
  75                          i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D",
  76                          readl((u32 __iomem *)vc4->hvs->dlist + i + 0),
  77                          readl((u32 __iomem *)vc4->hvs->dlist + i + 1),
  78                          readl((u32 __iomem *)vc4->hvs->dlist + i + 2),
  79                          readl((u32 __iomem *)vc4->hvs->dlist + i + 3));
  80         }
  81 }
  82
  83 #ifdef CONFIG_DEBUG_FS
  84 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused)
  85 {
  86         struct drm_info_node *node = (struct drm_info_node *)m->private;
  87         struct drm_device *dev = node->minor->dev;
  88         struct vc4_dev *vc4 = to_vc4_dev(dev);
  89         struct drm_printer p = drm_seq_file_printer(m);
  90
  91         drm_print_regset32(&p, &vc4->hvs->regset);
  92
  93         return 0;
  94 }
  95
  96 int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)
  97 {
  98         struct drm_info_node *node = m->private;
  99         struct drm_device *dev = node->minor->dev;
 100         struct vc4_dev *vc4 = to_vc4_dev(dev);
 101         struct drm_printer p = drm_seq_file_printer(m);
 102
 103         drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));
 104
 105         return 0;
 106 }
 107 #endif
 108
 109 /* The filter kernel is composed of dwords each containing 3 9-bit
 110  * signed integers packed next to each other.
 111  */
 112 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff)
 113 #define VC4_PPF_FILTER_WORD(c0, c1, c2)                         \
 114         ((((c0) & 0x1ff) << 0) |                                \
 115          (((c1) & 0x1ff) << 9) |                                \
 116          (((c2) & 0x1ff) << 18))
 117
 118 /* The whole filter kernel is arranged as the coefficients 0-16 going
 119  * up, then a pad, then 17-31 going down and reversed within the
 120  * dwords.  This means that a linear phase kernel (where it's
 121  * symmetrical at the boundary between 15 and 16) has the last 5
 122  * dwords matching the first 5, but reversed.
 123  */
 124 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8,     \
 125                                 c9, c10, c11, c12, c13, c14, c15)       \
 126         {VC4_PPF_FILTER_WORD(c0, c1, c2),                               \
 127          VC4_PPF_FILTER_WORD(c3, c4, c5),                               \
 128          VC4_PPF_FILTER_WORD(c6, c7, c8),                               \
 129          VC4_PPF_FILTER_WORD(c9, c10, c11),                             \
 130          VC4_PPF_FILTER_WORD(c12, c13, c14),                            \
 131          VC4_PPF_FILTER_WORD(c15, c15, 0)}
 132
 133 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6
 134 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1)
 135
 136 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali.
 137  * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf
 138  */
 139 static const u32 mitchell_netravali_1_3_1_3_kernel[] =
 140         VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18,
 141                                 50, 82, 119, 155, 187, 213, 227);
 142
 143 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
 144                                         struct drm_mm_node *space,
 145                                         const u32 *kernel)
 146 {
 147         int ret, i;
 148         u32 __iomem *dst_kernel;
 149
 150         ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS);
 151         if (ret) {
 152                 DRM_ERROR("Failed to allocate space for filter kernel: %d\n",
 153                           ret);
 154                 return ret;
 155         }
 156
 157         dst_kernel = hvs->dlist + space->start;
 158
 159         for (i = 0; i < VC4_KERNEL_DWORDS; i++) {
 160                 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS)
 161                         writel(kernel[i], &dst_kernel[i]);
 162                 else {
 163                         writel(kernel[VC4_KERNEL_DWORDS - i - 1],
 164                                &dst_kernel[i]);
 165                 }
 166         }
 167
 168         return 0;
 169 }
 170
 171 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)
 172 {
 173         struct vc4_dev *vc4 = to_vc4_dev(dev);
 174         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 175
 176         dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);
 177
 178         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 179 }
 180
 181 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)
 182 {
 183         struct vc4_dev *vc4 = to_vc4_dev(dev);
 184         u32 dispctrl = HVS_READ(SCALER_DISPCTRL);
 185
 186         dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);
 187
 188         HVS_WRITE(SCALER_DISPSTAT,
 189                   SCALER_DISPSTAT_EUFLOW(channel));
 190         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 191 }
 192
 193 static void vc4_hvs_report_underrun(struct drm_device *dev)
 194 {
 195         struct vc4_dev *vc4 = to_vc4_dev(dev);
 196
 197         atomic_inc(&vc4->underrun);
 198         DRM_DEV_ERROR(dev->dev, "HVS underrun\n");
 199 }
 200
 201 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
 202 {
 203         struct drm_device *dev = data;
 204         struct vc4_dev *vc4 = to_vc4_dev(dev);
 205         irqreturn_t irqret = IRQ_NONE;
 206         int channel;
 207         u32 control;
 208         u32 status;
 209
 210         status = HVS_READ(SCALER_DISPSTAT);
 211         control = HVS_READ(SCALER_DISPCTRL);
 212
 213         for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
 214                 /* Interrupt masking is not always honored, so check it here. */
 215                 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
 216                     control & SCALER_DISPCTRL_DSPEISLUR(channel)) {
 217                         vc4_hvs_mask_underrun(dev, channel);
 218                         vc4_hvs_report_underrun(dev);
 219
 220                         irqret = IRQ_HANDLED;
 221                 }
 222         }
 223
 224         /* Clear every per-channel interrupt flag. */
 225         HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |
 226                                    SCALER_DISPSTAT_IRQMASK(1) |
 227                                    SCALER_DISPSTAT_IRQMASK(2));
 228
 229         return irqret;
 230 }
 231
 232 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 233 {
 234         struct platform_device *pdev = to_platform_device(dev);
 235         struct drm_device *drm = dev_get_drvdata(master);
 236         struct vc4_dev *vc4 = drm->dev_private;
 237         struct vc4_hvs *hvs = NULL;
 238         int ret;
 239         u32 dispctrl;
 240
 241         hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL);
 242         if (!hvs)
 243                 return -ENOMEM;
 244
 245         hvs->pdev = pdev;
 246
 247         hvs->regs = vc4_ioremap_regs(pdev, 0);
 248         if (IS_ERR(hvs->regs))
 249                 return PTR_ERR(hvs->regs);
 250
 251         hvs->regset.base = hvs->regs;
 252         hvs->regset.regs = hvs_regs;
 253         hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
 254
 255         hvs->dlist = hvs->regs + SCALER_DLIST_START;
 256
 257         spin_lock_init(&hvs->mm_lock);
 258
 259         /* Set up the HVS display list memory manager.  We never
 260          * overwrite the setup from the bootloader (just 128b out of
 261          * our 16K), since we don't want to scramble the screen when
 262          * transitioning from the firmware's boot setup to runtime.
 263          */
 264         drm_mm_init(&hvs->dlist_mm,
 265                     HVS_BOOTLOADER_DLIST_END,
 266                     (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
 267
 268         /* Set up the HVS LBM memory manager.  We could have some more
 269          * complicated data structure that allowed reuse of LBM areas
 270          * between planes when they don't overlap on the screen, but
 271          * for now we just allocate globally.
 272          */
 273         drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
 274
 275         /* Upload filter kernels.  We only have the one for now, so we
 276          * keep it around for the lifetime of the driver.
 277          */
 278         ret = vc4_hvs_upload_linear_kernel(hvs,
 279                                            &hvs->mitchell_netravali_filter,
 280                                            mitchell_netravali_1_3_1_3_kernel);
 281         if (ret)
 282                 return ret;
 283
 284         vc4->hvs = hvs;
 285
 286         dispctrl = HVS_READ(SCALER_DISPCTRL);
 287
 288         dispctrl |= SCALER_DISPCTRL_ENABLE;
 289         dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |
 290                     SCALER_DISPCTRL_DISPEIRQ(1) |
 291                     SCALER_DISPCTRL_DISPEIRQ(2);
 292
 293         /* Set DSP3 (PV1) to use HVS channel 2, which would otherwise
 294          * be unused.
 295          */
 296         dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 297         dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
 298                       SCALER_DISPCTRL_SLVWREIRQ |
 299                       SCALER_DISPCTRL_SLVRDEIRQ |
 300                       SCALER_DISPCTRL_DSPEIEOF(0) |
 301                       SCALER_DISPCTRL_DSPEIEOF(1) |
 302                       SCALER_DISPCTRL_DSPEIEOF(2) |
 303                       SCALER_DISPCTRL_DSPEIEOLN(0) |
 304                       SCALER_DISPCTRL_DSPEIEOLN(1) |
 305                       SCALER_DISPCTRL_DSPEIEOLN(2) |
 306                       SCALER_DISPCTRL_DSPEISLUR(0) |
 307                       SCALER_DISPCTRL_DSPEISLUR(1) |
 308                       SCALER_DISPCTRL_DSPEISLUR(2) |
 309                       SCALER_DISPCTRL_SCLEIRQ);
 310         dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 311
 312         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 313
 314         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
 315                                vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
 316         if (ret)
 317                 return ret;
 318
 319         return 0;
 320 }
 321
 322 static void vc4_hvs_unbind(struct device *dev, struct device *master,
 323                            void *data)
 324 {
 325         struct drm_device *drm = dev_get_drvdata(master);
 326         struct vc4_dev *vc4 = drm->dev_private;
 327
 328         if (vc4->hvs->mitchell_netravali_filter.allocated)
 329                 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter);
 330
 331         drm_mm_takedown(&vc4->hvs->dlist_mm);
 332         drm_mm_takedown(&vc4->hvs->lbm_mm);
 333
 334         vc4->hvs = NULL;
 335 }
 336
 337 static const struct component_ops vc4_hvs_ops = {
 338         .bind   = vc4_hvs_bind,
 339         .unbind = vc4_hvs_unbind,
 340 };
 341
 342 static int vc4_hvs_dev_probe(struct platform_device *pdev)
 343 {
 344         return component_add(&pdev->dev, &vc4_hvs_ops);
 345 }
 346
 347 static int vc4_hvs_dev_remove(struct platform_device *pdev)
 348 {
 349         component_del(&pdev->dev, &vc4_hvs_ops);
 350         return 0;
 351 }
 352
 353 static const struct of_device_id vc4_hvs_dt_match[] = {
 354         { .compatible = "brcm,bcm2835-hvs" },
 355         {}
 356 };
 357
 358 struct platform_driver vc4_hvs_driver = {
 359         .probe = vc4_hvs_dev_probe,
 360         .remove = vc4_hvs_dev_remove,
 361         .driver = {
 362                 .name = "vc4_hvs",
 363                 .of_match_table = vc4_hvs_dt_match,
 364         },
 365 };