drivers/gpu/drm/vc4/vc4_plane.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /**
  10  * DOC: VC4 plane module
  11  *
  12  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  13  *
  14  * At atomic modeset check time, we compute the HVS display element
  15  * state that would be necessary for displaying the plane (giving us a
  16  * chance to figure out if a plane configuration is invalid), then at
  17  * atomic flush time the CRTC will ask us to write our element state
  18  * into the region of the HVS that it has allocated for us.
  19  */
  20
  21 #include <drm/drm_atomic.h>
  22 #include <drm/drm_atomic_helper.h>
  23 #include <drm/drm_fb_cma_helper.h>
  24 #include <drm/drm_plane_helper.h>
  25 #include <drm/drm_atomic_uapi.h>
  26
  27 #include "uapi/drm/vc4_drm.h"
  28 #include "vc4_drv.h"
  29 #include "vc4_regs.h"
  30
  31 static const struct hvs_format {
  32         u32 drm; /* DRM_FORMAT_* */
  33         u32 hvs; /* HVS_FORMAT_* */
  34         u32 pixel_order;
  35 } hvs_formats[] = {
  36         {
  37                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  38                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  39         },
  40         {
  41                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  42                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  43         },
  44         {
  45                 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  46                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  47         },
  48         {
  49                 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  50                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  51         },
  52         {
  53                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  54                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  55         },
  56         {
  57                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  58                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  59         },
  60         {
  61                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  62                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  63         },
  64         {
  65                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  66                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  67         },
  68         {
  69                 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  70                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  71         },
  72         {
  73                 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  74                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  75         },
  76         {
  77                 .drm = DRM_FORMAT_YUV422,
  78                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  79                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  80         },
  81         {
  82                 .drm = DRM_FORMAT_YVU422,
  83                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  84                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  85         },
  86         {
  87                 .drm = DRM_FORMAT_YUV420,
  88                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  89                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  90         },
  91         {
  92                 .drm = DRM_FORMAT_YVU420,
  93                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  94                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  95         },
  96         {
  97                 .drm = DRM_FORMAT_NV12,
  98                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  99                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 100         },
 101         {
 102                 .drm = DRM_FORMAT_NV21,
 103                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 104                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 105         },
 106         {
 107                 .drm = DRM_FORMAT_NV16,
 108                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 109                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 110         },
 111         {
 112                 .drm = DRM_FORMAT_NV61,
 113                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 114                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 115         },
 116 };
 117
 118 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 119 {
 120         unsigned i;
 121
 122         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 123                 if (hvs_formats[i].drm == drm_format)
 124                         return &hvs_formats[i];
 125         }
 126
 127         return NULL;
 128 }
 129
 130 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 131 {
 132         if (dst > src)
 133                 return VC4_SCALING_PPF;
 134         else if (dst < src)
 135                 return VC4_SCALING_TPZ;
 136         else
 137                 return VC4_SCALING_NONE;
 138 }
 139
 140 static bool plane_enabled(struct drm_plane_state *state)
 141 {
 142         return state->fb && state->crtc;
 143 }
 144
 145 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 146 {
 147         struct vc4_plane_state *vc4_state;
 148
 149         if (WARN_ON(!plane->state))
 150                 return NULL;
 151
 152         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 153         if (!vc4_state)
 154                 return NULL;
 155
 156         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 157
 158         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 159
 160         if (vc4_state->dlist) {
 161                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 162                                            vc4_state->dlist_count * 4,
 163                                            GFP_KERNEL);
 164                 if (!vc4_state->dlist) {
 165                         kfree(vc4_state);
 166                         return NULL;
 167                 }
 168                 vc4_state->dlist_size = vc4_state->dlist_count;
 169         }
 170
 171         return &vc4_state->base;
 172 }
 173
 174 static void vc4_plane_destroy_state(struct drm_plane *plane,
 175                                     struct drm_plane_state *state)
 176 {
 177         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 178         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 179
 180         if (vc4_state->lbm.allocated) {
 181                 unsigned long irqflags;
 182
 183                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 184                 drm_mm_remove_node(&vc4_state->lbm);
 185                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 186         }
 187
 188         kfree(vc4_state->dlist);
 189         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 190         kfree(state);
 191 }
 192
 193 /* Called during init to allocate the plane's atomic state. */
 194 static void vc4_plane_reset(struct drm_plane *plane)
 195 {
 196         struct vc4_plane_state *vc4_state;
 197
 198         WARN_ON(plane->state);
 199
 200         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 201         if (!vc4_state)
 202                 return;
 203
 204         __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
 205 }
 206
 207 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 208 {
 209         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 210                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 211                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 212
 213                 if (!new_dlist)
 214                         return;
 215                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 216
 217                 kfree(vc4_state->dlist);
 218                 vc4_state->dlist = new_dlist;
 219                 vc4_state->dlist_size = new_size;
 220         }
 221
 222         vc4_state->dlist[vc4_state->dlist_count++] = val;
 223 }
 224
 225 /* Returns the scl0/scl1 field based on whether the dimensions need to
 226  * be up/down/non-scaled.
 227  *
 228  * This is a replication of a table from the spec.
 229  */
 230 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 231 {
 232         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 233
 234         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 235         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 236                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 237         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 238                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 239         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 240                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 241         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 242                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 243         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 244                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 245         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 246                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 247         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 248                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 249         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 250                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 251         default:
 252         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 253                 /* The unity case is independently handled by
 254                  * SCALER_CTL0_UNITY.
 255                  */
 256                 return 0;
 257         }
 258 }
 259
 260 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 261 {
 262         struct drm_plane *plane = state->plane;
 263         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 264         struct drm_framebuffer *fb = state->fb;
 265         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 266         u32 subpixel_src_mask = (1 << 16) - 1;
 267         u32 format = fb->format->format;
 268         int num_planes = fb->format->num_planes;
 269         int min_scale = 1, max_scale = INT_MAX;
 270         struct drm_crtc_state *crtc_state;
 271         u32 h_subsample, v_subsample;
 272         int i, ret;
 273
 274         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 275                                                         state->crtc);
 276         if (!crtc_state) {
 277                 DRM_DEBUG_KMS("Invalid crtc state\n");
 278                 return -EINVAL;
 279         }
 280
 281         /* No configuring scaling on the cursor plane, since it gets
 282          * non-vblank-synced updates, and scaling requires LBM changes which
 283          * have to be vblank-synced.
 284          */
 285         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
 286                 min_scale = DRM_PLANE_HELPER_NO_SCALING;
 287                 max_scale = DRM_PLANE_HELPER_NO_SCALING;
 288         } else {
 289                 min_scale = 1;
 290                 max_scale = INT_MAX;
 291         }
 292
 293         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 294                                                   min_scale, max_scale,
 295                                                   true, true);
 296         if (ret)
 297                 return ret;
 298
 299         h_subsample = drm_format_horz_chroma_subsampling(format);
 300         v_subsample = drm_format_vert_chroma_subsampling(format);
 301
 302         for (i = 0; i < num_planes; i++)
 303                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 304
 305         /* We don't support subpixel source positioning for scaling. */
 306         if ((state->src.x1 & subpixel_src_mask) ||
 307             (state->src.x2 & subpixel_src_mask) ||
 308             (state->src.y1 & subpixel_src_mask) ||
 309             (state->src.y2 & subpixel_src_mask)) {
 310                 return -EINVAL;
 311         }
 312
 313         vc4_state->src_x = state->src.x1 >> 16;
 314         vc4_state->src_y = state->src.y1 >> 16;
 315         vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
 316         vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
 317
 318         vc4_state->crtc_x = state->dst.x1;
 319         vc4_state->crtc_y = state->dst.y1;
 320         vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
 321         vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
 322
 323         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 324                                                        vc4_state->crtc_w);
 325         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 326                                                        vc4_state->crtc_h);
 327
 328         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 329                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 330
 331         if (num_planes > 1) {
 332                 vc4_state->is_yuv = true;
 333
 334                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 335                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 336
 337                 vc4_state->x_scaling[1] =
 338                         vc4_get_scaling_mode(vc4_state->src_w[1],
 339                                              vc4_state->crtc_w);
 340                 vc4_state->y_scaling[1] =
 341                         vc4_get_scaling_mode(vc4_state->src_h[1],
 342                                              vc4_state->crtc_h);
 343
 344                 /* YUV conversion requires that horizontal scaling be enabled,
 345                  * even on a plane that's otherwise 1:1. Looks like only PPF
 346                  * works in that case, so let's pick that one.
 347                  */
 348                 if (vc4_state->is_unity)
 349                         vc4_state->x_scaling[0] = VC4_SCALING_PPF;
 350         } else {
 351                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 352                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 353         }
 354
 355         /* Adjust the base pointer to the first pixel to be scanned out. */
 356         for (i = 0; i < num_planes; i++) {
 357                 vc4_state->offsets[i] += (vc4_state->src_y /
 358                                           (i ? v_subsample : 1)) *
 359                                          fb->pitches[i];
 360                 vc4_state->offsets[i] += (vc4_state->src_x /
 361                                           (i ? h_subsample : 1)) *
 362                                          fb->format->cpp[i];
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 369 {
 370         u32 scale, recip;
 371
 372         scale = (1 << 16) * src / dst;
 373
 374         /* The specs note that while the reciprocal would be defined
 375          * as (1<<32)/scale, ~0 is close enough.
 376          */
 377         recip = ~0 / scale;
 378
 379         vc4_dlist_write(vc4_state,
 380                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 381                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 382         vc4_dlist_write(vc4_state,
 383                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 384 }
 385
 386 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 387 {
 388         u32 scale = (1 << 16) * src / dst;
 389
 390         vc4_dlist_write(vc4_state,
 391                         SCALER_PPF_AGC |
 392                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 393                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 394 }
 395
 396 static u32 vc4_lbm_size(struct drm_plane_state *state)
 397 {
 398         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 399         /* This is the worst case number.  One of the two sizes will
 400          * be used depending on the scaling configuration.
 401          */
 402         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 403         u32 lbm;
 404
 405         if (!vc4_state->is_yuv) {
 406                 if (vc4_state->is_unity)
 407                         return 0;
 408                 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 409                         lbm = pix_per_line * 8;
 410                 else {
 411                         /* In special cases, this multiplier might be 12. */
 412                         lbm = pix_per_line * 16;
 413                 }
 414         } else {
 415                 /* There are cases for this going down to a multiplier
 416                  * of 2, but according to the firmware source, the
 417                  * table in the docs is somewhat wrong.
 418                  */
 419                 lbm = pix_per_line * 16;
 420         }
 421
 422         lbm = roundup(lbm, 32);
 423
 424         return lbm;
 425 }
 426
 427 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 428                                          int channel)
 429 {
 430         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 431
 432         /* Ch0 H-PPF Word 0: Scaling Parameters */
 433         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 434                 vc4_write_ppf(vc4_state,
 435                               vc4_state->src_w[channel], vc4_state->crtc_w);
 436         }
 437
 438         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 439         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 440                 vc4_write_ppf(vc4_state,
 441                               vc4_state->src_h[channel], vc4_state->crtc_h);
 442                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 443         }
 444
 445         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 446         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 447                 vc4_write_tpz(vc4_state,
 448                               vc4_state->src_w[channel], vc4_state->crtc_w);
 449         }
 450
 451         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 452         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 453                 vc4_write_tpz(vc4_state,
 454                               vc4_state->src_h[channel], vc4_state->crtc_h);
 455                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 456         }
 457 }
 458
 459 /* Writes out a full display list for an active plane to the plane's
 460  * private dlist state.
 461  */
 462 static int vc4_plane_mode_set(struct drm_plane *plane,
 463                               struct drm_plane_state *state)
 464 {
 465         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 466         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 467         struct drm_framebuffer *fb = state->fb;
 468         u32 ctl0_offset = vc4_state->dlist_count;
 469         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 470         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 471         int num_planes = drm_format_num_planes(format->drm);
 472         bool mix_plane_alpha;
 473         bool covers_screen;
 474         u32 scl0, scl1, pitch0;
 475         u32 lbm_size, tiling;
 476         unsigned long irqflags;
 477         u32 hvs_format = format->hvs;
 478         int ret, i;
 479
 480         ret = vc4_plane_setup_clipping_and_scaling(state);
 481         if (ret)
 482                 return ret;
 483
 484         /* Allocate the LBM memory that the HVS will use for temporary
 485          * storage due to our scaling/format conversion.
 486          */
 487         lbm_size = vc4_lbm_size(state);
 488         if (lbm_size) {
 489                 if (!vc4_state->lbm.allocated) {
 490                         spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 491                         ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 492                                                          &vc4_state->lbm,
 493                                                          lbm_size, 32, 0, 0);
 494                         spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 495                 } else {
 496                         WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 497                 }
 498         }
 499
 500         if (ret)
 501                 return ret;
 502
 503         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 504          * and 4:4:4, scl1 should be set to scl0 so both channels of
 505          * the scaler do the same thing.  For YUV, the Y plane needs
 506          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 507          * the scl fields here.
 508          */
 509         if (num_planes == 1) {
 510                 scl0 = vc4_get_scl_field(state, 0);
 511                 scl1 = scl0;
 512         } else {
 513                 scl0 = vc4_get_scl_field(state, 1);
 514                 scl1 = vc4_get_scl_field(state, 0);
 515         }
 516
 517         switch (base_format_mod) {
 518         case DRM_FORMAT_MOD_LINEAR:
 519                 tiling = SCALER_CTL0_TILING_LINEAR;
 520                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 521                 break;
 522
 523         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 524                 /* For T-tiled, the FB pitch is "how many bytes from
 525                  * one row to the next, such that pitch * tile_h ==
 526                  * tile_size * tiles_per_row."
 527                  */
 528                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 529                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 530                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 531
 532                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 533
 534                 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
 535                           VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
 536                           VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
 537                 break;
 538         }
 539
 540         case DRM_FORMAT_MOD_BROADCOM_SAND64:
 541         case DRM_FORMAT_MOD_BROADCOM_SAND128:
 542         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 543                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
 544
 545                 /* Column-based NV12 or RGBA.
 546                  */
 547                 if (fb->format->num_planes > 1) {
 548                         if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) {
 549                                 DRM_DEBUG_KMS("SAND format only valid for NV12/21");
 550                                 return -EINVAL;
 551                         }
 552                         hvs_format = HVS_PIXEL_FORMAT_H264;
 553                 } else {
 554                         if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) {
 555                                 DRM_DEBUG_KMS("SAND256 format only valid for H.264");
 556                                 return -EINVAL;
 557                         }
 558                 }
 559
 560                 switch (base_format_mod) {
 561                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 562                         tiling = SCALER_CTL0_TILING_64B;
 563                         break;
 564                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 565                         tiling = SCALER_CTL0_TILING_128B;
 566                         break;
 567                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 568                         tiling = SCALER_CTL0_TILING_256B_OR_T;
 569                         break;
 570                 default:
 571                         break;
 572                 }
 573
 574                 if (param > SCALER_TILE_HEIGHT_MASK) {
 575                         DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
 576                         return -EINVAL;
 577                 }
 578
 579                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
 580                 break;
 581         }
 582
 583         default:
 584                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 585                               (long long)fb->modifier);
 586                 return -EINVAL;
 587         }
 588
 589         /* Control word */
 590         vc4_dlist_write(vc4_state,
 591                         SCALER_CTL0_VALID |
 592                         VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
 593                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 594                         (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 595                         VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 596                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 597                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 598                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 599
 600         /* Position Word 0: Image Positions and Alpha Value */
 601         vc4_state->pos0_offset = vc4_state->dlist_count;
 602         vc4_dlist_write(vc4_state,
 603                         VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
 604                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 605                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 606
 607         /* Position Word 1: Scaled Image Dimensions. */
 608         if (!vc4_state->is_unity) {
 609                 vc4_dlist_write(vc4_state,
 610                                 VC4_SET_FIELD(vc4_state->crtc_w,
 611                                               SCALER_POS1_SCL_WIDTH) |
 612                                 VC4_SET_FIELD(vc4_state->crtc_h,
 613                                               SCALER_POS1_SCL_HEIGHT));
 614         }
 615
 616         /* Don't waste cycles mixing with plane alpha if the set alpha
 617          * is opaque or there is no per-pixel alpha information.
 618          * In any case we use the alpha property value as the fixed alpha.
 619          */
 620         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 621                           fb->format->has_alpha;
 622
 623         /* Position Word 2: Source Image Size, Alpha */
 624         vc4_state->pos2_offset = vc4_state->dlist_count;
 625         vc4_dlist_write(vc4_state,
 626                         VC4_SET_FIELD(fb->format->has_alpha ?
 627                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 628                                       SCALER_POS2_ALPHA_MODE_FIXED,
 629                                       SCALER_POS2_ALPHA_MODE) |
 630                         (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
 631                         (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
 632                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 633                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 634
 635         /* Position Word 3: Context.  Written by the HVS. */
 636         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 637
 638
 639         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 640          *
 641          * The pointers may be any byte address.
 642          */
 643         vc4_state->ptr0_offset = vc4_state->dlist_count;
 644         for (i = 0; i < num_planes; i++)
 645                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 646
 647         /* Pointer Context Word 0/1/2: Written by the HVS */
 648         for (i = 0; i < num_planes; i++)
 649                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 650
 651         /* Pitch word 0 */
 652         vc4_dlist_write(vc4_state, pitch0);
 653
 654         /* Pitch word 1/2 */
 655         for (i = 1; i < num_planes; i++) {
 656                 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
 657                         vc4_dlist_write(vc4_state,
 658                                         VC4_SET_FIELD(fb->pitches[i],
 659                                                       SCALER_SRC_PITCH));
 660                 } else {
 661                         vc4_dlist_write(vc4_state, pitch0);
 662                 }
 663         }
 664
 665         /* Colorspace conversion words */
 666         if (vc4_state->is_yuv) {
 667                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 668                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 669                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 670         }
 671
 672         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 673             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 674             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 675             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 676                 /* LBM Base Address. */
 677                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 678                     vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 679                         vc4_dlist_write(vc4_state, vc4_state->lbm.start);
 680                 }
 681
 682                 if (num_planes > 1) {
 683                         /* Emit Cb/Cr as channel 0 and Y as channel
 684                          * 1. This matches how we set up scl0/scl1
 685                          * above.
 686                          */
 687                         vc4_write_scaling_parameters(state, 1);
 688                 }
 689                 vc4_write_scaling_parameters(state, 0);
 690
 691                 /* If any PPF setup was done, then all the kernel
 692                  * pointers get uploaded.
 693                  */
 694                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 695                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 696                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 697                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 698                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 699                                                    SCALER_PPF_KERNEL_OFFSET);
 700
 701                         /* HPPF plane 0 */
 702                         vc4_dlist_write(vc4_state, kernel);
 703                         /* VPPF plane 0 */
 704                         vc4_dlist_write(vc4_state, kernel);
 705                         /* HPPF plane 1 */
 706                         vc4_dlist_write(vc4_state, kernel);
 707                         /* VPPF plane 1 */
 708                         vc4_dlist_write(vc4_state, kernel);
 709                 }
 710         }
 711
 712         vc4_state->dlist[ctl0_offset] |=
 713                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 714
 715         /* crtc_* are already clipped coordinates. */
 716         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
 717                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
 718                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
 719         /* Background fill might be necessary when the plane has per-pixel
 720          * alpha content or a non-opaque plane alpha and could blend from the
 721          * background or does not cover the entire screen.
 722          */
 723         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
 724                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
 725
 726         return 0;
 727 }
 728
 729 /* If a modeset involves changing the setup of a plane, the atomic
 730  * infrastructure will call this to validate a proposed plane setup.
 731  * However, if a plane isn't getting updated, this (and the
 732  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 733  * compute the dlist here and have all active plane dlists get updated
 734  * in the CRTC's flush.
 735  */
 736 static int vc4_plane_atomic_check(struct drm_plane *plane,
 737                                   struct drm_plane_state *state)
 738 {
 739         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 740
 741         vc4_state->dlist_count = 0;
 742
 743         if (plane_enabled(state))
 744                 return vc4_plane_mode_set(plane, state);
 745         else
 746                 return 0;
 747 }
 748
 749 static void vc4_plane_atomic_update(struct drm_plane *plane,
 750                                     struct drm_plane_state *old_state)
 751 {
 752         /* No contents here.  Since we don't know where in the CRTC's
 753          * dlist we should be stored, our dlist is uploaded to the
 754          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 755          * time.
 756          */
 757 }
 758
 759 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 760 {
 761         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 762         int i;
 763
 764         vc4_state->hw_dlist = dlist;
 765
 766         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 767         for (i = 0; i < vc4_state->dlist_count; i++)
 768                 writel(vc4_state->dlist[i], &dlist[i]);
 769
 770         return vc4_state->dlist_count;
 771 }
 772
 773 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 774 {
 775         const struct vc4_plane_state *vc4_state =
 776                 container_of(state, typeof(*vc4_state), base);
 777
 778         return vc4_state->dlist_count;
 779 }
 780
 781 /* Updates the plane to immediately (well, once the FIFO needs
 782  * refilling) scan out from at a new framebuffer.
 783  */
 784 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 785 {
 786         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 787         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 788         uint32_t addr;
 789
 790         /* We're skipping the address adjustment for negative origin,
 791          * because this is only called on the primary plane.
 792          */
 793         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
 794         addr = bo->paddr + fb->offsets[0];
 795
 796         /* Write the new address into the hardware immediately.  The
 797          * scanout will start from this address as soon as the FIFO
 798          * needs to refill with pixels.
 799          */
 800         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 801
 802         /* Also update the CPU-side dlist copy, so that any later
 803          * atomic updates that don't do a new modeset on our plane
 804          * also use our updated address.
 805          */
 806         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
 807 }
 808
 809 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
 810                                           struct drm_plane_state *state)
 811 {
 812         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 813
 814         if (plane->state->fb != state->fb) {
 815                 vc4_plane_async_set_fb(plane, state->fb);
 816                 drm_atomic_set_fb_for_plane(plane->state, state->fb);
 817         }
 818
 819         /* Set the cursor's position on the screen.  This is the
 820          * expected change from the drm_mode_cursor_universal()
 821          * helper.
 822          */
 823         plane->state->crtc_x = state->crtc_x;
 824         plane->state->crtc_y = state->crtc_y;
 825
 826         /* Allow changing the start position within the cursor BO, if
 827          * that matters.
 828          */
 829         plane->state->src_x = state->src_x;
 830         plane->state->src_y = state->src_y;
 831
 832         /* Update the display list based on the new crtc_x/y. */
 833         vc4_plane_atomic_check(plane, plane->state);
 834
 835         /* Note that we can't just call vc4_plane_write_dlist()
 836          * because that would smash the context data that the HVS is
 837          * currently using.
 838          */
 839         writel(vc4_state->dlist[vc4_state->pos0_offset],
 840                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
 841         writel(vc4_state->dlist[vc4_state->pos2_offset],
 842                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
 843         writel(vc4_state->dlist[vc4_state->ptr0_offset],
 844                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
 845 }
 846
 847 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
 848                                         struct drm_plane_state *state)
 849 {
 850         /* No configuring new scaling in the fast path. */
 851         if (plane->state->crtc_w != state->crtc_w ||
 852             plane->state->crtc_h != state->crtc_h ||
 853             plane->state->src_w != state->src_w ||
 854             plane->state->src_h != state->src_h)
 855                 return -EINVAL;
 856
 857         return 0;
 858 }
 859
 860 static int vc4_prepare_fb(struct drm_plane *plane,
 861                           struct drm_plane_state *state)
 862 {
 863         struct vc4_bo *bo;
 864         struct dma_fence *fence;
 865         int ret;
 866
 867         if (!state->fb)
 868                 return 0;
 869
 870         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 871
 872         fence = reservation_object_get_excl_rcu(bo->resv);
 873         drm_atomic_set_fence_for_plane(state, fence);
 874
 875         if (plane->state->fb == state->fb)
 876                 return 0;
 877
 878         ret = vc4_bo_inc_usecnt(bo);
 879         if (ret)
 880                 return ret;
 881
 882         return 0;
 883 }
 884
 885 static void vc4_cleanup_fb(struct drm_plane *plane,
 886                            struct drm_plane_state *state)
 887 {
 888         struct vc4_bo *bo;
 889
 890         if (plane->state->fb == state->fb || !state->fb)
 891                 return;
 892
 893         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
 894         vc4_bo_dec_usecnt(bo);
 895 }
 896
 897 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
 898         .atomic_check = vc4_plane_atomic_check,
 899         .atomic_update = vc4_plane_atomic_update,
 900         .prepare_fb = vc4_prepare_fb,
 901         .cleanup_fb = vc4_cleanup_fb,
 902         .atomic_async_check = vc4_plane_atomic_async_check,
 903         .atomic_async_update = vc4_plane_atomic_async_update,
 904 };
 905
 906 static void vc4_plane_destroy(struct drm_plane *plane)
 907 {
 908         drm_plane_cleanup(plane);
 909 }
 910
 911 static bool vc4_format_mod_supported(struct drm_plane *plane,
 912                                      uint32_t format,
 913                                      uint64_t modifier)
 914 {
 915         /* Support T_TILING for RGB formats only. */
 916         switch (format) {
 917         case DRM_FORMAT_XRGB8888:
 918         case DRM_FORMAT_ARGB8888:
 919         case DRM_FORMAT_ABGR8888:
 920         case DRM_FORMAT_XBGR8888:
 921         case DRM_FORMAT_RGB565:
 922         case DRM_FORMAT_BGR565:
 923         case DRM_FORMAT_ARGB1555:
 924         case DRM_FORMAT_XRGB1555:
 925                 switch (fourcc_mod_broadcom_mod(modifier)) {
 926                 case DRM_FORMAT_MOD_LINEAR:
 927                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
 928                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 929                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 930                         return true;
 931                 default:
 932                         return false;
 933                 }
 934         case DRM_FORMAT_NV12:
 935         case DRM_FORMAT_NV21:
 936                 switch (fourcc_mod_broadcom_mod(modifier)) {
 937                 case DRM_FORMAT_MOD_LINEAR:
 938                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 939                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 940                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 941                         return true;
 942                 default:
 943                         return false;
 944                 }
 945         case DRM_FORMAT_YUV422:
 946         case DRM_FORMAT_YVU422:
 947         case DRM_FORMAT_YUV420:
 948         case DRM_FORMAT_YVU420:
 949         case DRM_FORMAT_NV16:
 950         case DRM_FORMAT_NV61:
 951         default:
 952                 return (modifier == DRM_FORMAT_MOD_LINEAR);
 953         }
 954 }
 955
 956 static const struct drm_plane_funcs vc4_plane_funcs = {
 957         .update_plane = drm_atomic_helper_update_plane,
 958         .disable_plane = drm_atomic_helper_disable_plane,
 959         .destroy = vc4_plane_destroy,
 960         .set_property = NULL,
 961         .reset = vc4_plane_reset,
 962         .atomic_duplicate_state = vc4_plane_duplicate_state,
 963         .atomic_destroy_state = vc4_plane_destroy_state,
 964         .format_mod_supported = vc4_format_mod_supported,
 965 };
 966
 967 struct drm_plane *vc4_plane_init(struct drm_device *dev,
 968                                  enum drm_plane_type type)
 969 {
 970         struct drm_plane *plane = NULL;
 971         struct vc4_plane *vc4_plane;
 972         u32 formats[ARRAY_SIZE(hvs_formats)];
 973         u32 num_formats = 0;
 974         int ret = 0;
 975         unsigned i;
 976         static const uint64_t modifiers[] = {
 977                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 978                 DRM_FORMAT_MOD_BROADCOM_SAND128,
 979                 DRM_FORMAT_MOD_BROADCOM_SAND64,
 980                 DRM_FORMAT_MOD_BROADCOM_SAND256,
 981                 DRM_FORMAT_MOD_LINEAR,
 982                 DRM_FORMAT_MOD_INVALID
 983         };
 984
 985         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
 986                                  GFP_KERNEL);
 987         if (!vc4_plane)
 988                 return ERR_PTR(-ENOMEM);
 989
 990         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 991                 /* Don't allow YUV in cursor planes, since that means
 992                  * tuning on the scaler, which we don't allow for the
 993                  * cursor.
 994                  */
 995                 if (type != DRM_PLANE_TYPE_CURSOR ||
 996                     hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) {
 997                         formats[num_formats++] = hvs_formats[i].drm;
 998                 }
 999         }
1000         plane = &vc4_plane->base;
1001         ret = drm_universal_plane_init(dev, plane, 0,
1002                                        &vc4_plane_funcs,
1003                                        formats, num_formats,
1004                                        modifiers, type, NULL);
1005
1006         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1007
1008         drm_plane_create_alpha_property(plane);
1009
1010         return plane;
1011 }