drivers/gpu/drm/vc4/vc4_v3d.c

   1 /*
   2  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/component.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include <drm/drm_irq.h>
  25
  26 #include "vc4_drv.h"
  27 #include "vc4_regs.h"
  28
  29 static const struct debugfs_reg32 v3d_regs[] = {
  30         VC4_REG32(V3D_IDENT0),
  31         VC4_REG32(V3D_IDENT1),
  32         VC4_REG32(V3D_IDENT2),
  33         VC4_REG32(V3D_SCRATCH),
  34         VC4_REG32(V3D_L2CACTL),
  35         VC4_REG32(V3D_SLCACTL),
  36         VC4_REG32(V3D_INTCTL),
  37         VC4_REG32(V3D_INTENA),
  38         VC4_REG32(V3D_INTDIS),
  39         VC4_REG32(V3D_CT0CS),
  40         VC4_REG32(V3D_CT1CS),
  41         VC4_REG32(V3D_CT0EA),
  42         VC4_REG32(V3D_CT1EA),
  43         VC4_REG32(V3D_CT0CA),
  44         VC4_REG32(V3D_CT1CA),
  45         VC4_REG32(V3D_CT00RA0),
  46         VC4_REG32(V3D_CT01RA0),
  47         VC4_REG32(V3D_CT0LC),
  48         VC4_REG32(V3D_CT1LC),
  49         VC4_REG32(V3D_CT0PC),
  50         VC4_REG32(V3D_CT1PC),
  51         VC4_REG32(V3D_PCS),
  52         VC4_REG32(V3D_BFC),
  53         VC4_REG32(V3D_RFC),
  54         VC4_REG32(V3D_BPCA),
  55         VC4_REG32(V3D_BPCS),
  56         VC4_REG32(V3D_BPOA),
  57         VC4_REG32(V3D_BPOS),
  58         VC4_REG32(V3D_BXCF),
  59         VC4_REG32(V3D_SQRSV0),
  60         VC4_REG32(V3D_SQRSV1),
  61         VC4_REG32(V3D_SQCNTL),
  62         VC4_REG32(V3D_SRQPC),
  63         VC4_REG32(V3D_SRQUA),
  64         VC4_REG32(V3D_SRQUL),
  65         VC4_REG32(V3D_SRQCS),
  66         VC4_REG32(V3D_VPACNTL),
  67         VC4_REG32(V3D_VPMBASE),
  68         VC4_REG32(V3D_PCTRC),
  69         VC4_REG32(V3D_PCTRE),
  70         VC4_REG32(V3D_PCTR(0)),
  71         VC4_REG32(V3D_PCTRS(0)),
  72         VC4_REG32(V3D_PCTR(1)),
  73         VC4_REG32(V3D_PCTRS(1)),
  74         VC4_REG32(V3D_PCTR(2)),
  75         VC4_REG32(V3D_PCTRS(2)),
  76         VC4_REG32(V3D_PCTR(3)),
  77         VC4_REG32(V3D_PCTRS(3)),
  78         VC4_REG32(V3D_PCTR(4)),
  79         VC4_REG32(V3D_PCTRS(4)),
  80         VC4_REG32(V3D_PCTR(5)),
  81         VC4_REG32(V3D_PCTRS(5)),
  82         VC4_REG32(V3D_PCTR(6)),
  83         VC4_REG32(V3D_PCTRS(6)),
  84         VC4_REG32(V3D_PCTR(7)),
  85         VC4_REG32(V3D_PCTRS(7)),
  86         VC4_REG32(V3D_PCTR(8)),
  87         VC4_REG32(V3D_PCTRS(8)),
  88         VC4_REG32(V3D_PCTR(9)),
  89         VC4_REG32(V3D_PCTRS(9)),
  90         VC4_REG32(V3D_PCTR(10)),
  91         VC4_REG32(V3D_PCTRS(10)),
  92         VC4_REG32(V3D_PCTR(11)),
  93         VC4_REG32(V3D_PCTRS(11)),
  94         VC4_REG32(V3D_PCTR(12)),
  95         VC4_REG32(V3D_PCTRS(12)),
  96         VC4_REG32(V3D_PCTR(13)),
  97         VC4_REG32(V3D_PCTRS(13)),
  98         VC4_REG32(V3D_PCTR(14)),
  99         VC4_REG32(V3D_PCTRS(14)),
 100         VC4_REG32(V3D_PCTR(15)),
 101         VC4_REG32(V3D_PCTRS(15)),
 102         VC4_REG32(V3D_DBGE),
 103         VC4_REG32(V3D_FDBGO),
 104         VC4_REG32(V3D_FDBGB),
 105         VC4_REG32(V3D_FDBGR),
 106         VC4_REG32(V3D_FDBGS),
 107         VC4_REG32(V3D_ERRSTAT),
 108 };
 109
 110 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
 111 {
 112         struct drm_info_node *node = (struct drm_info_node *)m->private;
 113         struct drm_device *dev = node->minor->dev;
 114         struct vc4_dev *vc4 = to_vc4_dev(dev);
 115         int ret = vc4_v3d_pm_get(vc4);
 116
 117         if (ret == 0) {
 118                 uint32_t ident1 = V3D_READ(V3D_IDENT1);
 119                 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
 120                 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
 121                 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
 122
 123                 seq_printf(m, "Revision:   %d\n",
 124                            VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
 125                 seq_printf(m, "Slices:     %d\n", nslc);
 126                 seq_printf(m, "TMUs:       %d\n", nslc * tups);
 127                 seq_printf(m, "QPUs:       %d\n", nslc * qups);
 128                 seq_printf(m, "Semaphores: %d\n",
 129                            VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
 130                 vc4_v3d_pm_put(vc4);
 131         }
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably
 138  * get the pm_runtime refcount to 0 in vc4_reset().
 139  */
 140 int
 141 vc4_v3d_pm_get(struct vc4_dev *vc4)
 142 {
 143         mutex_lock(&vc4->power_lock);
 144         if (vc4->power_refcount++ == 0) {
 145                 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
 146
 147                 if (ret < 0) {
 148                         vc4->power_refcount--;
 149                         mutex_unlock(&vc4->power_lock);
 150                         return ret;
 151                 }
 152         }
 153         mutex_unlock(&vc4->power_lock);
 154
 155         return 0;
 156 }
 157
 158 void
 159 vc4_v3d_pm_put(struct vc4_dev *vc4)
 160 {
 161         mutex_lock(&vc4->power_lock);
 162         if (--vc4->power_refcount == 0) {
 163                 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
 164                 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
 165         }
 166         mutex_unlock(&vc4->power_lock);
 167 }
 168
 169 static void vc4_v3d_init_hw(struct drm_device *dev)
 170 {
 171         struct vc4_dev *vc4 = to_vc4_dev(dev);
 172
 173         /* Take all the memory that would have been reserved for user
 174          * QPU programs, since we don't have an interface for running
 175          * them, anyway.
 176          */
 177         V3D_WRITE(V3D_VPMBASE, 0);
 178 }
 179
 180 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
 181 {
 182         struct drm_device *dev = vc4->dev;
 183         unsigned long irqflags;
 184         int slot;
 185         uint64_t seqno = 0;
 186         struct vc4_exec_info *exec;
 187
 188 try_again:
 189         spin_lock_irqsave(&vc4->job_lock, irqflags);
 190         slot = ffs(~vc4->bin_alloc_used);
 191         if (slot != 0) {
 192                 /* Switch from ffs() bit index to a 0-based index. */
 193                 slot--;
 194                 vc4->bin_alloc_used |= BIT(slot);
 195                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 196                 return slot;
 197         }
 198
 199         /* Couldn't find an open slot.  Wait for render to complete
 200          * and try again.
 201          */
 202         exec = vc4_last_render_job(vc4);
 203         if (exec)
 204                 seqno = exec->seqno;
 205         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 206
 207         if (seqno) {
 208                 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true);
 209
 210                 if (ret == 0)
 211                         goto try_again;
 212
 213                 return ret;
 214         }
 215
 216         return -ENOMEM;
 217 }
 218
 219 /**
 220  * bin_bo_alloc() - allocates the memory that will be used for
 221  * tile binning.
 222  *
 223  * The binner has a limitation that the addresses in the tile state
 224  * buffer that point into the tile alloc buffer or binner overflow
 225  * memory only have 28 bits (256MB), and the top 4 on the bus for
 226  * tile alloc references end up coming from the tile state buffer's
 227  * address.
 228  *
 229  * To work around this, we allocate a single large buffer while V3D is
 230  * in use, make sure that it has the top 4 bits constant across its
 231  * entire extent, and then put the tile state, tile alloc, and binner
 232  * overflow memory inside that buffer.
 233  *
 234  * This creates a limitation where we may not be able to execute a job
 235  * if it doesn't fit within the buffer that we allocated up front.
 236  * However, it turns out that 16MB is "enough for anybody", and
 237  * real-world applications run into allocation failures from the
 238  * overall CMA pool before they make scenes complicated enough to run
 239  * out of bin space.
 240  */
 241 static int bin_bo_alloc(struct vc4_dev *vc4)
 242 {
 243         struct vc4_v3d *v3d = vc4->v3d;
 244         uint32_t size = 16 * 1024 * 1024;
 245         int ret = 0;
 246         struct list_head list;
 247
 248         if (!v3d)
 249                 return -ENODEV;
 250
 251         /* We may need to try allocating more than once to get a BO
 252          * that doesn't cross 256MB.  Track the ones we've allocated
 253          * that failed so far, so that we can free them when we've got
 254          * one that succeeded (if we freed them right away, our next
 255          * allocation would probably be the same chunk of memory).
 256          */
 257         INIT_LIST_HEAD(&list);
 258
 259         while (true) {
 260                 struct vc4_bo *bo = vc4_bo_create(vc4->dev, size, true,
 261                                                   VC4_BO_TYPE_BIN);
 262
 263                 if (IS_ERR(bo)) {
 264                         ret = PTR_ERR(bo);
 265
 266                         dev_err(&v3d->pdev->dev,
 267                                 "Failed to allocate memory for tile binning: "
 268                                 "%d. You may need to enable CMA or give it "
 269                                 "more memory.",
 270                                 ret);
 271                         break;
 272                 }
 273
 274                 /* Check if this BO won't trigger the addressing bug. */
 275                 if ((bo->base.paddr & 0xf0000000) ==
 276                     ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) {
 277                         vc4->bin_bo = bo;
 278
 279                         /* Set up for allocating 512KB chunks of
 280                          * binner memory.  The biggest allocation we
 281                          * need to do is for the initial tile alloc +
 282                          * tile state buffer.  We can render to a
 283                          * maximum of ((2048*2048) / (32*32) = 4096
 284                          * tiles in a frame (until we do floating
 285                          * point rendering, at which point it would be
 286                          * 8192).  Tile state is 48b/tile (rounded to
 287                          * a page), and tile alloc is 32b/tile
 288                          * (rounded to a page), plus a page of extra,
 289                          * for a total of 320kb for our worst-case.
 290                          * We choose 512kb so that it divides evenly
 291                          * into our 16MB, and the rest of the 512kb
 292                          * will be used as storage for the overflow
 293                          * from the initial 32b CL per bin.
 294                          */
 295                         vc4->bin_alloc_size = 512 * 1024;
 296                         vc4->bin_alloc_used = 0;
 297                         vc4->bin_alloc_overflow = 0;
 298                         WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
 299                                      bo->base.base.size / vc4->bin_alloc_size);
 300
 301                         kref_init(&vc4->bin_bo_kref);
 302
 303                         /* Enable the out-of-memory interrupt to set our
 304                          * newly-allocated binner BO, potentially from an
 305                          * already-pending-but-masked interrupt.
 306                          */
 307                         V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
 308
 309                         break;
 310                 }
 311
 312                 /* Put it on the list to free later, and try again. */
 313                 list_add(&bo->unref_head, &list);
 314         }
 315
 316         /* Free all the BOs we allocated but didn't choose. */
 317         while (!list_empty(&list)) {
 318                 struct vc4_bo *bo = list_last_entry(&list,
 319                                                     struct vc4_bo, unref_head);
 320
 321                 list_del(&bo->unref_head);
 322                 drm_gem_object_put_unlocked(&bo->base.base);
 323         }
 324
 325         return ret;
 326 }
 327
 328 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used)
 329 {
 330         int ret = 0;
 331
 332         mutex_lock(&vc4->bin_bo_lock);
 333
 334         if (used && *used)
 335                 goto complete;
 336
 337         if (vc4->bin_bo)
 338                 kref_get(&vc4->bin_bo_kref);
 339         else
 340                 ret = bin_bo_alloc(vc4);
 341
 342         if (ret == 0 && used)
 343                 *used = true;
 344
 345 complete:
 346         mutex_unlock(&vc4->bin_bo_lock);
 347
 348         return ret;
 349 }
 350
 351 static void bin_bo_release(struct kref *ref)
 352 {
 353         struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref);
 354
 355         if (WARN_ON_ONCE(!vc4->bin_bo))
 356                 return;
 357
 358         drm_gem_object_put_unlocked(&vc4->bin_bo->base.base);
 359         vc4->bin_bo = NULL;
 360 }
 361
 362 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
 363 {
 364         mutex_lock(&vc4->bin_bo_lock);
 365         kref_put(&vc4->bin_bo_kref, bin_bo_release);
 366         mutex_unlock(&vc4->bin_bo_lock);
 367 }
 368
 369 #ifdef CONFIG_PM
 370 static int vc4_v3d_runtime_suspend(struct device *dev)
 371 {
 372         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 373         struct vc4_dev *vc4 = v3d->vc4;
 374
 375         vc4_irq_uninstall(vc4->dev);
 376
 377         clk_disable_unprepare(v3d->clk);
 378
 379         return 0;
 380 }
 381
 382 static int vc4_v3d_runtime_resume(struct device *dev)
 383 {
 384         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 385         struct vc4_dev *vc4 = v3d->vc4;
 386         int ret;
 387
 388         ret = clk_prepare_enable(v3d->clk);
 389         if (ret != 0)
 390                 return ret;
 391
 392         vc4_v3d_init_hw(vc4->dev);
 393
 394         /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
 395         enable_irq(vc4->dev->irq);
 396         vc4_irq_postinstall(vc4->dev);
 397
 398         return 0;
 399 }
 400 #endif
 401
 402 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
 403 {
 404         struct platform_device *pdev = to_platform_device(dev);
 405         struct drm_device *drm = dev_get_drvdata(master);
 406         struct vc4_dev *vc4 = to_vc4_dev(drm);
 407         struct vc4_v3d *v3d = NULL;
 408         int ret;
 409
 410         v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
 411         if (!v3d)
 412                 return -ENOMEM;
 413
 414         dev_set_drvdata(dev, v3d);
 415
 416         v3d->pdev = pdev;
 417
 418         v3d->regs = vc4_ioremap_regs(pdev, 0);
 419         if (IS_ERR(v3d->regs))
 420                 return PTR_ERR(v3d->regs);
 421         v3d->regset.base = v3d->regs;
 422         v3d->regset.regs = v3d_regs;
 423         v3d->regset.nregs = ARRAY_SIZE(v3d_regs);
 424
 425         vc4->v3d = v3d;
 426         v3d->vc4 = vc4;
 427
 428         v3d->clk = devm_clk_get(dev, NULL);
 429         if (IS_ERR(v3d->clk)) {
 430                 int ret = PTR_ERR(v3d->clk);
 431
 432                 if (ret == -ENOENT) {
 433                         /* bcm2835 didn't have a clock reference in the DT. */
 434                         ret = 0;
 435                         v3d->clk = NULL;
 436                 } else {
 437                         if (ret != -EPROBE_DEFER)
 438                                 dev_err(dev, "Failed to get V3D clock: %d\n",
 439                                         ret);
 440                         return ret;
 441                 }
 442         }
 443
 444         if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
 445                 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
 446                           V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
 447                 return -EINVAL;
 448         }
 449
 450         ret = clk_prepare_enable(v3d->clk);
 451         if (ret != 0)
 452                 return ret;
 453
 454         /* Reset the binner overflow address/size at setup, to be sure
 455          * we don't reuse an old one.
 456          */
 457         V3D_WRITE(V3D_BPOA, 0);
 458         V3D_WRITE(V3D_BPOS, 0);
 459
 460         vc4_v3d_init_hw(drm);
 461
 462         ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
 463         if (ret) {
 464                 DRM_ERROR("Failed to install IRQ handler\n");
 465                 return ret;
 466         }
 467
 468         pm_runtime_set_active(dev);
 469         pm_runtime_use_autosuspend(dev);
 470         pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
 471         pm_runtime_enable(dev);
 472
 473         vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL);
 474         vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset);
 475
 476         return 0;
 477 }
 478
 479 static void vc4_v3d_unbind(struct device *dev, struct device *master,
 480                            void *data)
 481 {
 482         struct drm_device *drm = dev_get_drvdata(master);
 483         struct vc4_dev *vc4 = to_vc4_dev(drm);
 484
 485         pm_runtime_disable(dev);
 486
 487         drm_irq_uninstall(drm);
 488
 489         /* Disable the binner's overflow memory address, so the next
 490          * driver probe (if any) doesn't try to reuse our old
 491          * allocation.
 492          */
 493         V3D_WRITE(V3D_BPOA, 0);
 494         V3D_WRITE(V3D_BPOS, 0);
 495
 496         vc4->v3d = NULL;
 497 }
 498
 499 static const struct dev_pm_ops vc4_v3d_pm_ops = {
 500         SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
 501 };
 502
 503 static const struct component_ops vc4_v3d_ops = {
 504         .bind   = vc4_v3d_bind,
 505         .unbind = vc4_v3d_unbind,
 506 };
 507
 508 static int vc4_v3d_dev_probe(struct platform_device *pdev)
 509 {
 510         return component_add(&pdev->dev, &vc4_v3d_ops);
 511 }
 512
 513 static int vc4_v3d_dev_remove(struct platform_device *pdev)
 514 {
 515         component_del(&pdev->dev, &vc4_v3d_ops);
 516         return 0;
 517 }
 518
 519 const struct of_device_id vc4_v3d_dt_match[] = {
 520         { .compatible = "brcm,bcm2835-v3d" },
 521         { .compatible = "brcm,cygnus-v3d" },
 522         { .compatible = "brcm,vc4-v3d" },
 523         {}
 524 };
 525
 526 struct platform_driver vc4_v3d_driver = {
 527         .probe = vc4_v3d_dev_probe,
 528         .remove = vc4_v3d_dev_remove,
 529         .driver = {
 530                 .name = "vc4_v3d",
 531                 .of_match_table = vc4_v3d_dt_match,
 532                 .pm = &vc4_v3d_pm_ops,
 533         },
 534 };