drivers/gpu/drm/vc4/vc4_v3d.c

   1 /*
   2  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/component.h>
  21 #include <linux/pm_runtime.h>
  22 #include "vc4_drv.h"
  23 #include "vc4_regs.h"
  24
  25 #ifdef CONFIG_DEBUG_FS
  26 static const struct debugfs_reg32 v3d_regs[] = {
  27         VC4_REG32(V3D_IDENT0),
  28         VC4_REG32(V3D_IDENT1),
  29         VC4_REG32(V3D_IDENT2),
  30         VC4_REG32(V3D_SCRATCH),
  31         VC4_REG32(V3D_L2CACTL),
  32         VC4_REG32(V3D_SLCACTL),
  33         VC4_REG32(V3D_INTCTL),
  34         VC4_REG32(V3D_INTENA),
  35         VC4_REG32(V3D_INTDIS),
  36         VC4_REG32(V3D_CT0CS),
  37         VC4_REG32(V3D_CT1CS),
  38         VC4_REG32(V3D_CT0EA),
  39         VC4_REG32(V3D_CT1EA),
  40         VC4_REG32(V3D_CT0CA),
  41         VC4_REG32(V3D_CT1CA),
  42         VC4_REG32(V3D_CT00RA0),
  43         VC4_REG32(V3D_CT01RA0),
  44         VC4_REG32(V3D_CT0LC),
  45         VC4_REG32(V3D_CT1LC),
  46         VC4_REG32(V3D_CT0PC),
  47         VC4_REG32(V3D_CT1PC),
  48         VC4_REG32(V3D_PCS),
  49         VC4_REG32(V3D_BFC),
  50         VC4_REG32(V3D_RFC),
  51         VC4_REG32(V3D_BPCA),
  52         VC4_REG32(V3D_BPCS),
  53         VC4_REG32(V3D_BPOA),
  54         VC4_REG32(V3D_BPOS),
  55         VC4_REG32(V3D_BXCF),
  56         VC4_REG32(V3D_SQRSV0),
  57         VC4_REG32(V3D_SQRSV1),
  58         VC4_REG32(V3D_SQCNTL),
  59         VC4_REG32(V3D_SRQPC),
  60         VC4_REG32(V3D_SRQUA),
  61         VC4_REG32(V3D_SRQUL),
  62         VC4_REG32(V3D_SRQCS),
  63         VC4_REG32(V3D_VPACNTL),
  64         VC4_REG32(V3D_VPMBASE),
  65         VC4_REG32(V3D_PCTRC),
  66         VC4_REG32(V3D_PCTRE),
  67         VC4_REG32(V3D_PCTR(0)),
  68         VC4_REG32(V3D_PCTRS(0)),
  69         VC4_REG32(V3D_PCTR(1)),
  70         VC4_REG32(V3D_PCTRS(1)),
  71         VC4_REG32(V3D_PCTR(2)),
  72         VC4_REG32(V3D_PCTRS(2)),
  73         VC4_REG32(V3D_PCTR(3)),
  74         VC4_REG32(V3D_PCTRS(3)),
  75         VC4_REG32(V3D_PCTR(4)),
  76         VC4_REG32(V3D_PCTRS(4)),
  77         VC4_REG32(V3D_PCTR(5)),
  78         VC4_REG32(V3D_PCTRS(5)),
  79         VC4_REG32(V3D_PCTR(6)),
  80         VC4_REG32(V3D_PCTRS(6)),
  81         VC4_REG32(V3D_PCTR(7)),
  82         VC4_REG32(V3D_PCTRS(7)),
  83         VC4_REG32(V3D_PCTR(8)),
  84         VC4_REG32(V3D_PCTRS(8)),
  85         VC4_REG32(V3D_PCTR(9)),
  86         VC4_REG32(V3D_PCTRS(9)),
  87         VC4_REG32(V3D_PCTR(10)),
  88         VC4_REG32(V3D_PCTRS(10)),
  89         VC4_REG32(V3D_PCTR(11)),
  90         VC4_REG32(V3D_PCTRS(11)),
  91         VC4_REG32(V3D_PCTR(12)),
  92         VC4_REG32(V3D_PCTRS(12)),
  93         VC4_REG32(V3D_PCTR(13)),
  94         VC4_REG32(V3D_PCTRS(13)),
  95         VC4_REG32(V3D_PCTR(14)),
  96         VC4_REG32(V3D_PCTRS(14)),
  97         VC4_REG32(V3D_PCTR(15)),
  98         VC4_REG32(V3D_PCTRS(15)),
  99         VC4_REG32(V3D_DBGE),
 100         VC4_REG32(V3D_FDBGO),
 101         VC4_REG32(V3D_FDBGB),
 102         VC4_REG32(V3D_FDBGR),
 103         VC4_REG32(V3D_FDBGS),
 104         VC4_REG32(V3D_ERRSTAT),
 105 };
 106
 107 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
 108 {
 109         struct drm_info_node *node = (struct drm_info_node *)m->private;
 110         struct drm_device *dev = node->minor->dev;
 111         struct vc4_dev *vc4 = to_vc4_dev(dev);
 112         struct drm_printer p = drm_seq_file_printer(m);
 113
 114         drm_print_regset32(&p, &vc4->v3d->regset);
 115
 116         return 0;
 117 }
 118
 119 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused)
 120 {
 121         struct drm_info_node *node = (struct drm_info_node *)m->private;
 122         struct drm_device *dev = node->minor->dev;
 123         struct vc4_dev *vc4 = to_vc4_dev(dev);
 124         int ret = vc4_v3d_pm_get(vc4);
 125
 126         if (ret == 0) {
 127                 uint32_t ident1 = V3D_READ(V3D_IDENT1);
 128                 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC);
 129                 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS);
 130                 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS);
 131
 132                 seq_printf(m, "Revision:   %d\n",
 133                            VC4_GET_FIELD(ident1, V3D_IDENT1_REV));
 134                 seq_printf(m, "Slices:     %d\n", nslc);
 135                 seq_printf(m, "TMUs:       %d\n", nslc * tups);
 136                 seq_printf(m, "QPUs:       %d\n", nslc * qups);
 137                 seq_printf(m, "Semaphores: %d\n",
 138                            VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM));
 139                 vc4_v3d_pm_put(vc4);
 140         }
 141
 142         return 0;
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 /**
 147  * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably
 148  * get the pm_runtime refcount to 0 in vc4_reset().
 149  */
 150 int
 151 vc4_v3d_pm_get(struct vc4_dev *vc4)
 152 {
 153         mutex_lock(&vc4->power_lock);
 154         if (vc4->power_refcount++ == 0) {
 155                 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
 156
 157                 if (ret < 0) {
 158                         vc4->power_refcount--;
 159                         mutex_unlock(&vc4->power_lock);
 160                         return ret;
 161                 }
 162         }
 163         mutex_unlock(&vc4->power_lock);
 164
 165         return 0;
 166 }
 167
 168 void
 169 vc4_v3d_pm_put(struct vc4_dev *vc4)
 170 {
 171         mutex_lock(&vc4->power_lock);
 172         if (--vc4->power_refcount == 0) {
 173                 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
 174                 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev);
 175         }
 176         mutex_unlock(&vc4->power_lock);
 177 }
 178
 179 static void vc4_v3d_init_hw(struct drm_device *dev)
 180 {
 181         struct vc4_dev *vc4 = to_vc4_dev(dev);
 182
 183         /* Take all the memory that would have been reserved for user
 184          * QPU programs, since we don't have an interface for running
 185          * them, anyway.
 186          */
 187         V3D_WRITE(V3D_VPMBASE, 0);
 188 }
 189
 190 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4)
 191 {
 192         struct drm_device *dev = vc4->dev;
 193         unsigned long irqflags;
 194         int slot;
 195         uint64_t seqno = 0;
 196         struct vc4_exec_info *exec;
 197
 198 try_again:
 199         spin_lock_irqsave(&vc4->job_lock, irqflags);
 200         slot = ffs(~vc4->bin_alloc_used);
 201         if (slot != 0) {
 202                 /* Switch from ffs() bit index to a 0-based index. */
 203                 slot--;
 204                 vc4->bin_alloc_used |= BIT(slot);
 205                 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 206                 return slot;
 207         }
 208
 209         /* Couldn't find an open slot.  Wait for render to complete
 210          * and try again.
 211          */
 212         exec = vc4_last_render_job(vc4);
 213         if (exec)
 214                 seqno = exec->seqno;
 215         spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 216
 217         if (seqno) {
 218                 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true);
 219
 220                 if (ret == 0)
 221                         goto try_again;
 222
 223                 return ret;
 224         }
 225
 226         return -ENOMEM;
 227 }
 228
 229 /**
 230  * vc4_allocate_bin_bo() - allocates the memory that will be used for
 231  * tile binning.
 232  *
 233  * The binner has a limitation that the addresses in the tile state
 234  * buffer that point into the tile alloc buffer or binner overflow
 235  * memory only have 28 bits (256MB), and the top 4 on the bus for
 236  * tile alloc references end up coming from the tile state buffer's
 237  * address.
 238  *
 239  * To work around this, we allocate a single large buffer while V3D is
 240  * in use, make sure that it has the top 4 bits constant across its
 241  * entire extent, and then put the tile state, tile alloc, and binner
 242  * overflow memory inside that buffer.
 243  *
 244  * This creates a limitation where we may not be able to execute a job
 245  * if it doesn't fit within the buffer that we allocated up front.
 246  * However, it turns out that 16MB is "enough for anybody", and
 247  * real-world applications run into allocation failures from the
 248  * overall CMA pool before they make scenes complicated enough to run
 249  * out of bin space.
 250  */
 251 static int vc4_allocate_bin_bo(struct drm_device *drm)
 252 {
 253         struct vc4_dev *vc4 = to_vc4_dev(drm);
 254         struct vc4_v3d *v3d = vc4->v3d;
 255         uint32_t size = 16 * 1024 * 1024;
 256         int ret = 0;
 257         struct list_head list;
 258
 259         /* We may need to try allocating more than once to get a BO
 260          * that doesn't cross 256MB.  Track the ones we've allocated
 261          * that failed so far, so that we can free them when we've got
 262          * one that succeeded (if we freed them right away, our next
 263          * allocation would probably be the same chunk of memory).
 264          */
 265         INIT_LIST_HEAD(&list);
 266
 267         while (true) {
 268                 struct vc4_bo *bo = vc4_bo_create(drm, size, true,
 269                                                   VC4_BO_TYPE_BIN);
 270
 271                 if (IS_ERR(bo)) {
 272                         ret = PTR_ERR(bo);
 273
 274                         dev_err(&v3d->pdev->dev,
 275                                 "Failed to allocate memory for tile binning: "
 276                                 "%d. You may need to enable CMA or give it "
 277                                 "more memory.",
 278                                 ret);
 279                         break;
 280                 }
 281
 282                 /* Check if this BO won't trigger the addressing bug. */
 283                 if ((bo->base.paddr & 0xf0000000) ==
 284                     ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) {
 285                         vc4->bin_bo = bo;
 286
 287                         /* Set up for allocating 512KB chunks of
 288                          * binner memory.  The biggest allocation we
 289                          * need to do is for the initial tile alloc +
 290                          * tile state buffer.  We can render to a
 291                          * maximum of ((2048*2048) / (32*32) = 4096
 292                          * tiles in a frame (until we do floating
 293                          * point rendering, at which point it would be
 294                          * 8192).  Tile state is 48b/tile (rounded to
 295                          * a page), and tile alloc is 32b/tile
 296                          * (rounded to a page), plus a page of extra,
 297                          * for a total of 320kb for our worst-case.
 298                          * We choose 512kb so that it divides evenly
 299                          * into our 16MB, and the rest of the 512kb
 300                          * will be used as storage for the overflow
 301                          * from the initial 32b CL per bin.
 302                          */
 303                         vc4->bin_alloc_size = 512 * 1024;
 304                         vc4->bin_alloc_used = 0;
 305                         vc4->bin_alloc_overflow = 0;
 306                         WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 !=
 307                                      bo->base.base.size / vc4->bin_alloc_size);
 308
 309                         break;
 310                 }
 311
 312                 /* Put it on the list to free later, and try again. */
 313                 list_add(&bo->unref_head, &list);
 314         }
 315
 316         /* Free all the BOs we allocated but didn't choose. */
 317         while (!list_empty(&list)) {
 318                 struct vc4_bo *bo = list_last_entry(&list,
 319                                                     struct vc4_bo, unref_head);
 320
 321                 list_del(&bo->unref_head);
 322                 drm_gem_object_put_unlocked(&bo->base.base);
 323         }
 324
 325         return ret;
 326 }
 327
 328 #ifdef CONFIG_PM
 329 static int vc4_v3d_runtime_suspend(struct device *dev)
 330 {
 331         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 332         struct vc4_dev *vc4 = v3d->vc4;
 333
 334         vc4_irq_uninstall(vc4->dev);
 335
 336         drm_gem_object_put_unlocked(&vc4->bin_bo->base.base);
 337         vc4->bin_bo = NULL;
 338
 339         clk_disable_unprepare(v3d->clk);
 340
 341         return 0;
 342 }
 343
 344 static int vc4_v3d_runtime_resume(struct device *dev)
 345 {
 346         struct vc4_v3d *v3d = dev_get_drvdata(dev);
 347         struct vc4_dev *vc4 = v3d->vc4;
 348         int ret;
 349
 350         ret = vc4_allocate_bin_bo(vc4->dev);
 351         if (ret)
 352                 return ret;
 353
 354         ret = clk_prepare_enable(v3d->clk);
 355         if (ret != 0)
 356                 return ret;
 357
 358         vc4_v3d_init_hw(vc4->dev);
 359
 360         /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */
 361         enable_irq(vc4->dev->irq);
 362         vc4_irq_postinstall(vc4->dev);
 363
 364         return 0;
 365 }
 366 #endif
 367
 368 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data)
 369 {
 370         struct platform_device *pdev = to_platform_device(dev);
 371         struct drm_device *drm = dev_get_drvdata(master);
 372         struct vc4_dev *vc4 = to_vc4_dev(drm);
 373         struct vc4_v3d *v3d = NULL;
 374         int ret;
 375
 376         v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL);
 377         if (!v3d)
 378                 return -ENOMEM;
 379
 380         dev_set_drvdata(dev, v3d);
 381
 382         v3d->pdev = pdev;
 383
 384         v3d->regs = vc4_ioremap_regs(pdev, 0);
 385         if (IS_ERR(v3d->regs))
 386                 return PTR_ERR(v3d->regs);
 387         v3d->regset.base = v3d->regs;
 388         v3d->regset.regs = v3d_regs;
 389         v3d->regset.nregs = ARRAY_SIZE(v3d_regs);
 390
 391         vc4->v3d = v3d;
 392         v3d->vc4 = vc4;
 393
 394         v3d->clk = devm_clk_get(dev, NULL);
 395         if (IS_ERR(v3d->clk)) {
 396                 int ret = PTR_ERR(v3d->clk);
 397
 398                 if (ret == -ENOENT) {
 399                         /* bcm2835 didn't have a clock reference in the DT. */
 400                         ret = 0;
 401                         v3d->clk = NULL;
 402                 } else {
 403                         if (ret != -EPROBE_DEFER)
 404                                 dev_err(dev, "Failed to get V3D clock: %d\n",
 405                                         ret);
 406                         return ret;
 407                 }
 408         }
 409
 410         if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) {
 411                 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n",
 412                           V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0);
 413                 return -EINVAL;
 414         }
 415
 416         ret = clk_prepare_enable(v3d->clk);
 417         if (ret != 0)
 418                 return ret;
 419
 420         ret = vc4_allocate_bin_bo(drm);
 421         if (ret) {
 422                 clk_disable_unprepare(v3d->clk);
 423                 return ret;
 424         }
 425
 426         /* Reset the binner overflow address/size at setup, to be sure
 427          * we don't reuse an old one.
 428          */
 429         V3D_WRITE(V3D_BPOA, 0);
 430         V3D_WRITE(V3D_BPOS, 0);
 431
 432         vc4_v3d_init_hw(drm);
 433
 434         ret = drm_irq_install(drm, platform_get_irq(pdev, 0));
 435         if (ret) {
 436                 DRM_ERROR("Failed to install IRQ handler\n");
 437                 return ret;
 438         }
 439
 440         pm_runtime_set_active(dev);
 441         pm_runtime_use_autosuspend(dev);
 442         pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */
 443         pm_runtime_enable(dev);
 444
 445         return 0;
 446 }
 447
 448 static void vc4_v3d_unbind(struct device *dev, struct device *master,
 449                            void *data)
 450 {
 451         struct drm_device *drm = dev_get_drvdata(master);
 452         struct vc4_dev *vc4 = to_vc4_dev(drm);
 453
 454         pm_runtime_disable(dev);
 455
 456         drm_irq_uninstall(drm);
 457
 458         /* Disable the binner's overflow memory address, so the next
 459          * driver probe (if any) doesn't try to reuse our old
 460          * allocation.
 461          */
 462         V3D_WRITE(V3D_BPOA, 0);
 463         V3D_WRITE(V3D_BPOS, 0);
 464
 465         vc4->v3d = NULL;
 466 }
 467
 468 static const struct dev_pm_ops vc4_v3d_pm_ops = {
 469         SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL)
 470 };
 471
 472 static const struct component_ops vc4_v3d_ops = {
 473         .bind   = vc4_v3d_bind,
 474         .unbind = vc4_v3d_unbind,
 475 };
 476
 477 static int vc4_v3d_dev_probe(struct platform_device *pdev)
 478 {
 479         return component_add(&pdev->dev, &vc4_v3d_ops);
 480 }
 481
 482 static int vc4_v3d_dev_remove(struct platform_device *pdev)
 483 {
 484         component_del(&pdev->dev, &vc4_v3d_ops);
 485         return 0;
 486 }
 487
 488 static const struct of_device_id vc4_v3d_dt_match[] = {
 489         { .compatible = "brcm,bcm2835-v3d" },
 490         { .compatible = "brcm,cygnus-v3d" },
 491         { .compatible = "brcm,vc4-v3d" },
 492         {}
 493 };
 494
 495 struct platform_driver vc4_v3d_driver = {
 496         .probe = vc4_v3d_dev_probe,
 497         .remove = vc4_v3d_dev_remove,
 498         .driver = {
 499                 .name = "vc4_v3d",
 500                 .of_match_table = vc4_v3d_dt_match,
 501                 .pm = &vc4_v3d_pm_ops,
 502         },
 503 };