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1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3  *
4  * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 #include <linux/module.h>
28 #include <linux/console.h>
29
30 #include <drm/drmP.h>
31 #include "vmwgfx_drv.h"
32 #include "vmwgfx_binding.h"
33 #include "ttm_object.h"
34 #include <drm/ttm/ttm_placement.h>
35 #include <drm/ttm/ttm_bo_driver.h>
36 #include <drm/ttm/ttm_module.h>
37 #include <linux/intel-iommu.h>
38
39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
40 #define VMWGFX_CHIP_SVGAII 0
41 #define VMW_FB_RESERVATION 0
42
43 #define VMW_MIN_INITIAL_WIDTH 800
44 #define VMW_MIN_INITIAL_HEIGHT 600
45
46 #ifndef VMWGFX_GIT_VERSION
47 #define VMWGFX_GIT_VERSION "Unknown"
48 #endif
49
50 #define VMWGFX_REPO "In Tree"
51
52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
53
54
55 /**
56  * Fully encoded drm commands. Might move to vmw_drm.h
57  */
58
59 #define DRM_IOCTL_VMW_GET_PARAM                                 \
60         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
61                  struct drm_vmw_getparam_arg)
62 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
63         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
64                 union drm_vmw_alloc_dmabuf_arg)
65 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
66         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
67                 struct drm_vmw_unref_dmabuf_arg)
68 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
69         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
70                  struct drm_vmw_cursor_bypass_arg)
71
72 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
73         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
74                  struct drm_vmw_control_stream_arg)
75 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
76         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
77                  struct drm_vmw_stream_arg)
78 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
79         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
80                  struct drm_vmw_stream_arg)
81
82 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
83         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
84                 struct drm_vmw_context_arg)
85 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
86         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
87                 struct drm_vmw_context_arg)
88 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
89         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
90                  union drm_vmw_surface_create_arg)
91 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
93                  struct drm_vmw_surface_arg)
94 #define DRM_IOCTL_VMW_REF_SURFACE                               \
95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
96                  union drm_vmw_surface_reference_arg)
97 #define DRM_IOCTL_VMW_EXECBUF                                   \
98         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
99                 struct drm_vmw_execbuf_arg)
100 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
102                  struct drm_vmw_get_3d_cap_arg)
103 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
104         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
105                  struct drm_vmw_fence_wait_arg)
106 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
107         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
108                  struct drm_vmw_fence_signaled_arg)
109 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
111                  struct drm_vmw_fence_arg)
112 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
114                  struct drm_vmw_fence_event_arg)
115 #define DRM_IOCTL_VMW_PRESENT                                   \
116         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
117                  struct drm_vmw_present_arg)
118 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
120                  struct drm_vmw_present_readback_arg)
121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
122         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
123                  struct drm_vmw_update_layout_arg)
124 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
126                  struct drm_vmw_shader_create_arg)
127 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
129                  struct drm_vmw_shader_arg)
130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
131         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
132                  union drm_vmw_gb_surface_create_arg)
133 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
134         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
135                  union drm_vmw_gb_surface_reference_arg)
136 #define DRM_IOCTL_VMW_SYNCCPU                                   \
137         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
138                  struct drm_vmw_synccpu_arg)
139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT                   \
140         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,    \
141                 struct drm_vmw_context_arg)
142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT                             \
143         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT,      \
144                 union drm_vmw_gb_surface_create_ext_arg)
145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT                                \
146         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT,         \
147                 union drm_vmw_gb_surface_reference_ext_arg)
148
149 /**
150  * The core DRM version of this macro doesn't account for
151  * DRM_COMMAND_BASE.
152  */
153
154 #define VMW_IOCTL_DEF(ioctl, func, flags) \
155   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
156
157 /**
158  * Ioctl definitions.
159  */
160
161 static const struct drm_ioctl_desc vmw_ioctls[] = {
162         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
163                       DRM_AUTH | DRM_RENDER_ALLOW),
164         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
165                       DRM_AUTH | DRM_RENDER_ALLOW),
166         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
167                       DRM_RENDER_ALLOW),
168         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
169                       vmw_kms_cursor_bypass_ioctl,
170                       DRM_MASTER),
171
172         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
173                       DRM_MASTER),
174         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
175                       DRM_MASTER),
176         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
177                       DRM_MASTER),
178
179         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
180                       DRM_AUTH | DRM_RENDER_ALLOW),
181         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
182                       DRM_RENDER_ALLOW),
183         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
184                       DRM_AUTH | DRM_RENDER_ALLOW),
185         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
186                       DRM_RENDER_ALLOW),
187         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
188                       DRM_AUTH | DRM_RENDER_ALLOW),
189         VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH |
190                       DRM_RENDER_ALLOW),
191         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
192                       DRM_RENDER_ALLOW),
193         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
194                       vmw_fence_obj_signaled_ioctl,
195                       DRM_RENDER_ALLOW),
196         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
197                       DRM_RENDER_ALLOW),
198         VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
199                       DRM_AUTH | DRM_RENDER_ALLOW),
200         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
201                       DRM_AUTH | DRM_RENDER_ALLOW),
202
203         /* these allow direct access to the framebuffers mark as master only */
204         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
205                       DRM_MASTER | DRM_AUTH),
206         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
207                       vmw_present_readback_ioctl,
208                       DRM_MASTER | DRM_AUTH),
209         /*
210          * The permissions of the below ioctl are overridden in
211          * vmw_generic_ioctl(). We require either
212          * DRM_MASTER or capable(CAP_SYS_ADMIN).
213          */
214         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
215                       vmw_kms_update_layout_ioctl,
216                       DRM_RENDER_ALLOW),
217         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
218                       vmw_shader_define_ioctl,
219                       DRM_AUTH | DRM_RENDER_ALLOW),
220         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
221                       vmw_shader_destroy_ioctl,
222                       DRM_RENDER_ALLOW),
223         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
224                       vmw_gb_surface_define_ioctl,
225                       DRM_AUTH | DRM_RENDER_ALLOW),
226         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
227                       vmw_gb_surface_reference_ioctl,
228                       DRM_AUTH | DRM_RENDER_ALLOW),
229         VMW_IOCTL_DEF(VMW_SYNCCPU,
230                       vmw_user_bo_synccpu_ioctl,
231                       DRM_RENDER_ALLOW),
232         VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
233                       vmw_extended_context_define_ioctl,
234                       DRM_AUTH | DRM_RENDER_ALLOW),
235         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
236                       vmw_gb_surface_define_ext_ioctl,
237                       DRM_AUTH | DRM_RENDER_ALLOW),
238         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
239                       vmw_gb_surface_reference_ext_ioctl,
240                       DRM_AUTH | DRM_RENDER_ALLOW),
241 };
242
243 static const struct pci_device_id vmw_pci_id_list[] = {
244         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
245         {0, 0, 0}
246 };
247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
248
249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
250 static int vmw_force_iommu;
251 static int vmw_restrict_iommu;
252 static int vmw_force_coherent;
253 static int vmw_restrict_dma_mask;
254 static int vmw_assume_16bpp;
255
256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
257 static void vmw_master_init(struct vmw_master *);
258 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
259                               void *ptr);
260
261 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
262 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
263 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
264 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
265 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
266 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
267 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
268 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
269 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
270 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
271 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
272 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
273
274
275 static void vmw_print_capabilities2(uint32_t capabilities2)
276 {
277         DRM_INFO("Capabilities2:\n");
278         if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
279                 DRM_INFO("  Grow oTable.\n");
280         if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
281                 DRM_INFO("  IntraSurface copy.\n");
282 }
283
284 static void vmw_print_capabilities(uint32_t capabilities)
285 {
286         DRM_INFO("Capabilities:\n");
287         if (capabilities & SVGA_CAP_RECT_COPY)
288                 DRM_INFO("  Rect copy.\n");
289         if (capabilities & SVGA_CAP_CURSOR)
290                 DRM_INFO("  Cursor.\n");
291         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
292                 DRM_INFO("  Cursor bypass.\n");
293         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
294                 DRM_INFO("  Cursor bypass 2.\n");
295         if (capabilities & SVGA_CAP_8BIT_EMULATION)
296                 DRM_INFO("  8bit emulation.\n");
297         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
298                 DRM_INFO("  Alpha cursor.\n");
299         if (capabilities & SVGA_CAP_3D)
300                 DRM_INFO("  3D.\n");
301         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
302                 DRM_INFO("  Extended Fifo.\n");
303         if (capabilities & SVGA_CAP_MULTIMON)
304                 DRM_INFO("  Multimon.\n");
305         if (capabilities & SVGA_CAP_PITCHLOCK)
306                 DRM_INFO("  Pitchlock.\n");
307         if (capabilities & SVGA_CAP_IRQMASK)
308                 DRM_INFO("  Irq mask.\n");
309         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
310                 DRM_INFO("  Display Topology.\n");
311         if (capabilities & SVGA_CAP_GMR)
312                 DRM_INFO("  GMR.\n");
313         if (capabilities & SVGA_CAP_TRACES)
314                 DRM_INFO("  Traces.\n");
315         if (capabilities & SVGA_CAP_GMR2)
316                 DRM_INFO("  GMR2.\n");
317         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
318                 DRM_INFO("  Screen Object 2.\n");
319         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
320                 DRM_INFO("  Command Buffers.\n");
321         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
322                 DRM_INFO("  Command Buffers 2.\n");
323         if (capabilities & SVGA_CAP_GBOBJECTS)
324                 DRM_INFO("  Guest Backed Resources.\n");
325         if (capabilities & SVGA_CAP_DX)
326                 DRM_INFO("  DX Features.\n");
327         if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
328                 DRM_INFO("  HP Command Queue.\n");
329 }
330
331 /**
332  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
333  *
334  * @dev_priv: A device private structure.
335  *
336  * This function creates a small buffer object that holds the query
337  * result for dummy queries emitted as query barriers.
338  * The function will then map the first page and initialize a pending
339  * occlusion query result structure, Finally it will unmap the buffer.
340  * No interruptible waits are done within this function.
341  *
342  * Returns an error if bo creation or initialization fails.
343  */
344 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
345 {
346         int ret;
347         struct vmw_buffer_object *vbo;
348         struct ttm_bo_kmap_obj map;
349         volatile SVGA3dQueryResult *result;
350         bool dummy;
351
352         /*
353          * Create the vbo as pinned, so that a tryreserve will
354          * immediately succeed. This is because we're the only
355          * user of the bo currently.
356          */
357         vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
358         if (!vbo)
359                 return -ENOMEM;
360
361         ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
362                           &vmw_sys_ne_placement, false,
363                           &vmw_bo_bo_free);
364         if (unlikely(ret != 0))
365                 return ret;
366
367         ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
368         BUG_ON(ret != 0);
369         vmw_bo_pin_reserved(vbo, true);
370
371         ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
372         if (likely(ret == 0)) {
373                 result = ttm_kmap_obj_virtual(&map, &dummy);
374                 result->totalSize = sizeof(*result);
375                 result->state = SVGA3D_QUERYSTATE_PENDING;
376                 result->result32 = 0xff;
377                 ttm_bo_kunmap(&map);
378         }
379         vmw_bo_pin_reserved(vbo, false);
380         ttm_bo_unreserve(&vbo->base);
381
382         if (unlikely(ret != 0)) {
383                 DRM_ERROR("Dummy query buffer map failed.\n");
384                 vmw_bo_unreference(&vbo);
385         } else
386                 dev_priv->dummy_query_bo = vbo;
387
388         return ret;
389 }
390
391 /**
392  * vmw_request_device_late - Perform late device setup
393  *
394  * @dev_priv: Pointer to device private.
395  *
396  * This function performs setup of otables and enables large command
397  * buffer submission. These tasks are split out to a separate function
398  * because it reverts vmw_release_device_early and is intended to be used
399  * by an error path in the hibernation code.
400  */
401 static int vmw_request_device_late(struct vmw_private *dev_priv)
402 {
403         int ret;
404
405         if (dev_priv->has_mob) {
406                 ret = vmw_otables_setup(dev_priv);
407                 if (unlikely(ret != 0)) {
408                         DRM_ERROR("Unable to initialize "
409                                   "guest Memory OBjects.\n");
410                         return ret;
411                 }
412         }
413
414         if (dev_priv->cman) {
415                 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
416                                                256*4096, 2*4096);
417                 if (ret) {
418                         struct vmw_cmdbuf_man *man = dev_priv->cman;
419
420                         dev_priv->cman = NULL;
421                         vmw_cmdbuf_man_destroy(man);
422                 }
423         }
424
425         return 0;
426 }
427
428 static int vmw_request_device(struct vmw_private *dev_priv)
429 {
430         int ret;
431
432         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
433         if (unlikely(ret != 0)) {
434                 DRM_ERROR("Unable to initialize FIFO.\n");
435                 return ret;
436         }
437         vmw_fence_fifo_up(dev_priv->fman);
438         dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
439         if (IS_ERR(dev_priv->cman)) {
440                 dev_priv->cman = NULL;
441                 dev_priv->has_dx = false;
442         }
443
444         ret = vmw_request_device_late(dev_priv);
445         if (ret)
446                 goto out_no_mob;
447
448         ret = vmw_dummy_query_bo_create(dev_priv);
449         if (unlikely(ret != 0))
450                 goto out_no_query_bo;
451
452         return 0;
453
454 out_no_query_bo:
455         if (dev_priv->cman)
456                 vmw_cmdbuf_remove_pool(dev_priv->cman);
457         if (dev_priv->has_mob) {
458                 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
459                 vmw_otables_takedown(dev_priv);
460         }
461         if (dev_priv->cman)
462                 vmw_cmdbuf_man_destroy(dev_priv->cman);
463 out_no_mob:
464         vmw_fence_fifo_down(dev_priv->fman);
465         vmw_fifo_release(dev_priv, &dev_priv->fifo);
466         return ret;
467 }
468
469 /**
470  * vmw_release_device_early - Early part of fifo takedown.
471  *
472  * @dev_priv: Pointer to device private struct.
473  *
474  * This is the first part of command submission takedown, to be called before
475  * buffer management is taken down.
476  */
477 static void vmw_release_device_early(struct vmw_private *dev_priv)
478 {
479         /*
480          * Previous destructions should've released
481          * the pinned bo.
482          */
483
484         BUG_ON(dev_priv->pinned_bo != NULL);
485
486         vmw_bo_unreference(&dev_priv->dummy_query_bo);
487         if (dev_priv->cman)
488                 vmw_cmdbuf_remove_pool(dev_priv->cman);
489
490         if (dev_priv->has_mob) {
491                 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
492                 vmw_otables_takedown(dev_priv);
493         }
494 }
495
496 /**
497  * vmw_release_device_late - Late part of fifo takedown.
498  *
499  * @dev_priv: Pointer to device private struct.
500  *
501  * This is the last part of the command submission takedown, to be called when
502  * command submission is no longer needed. It may wait on pending fences.
503  */
504 static void vmw_release_device_late(struct vmw_private *dev_priv)
505 {
506         vmw_fence_fifo_down(dev_priv->fman);
507         if (dev_priv->cman)
508                 vmw_cmdbuf_man_destroy(dev_priv->cman);
509
510         vmw_fifo_release(dev_priv, &dev_priv->fifo);
511 }
512
513 /**
514  * Sets the initial_[width|height] fields on the given vmw_private.
515  *
516  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
517  * clamping the value to fb_max_[width|height] fields and the
518  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
519  * If the values appear to be invalid, set them to
520  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
521  */
522 static void vmw_get_initial_size(struct vmw_private *dev_priv)
523 {
524         uint32_t width;
525         uint32_t height;
526
527         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
528         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
529
530         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
531         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
532
533         if (width > dev_priv->fb_max_width ||
534             height > dev_priv->fb_max_height) {
535
536                 /*
537                  * This is a host error and shouldn't occur.
538                  */
539
540                 width = VMW_MIN_INITIAL_WIDTH;
541                 height = VMW_MIN_INITIAL_HEIGHT;
542         }
543
544         dev_priv->initial_width = width;
545         dev_priv->initial_height = height;
546 }
547
548 /**
549  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
550  * system.
551  *
552  * @dev_priv: Pointer to a struct vmw_private
553  *
554  * This functions tries to determine the IOMMU setup and what actions
555  * need to be taken by the driver to make system pages visible to the
556  * device.
557  * If this function decides that DMA is not possible, it returns -EINVAL.
558  * The driver may then try to disable features of the device that require
559  * DMA.
560  */
561 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
562 {
563         static const char *names[vmw_dma_map_max] = {
564                 [vmw_dma_phys] = "Using physical TTM page addresses.",
565                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
566                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
567                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
568
569         if (vmw_force_coherent)
570                 dev_priv->map_mode = vmw_dma_alloc_coherent;
571         else if (intel_iommu_enabled)
572                 dev_priv->map_mode = vmw_dma_map_populate;
573         else if (!vmw_force_iommu)
574                 dev_priv->map_mode = vmw_dma_phys;
575         else if (IS_ENABLED(CONFIG_SWIOTLB) && swiotlb_nr_tbl())
576                 dev_priv->map_mode = vmw_dma_alloc_coherent;
577         else
578                 dev_priv->map_mode = vmw_dma_map_populate;
579
580         if (dev_priv->map_mode == vmw_dma_map_populate && vmw_restrict_iommu)
581                 dev_priv->map_mode = vmw_dma_map_bind;
582
583         /* No TTM coherent page pool? FIXME: Ask TTM instead! */
584         if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) &&
585             (dev_priv->map_mode == vmw_dma_alloc_coherent))
586                 return -EINVAL;
587
588         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
589         return 0;
590 }
591
592 /**
593  * vmw_dma_masks - set required page- and dma masks
594  *
595  * @dev: Pointer to struct drm-device
596  *
597  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
598  * restriction also for 64-bit systems.
599  */
600 static int vmw_dma_masks(struct vmw_private *dev_priv)
601 {
602         struct drm_device *dev = dev_priv->dev;
603         int ret = 0;
604
605         ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
606         if (dev_priv->map_mode != vmw_dma_phys &&
607             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
608                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
609                 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
610         }
611
612         return ret;
613 }
614
615 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
616 {
617         struct vmw_private *dev_priv;
618         int ret;
619         uint32_t svga_id;
620         enum vmw_res_type i;
621         bool refuse_dma = false;
622         char host_log[100] = {0};
623
624         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
625         if (unlikely(!dev_priv)) {
626                 DRM_ERROR("Failed allocating a device private struct.\n");
627                 return -ENOMEM;
628         }
629
630         pci_set_master(dev->pdev);
631
632         dev_priv->dev = dev;
633         dev_priv->vmw_chipset = chipset;
634         dev_priv->last_read_seqno = (uint32_t) -100;
635         mutex_init(&dev_priv->cmdbuf_mutex);
636         mutex_init(&dev_priv->release_mutex);
637         mutex_init(&dev_priv->binding_mutex);
638         mutex_init(&dev_priv->global_kms_state_mutex);
639         ttm_lock_init(&dev_priv->reservation_sem);
640         spin_lock_init(&dev_priv->resource_lock);
641         spin_lock_init(&dev_priv->hw_lock);
642         spin_lock_init(&dev_priv->waiter_lock);
643         spin_lock_init(&dev_priv->cap_lock);
644         spin_lock_init(&dev_priv->svga_lock);
645         spin_lock_init(&dev_priv->cursor_lock);
646
647         for (i = vmw_res_context; i < vmw_res_max; ++i) {
648                 idr_init(&dev_priv->res_idr[i]);
649                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
650         }
651
652         mutex_init(&dev_priv->init_mutex);
653         init_waitqueue_head(&dev_priv->fence_queue);
654         init_waitqueue_head(&dev_priv->fifo_queue);
655         dev_priv->fence_queue_waiters = 0;
656         dev_priv->fifo_queue_waiters = 0;
657
658         dev_priv->used_memory_size = 0;
659
660         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
661         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
662         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
663
664         dev_priv->assume_16bpp = !!vmw_assume_16bpp;
665
666         dev_priv->enable_fb = enable_fbdev;
667
668         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
669         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
670         if (svga_id != SVGA_ID_2) {
671                 ret = -ENOSYS;
672                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
673                 goto out_err0;
674         }
675
676         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
677
678         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
679                 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
680         }
681
682
683         ret = vmw_dma_select_mode(dev_priv);
684         if (unlikely(ret != 0)) {
685                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
686                 refuse_dma = true;
687         }
688
689         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
690         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
691         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
692         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
693
694         vmw_get_initial_size(dev_priv);
695
696         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
697                 dev_priv->max_gmr_ids =
698                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
699                 dev_priv->max_gmr_pages =
700                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
701                 dev_priv->memory_size =
702                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
703                 dev_priv->memory_size -= dev_priv->vram_size;
704         } else {
705                 /*
706                  * An arbitrary limit of 512MiB on surface
707                  * memory. But all HWV8 hardware supports GMR2.
708                  */
709                 dev_priv->memory_size = 512*1024*1024;
710         }
711         dev_priv->max_mob_pages = 0;
712         dev_priv->max_mob_size = 0;
713         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
714                 uint64_t mem_size =
715                         vmw_read(dev_priv,
716                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
717
718                 /*
719                  * Workaround for low memory 2D VMs to compensate for the
720                  * allocation taken by fbdev
721                  */
722                 if (!(dev_priv->capabilities & SVGA_CAP_3D))
723                         mem_size *= 3;
724
725                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
726                 dev_priv->prim_bb_mem =
727                         vmw_read(dev_priv,
728                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
729                 dev_priv->max_mob_size =
730                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
731                 dev_priv->stdu_max_width =
732                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
733                 dev_priv->stdu_max_height =
734                         vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
735
736                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
737                           SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
738                 dev_priv->texture_max_width = vmw_read(dev_priv,
739                                                        SVGA_REG_DEV_CAP);
740                 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
741                           SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
742                 dev_priv->texture_max_height = vmw_read(dev_priv,
743                                                         SVGA_REG_DEV_CAP);
744         } else {
745                 dev_priv->texture_max_width = 8192;
746                 dev_priv->texture_max_height = 8192;
747                 dev_priv->prim_bb_mem = dev_priv->vram_size;
748         }
749
750         vmw_print_capabilities(dev_priv->capabilities);
751         if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
752                 vmw_print_capabilities2(dev_priv->capabilities2);
753
754         ret = vmw_dma_masks(dev_priv);
755         if (unlikely(ret != 0))
756                 goto out_err0;
757
758         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
759                 DRM_INFO("Max GMR ids is %u\n",
760                          (unsigned)dev_priv->max_gmr_ids);
761                 DRM_INFO("Max number of GMR pages is %u\n",
762                          (unsigned)dev_priv->max_gmr_pages);
763                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
764                          (unsigned)dev_priv->memory_size / 1024);
765         }
766         DRM_INFO("Maximum display memory size is %u kiB\n",
767                  dev_priv->prim_bb_mem / 1024);
768         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
769                  dev_priv->vram_start, dev_priv->vram_size / 1024);
770         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
771                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
772
773         vmw_master_init(&dev_priv->fbdev_master);
774         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
775         dev_priv->active_master = &dev_priv->fbdev_master;
776
777         dev_priv->mmio_virt = memremap(dev_priv->mmio_start,
778                                        dev_priv->mmio_size, MEMREMAP_WB);
779
780         if (unlikely(dev_priv->mmio_virt == NULL)) {
781                 ret = -ENOMEM;
782                 DRM_ERROR("Failed mapping MMIO.\n");
783                 goto out_err0;
784         }
785
786         /* Need mmio memory to check for fifo pitchlock cap. */
787         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
788             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
789             !vmw_fifo_have_pitchlock(dev_priv)) {
790                 ret = -ENOSYS;
791                 DRM_ERROR("Hardware has no pitchlock\n");
792                 goto out_err4;
793         }
794
795         dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
796                                                 &vmw_prime_dmabuf_ops);
797
798         if (unlikely(dev_priv->tdev == NULL)) {
799                 DRM_ERROR("Unable to initialize TTM object management.\n");
800                 ret = -ENOMEM;
801                 goto out_err4;
802         }
803
804         dev->dev_private = dev_priv;
805
806         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
807         dev_priv->stealth = (ret != 0);
808         if (dev_priv->stealth) {
809                 /**
810                  * Request at least the mmio PCI resource.
811                  */
812
813                 DRM_INFO("It appears like vesafb is loaded. "
814                          "Ignore above error if any.\n");
815                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
816                 if (unlikely(ret != 0)) {
817                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
818                         goto out_no_device;
819                 }
820         }
821
822         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
823                 ret = vmw_irq_install(dev, dev->pdev->irq);
824                 if (ret != 0) {
825                         DRM_ERROR("Failed installing irq: %d\n", ret);
826                         goto out_no_irq;
827                 }
828         }
829
830         dev_priv->fman = vmw_fence_manager_init(dev_priv);
831         if (unlikely(dev_priv->fman == NULL)) {
832                 ret = -ENOMEM;
833                 goto out_no_fman;
834         }
835
836         ret = ttm_bo_device_init(&dev_priv->bdev,
837                                  &vmw_bo_driver,
838                                  dev->anon_inode->i_mapping,
839                                  VMWGFX_FILE_PAGE_OFFSET,
840                                  false);
841         if (unlikely(ret != 0)) {
842                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
843                 goto out_no_bdev;
844         }
845
846         /*
847          * Enable VRAM, but initially don't use it until SVGA is enabled and
848          * unhidden.
849          */
850         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
851                              (dev_priv->vram_size >> PAGE_SHIFT));
852         if (unlikely(ret != 0)) {
853                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
854                 goto out_no_vram;
855         }
856         dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
857
858         dev_priv->has_gmr = true;
859         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
860             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
861                                          VMW_PL_GMR) != 0) {
862                 DRM_INFO("No GMR memory available. "
863                          "Graphics memory resources are very limited.\n");
864                 dev_priv->has_gmr = false;
865         }
866
867         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
868                 dev_priv->has_mob = true;
869                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
870                                    VMW_PL_MOB) != 0) {
871                         DRM_INFO("No MOB memory available. "
872                                  "3D will be disabled.\n");
873                         dev_priv->has_mob = false;
874                 }
875         }
876
877         if (dev_priv->has_mob) {
878                 spin_lock(&dev_priv->cap_lock);
879                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
880                 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
881                 spin_unlock(&dev_priv->cap_lock);
882         }
883
884         vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
885         ret = vmw_kms_init(dev_priv);
886         if (unlikely(ret != 0))
887                 goto out_no_kms;
888         vmw_overlay_init(dev_priv);
889
890         ret = vmw_request_device(dev_priv);
891         if (ret)
892                 goto out_no_fifo;
893
894         if (dev_priv->has_dx) {
895                 /*
896                  * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1
897                  * support
898                  */
899                 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) {
900                         vmw_write(dev_priv, SVGA_REG_DEV_CAP,
901                                         SVGA3D_DEVCAP_SM41);
902                         dev_priv->has_sm4_1 = vmw_read(dev_priv,
903                                                         SVGA_REG_DEV_CAP);
904                 }
905         }
906
907         DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
908         DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC)
909                  ? "yes." : "no.");
910         DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no.");
911
912         snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s",
913                 VMWGFX_REPO, VMWGFX_GIT_VERSION);
914         vmw_host_log(host_log);
915
916         memset(host_log, 0, sizeof(host_log));
917         snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
918                 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
919                 VMWGFX_DRIVER_PATCHLEVEL);
920         vmw_host_log(host_log);
921
922         if (dev_priv->enable_fb) {
923                 vmw_fifo_resource_inc(dev_priv);
924                 vmw_svga_enable(dev_priv);
925                 vmw_fb_init(dev_priv);
926         }
927
928         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
929         register_pm_notifier(&dev_priv->pm_nb);
930
931         return 0;
932
933 out_no_fifo:
934         vmw_overlay_close(dev_priv);
935         vmw_kms_close(dev_priv);
936 out_no_kms:
937         if (dev_priv->has_mob)
938                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
939         if (dev_priv->has_gmr)
940                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
941         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
942 out_no_vram:
943         (void)ttm_bo_device_release(&dev_priv->bdev);
944 out_no_bdev:
945         vmw_fence_manager_takedown(dev_priv->fman);
946 out_no_fman:
947         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
948                 vmw_irq_uninstall(dev_priv->dev);
949 out_no_irq:
950         if (dev_priv->stealth)
951                 pci_release_region(dev->pdev, 2);
952         else
953                 pci_release_regions(dev->pdev);
954 out_no_device:
955         ttm_object_device_release(&dev_priv->tdev);
956 out_err4:
957         memunmap(dev_priv->mmio_virt);
958 out_err0:
959         for (i = vmw_res_context; i < vmw_res_max; ++i)
960                 idr_destroy(&dev_priv->res_idr[i]);
961
962         if (dev_priv->ctx.staged_bindings)
963                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
964         kfree(dev_priv);
965         return ret;
966 }
967
968 static void vmw_driver_unload(struct drm_device *dev)
969 {
970         struct vmw_private *dev_priv = vmw_priv(dev);
971         enum vmw_res_type i;
972
973         unregister_pm_notifier(&dev_priv->pm_nb);
974
975         if (dev_priv->ctx.res_ht_initialized)
976                 drm_ht_remove(&dev_priv->ctx.res_ht);
977         vfree(dev_priv->ctx.cmd_bounce);
978         if (dev_priv->enable_fb) {
979                 vmw_fb_off(dev_priv);
980                 vmw_fb_close(dev_priv);
981                 vmw_fifo_resource_dec(dev_priv);
982                 vmw_svga_disable(dev_priv);
983         }
984
985         vmw_kms_close(dev_priv);
986         vmw_overlay_close(dev_priv);
987
988         if (dev_priv->has_gmr)
989                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
990         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
991
992         vmw_release_device_early(dev_priv);
993         if (dev_priv->has_mob)
994                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
995         (void) ttm_bo_device_release(&dev_priv->bdev);
996         vmw_release_device_late(dev_priv);
997         vmw_fence_manager_takedown(dev_priv->fman);
998         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
999                 vmw_irq_uninstall(dev_priv->dev);
1000         if (dev_priv->stealth)
1001                 pci_release_region(dev->pdev, 2);
1002         else
1003                 pci_release_regions(dev->pdev);
1004
1005         ttm_object_device_release(&dev_priv->tdev);
1006         memunmap(dev_priv->mmio_virt);
1007         if (dev_priv->ctx.staged_bindings)
1008                 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1009
1010         for (i = vmw_res_context; i < vmw_res_max; ++i)
1011                 idr_destroy(&dev_priv->res_idr[i]);
1012
1013         kfree(dev_priv);
1014 }
1015
1016 static void vmw_postclose(struct drm_device *dev,
1017                          struct drm_file *file_priv)
1018 {
1019         struct vmw_fpriv *vmw_fp;
1020
1021         vmw_fp = vmw_fpriv(file_priv);
1022
1023         if (vmw_fp->locked_master) {
1024                 struct vmw_master *vmaster =
1025                         vmw_master(vmw_fp->locked_master);
1026
1027                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1028                 ttm_vt_unlock(&vmaster->lock);
1029                 drm_master_put(&vmw_fp->locked_master);
1030         }
1031
1032         ttm_object_file_release(&vmw_fp->tfile);
1033         kfree(vmw_fp);
1034 }
1035
1036 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1037 {
1038         struct vmw_private *dev_priv = vmw_priv(dev);
1039         struct vmw_fpriv *vmw_fp;
1040         int ret = -ENOMEM;
1041
1042         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1043         if (unlikely(!vmw_fp))
1044                 return ret;
1045
1046         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1047         if (unlikely(vmw_fp->tfile == NULL))
1048                 goto out_no_tfile;
1049
1050         file_priv->driver_priv = vmw_fp;
1051
1052         return 0;
1053
1054 out_no_tfile:
1055         kfree(vmw_fp);
1056         return ret;
1057 }
1058
1059 static struct vmw_master *vmw_master_check(struct drm_device *dev,
1060                                            struct drm_file *file_priv,
1061                                            unsigned int flags)
1062 {
1063         int ret;
1064         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1065         struct vmw_master *vmaster;
1066
1067         if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH))
1068                 return NULL;
1069
1070         ret = mutex_lock_interruptible(&dev->master_mutex);
1071         if (unlikely(ret != 0))
1072                 return ERR_PTR(-ERESTARTSYS);
1073
1074         if (drm_is_current_master(file_priv)) {
1075                 mutex_unlock(&dev->master_mutex);
1076                 return NULL;
1077         }
1078
1079         /*
1080          * Check if we were previously master, but now dropped. In that
1081          * case, allow at least render node functionality.
1082          */
1083         if (vmw_fp->locked_master) {
1084                 mutex_unlock(&dev->master_mutex);
1085
1086                 if (flags & DRM_RENDER_ALLOW)
1087                         return NULL;
1088
1089                 DRM_ERROR("Dropped master trying to access ioctl that "
1090                           "requires authentication.\n");
1091                 return ERR_PTR(-EACCES);
1092         }
1093         mutex_unlock(&dev->master_mutex);
1094
1095         /*
1096          * Take the TTM lock. Possibly sleep waiting for the authenticating
1097          * master to become master again, or for a SIGTERM if the
1098          * authenticating master exits.
1099          */
1100         vmaster = vmw_master(file_priv->master);
1101         ret = ttm_read_lock(&vmaster->lock, true);
1102         if (unlikely(ret != 0))
1103                 vmaster = ERR_PTR(ret);
1104
1105         return vmaster;
1106 }
1107
1108 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1109                               unsigned long arg,
1110                               long (*ioctl_func)(struct file *, unsigned int,
1111                                                  unsigned long))
1112 {
1113         struct drm_file *file_priv = filp->private_data;
1114         struct drm_device *dev = file_priv->minor->dev;
1115         unsigned int nr = DRM_IOCTL_NR(cmd);
1116         struct vmw_master *vmaster;
1117         unsigned int flags;
1118         long ret;
1119
1120         /*
1121          * Do extra checking on driver private ioctls.
1122          */
1123
1124         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1125             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1126                 const struct drm_ioctl_desc *ioctl =
1127                         &vmw_ioctls[nr - DRM_COMMAND_BASE];
1128
1129                 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1130                         ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1131                         if (unlikely(ret != 0))
1132                                 return ret;
1133
1134                         if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1135                                 goto out_io_encoding;
1136
1137                         return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1138                                                         _IOC_SIZE(cmd));
1139                 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1140                         if (!drm_is_current_master(file_priv) &&
1141                             !capable(CAP_SYS_ADMIN))
1142                                 return -EACCES;
1143                 }
1144
1145                 if (unlikely(ioctl->cmd != cmd))
1146                         goto out_io_encoding;
1147
1148                 flags = ioctl->flags;
1149         } else if (!drm_ioctl_flags(nr, &flags))
1150                 return -EINVAL;
1151
1152         vmaster = vmw_master_check(dev, file_priv, flags);
1153         if (IS_ERR(vmaster)) {
1154                 ret = PTR_ERR(vmaster);
1155
1156                 if (ret != -ERESTARTSYS)
1157                         DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1158                                  nr, ret);
1159                 return ret;
1160         }
1161
1162         ret = ioctl_func(filp, cmd, arg);
1163         if (vmaster)
1164                 ttm_read_unlock(&vmaster->lock);
1165
1166         return ret;
1167
1168 out_io_encoding:
1169         DRM_ERROR("Invalid command format, ioctl %d\n",
1170                   nr - DRM_COMMAND_BASE);
1171
1172         return -EINVAL;
1173 }
1174
1175 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1176                                unsigned long arg)
1177 {
1178         return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1179 }
1180
1181 #ifdef CONFIG_COMPAT
1182 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1183                              unsigned long arg)
1184 {
1185         return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1186 }
1187 #endif
1188
1189 static void vmw_lastclose(struct drm_device *dev)
1190 {
1191 }
1192
1193 static void vmw_master_init(struct vmw_master *vmaster)
1194 {
1195         ttm_lock_init(&vmaster->lock);
1196 }
1197
1198 static int vmw_master_create(struct drm_device *dev,
1199                              struct drm_master *master)
1200 {
1201         struct vmw_master *vmaster;
1202
1203         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1204         if (unlikely(!vmaster))
1205                 return -ENOMEM;
1206
1207         vmw_master_init(vmaster);
1208         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1209         master->driver_priv = vmaster;
1210
1211         return 0;
1212 }
1213
1214 static void vmw_master_destroy(struct drm_device *dev,
1215                                struct drm_master *master)
1216 {
1217         struct vmw_master *vmaster = vmw_master(master);
1218
1219         master->driver_priv = NULL;
1220         kfree(vmaster);
1221 }
1222
1223 static int vmw_master_set(struct drm_device *dev,
1224                           struct drm_file *file_priv,
1225                           bool from_open)
1226 {
1227         struct vmw_private *dev_priv = vmw_priv(dev);
1228         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1229         struct vmw_master *active = dev_priv->active_master;
1230         struct vmw_master *vmaster = vmw_master(file_priv->master);
1231         int ret = 0;
1232
1233         if (active) {
1234                 BUG_ON(active != &dev_priv->fbdev_master);
1235                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1236                 if (unlikely(ret != 0))
1237                         return ret;
1238
1239                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1240                 dev_priv->active_master = NULL;
1241         }
1242
1243         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1244         if (!from_open) {
1245                 ttm_vt_unlock(&vmaster->lock);
1246                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1247                 drm_master_put(&vmw_fp->locked_master);
1248         }
1249
1250         dev_priv->active_master = vmaster;
1251         drm_sysfs_hotplug_event(dev);
1252
1253         return 0;
1254 }
1255
1256 static void vmw_master_drop(struct drm_device *dev,
1257                             struct drm_file *file_priv)
1258 {
1259         struct vmw_private *dev_priv = vmw_priv(dev);
1260         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1261         struct vmw_master *vmaster = vmw_master(file_priv->master);
1262         int ret;
1263
1264         /**
1265          * Make sure the master doesn't disappear while we have
1266          * it locked.
1267          */
1268
1269         vmw_fp->locked_master = drm_master_get(file_priv->master);
1270         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1271         vmw_kms_legacy_hotspot_clear(dev_priv);
1272         if (unlikely((ret != 0))) {
1273                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1274                 drm_master_put(&vmw_fp->locked_master);
1275         }
1276
1277         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1278
1279         if (!dev_priv->enable_fb)
1280                 vmw_svga_disable(dev_priv);
1281
1282         dev_priv->active_master = &dev_priv->fbdev_master;
1283         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1284         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1285 }
1286
1287 /**
1288  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1289  *
1290  * @dev_priv: Pointer to device private struct.
1291  * Needs the reservation sem to be held in non-exclusive mode.
1292  */
1293 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1294 {
1295         spin_lock(&dev_priv->svga_lock);
1296         if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1297                 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1298                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1299         }
1300         spin_unlock(&dev_priv->svga_lock);
1301 }
1302
1303 /**
1304  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1305  *
1306  * @dev_priv: Pointer to device private struct.
1307  */
1308 void vmw_svga_enable(struct vmw_private *dev_priv)
1309 {
1310         (void) ttm_read_lock(&dev_priv->reservation_sem, false);
1311         __vmw_svga_enable(dev_priv);
1312         ttm_read_unlock(&dev_priv->reservation_sem);
1313 }
1314
1315 /**
1316  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1317  *
1318  * @dev_priv: Pointer to device private struct.
1319  * Needs the reservation sem to be held in exclusive mode.
1320  * Will not empty VRAM. VRAM must be emptied by caller.
1321  */
1322 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1323 {
1324         spin_lock(&dev_priv->svga_lock);
1325         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1326                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1327                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1328                           SVGA_REG_ENABLE_HIDE |
1329                           SVGA_REG_ENABLE_ENABLE);
1330         }
1331         spin_unlock(&dev_priv->svga_lock);
1332 }
1333
1334 /**
1335  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1336  * running.
1337  *
1338  * @dev_priv: Pointer to device private struct.
1339  * Will empty VRAM.
1340  */
1341 void vmw_svga_disable(struct vmw_private *dev_priv)
1342 {
1343         /*
1344          * Disabling SVGA will turn off device modesetting capabilities, so
1345          * notify KMS about that so that it doesn't cache atomic state that
1346          * isn't valid anymore, for example crtcs turned on.
1347          * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1348          * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1349          * end up with lock order reversal. Thus, a master may actually perform
1350          * a new modeset just after we call vmw_kms_lost_device() and race with
1351          * vmw_svga_disable(), but that should at worst cause atomic KMS state
1352          * to be inconsistent with the device, causing modesetting problems.
1353          *
1354          */
1355         vmw_kms_lost_device(dev_priv->dev);
1356         ttm_write_lock(&dev_priv->reservation_sem, false);
1357         spin_lock(&dev_priv->svga_lock);
1358         if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1359                 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1360                 spin_unlock(&dev_priv->svga_lock);
1361                 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1362                         DRM_ERROR("Failed evicting VRAM buffers.\n");
1363                 vmw_write(dev_priv, SVGA_REG_ENABLE,
1364                           SVGA_REG_ENABLE_HIDE |
1365                           SVGA_REG_ENABLE_ENABLE);
1366         } else
1367                 spin_unlock(&dev_priv->svga_lock);
1368         ttm_write_unlock(&dev_priv->reservation_sem);
1369 }
1370
1371 static void vmw_remove(struct pci_dev *pdev)
1372 {
1373         struct drm_device *dev = pci_get_drvdata(pdev);
1374
1375         pci_disable_device(pdev);
1376         drm_put_dev(dev);
1377 }
1378
1379 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1380                               void *ptr)
1381 {
1382         struct vmw_private *dev_priv =
1383                 container_of(nb, struct vmw_private, pm_nb);
1384
1385         switch (val) {
1386         case PM_HIBERNATION_PREPARE:
1387                 /*
1388                  * Take the reservation sem in write mode, which will make sure
1389                  * there are no other processes holding a buffer object
1390                  * reservation, meaning we should be able to evict all buffer
1391                  * objects if needed.
1392                  * Once user-space processes have been frozen, we can release
1393                  * the lock again.
1394                  */
1395                 ttm_suspend_lock(&dev_priv->reservation_sem);
1396                 dev_priv->suspend_locked = true;
1397                 break;
1398         case PM_POST_HIBERNATION:
1399         case PM_POST_RESTORE:
1400                 if (READ_ONCE(dev_priv->suspend_locked)) {
1401                         dev_priv->suspend_locked = false;
1402                         ttm_suspend_unlock(&dev_priv->reservation_sem);
1403                 }
1404                 break;
1405         default:
1406                 break;
1407         }
1408         return 0;
1409 }
1410
1411 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1412 {
1413         struct drm_device *dev = pci_get_drvdata(pdev);
1414         struct vmw_private *dev_priv = vmw_priv(dev);
1415
1416         if (dev_priv->refuse_hibernation)
1417                 return -EBUSY;
1418
1419         pci_save_state(pdev);
1420         pci_disable_device(pdev);
1421         pci_set_power_state(pdev, PCI_D3hot);
1422         return 0;
1423 }
1424
1425 static int vmw_pci_resume(struct pci_dev *pdev)
1426 {
1427         pci_set_power_state(pdev, PCI_D0);
1428         pci_restore_state(pdev);
1429         return pci_enable_device(pdev);
1430 }
1431
1432 static int vmw_pm_suspend(struct device *kdev)
1433 {
1434         struct pci_dev *pdev = to_pci_dev(kdev);
1435         struct pm_message dummy;
1436
1437         dummy.event = 0;
1438
1439         return vmw_pci_suspend(pdev, dummy);
1440 }
1441
1442 static int vmw_pm_resume(struct device *kdev)
1443 {
1444         struct pci_dev *pdev = to_pci_dev(kdev);
1445
1446         return vmw_pci_resume(pdev);
1447 }
1448
1449 static int vmw_pm_freeze(struct device *kdev)
1450 {
1451         struct pci_dev *pdev = to_pci_dev(kdev);
1452         struct drm_device *dev = pci_get_drvdata(pdev);
1453         struct vmw_private *dev_priv = vmw_priv(dev);
1454         int ret;
1455
1456         /*
1457          * Unlock for vmw_kms_suspend.
1458          * No user-space processes should be running now.
1459          */
1460         ttm_suspend_unlock(&dev_priv->reservation_sem);
1461         ret = vmw_kms_suspend(dev_priv->dev);
1462         if (ret) {
1463                 ttm_suspend_lock(&dev_priv->reservation_sem);
1464                 DRM_ERROR("Failed to freeze modesetting.\n");
1465                 return ret;
1466         }
1467         if (dev_priv->enable_fb)
1468                 vmw_fb_off(dev_priv);
1469
1470         ttm_suspend_lock(&dev_priv->reservation_sem);
1471         vmw_execbuf_release_pinned_bo(dev_priv);
1472         vmw_resource_evict_all(dev_priv);
1473         vmw_release_device_early(dev_priv);
1474         ttm_bo_swapout_all(&dev_priv->bdev);
1475         if (dev_priv->enable_fb)
1476                 vmw_fifo_resource_dec(dev_priv);
1477         if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1478                 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1479                 if (dev_priv->enable_fb)
1480                         vmw_fifo_resource_inc(dev_priv);
1481                 WARN_ON(vmw_request_device_late(dev_priv));
1482                 dev_priv->suspend_locked = false;
1483                 ttm_suspend_unlock(&dev_priv->reservation_sem);
1484                 if (dev_priv->suspend_state)
1485                         vmw_kms_resume(dev);
1486                 if (dev_priv->enable_fb)
1487                         vmw_fb_on(dev_priv);
1488                 return -EBUSY;
1489         }
1490
1491         vmw_fence_fifo_down(dev_priv->fman);
1492         __vmw_svga_disable(dev_priv);
1493         
1494         vmw_release_device_late(dev_priv);
1495         return 0;
1496 }
1497
1498 static int vmw_pm_restore(struct device *kdev)
1499 {
1500         struct pci_dev *pdev = to_pci_dev(kdev);
1501         struct drm_device *dev = pci_get_drvdata(pdev);
1502         struct vmw_private *dev_priv = vmw_priv(dev);
1503         int ret;
1504
1505         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1506         (void) vmw_read(dev_priv, SVGA_REG_ID);
1507
1508         if (dev_priv->enable_fb)
1509                 vmw_fifo_resource_inc(dev_priv);
1510
1511         ret = vmw_request_device(dev_priv);
1512         if (ret)
1513                 return ret;
1514
1515         if (dev_priv->enable_fb)
1516                 __vmw_svga_enable(dev_priv);
1517
1518         vmw_fence_fifo_up(dev_priv->fman);
1519         dev_priv->suspend_locked = false;
1520         ttm_suspend_unlock(&dev_priv->reservation_sem);
1521         if (dev_priv->suspend_state)
1522                 vmw_kms_resume(dev_priv->dev);
1523
1524         if (dev_priv->enable_fb)
1525                 vmw_fb_on(dev_priv);
1526
1527         return 0;
1528 }
1529
1530 static const struct dev_pm_ops vmw_pm_ops = {
1531         .freeze = vmw_pm_freeze,
1532         .thaw = vmw_pm_restore,
1533         .restore = vmw_pm_restore,
1534         .suspend = vmw_pm_suspend,
1535         .resume = vmw_pm_resume,
1536 };
1537
1538 static const struct file_operations vmwgfx_driver_fops = {
1539         .owner = THIS_MODULE,
1540         .open = drm_open,
1541         .release = drm_release,
1542         .unlocked_ioctl = vmw_unlocked_ioctl,
1543         .mmap = vmw_mmap,
1544         .poll = vmw_fops_poll,
1545         .read = vmw_fops_read,
1546 #if defined(CONFIG_COMPAT)
1547         .compat_ioctl = vmw_compat_ioctl,
1548 #endif
1549         .llseek = noop_llseek,
1550 };
1551
1552 static struct drm_driver driver = {
1553         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1554         DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC,
1555         .load = vmw_driver_load,
1556         .unload = vmw_driver_unload,
1557         .lastclose = vmw_lastclose,
1558         .get_vblank_counter = vmw_get_vblank_counter,
1559         .enable_vblank = vmw_enable_vblank,
1560         .disable_vblank = vmw_disable_vblank,
1561         .ioctls = vmw_ioctls,
1562         .num_ioctls = ARRAY_SIZE(vmw_ioctls),
1563         .master_create = vmw_master_create,
1564         .master_destroy = vmw_master_destroy,
1565         .master_set = vmw_master_set,
1566         .master_drop = vmw_master_drop,
1567         .open = vmw_driver_open,
1568         .postclose = vmw_postclose,
1569
1570         .dumb_create = vmw_dumb_create,
1571         .dumb_map_offset = vmw_dumb_map_offset,
1572         .dumb_destroy = vmw_dumb_destroy,
1573
1574         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1575         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1576
1577         .fops = &vmwgfx_driver_fops,
1578         .name = VMWGFX_DRIVER_NAME,
1579         .desc = VMWGFX_DRIVER_DESC,
1580         .date = VMWGFX_DRIVER_DATE,
1581         .major = VMWGFX_DRIVER_MAJOR,
1582         .minor = VMWGFX_DRIVER_MINOR,
1583         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1584 };
1585
1586 static struct pci_driver vmw_pci_driver = {
1587         .name = VMWGFX_DRIVER_NAME,
1588         .id_table = vmw_pci_id_list,
1589         .probe = vmw_probe,
1590         .remove = vmw_remove,
1591         .driver = {
1592                 .pm = &vmw_pm_ops
1593         }
1594 };
1595
1596 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1597 {
1598         return drm_get_pci_dev(pdev, ent, &driver);
1599 }
1600
1601 static int __init vmwgfx_init(void)
1602 {
1603         int ret;
1604
1605         if (vgacon_text_force())
1606                 return -EINVAL;
1607
1608         ret = pci_register_driver(&vmw_pci_driver);
1609         if (ret)
1610                 DRM_ERROR("Failed initializing DRM.\n");
1611         return ret;
1612 }
1613
1614 static void __exit vmwgfx_exit(void)
1615 {
1616         pci_unregister_driver(&vmw_pci_driver);
1617 }
1618
1619 module_init(vmwgfx_init);
1620 module_exit(vmwgfx_exit);
1621
1622 MODULE_AUTHOR("VMware Inc. and others");
1623 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1624 MODULE_LICENSE("GPL and additional rights");
1625 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1626                __stringify(VMWGFX_DRIVER_MINOR) "."
1627                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1628                "0");