drivers/gpu/drm/zte/zx_plane.c

   1 /*
   2  * Copyright 2016 Linaro Ltd.
   3  * Copyright 2016 ZTE Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <drm/drm_atomic.h>
  12 #include <drm/drm_atomic_helper.h>
  13 #include <drm/drm_fb_cma_helper.h>
  14 #include <drm/drm_fourcc.h>
  15 #include <drm/drm_gem_cma_helper.h>
  16 #include <drm/drm_modeset_helper_vtables.h>
  17 #include <drm/drm_plane_helper.h>
  18
  19 #include "zx_common_regs.h"
  20 #include "zx_drm_drv.h"
  21 #include "zx_plane.h"
  22 #include "zx_plane_regs.h"
  23 #include "zx_vou.h"
  24
  25 static const uint32_t gl_formats[] = {
  26         DRM_FORMAT_ARGB8888,
  27         DRM_FORMAT_XRGB8888,
  28         DRM_FORMAT_RGB888,
  29         DRM_FORMAT_RGB565,
  30         DRM_FORMAT_ARGB1555,
  31         DRM_FORMAT_ARGB4444,
  32 };
  33
  34 static const uint32_t vl_formats[] = {
  35         DRM_FORMAT_NV12,        /* Semi-planar YUV420 */
  36         DRM_FORMAT_YUV420,      /* Planar YUV420 */
  37         DRM_FORMAT_YUYV,        /* Packed YUV422 */
  38         DRM_FORMAT_YVYU,
  39         DRM_FORMAT_UYVY,
  40         DRM_FORMAT_VYUY,
  41         DRM_FORMAT_YUV444,      /* YUV444 8bit */
  42         /*
  43          * TODO: add formats below that HW supports:
  44          *  - YUV420 P010
  45          *  - YUV420 Hantro
  46          *  - YUV444 10bit
  47          */
  48 };
  49
  50 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
  51
  52 static int zx_vl_plane_atomic_check(struct drm_plane *plane,
  53                                     struct drm_plane_state *plane_state)
  54 {
  55         struct drm_framebuffer *fb = plane_state->fb;
  56         struct drm_crtc *crtc = plane_state->crtc;
  57         struct drm_crtc_state *crtc_state;
  58         int min_scale = FRAC_16_16(1, 8);
  59         int max_scale = FRAC_16_16(8, 1);
  60
  61         if (!crtc || !fb)
  62                 return 0;
  63
  64         crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
  65                                                         crtc);
  66         if (WARN_ON(!crtc_state))
  67                 return -EINVAL;
  68
  69         /* nothing to check when disabling or disabled */
  70         if (!crtc_state->enable)
  71                 return 0;
  72
  73         /* plane must be enabled */
  74         if (!plane_state->crtc)
  75                 return -EINVAL;
  76
  77         return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
  78                                                    min_scale, max_scale,
  79                                                    true, true);
  80 }
  81
  82 static int zx_vl_get_fmt(uint32_t format)
  83 {
  84         switch (format) {
  85         case DRM_FORMAT_NV12:
  86                 return VL_FMT_YUV420;
  87         case DRM_FORMAT_YUV420:
  88                 return VL_YUV420_PLANAR | VL_FMT_YUV420;
  89         case DRM_FORMAT_YUYV:
  90                 return VL_YUV422_YUYV | VL_FMT_YUV422;
  91         case DRM_FORMAT_YVYU:
  92                 return VL_YUV422_YVYU | VL_FMT_YUV422;
  93         case DRM_FORMAT_UYVY:
  94                 return VL_YUV422_UYVY | VL_FMT_YUV422;
  95         case DRM_FORMAT_VYUY:
  96                 return VL_YUV422_VYUY | VL_FMT_YUV422;
  97         case DRM_FORMAT_YUV444:
  98                 return VL_FMT_YUV444_8BIT;
  99         default:
 100                 WARN_ONCE(1, "invalid pixel format %d\n", format);
 101                 return -EINVAL;
 102         }
 103 }
 104
 105 static inline void zx_vl_set_update(struct zx_plane *zplane)
 106 {
 107         void __iomem *layer = zplane->layer;
 108
 109         zx_writel_mask(layer + VL_CTRL0, VL_UPDATE, VL_UPDATE);
 110 }
 111
 112 static inline void zx_vl_rsz_set_update(struct zx_plane *zplane)
 113 {
 114         zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1);
 115 }
 116
 117 static int zx_vl_rsz_get_fmt(uint32_t format)
 118 {
 119         switch (format) {
 120         case DRM_FORMAT_NV12:
 121         case DRM_FORMAT_YUV420:
 122                 return RSZ_VL_FMT_YCBCR420;
 123         case DRM_FORMAT_YUYV:
 124         case DRM_FORMAT_YVYU:
 125         case DRM_FORMAT_UYVY:
 126         case DRM_FORMAT_VYUY:
 127                 return RSZ_VL_FMT_YCBCR422;
 128         case DRM_FORMAT_YUV444:
 129                 return RSZ_VL_FMT_YCBCR444;
 130         default:
 131                 WARN_ONCE(1, "invalid pixel format %d\n", format);
 132                 return -EINVAL;
 133         }
 134 }
 135
 136 static inline u32 rsz_step_value(u32 src, u32 dst)
 137 {
 138         u32 val = 0;
 139
 140         if (src == dst)
 141                 val = 0;
 142         else if (src < dst)
 143                 val = RSZ_PARA_STEP((src << 16) / dst);
 144         else if (src > dst)
 145                 val = RSZ_DATA_STEP(src / dst) |
 146                       RSZ_PARA_STEP(((src << 16) / dst) & 0xffff);
 147
 148         return val;
 149 }
 150
 151 static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format,
 152                             u32 src_w, u32 src_h, u32 dst_w, u32 dst_h)
 153 {
 154         void __iomem *rsz = zplane->rsz;
 155         u32 src_chroma_w = src_w;
 156         u32 src_chroma_h = src_h;
 157         int fmt;
 158
 159         /* Set up source and destination resolution */
 160         zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1));
 161         zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1));
 162
 163         /* Configure data format for VL RSZ */
 164         fmt = zx_vl_rsz_get_fmt(format);
 165         if (fmt >= 0)
 166                 zx_writel_mask(rsz + RSZ_VL_CTRL_CFG, RSZ_VL_FMT_MASK, fmt);
 167
 168         /* Calculate Chroma height and width */
 169         if (fmt == RSZ_VL_FMT_YCBCR420) {
 170                 src_chroma_w = src_w >> 1;
 171                 src_chroma_h = src_h >> 1;
 172         } else if (fmt == RSZ_VL_FMT_YCBCR422) {
 173                 src_chroma_w = src_w >> 1;
 174         }
 175
 176         /* Set up Luma and Chroma step registers */
 177         zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w));
 178         zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h));
 179         zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w));
 180         zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h));
 181
 182         zx_vl_rsz_set_update(zplane);
 183 }
 184
 185 static void zx_vl_plane_atomic_update(struct drm_plane *plane,
 186                                       struct drm_plane_state *old_state)
 187 {
 188         struct zx_plane *zplane = to_zx_plane(plane);
 189         struct drm_plane_state *state = plane->state;
 190         struct drm_framebuffer *fb = state->fb;
 191         struct drm_rect *src = &state->src;
 192         struct drm_rect *dst = &state->dst;
 193         struct drm_gem_cma_object *cma_obj;
 194         void __iomem *layer = zplane->layer;
 195         void __iomem *hbsc = zplane->hbsc;
 196         void __iomem *paddr_reg;
 197         dma_addr_t paddr;
 198         u32 src_x, src_y, src_w, src_h;
 199         u32 dst_x, dst_y, dst_w, dst_h;
 200         uint32_t format;
 201         int fmt;
 202         int i;
 203
 204         if (!fb)
 205                 return;
 206
 207         format = fb->format->format;
 208
 209         src_x = src->x1 >> 16;
 210         src_y = src->y1 >> 16;
 211         src_w = drm_rect_width(src) >> 16;
 212         src_h = drm_rect_height(src) >> 16;
 213
 214         dst_x = dst->x1;
 215         dst_y = dst->y1;
 216         dst_w = drm_rect_width(dst);
 217         dst_h = drm_rect_height(dst);
 218
 219         /* Set up data address registers for Y, Cb and Cr planes */
 220         paddr_reg = layer + VL_Y;
 221         for (i = 0; i < fb->format->num_planes; i++) {
 222                 cma_obj = drm_fb_cma_get_gem_obj(fb, i);
 223                 paddr = cma_obj->paddr + fb->offsets[i];
 224                 paddr += src_y * fb->pitches[i];
 225                 paddr += src_x * fb->format->cpp[i];
 226                 zx_writel(paddr_reg, paddr);
 227                 paddr_reg += 4;
 228         }
 229
 230         /* Set up source height/width register */
 231         zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h));
 232
 233         /* Set up start position register */
 234         zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y));
 235
 236         /* Set up end position register */
 237         zx_writel(layer + VL_POS_END,
 238                   GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h));
 239
 240         /* Strides of Cb and Cr planes should be identical */
 241         zx_writel(layer + VL_STRIDE, LUMA_STRIDE(fb->pitches[0]) |
 242                   CHROMA_STRIDE(fb->pitches[1]));
 243
 244         /* Set up video layer data format */
 245         fmt = zx_vl_get_fmt(format);
 246         if (fmt >= 0)
 247                 zx_writel(layer + VL_CTRL1, fmt);
 248
 249         /* Always use scaler since it exists (set for not bypass) */
 250         zx_writel_mask(layer + VL_CTRL2, VL_SCALER_BYPASS_MODE,
 251                        VL_SCALER_BYPASS_MODE);
 252
 253         zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h);
 254
 255         /* Enable HBSC block */
 256         zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
 257
 258         zx_vou_layer_enable(plane);
 259
 260         zx_vl_set_update(zplane);
 261 }
 262
 263 static void zx_plane_atomic_disable(struct drm_plane *plane,
 264                                     struct drm_plane_state *old_state)
 265 {
 266         struct zx_plane *zplane = to_zx_plane(plane);
 267         void __iomem *hbsc = zplane->hbsc;
 268
 269         zx_vou_layer_disable(plane, old_state);
 270
 271         /* Disable HBSC block */
 272         zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, 0);
 273 }
 274
 275 static const struct drm_plane_helper_funcs zx_vl_plane_helper_funcs = {
 276         .atomic_check = zx_vl_plane_atomic_check,
 277         .atomic_update = zx_vl_plane_atomic_update,
 278         .atomic_disable = zx_plane_atomic_disable,
 279 };
 280
 281 static int zx_gl_plane_atomic_check(struct drm_plane *plane,
 282                                     struct drm_plane_state *plane_state)
 283 {
 284         struct drm_framebuffer *fb = plane_state->fb;
 285         struct drm_crtc *crtc = plane_state->crtc;
 286         struct drm_crtc_state *crtc_state;
 287
 288         if (!crtc || !fb)
 289                 return 0;
 290
 291         crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
 292                                                         crtc);
 293         if (WARN_ON(!crtc_state))
 294                 return -EINVAL;
 295
 296         /* nothing to check when disabling or disabled */
 297         if (!crtc_state->enable)
 298                 return 0;
 299
 300         /* plane must be enabled */
 301         if (!plane_state->crtc)
 302                 return -EINVAL;
 303
 304         return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
 305                                                    DRM_PLANE_HELPER_NO_SCALING,
 306                                                    DRM_PLANE_HELPER_NO_SCALING,
 307                                                    false, true);
 308 }
 309
 310 static int zx_gl_get_fmt(uint32_t format)
 311 {
 312         switch (format) {
 313         case DRM_FORMAT_ARGB8888:
 314         case DRM_FORMAT_XRGB8888:
 315                 return GL_FMT_ARGB8888;
 316         case DRM_FORMAT_RGB888:
 317                 return GL_FMT_RGB888;
 318         case DRM_FORMAT_RGB565:
 319                 return GL_FMT_RGB565;
 320         case DRM_FORMAT_ARGB1555:
 321                 return GL_FMT_ARGB1555;
 322         case DRM_FORMAT_ARGB4444:
 323                 return GL_FMT_ARGB4444;
 324         default:
 325                 WARN_ONCE(1, "invalid pixel format %d\n", format);
 326                 return -EINVAL;
 327         }
 328 }
 329
 330 static inline void zx_gl_set_update(struct zx_plane *zplane)
 331 {
 332         void __iomem *layer = zplane->layer;
 333
 334         zx_writel_mask(layer + GL_CTRL0, GL_UPDATE, GL_UPDATE);
 335 }
 336
 337 static inline void zx_gl_rsz_set_update(struct zx_plane *zplane)
 338 {
 339         zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1);
 340 }
 341
 342 static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h,
 343                             u32 dst_w, u32 dst_h)
 344 {
 345         void __iomem *rsz = zplane->rsz;
 346
 347         zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1));
 348         zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1));
 349
 350         zx_gl_rsz_set_update(zplane);
 351 }
 352
 353 static void zx_gl_plane_atomic_update(struct drm_plane *plane,
 354                                       struct drm_plane_state *old_state)
 355 {
 356         struct zx_plane *zplane = to_zx_plane(plane);
 357         struct drm_framebuffer *fb = plane->state->fb;
 358         struct drm_gem_cma_object *cma_obj;
 359         void __iomem *layer = zplane->layer;
 360         void __iomem *csc = zplane->csc;
 361         void __iomem *hbsc = zplane->hbsc;
 362         u32 src_x, src_y, src_w, src_h;
 363         u32 dst_x, dst_y, dst_w, dst_h;
 364         unsigned int bpp;
 365         uint32_t format;
 366         dma_addr_t paddr;
 367         u32 stride;
 368         int fmt;
 369
 370         if (!fb)
 371                 return;
 372
 373         format = fb->format->format;
 374         stride = fb->pitches[0];
 375
 376         src_x = plane->state->src_x >> 16;
 377         src_y = plane->state->src_y >> 16;
 378         src_w = plane->state->src_w >> 16;
 379         src_h = plane->state->src_h >> 16;
 380
 381         dst_x = plane->state->crtc_x;
 382         dst_y = plane->state->crtc_y;
 383         dst_w = plane->state->crtc_w;
 384         dst_h = plane->state->crtc_h;
 385
 386         bpp = fb->format->cpp[0];
 387
 388         cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
 389         paddr = cma_obj->paddr + fb->offsets[0];
 390         paddr += src_y * stride + src_x * bpp / 8;
 391         zx_writel(layer + GL_ADDR, paddr);
 392
 393         /* Set up source height/width register */
 394         zx_writel(layer + GL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h));
 395
 396         /* Set up start position register */
 397         zx_writel(layer + GL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y));
 398
 399         /* Set up end position register */
 400         zx_writel(layer + GL_POS_END,
 401                   GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h));
 402
 403         /* Set up stride register */
 404         zx_writel(layer + GL_STRIDE, stride & 0xffff);
 405
 406         /* Set up graphic layer data format */
 407         fmt = zx_gl_get_fmt(format);
 408         if (fmt >= 0)
 409                 zx_writel_mask(layer + GL_CTRL1, GL_DATA_FMT_MASK,
 410                                fmt << GL_DATA_FMT_SHIFT);
 411
 412         /* Initialize global alpha with a sane value */
 413         zx_writel_mask(layer + GL_CTRL2, GL_GLOBAL_ALPHA_MASK,
 414                        0xff << GL_GLOBAL_ALPHA_SHIFT);
 415
 416         /* Setup CSC for the GL */
 417         if (dst_h > 720)
 418                 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
 419                                CSC_BT709_IMAGE_RGB2YCBCR << CSC_COV_MODE_SHIFT);
 420         else
 421                 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK,
 422                                CSC_BT601_IMAGE_RGB2YCBCR << CSC_COV_MODE_SHIFT);
 423         zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, CSC_WORK_ENABLE);
 424
 425         /* Always use scaler since it exists (set for not bypass) */
 426         zx_writel_mask(layer + GL_CTRL3, GL_SCALER_BYPASS_MODE,
 427                        GL_SCALER_BYPASS_MODE);
 428
 429         zx_gl_rsz_setup(zplane, src_w, src_h, dst_w, dst_h);
 430
 431         /* Enable HBSC block */
 432         zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
 433
 434         zx_vou_layer_enable(plane);
 435
 436         zx_gl_set_update(zplane);
 437 }
 438
 439 static const struct drm_plane_helper_funcs zx_gl_plane_helper_funcs = {
 440         .atomic_check = zx_gl_plane_atomic_check,
 441         .atomic_update = zx_gl_plane_atomic_update,
 442         .atomic_disable = zx_plane_atomic_disable,
 443 };
 444
 445 static void zx_plane_destroy(struct drm_plane *plane)
 446 {
 447         drm_plane_cleanup(plane);
 448 }
 449
 450 static const struct drm_plane_funcs zx_plane_funcs = {
 451         .update_plane = drm_atomic_helper_update_plane,
 452         .disable_plane = drm_atomic_helper_disable_plane,
 453         .destroy = zx_plane_destroy,
 454         .reset = drm_atomic_helper_plane_reset,
 455         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 456         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 457 };
 458
 459 void zx_plane_set_update(struct drm_plane *plane)
 460 {
 461         struct zx_plane *zplane = to_zx_plane(plane);
 462
 463         /* Do nothing if the plane is not enabled */
 464         if (!plane->state->crtc)
 465                 return;
 466
 467         switch (plane->type) {
 468         case DRM_PLANE_TYPE_PRIMARY:
 469                 zx_gl_rsz_set_update(zplane);
 470                 zx_gl_set_update(zplane);
 471                 break;
 472         case DRM_PLANE_TYPE_OVERLAY:
 473                 zx_vl_rsz_set_update(zplane);
 474                 zx_vl_set_update(zplane);
 475                 break;
 476         default:
 477                 WARN_ONCE(1, "unsupported plane type %d\n", plane->type);
 478         }
 479 }
 480
 481 static void zx_plane_hbsc_init(struct zx_plane *zplane)
 482 {
 483         void __iomem *hbsc = zplane->hbsc;
 484
 485         /*
 486          *  Initialize HBSC block with a sane configuration per recommedation
 487          *  from ZTE BSP code.
 488          */
 489         zx_writel(hbsc + HBSC_SATURATION, 0x200);
 490         zx_writel(hbsc + HBSC_HUE, 0x0);
 491         zx_writel(hbsc + HBSC_BRIGHT, 0x0);
 492         zx_writel(hbsc + HBSC_CONTRAST, 0x200);
 493
 494         zx_writel(hbsc + HBSC_THRESHOLD_COL1, (0x3ac << 16) | 0x40);
 495         zx_writel(hbsc + HBSC_THRESHOLD_COL2, (0x3c0 << 16) | 0x40);
 496         zx_writel(hbsc + HBSC_THRESHOLD_COL3, (0x3c0 << 16) | 0x40);
 497 }
 498
 499 int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane,
 500                   enum drm_plane_type type)
 501 {
 502         const struct drm_plane_helper_funcs *helper;
 503         struct drm_plane *plane = &zplane->plane;
 504         struct device *dev = zplane->dev;
 505         const uint32_t *formats;
 506         unsigned int format_count;
 507         int ret;
 508
 509         zx_plane_hbsc_init(zplane);
 510
 511         switch (type) {
 512         case DRM_PLANE_TYPE_PRIMARY:
 513                 helper = &zx_gl_plane_helper_funcs;
 514                 formats = gl_formats;
 515                 format_count = ARRAY_SIZE(gl_formats);
 516                 break;
 517         case DRM_PLANE_TYPE_OVERLAY:
 518                 helper = &zx_vl_plane_helper_funcs;
 519                 formats = vl_formats;
 520                 format_count = ARRAY_SIZE(vl_formats);
 521                 break;
 522         default:
 523                 return -ENODEV;
 524         }
 525
 526         ret = drm_universal_plane_init(drm, plane, VOU_CRTC_MASK,
 527                                        &zx_plane_funcs, formats, format_count,
 528                                        NULL, type, NULL);
 529         if (ret) {
 530                 DRM_DEV_ERROR(dev, "failed to init universal plane: %d\n", ret);
 531                 return ret;
 532         }
 533
 534         drm_plane_helper_add(plane, helper);
 535
 536         return 0;
 537 }