drivers/hwmon/k10temp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h
   4  *              processor hardware monitoring
   5  *
   6  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
   7  * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
   8  *
   9  * Implementation notes:
  10  * - CCD register address information as well as the calculation to
  11  *   convert raw register values is from https://github.com/ocerman/zenpower.
  12  *   The information is not confirmed from chip datasheets, but experiments
  13  *   suggest that it provides reasonable temperature values.
  14  * - Register addresses to read chip voltage and current are also from
  15  *   https://github.com/ocerman/zenpower, and not confirmed from chip
  16  *   datasheets. Current calibration is board specific and not typically
  17  *   shared by board vendors. For this reason, current values are
  18  *   normalized to report 1A/LSB for core current and and 0.25A/LSB for SoC
  19  *   current. Reported values can be adjusted using the sensors configuration
  20  *   file.
  21  */
  22
  23 #include <linux/bitops.h>
  24 #include <linux/debugfs.h>
  25 #include <linux/err.h>
  26 #include <linux/hwmon.h>
  27 #include <linux/init.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/pci_ids.h>
  31 #include <asm/amd_nb.h>
  32 #include <asm/processor.h>
  33
  34 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
  35 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  36 MODULE_LICENSE("GPL");
  37
  38 static bool force;
  39 module_param(force, bool, 0444);
  40 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
  41
  42 /* Provide lock for writing to NB_SMU_IND_ADDR */
  43 static DEFINE_MUTEX(nb_smu_ind_mutex);
  44
  45 #ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
  46 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3        0x15b3
  47 #endif
  48
  49 /* CPUID function 0x80000001, ebx */
  50 #define CPUID_PKGTYPE_MASK      GENMASK(31, 28)
  51 #define CPUID_PKGTYPE_F         0x00000000
  52 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
  53
  54 /* DRAM controller (PCI function 2) */
  55 #define REG_DCT0_CONFIG_HIGH            0x094
  56 #define  DDR3_MODE                      BIT(8)
  57
  58 /* miscellaneous (PCI function 3) */
  59 #define REG_HARDWARE_THERMAL_CONTROL    0x64
  60 #define  HTC_ENABLE                     BIT(0)
  61
  62 #define REG_REPORTED_TEMPERATURE        0xa4
  63
  64 #define REG_NORTHBRIDGE_CAPABILITIES    0xe8
  65 #define  NB_CAP_HTC                     BIT(10)
  66
  67 /*
  68  * For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL
  69  * and REG_REPORTED_TEMPERATURE have been moved to
  70  * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
  71  * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
  72  */
  73 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET     0xd8200c64
  74 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET     0xd8200ca4
  75
  76 /* F17h M01h Access througn SMN */
  77 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET     0x00059800
  78
  79 #define F17H_M70H_CCD_TEMP(x)                   (0x00059954 + ((x) * 4))
  80 #define F17H_M70H_CCD_TEMP_VALID                BIT(11)
  81 #define F17H_M70H_CCD_TEMP_MASK                 GENMASK(10, 0)
  82
  83 #define F17H_M01H_SVI                           0x0005A000
  84 #define F17H_M01H_SVI_TEL_PLANE0                (F17H_M01H_SVI + 0xc)
  85 #define F17H_M01H_SVI_TEL_PLANE1                (F17H_M01H_SVI + 0x10)
  86
  87 #define CUR_TEMP_SHIFT                          21
  88 #define CUR_TEMP_RANGE_SEL_MASK                 BIT(19)
  89
  90 #define CFACTOR_ICORE                           1000000 /* 1A / LSB     */
  91 #define CFACTOR_ISOC                            250000  /* 0.25A / LSB  */
  92
  93 struct k10temp_data {
  94         struct pci_dev *pdev;
  95         void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
  96         void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
  97         int temp_offset;
  98         u32 temp_adjust_mask;
  99         bool show_tdie;
 100         u32 show_tccd;
 101         u32 svi_addr[2];
 102         bool show_current;
 103         int cfactor[2];
 104 };
 105
 106 struct tctl_offset {
 107         u8 model;
 108         char const *id;
 109         int offset;
 110 };
 111
 112 static const struct tctl_offset tctl_offset_table[] = {
 113         { 0x17, "AMD Ryzen 5 1600X", 20000 },
 114         { 0x17, "AMD Ryzen 7 1700X", 20000 },
 115         { 0x17, "AMD Ryzen 7 1800X", 20000 },
 116         { 0x17, "AMD Ryzen 7 2700X", 10000 },
 117         { 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */
 118         { 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */
 119 };
 120
 121 static bool is_threadripper(void)
 122 {
 123         return strstr(boot_cpu_data.x86_model_id, "Threadripper");
 124 }
 125
 126 static bool is_epyc(void)
 127 {
 128         return strstr(boot_cpu_data.x86_model_id, "EPYC");
 129 }
 130
 131 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
 132 {
 133         pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
 134 }
 135
 136 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
 137 {
 138         pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
 139 }
 140
 141 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
 142                               unsigned int base, int offset, u32 *val)
 143 {
 144         mutex_lock(&nb_smu_ind_mutex);
 145         pci_bus_write_config_dword(pdev->bus, devfn,
 146                                    base, offset);
 147         pci_bus_read_config_dword(pdev->bus, devfn,
 148                                   base + 4, val);
 149         mutex_unlock(&nb_smu_ind_mutex);
 150 }
 151
 152 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 153 {
 154         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 155                           F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
 156 }
 157
 158 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
 159 {
 160         amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
 161                           F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
 162 }
 163
 164 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
 165 {
 166         amd_smn_read(amd_pci_dev_to_node_id(pdev),
 167                      F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
 168 }
 169
 170 static long get_raw_temp(struct k10temp_data *data)
 171 {
 172         u32 regval;
 173         long temp;
 174
 175         data->read_tempreg(data->pdev, &regval);
 176         temp = (regval >> CUR_TEMP_SHIFT) * 125;
 177         if (regval & data->temp_adjust_mask)
 178                 temp -= 49000;
 179         return temp;
 180 }
 181
 182 const char *k10temp_temp_label[] = {
 183         "Tdie",
 184         "Tctl",
 185         "Tccd1",
 186         "Tccd2",
 187         "Tccd3",
 188         "Tccd4",
 189         "Tccd5",
 190         "Tccd6",
 191         "Tccd7",
 192         "Tccd8",
 193 };
 194
 195 const char *k10temp_in_label[] = {
 196         "Vcore",
 197         "Vsoc",
 198 };
 199
 200 const char *k10temp_curr_label[] = {
 201         "Icore",
 202         "Isoc",
 203 };
 204
 205 static int k10temp_read_labels(struct device *dev,
 206                                enum hwmon_sensor_types type,
 207                                u32 attr, int channel, const char **str)
 208 {
 209         switch (type) {
 210         case hwmon_temp:
 211                 *str = k10temp_temp_label[channel];
 212                 break;
 213         case hwmon_in:
 214                 *str = k10temp_in_label[channel];
 215                 break;
 216         case hwmon_curr:
 217                 *str = k10temp_curr_label[channel];
 218                 break;
 219         default:
 220                 return -EOPNOTSUPP;
 221         }
 222         return 0;
 223 }
 224
 225 static int k10temp_read_curr(struct device *dev, u32 attr, int channel,
 226                              long *val)
 227 {
 228         struct k10temp_data *data = dev_get_drvdata(dev);
 229         u32 regval;
 230
 231         switch (attr) {
 232         case hwmon_curr_input:
 233                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 234                              data->svi_addr[channel], &regval);
 235                 *val = DIV_ROUND_CLOSEST(data->cfactor[channel] *
 236                                          (regval & 0xff),
 237                                          1000);
 238                 break;
 239         default:
 240                 return -EOPNOTSUPP;
 241         }
 242         return 0;
 243 }
 244
 245 static int k10temp_read_in(struct device *dev, u32 attr, int channel, long *val)
 246 {
 247         struct k10temp_data *data = dev_get_drvdata(dev);
 248         u32 regval;
 249
 250         switch (attr) {
 251         case hwmon_in_input:
 252                 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 253                              data->svi_addr[channel], &regval);
 254                 regval = (regval >> 16) & 0xff;
 255                 *val = DIV_ROUND_CLOSEST(155000 - regval * 625, 100);
 256                 break;
 257         default:
 258                 return -EOPNOTSUPP;
 259         }
 260         return 0;
 261 }
 262
 263 static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 264                              long *val)
 265 {
 266         struct k10temp_data *data = dev_get_drvdata(dev);
 267         u32 regval;
 268
 269         switch (attr) {
 270         case hwmon_temp_input:
 271                 switch (channel) {
 272                 case 0:         /* Tdie */
 273                         *val = get_raw_temp(data) - data->temp_offset;
 274                         if (*val < 0)
 275                                 *val = 0;
 276                         break;
 277                 case 1:         /* Tctl */
 278                         *val = get_raw_temp(data);
 279                         if (*val < 0)
 280                                 *val = 0;
 281                         break;
 282                 case 2 ... 9:           /* Tccd{1-8} */
 283                         amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
 284                                      F17H_M70H_CCD_TEMP(channel - 2), &regval);
 285                         *val = (regval & F17H_M70H_CCD_TEMP_MASK) * 125 - 49000;
 286                         break;
 287                 default:
 288                         return -EOPNOTSUPP;
 289                 }
 290                 break;
 291         case hwmon_temp_max:
 292                 *val = 70 * 1000;
 293                 break;
 294         case hwmon_temp_crit:
 295                 data->read_htcreg(data->pdev, &regval);
 296                 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
 297                 break;
 298         case hwmon_temp_crit_hyst:
 299                 data->read_htcreg(data->pdev, &regval);
 300                 *val = (((regval >> 16) & 0x7f)
 301                         - ((regval >> 24) & 0xf)) * 500 + 52000;
 302                 break;
 303         default:
 304                 return -EOPNOTSUPP;
 305         }
 306         return 0;
 307 }
 308
 309 static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
 310                         u32 attr, int channel, long *val)
 311 {
 312         switch (type) {
 313         case hwmon_temp:
 314                 return k10temp_read_temp(dev, attr, channel, val);
 315         case hwmon_in:
 316                 return k10temp_read_in(dev, attr, channel, val);
 317         case hwmon_curr:
 318                 return k10temp_read_curr(dev, attr, channel, val);
 319         default:
 320                 return -EOPNOTSUPP;
 321         }
 322 }
 323
 324 static umode_t k10temp_is_visible(const void *_data,
 325                                   enum hwmon_sensor_types type,
 326                                   u32 attr, int channel)
 327 {
 328         const struct k10temp_data *data = _data;
 329         struct pci_dev *pdev = data->pdev;
 330         u32 reg;
 331
 332         switch (type) {
 333         case hwmon_temp:
 334                 switch (attr) {
 335                 case hwmon_temp_input:
 336                         switch (channel) {
 337                         case 0:         /* Tdie, or Tctl if we don't show it */
 338                                 break;
 339                         case 1:         /* Tctl */
 340                                 if (!data->show_tdie)
 341                                         return 0;
 342                                 break;
 343                         case 2 ... 9:           /* Tccd{1-8} */
 344                                 if (!(data->show_tccd & BIT(channel - 2)))
 345                                         return 0;
 346                                 break;
 347                         default:
 348                                 return 0;
 349                         }
 350                         break;
 351                 case hwmon_temp_max:
 352                         if (channel || data->show_tdie)
 353                                 return 0;
 354                         break;
 355                 case hwmon_temp_crit:
 356                 case hwmon_temp_crit_hyst:
 357                         if (channel || !data->read_htcreg)
 358                                 return 0;
 359
 360                         pci_read_config_dword(pdev,
 361                                               REG_NORTHBRIDGE_CAPABILITIES,
 362                                               &reg);
 363                         if (!(reg & NB_CAP_HTC))
 364                                 return 0;
 365
 366                         data->read_htcreg(data->pdev, &reg);
 367                         if (!(reg & HTC_ENABLE))
 368                                 return 0;
 369                         break;
 370                 case hwmon_temp_label:
 371                         /* No labels if we don't show the die temperature */
 372                         if (!data->show_tdie)
 373                                 return 0;
 374                         switch (channel) {
 375                         case 0:         /* Tdie */
 376                         case 1:         /* Tctl */
 377                                 break;
 378                         case 2 ... 9:           /* Tccd{1-8} */
 379                                 if (!(data->show_tccd & BIT(channel - 2)))
 380                                         return 0;
 381                                 break;
 382                         default:
 383                                 return 0;
 384                         }
 385                         break;
 386                 default:
 387                         return 0;
 388                 }
 389                 break;
 390         case hwmon_in:
 391         case hwmon_curr:
 392                 if (!data->show_current)
 393                         return 0;
 394                 break;
 395         default:
 396                 return 0;
 397         }
 398         return 0444;
 399 }
 400
 401 static bool has_erratum_319(struct pci_dev *pdev)
 402 {
 403         u32 pkg_type, reg_dram_cfg;
 404
 405         if (boot_cpu_data.x86 != 0x10)
 406                 return false;
 407
 408         /*
 409          * Erratum 319: The thermal sensor of Socket F/AM2+ processors
 410          *              may be unreliable.
 411          */
 412         pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
 413         if (pkg_type == CPUID_PKGTYPE_F)
 414                 return true;
 415         if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
 416                 return false;
 417
 418         /* DDR3 memory implies socket AM3, which is good */
 419         pci_bus_read_config_dword(pdev->bus,
 420                                   PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
 421                                   REG_DCT0_CONFIG_HIGH, &reg_dram_cfg);
 422         if (reg_dram_cfg & DDR3_MODE)
 423                 return false;
 424
 425         /*
 426          * Unfortunately it is possible to run a socket AM3 CPU with DDR2
 427          * memory. We blacklist all the cores which do exist in socket AM2+
 428          * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
 429          * and AM3 formats, but that's the best we can do.
 430          */
 431         return boot_cpu_data.x86_model < 4 ||
 432                (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
 433 }
 434
 435 #ifdef CONFIG_DEBUG_FS
 436
 437 static void k10temp_smn_regs_show(struct seq_file *s, struct pci_dev *pdev,
 438                                   u32 addr, int count)
 439 {
 440         u32 reg;
 441         int i;
 442
 443         for (i = 0; i < count; i++) {
 444                 if (!(i & 3))
 445                         seq_printf(s, "0x%06x: ", addr + i * 4);
 446                 amd_smn_read(amd_pci_dev_to_node_id(pdev), addr + i * 4, &reg);
 447                 seq_printf(s, "%08x ", reg);
 448                 if ((i & 3) == 3)
 449                         seq_puts(s, "\n");
 450         }
 451 }
 452
 453 static int svi_show(struct seq_file *s, void *unused)
 454 {
 455         struct k10temp_data *data = s->private;
 456
 457         k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
 458         return 0;
 459 }
 460 DEFINE_SHOW_ATTRIBUTE(svi);
 461
 462 static int thm_show(struct seq_file *s, void *unused)
 463 {
 464         struct k10temp_data *data = s->private;
 465
 466         k10temp_smn_regs_show(s, data->pdev,
 467                               F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
 468         return 0;
 469 }
 470 DEFINE_SHOW_ATTRIBUTE(thm);
 471
 472 static void k10temp_debugfs_cleanup(void *ddir)
 473 {
 474         debugfs_remove_recursive(ddir);
 475 }
 476
 477 static void k10temp_init_debugfs(struct k10temp_data *data)
 478 {
 479         struct dentry *debugfs;
 480         char name[32];
 481
 482         /* Only show debugfs data for Family 17h/18h CPUs */
 483         if (!data->show_tdie)
 484                 return;
 485
 486         scnprintf(name, sizeof(name), "k10temp-%s", pci_name(data->pdev));
 487
 488         debugfs = debugfs_create_dir(name, NULL);
 489         if (debugfs) {
 490                 debugfs_create_file("svi", 0444, debugfs, data, &svi_fops);
 491                 debugfs_create_file("thm", 0444, debugfs, data, &thm_fops);
 492                 devm_add_action_or_reset(&data->pdev->dev,
 493                                          k10temp_debugfs_cleanup, debugfs);
 494         }
 495 }
 496
 497 #else
 498
 499 static void k10temp_init_debugfs(struct k10temp_data *data)
 500 {
 501 }
 502
 503 #endif
 504
 505 static const struct hwmon_channel_info *k10temp_info[] = {
 506         HWMON_CHANNEL_INFO(temp,
 507                            HWMON_T_INPUT | HWMON_T_MAX |
 508                            HWMON_T_CRIT | HWMON_T_CRIT_HYST |
 509                            HWMON_T_LABEL,
 510                            HWMON_T_INPUT | HWMON_T_LABEL,
 511                            HWMON_T_INPUT | HWMON_T_LABEL,
 512                            HWMON_T_INPUT | HWMON_T_LABEL,
 513                            HWMON_T_INPUT | HWMON_T_LABEL,
 514                            HWMON_T_INPUT | HWMON_T_LABEL,
 515                            HWMON_T_INPUT | HWMON_T_LABEL,
 516                            HWMON_T_INPUT | HWMON_T_LABEL,
 517                            HWMON_T_INPUT | HWMON_T_LABEL,
 518                            HWMON_T_INPUT | HWMON_T_LABEL),
 519         HWMON_CHANNEL_INFO(in,
 520                            HWMON_I_INPUT | HWMON_I_LABEL,
 521                            HWMON_I_INPUT | HWMON_I_LABEL),
 522         HWMON_CHANNEL_INFO(curr,
 523                            HWMON_C_INPUT | HWMON_C_LABEL,
 524                            HWMON_C_INPUT | HWMON_C_LABEL),
 525         NULL
 526 };
 527
 528 static const struct hwmon_ops k10temp_hwmon_ops = {
 529         .is_visible = k10temp_is_visible,
 530         .read = k10temp_read,
 531         .read_string = k10temp_read_labels,
 532 };
 533
 534 static const struct hwmon_chip_info k10temp_chip_info = {
 535         .ops = &k10temp_hwmon_ops,
 536         .info = k10temp_info,
 537 };
 538
 539 static void k10temp_get_ccd_support(struct pci_dev *pdev,
 540                                     struct k10temp_data *data, int limit)
 541 {
 542         u32 regval;
 543         int i;
 544
 545         for (i = 0; i < limit; i++) {
 546                 amd_smn_read(amd_pci_dev_to_node_id(pdev),
 547                              F17H_M70H_CCD_TEMP(i), &regval);
 548                 if (regval & F17H_M70H_CCD_TEMP_VALID)
 549                         data->show_tccd |= BIT(i);
 550         }
 551 }
 552
 553 static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 554 {
 555         int unreliable = has_erratum_319(pdev);
 556         struct device *dev = &pdev->dev;
 557         struct k10temp_data *data;
 558         struct device *hwmon_dev;
 559         int i;
 560
 561         if (unreliable) {
 562                 if (!force) {
 563                         dev_err(dev,
 564                                 "unreliable CPU thermal sensor; monitoring disabled\n");
 565                         return -ENODEV;
 566                 }
 567                 dev_warn(dev,
 568                          "unreliable CPU thermal sensor; check erratum 319\n");
 569         }
 570
 571         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 572         if (!data)
 573                 return -ENOMEM;
 574
 575         data->pdev = pdev;
 576
 577         if (boot_cpu_data.x86 == 0x15 &&
 578             ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
 579              (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
 580                 data->read_htcreg = read_htcreg_nb_f15;
 581                 data->read_tempreg = read_tempreg_nb_f15;
 582         } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
 583                 data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
 584                 data->read_tempreg = read_tempreg_nb_f17;
 585                 data->show_tdie = true;
 586
 587                 switch (boot_cpu_data.x86_model) {
 588                 case 0x1:       /* Zen */
 589                 case 0x8:       /* Zen+ */
 590                 case 0x11:      /* Zen APU */
 591                 case 0x18:      /* Zen+ APU */
 592                         data->show_current = !is_threadripper() && !is_epyc();
 593                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
 594                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
 595                         data->cfactor[0] = CFACTOR_ICORE;
 596                         data->cfactor[1] = CFACTOR_ISOC;
 597                         k10temp_get_ccd_support(pdev, data, 4);
 598                         break;
 599                 case 0x31:      /* Zen2 Threadripper */
 600                 case 0x71:      /* Zen2 */
 601                         data->show_current = !is_threadripper() && !is_epyc();
 602                         data->cfactor[0] = CFACTOR_ICORE;
 603                         data->cfactor[1] = CFACTOR_ISOC;
 604                         data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
 605                         data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
 606                         k10temp_get_ccd_support(pdev, data, 8);
 607                         break;
 608                 }
 609         } else {
 610                 data->read_htcreg = read_htcreg_pci;
 611                 data->read_tempreg = read_tempreg_pci;
 612         }
 613
 614         for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
 615                 const struct tctl_offset *entry = &tctl_offset_table[i];
 616
 617                 if (boot_cpu_data.x86 == entry->model &&
 618                     strstr(boot_cpu_data.x86_model_id, entry->id)) {
 619                         data->temp_offset = entry->offset;
 620                         break;
 621                 }
 622         }
 623
 624         hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
 625                                                          &k10temp_chip_info,
 626                                                          NULL);
 627         if (IS_ERR(hwmon_dev))
 628                 return PTR_ERR(hwmon_dev);
 629
 630         k10temp_init_debugfs(data);
 631
 632         return 0;
 633 }
 634
 635 static const struct pci_device_id k10temp_id_table[] = {
 636         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
 637         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
 638         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
 639         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
 640         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
 641         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
 642         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
 643         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
 644         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
 645         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
 646         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 647         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
 648         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
 649         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
 650         { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
 651         {}
 652 };
 653 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
 654
 655 static struct pci_driver k10temp_driver = {
 656         .name = "k10temp",
 657         .id_table = k10temp_id_table,
 658         .probe = k10temp_probe,
 659 };
 660
 661 module_pci_driver(k10temp_driver);