2 * nct6775 - Driver for the hardware monitoring functionality of
3 * Nuvoton NCT677x Super-I/O chips
5 * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net>
7 * Derived from w83627ehf driver
8 * Copyright (C) 2005-2012 Jean Delvare <jdelvare@suse.de>
9 * Copyright (C) 2006 Yuan Mu (Winbond),
10 * Rudolf Marek <r.marek@assembler.cz>
11 * David Hubbard <david.c.hubbard@gmail.com>
12 * Daniel J Blueman <daniel.blueman@gmail.com>
13 * Copyright (C) 2010 Sheng-Yuan Huang (Nuvoton) (PS00)
15 * Shamelessly ripped from the w83627hf driver
16 * Copyright (C) 2003 Mark Studebaker
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 * Supports the following chips:
35 * Chip #vin #fan #pwm #temp chip IDs man ID
36 * nct6106d 9 3 3 6+3 0xc450 0xc1 0x5ca3
37 * nct6775f 9 4 3 6+3 0xb470 0xc1 0x5ca3
38 * nct6776f 9 5 3 6+3 0xc330 0xc1 0x5ca3
39 * nct6779d 15 5 5 2+6 0xc560 0xc1 0x5ca3
40 * nct6791d 15 6 6 2+6 0xc800 0xc1 0x5ca3
41 * nct6792d 15 6 6 2+6 0xc910 0xc1 0x5ca3
42 * nct6793d 15 6 6 2+6 0xd120 0xc1 0x5ca3
43 * nct6795d 14 6 6 2+6 0xd350 0xc1 0x5ca3
44 * nct6796d 14 7 7 2+6 0xd420 0xc1 0x5ca3
45 * nct6797d 14 7 7 2+6 0xd450 0xc1 0x5ca3
47 * nct6798d 14 7 7 2+6 0xd458 0xc1 0x5ca3
50 * #temp lists the number of monitored temperature sources (first value) plus
51 * the number of directly connectable temperature sensors (second value).
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/module.h>
57 #include <linux/init.h>
58 #include <linux/slab.h>
59 #include <linux/jiffies.h>
60 #include <linux/platform_device.h>
61 #include <linux/hwmon.h>
62 #include <linux/hwmon-sysfs.h>
63 #include <linux/hwmon-vid.h>
64 #include <linux/err.h>
65 #include <linux/mutex.h>
66 #include <linux/acpi.h>
67 #include <linux/bitops.h>
68 #include <linux/dmi.h>
70 #include <linux/nospec.h>
75 enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793,
76 nct6795, nct6796, nct6797, nct6798 };
78 /* used to set data->name = nct6775_device_names[data->sio_kind] */
79 static const char * const nct6775_device_names[] = {
93 static const char * const nct6775_sio_names[] __initconst = {
107 static unsigned short force_id;
108 module_param(force_id, ushort, 0);
109 MODULE_PARM_DESC(force_id, "Override the detected device ID");
111 static unsigned short fan_debounce;
112 module_param(fan_debounce, ushort, 0);
113 MODULE_PARM_DESC(fan_debounce, "Enable debouncing for fan RPM signal");
115 #define DRVNAME "nct6775"
118 * Super-I/O constants and functions
121 #define NCT6775_LD_ACPI 0x0a
122 #define NCT6775_LD_HWM 0x0b
123 #define NCT6775_LD_VID 0x0d
124 #define NCT6775_LD_12 0x12
126 #define SIO_REG_LDSEL 0x07 /* Logical device select */
127 #define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
128 #define SIO_REG_ENABLE 0x30 /* Logical device enable */
129 #define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
131 #define SIO_NCT6106_ID 0xc450
132 #define SIO_NCT6775_ID 0xb470
133 #define SIO_NCT6776_ID 0xc330
134 #define SIO_NCT6779_ID 0xc560
135 #define SIO_NCT6791_ID 0xc800
136 #define SIO_NCT6792_ID 0xc910
137 #define SIO_NCT6793_ID 0xd120
138 #define SIO_NCT6795_ID 0xd350
139 #define SIO_NCT6796_ID 0xd420
140 #define SIO_NCT6797_ID 0xd450
141 #define SIO_NCT6798_ID 0xd458
142 #define SIO_ID_MASK 0xFFF8
144 enum pwm_enable { off, manual, thermal_cruise, speed_cruise, sf3, sf4 };
147 superio_outb(int ioreg, int reg, int val)
150 outb(val, ioreg + 1);
154 superio_inb(int ioreg, int reg)
157 return inb(ioreg + 1);
161 superio_select(int ioreg, int ld)
163 outb(SIO_REG_LDSEL, ioreg);
168 superio_enter(int ioreg)
171 * Try to reserve <ioreg> and <ioreg + 1> for exclusive access.
173 if (!request_muxed_region(ioreg, 2, DRVNAME))
183 superio_exit(int ioreg)
187 outb(0x02, ioreg + 1);
188 release_region(ioreg, 2);
195 #define IOREGION_ALIGNMENT (~7)
196 #define IOREGION_OFFSET 5
197 #define IOREGION_LENGTH 2
198 #define ADDR_REG_OFFSET 0
199 #define DATA_REG_OFFSET 1
201 #define NCT6775_REG_BANK 0x4E
202 #define NCT6775_REG_CONFIG 0x40
205 * Not currently used:
206 * REG_MAN_ID has the value 0x5ca3 for all supported chips.
207 * REG_CHIP_ID == 0x88/0xa1/0xc1 depending on chip model.
208 * REG_MAN_ID is at port 0x4f
209 * REG_CHIP_ID is at port 0x58
212 #define NUM_TEMP 10 /* Max number of temp attribute sets w/ limits*/
213 #define NUM_TEMP_FIXED 6 /* Max number of fixed temp attribute sets */
215 #define NUM_REG_ALARM 7 /* Max number of alarm registers */
216 #define NUM_REG_BEEP 5 /* Max number of beep registers */
220 /* Common and NCT6775 specific data */
222 /* Voltage min/max registers for nr=7..14 are in bank 5 */
224 static const u16 NCT6775_REG_IN_MAX[] = {
225 0x2b, 0x2d, 0x2f, 0x31, 0x33, 0x35, 0x37, 0x554, 0x556, 0x558, 0x55a,
226 0x55c, 0x55e, 0x560, 0x562 };
227 static const u16 NCT6775_REG_IN_MIN[] = {
228 0x2c, 0x2e, 0x30, 0x32, 0x34, 0x36, 0x38, 0x555, 0x557, 0x559, 0x55b,
229 0x55d, 0x55f, 0x561, 0x563 };
230 static const u16 NCT6775_REG_IN[] = {
231 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x550, 0x551, 0x552
234 #define NCT6775_REG_VBAT 0x5D
235 #define NCT6775_REG_DIODE 0x5E
236 #define NCT6775_DIODE_MASK 0x02
238 #define NCT6775_REG_FANDIV1 0x506
239 #define NCT6775_REG_FANDIV2 0x507
241 #define NCT6775_REG_CR_FAN_DEBOUNCE 0xf0
243 static const u16 NCT6775_REG_ALARM[NUM_REG_ALARM] = { 0x459, 0x45A, 0x45B };
245 /* 0..15 voltages, 16..23 fans, 24..29 temperatures, 30..31 intrusion */
247 static const s8 NCT6775_ALARM_BITS[] = {
248 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
249 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
251 6, 7, 11, -1, -1, /* fan1..fan5 */
252 -1, -1, -1, /* unused */
253 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
254 12, -1 }; /* intrusion0, intrusion1 */
256 #define FAN_ALARM_BASE 16
257 #define TEMP_ALARM_BASE 24
258 #define INTRUSION_ALARM_BASE 30
260 static const u16 NCT6775_REG_BEEP[NUM_REG_BEEP] = { 0x56, 0x57, 0x453, 0x4e };
263 * 0..14 voltages, 15 global beep enable, 16..23 fans, 24..29 temperatures,
266 static const s8 NCT6775_BEEP_BITS[] = {
267 0, 1, 2, 3, 8, 9, 10, 16, /* in0.. in7 */
268 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
269 21, /* global beep enable */
270 6, 7, 11, 28, -1, /* fan1..fan5 */
271 -1, -1, -1, /* unused */
272 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
273 12, -1 }; /* intrusion0, intrusion1 */
275 #define BEEP_ENABLE_BASE 15
277 static const u8 NCT6775_REG_CR_CASEOPEN_CLR[] = { 0xe6, 0xee };
278 static const u8 NCT6775_CR_CASEOPEN_CLR_MASK[] = { 0x20, 0x01 };
280 /* DC or PWM output fan configuration */
281 static const u8 NCT6775_REG_PWM_MODE[] = { 0x04, 0x04, 0x12 };
282 static const u8 NCT6775_PWM_MODE_MASK[] = { 0x01, 0x02, 0x01 };
284 /* Advanced Fan control, some values are common for all fans */
286 static const u16 NCT6775_REG_TARGET[] = {
287 0x101, 0x201, 0x301, 0x801, 0x901, 0xa01, 0xb01 };
288 static const u16 NCT6775_REG_FAN_MODE[] = {
289 0x102, 0x202, 0x302, 0x802, 0x902, 0xa02, 0xb02 };
290 static const u16 NCT6775_REG_FAN_STEP_DOWN_TIME[] = {
291 0x103, 0x203, 0x303, 0x803, 0x903, 0xa03, 0xb03 };
292 static const u16 NCT6775_REG_FAN_STEP_UP_TIME[] = {
293 0x104, 0x204, 0x304, 0x804, 0x904, 0xa04, 0xb04 };
294 static const u16 NCT6775_REG_FAN_STOP_OUTPUT[] = {
295 0x105, 0x205, 0x305, 0x805, 0x905, 0xa05, 0xb05 };
296 static const u16 NCT6775_REG_FAN_START_OUTPUT[] = {
297 0x106, 0x206, 0x306, 0x806, 0x906, 0xa06, 0xb06 };
298 static const u16 NCT6775_REG_FAN_MAX_OUTPUT[] = { 0x10a, 0x20a, 0x30a };
299 static const u16 NCT6775_REG_FAN_STEP_OUTPUT[] = { 0x10b, 0x20b, 0x30b };
301 static const u16 NCT6775_REG_FAN_STOP_TIME[] = {
302 0x107, 0x207, 0x307, 0x807, 0x907, 0xa07, 0xb07 };
303 static const u16 NCT6775_REG_PWM[] = {
304 0x109, 0x209, 0x309, 0x809, 0x909, 0xa09, 0xb09 };
305 static const u16 NCT6775_REG_PWM_READ[] = {
306 0x01, 0x03, 0x11, 0x13, 0x15, 0xa09, 0xb09 };
308 static const u16 NCT6775_REG_FAN[] = { 0x630, 0x632, 0x634, 0x636, 0x638 };
309 static const u16 NCT6775_REG_FAN_MIN[] = { 0x3b, 0x3c, 0x3d };
310 static const u16 NCT6775_REG_FAN_PULSES[NUM_FAN] = {
311 0x641, 0x642, 0x643, 0x644 };
312 static const u16 NCT6775_FAN_PULSE_SHIFT[NUM_FAN] = { };
314 static const u16 NCT6775_REG_TEMP[] = {
315 0x27, 0x150, 0x250, 0x62b, 0x62c, 0x62d };
317 static const u16 NCT6775_REG_TEMP_MON[] = { 0x73, 0x75, 0x77 };
319 static const u16 NCT6775_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
320 0, 0x152, 0x252, 0x628, 0x629, 0x62A };
321 static const u16 NCT6775_REG_TEMP_HYST[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
322 0x3a, 0x153, 0x253, 0x673, 0x678, 0x67D };
323 static const u16 NCT6775_REG_TEMP_OVER[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
324 0x39, 0x155, 0x255, 0x672, 0x677, 0x67C };
326 static const u16 NCT6775_REG_TEMP_SOURCE[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
327 0x621, 0x622, 0x623, 0x624, 0x625, 0x626 };
329 static const u16 NCT6775_REG_TEMP_SEL[] = {
330 0x100, 0x200, 0x300, 0x800, 0x900, 0xa00, 0xb00 };
332 static const u16 NCT6775_REG_WEIGHT_TEMP_SEL[] = {
333 0x139, 0x239, 0x339, 0x839, 0x939, 0xa39 };
334 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP[] = {
335 0x13a, 0x23a, 0x33a, 0x83a, 0x93a, 0xa3a };
336 static const u16 NCT6775_REG_WEIGHT_TEMP_STEP_TOL[] = {
337 0x13b, 0x23b, 0x33b, 0x83b, 0x93b, 0xa3b };
338 static const u16 NCT6775_REG_WEIGHT_DUTY_STEP[] = {
339 0x13c, 0x23c, 0x33c, 0x83c, 0x93c, 0xa3c };
340 static const u16 NCT6775_REG_WEIGHT_TEMP_BASE[] = {
341 0x13d, 0x23d, 0x33d, 0x83d, 0x93d, 0xa3d };
343 static const u16 NCT6775_REG_TEMP_OFFSET[] = { 0x454, 0x455, 0x456 };
345 static const u16 NCT6775_REG_AUTO_TEMP[] = {
346 0x121, 0x221, 0x321, 0x821, 0x921, 0xa21, 0xb21 };
347 static const u16 NCT6775_REG_AUTO_PWM[] = {
348 0x127, 0x227, 0x327, 0x827, 0x927, 0xa27, 0xb27 };
350 #define NCT6775_AUTO_TEMP(data, nr, p) ((data)->REG_AUTO_TEMP[nr] + (p))
351 #define NCT6775_AUTO_PWM(data, nr, p) ((data)->REG_AUTO_PWM[nr] + (p))
353 static const u16 NCT6775_REG_CRITICAL_ENAB[] = { 0x134, 0x234, 0x334 };
355 static const u16 NCT6775_REG_CRITICAL_TEMP[] = {
356 0x135, 0x235, 0x335, 0x835, 0x935, 0xa35, 0xb35 };
357 static const u16 NCT6775_REG_CRITICAL_TEMP_TOLERANCE[] = {
358 0x138, 0x238, 0x338, 0x838, 0x938, 0xa38, 0xb38 };
360 static const char *const nct6775_temp_label[] = {
374 "PCH_CHIP_CPU_MAX_TEMP",
384 #define NCT6775_TEMP_MASK 0x001ffffe
385 #define NCT6775_VIRT_TEMP_MASK 0x00000000
387 static const u16 NCT6775_REG_TEMP_ALTERNATE[32] = {
393 static const u16 NCT6775_REG_TEMP_CRIT[32] = {
404 /* NCT6776 specific data */
406 /* STEP_UP_TIME and STEP_DOWN_TIME regs are swapped for all chips but NCT6775 */
407 #define NCT6776_REG_FAN_STEP_UP_TIME NCT6775_REG_FAN_STEP_DOWN_TIME
408 #define NCT6776_REG_FAN_STEP_DOWN_TIME NCT6775_REG_FAN_STEP_UP_TIME
410 static const s8 NCT6776_ALARM_BITS[] = {
411 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
412 17, -1, -1, -1, -1, -1, -1, /* in8..in14 */
414 6, 7, 11, 10, 23, /* fan1..fan5 */
415 -1, -1, -1, /* unused */
416 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
417 12, 9 }; /* intrusion0, intrusion1 */
419 static const u16 NCT6776_REG_BEEP[NUM_REG_BEEP] = { 0xb2, 0xb3, 0xb4, 0xb5 };
421 static const s8 NCT6776_BEEP_BITS[] = {
422 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
423 8, -1, -1, -1, -1, -1, -1, /* in8..in14 */
424 24, /* global beep enable */
425 25, 26, 27, 28, 29, /* fan1..fan5 */
426 -1, -1, -1, /* unused */
427 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
428 30, 31 }; /* intrusion0, intrusion1 */
430 static const u16 NCT6776_REG_TOLERANCE_H[] = {
431 0x10c, 0x20c, 0x30c, 0x80c, 0x90c, 0xa0c, 0xb0c };
433 static const u8 NCT6776_REG_PWM_MODE[] = { 0x04, 0, 0, 0, 0, 0 };
434 static const u8 NCT6776_PWM_MODE_MASK[] = { 0x01, 0, 0, 0, 0, 0 };
436 static const u16 NCT6776_REG_FAN_MIN[] = {
437 0x63a, 0x63c, 0x63e, 0x640, 0x642, 0x64a, 0x64c };
438 static const u16 NCT6776_REG_FAN_PULSES[NUM_FAN] = {
439 0x644, 0x645, 0x646, 0x647, 0x648, 0x649 };
441 static const u16 NCT6776_REG_WEIGHT_DUTY_BASE[] = {
442 0x13e, 0x23e, 0x33e, 0x83e, 0x93e, 0xa3e };
444 static const u16 NCT6776_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6775_REG_TEMP)] = {
445 0x18, 0x152, 0x252, 0x628, 0x629, 0x62A };
447 static const char *const nct6776_temp_label[] = {
462 "PCH_CHIP_CPU_MAX_TEMP",
473 #define NCT6776_TEMP_MASK 0x007ffffe
474 #define NCT6776_VIRT_TEMP_MASK 0x00000000
476 static const u16 NCT6776_REG_TEMP_ALTERNATE[32] = {
482 static const u16 NCT6776_REG_TEMP_CRIT[32] = {
487 /* NCT6779 specific data */
489 static const u16 NCT6779_REG_IN[] = {
490 0x480, 0x481, 0x482, 0x483, 0x484, 0x485, 0x486, 0x487,
491 0x488, 0x489, 0x48a, 0x48b, 0x48c, 0x48d, 0x48e };
493 static const u16 NCT6779_REG_ALARM[NUM_REG_ALARM] = {
494 0x459, 0x45A, 0x45B, 0x568 };
496 static const s8 NCT6779_ALARM_BITS[] = {
497 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
498 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
500 6, 7, 11, 10, 23, /* fan1..fan5 */
501 -1, -1, -1, /* unused */
502 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
503 12, 9 }; /* intrusion0, intrusion1 */
505 static const s8 NCT6779_BEEP_BITS[] = {
506 0, 1, 2, 3, 4, 5, 6, 7, /* in0.. in7 */
507 8, 9, 10, 11, 12, 13, 14, /* in8..in14 */
508 24, /* global beep enable */
509 25, 26, 27, 28, 29, /* fan1..fan5 */
510 -1, -1, -1, /* unused */
511 16, 17, -1, -1, -1, -1, /* temp1..temp6 */
512 30, 31 }; /* intrusion0, intrusion1 */
514 static const u16 NCT6779_REG_FAN[] = {
515 0x4c0, 0x4c2, 0x4c4, 0x4c6, 0x4c8, 0x4ca, 0x4ce };
516 static const u16 NCT6779_REG_FAN_PULSES[NUM_FAN] = {
517 0x644, 0x645, 0x646, 0x647, 0x648, 0x649, 0x64f };
519 static const u16 NCT6779_REG_CRITICAL_PWM_ENABLE[] = {
520 0x136, 0x236, 0x336, 0x836, 0x936, 0xa36, 0xb36 };
521 #define NCT6779_CRITICAL_PWM_ENABLE_MASK 0x01
522 static const u16 NCT6779_REG_CRITICAL_PWM[] = {
523 0x137, 0x237, 0x337, 0x837, 0x937, 0xa37, 0xb37 };
525 static const u16 NCT6779_REG_TEMP[] = { 0x27, 0x150 };
526 static const u16 NCT6779_REG_TEMP_MON[] = { 0x73, 0x75, 0x77, 0x79, 0x7b };
527 static const u16 NCT6779_REG_TEMP_CONFIG[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
529 static const u16 NCT6779_REG_TEMP_HYST[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
531 static const u16 NCT6779_REG_TEMP_OVER[ARRAY_SIZE(NCT6779_REG_TEMP)] = {
534 static const u16 NCT6779_REG_TEMP_OFFSET[] = {
535 0x454, 0x455, 0x456, 0x44a, 0x44b, 0x44c };
537 static const char *const nct6779_temp_label[] = {
556 "PCH_CHIP_CPU_MAX_TEMP",
572 #define NCT6779_TEMP_MASK 0x07ffff7e
573 #define NCT6779_VIRT_TEMP_MASK 0x00000000
574 #define NCT6791_TEMP_MASK 0x87ffff7e
575 #define NCT6791_VIRT_TEMP_MASK 0x80000000
577 static const u16 NCT6779_REG_TEMP_ALTERNATE[32]
578 = { 0x490, 0x491, 0x492, 0x493, 0x494, 0x495, 0, 0,
579 0, 0, 0, 0, 0, 0, 0, 0,
580 0, 0x400, 0x401, 0x402, 0x404, 0x405, 0x406, 0x407,
583 static const u16 NCT6779_REG_TEMP_CRIT[32] = {
588 /* NCT6791 specific data */
590 #define NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE 0x28
592 static const u16 NCT6791_REG_WEIGHT_TEMP_SEL[NUM_FAN] = { 0, 0x239 };
593 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP[NUM_FAN] = { 0, 0x23a };
594 static const u16 NCT6791_REG_WEIGHT_TEMP_STEP_TOL[NUM_FAN] = { 0, 0x23b };
595 static const u16 NCT6791_REG_WEIGHT_DUTY_STEP[NUM_FAN] = { 0, 0x23c };
596 static const u16 NCT6791_REG_WEIGHT_TEMP_BASE[NUM_FAN] = { 0, 0x23d };
597 static const u16 NCT6791_REG_WEIGHT_DUTY_BASE[NUM_FAN] = { 0, 0x23e };
599 static const u16 NCT6791_REG_ALARM[NUM_REG_ALARM] = {
600 0x459, 0x45A, 0x45B, 0x568, 0x45D };
602 static const s8 NCT6791_ALARM_BITS[] = {
603 0, 1, 2, 3, 8, 21, 20, 16, /* in0.. in7 */
604 17, 24, 25, 26, 27, 28, 29, /* in8..in14 */
606 6, 7, 11, 10, 23, 33, /* fan1..fan6 */
608 4, 5, 13, -1, -1, -1, /* temp1..temp6 */
609 12, 9 }; /* intrusion0, intrusion1 */
611 /* NCT6792/NCT6793 specific data */
613 static const u16 NCT6792_REG_TEMP_MON[] = {
614 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d };
615 static const u16 NCT6792_REG_BEEP[NUM_REG_BEEP] = {
616 0xb2, 0xb3, 0xb4, 0xb5, 0xbf };
618 static const char *const nct6792_temp_label[] = {
637 "PCH_CHIP_CPU_MAX_TEMP",
646 "PECI Agent 0 Calibration",
647 "PECI Agent 1 Calibration",
653 #define NCT6792_TEMP_MASK 0x9fffff7e
654 #define NCT6792_VIRT_TEMP_MASK 0x80000000
656 static const char *const nct6793_temp_label[] = {
675 "PCH_CHIP_CPU_MAX_TEMP",
685 "PECI Agent 0 Calibration",
686 "PECI Agent 1 Calibration",
691 #define NCT6793_TEMP_MASK 0xbfff037e
692 #define NCT6793_VIRT_TEMP_MASK 0x80000000
694 static const char *const nct6795_temp_label[] = {
713 "PCH_CHIP_CPU_MAX_TEMP",
723 "PECI Agent 0 Calibration",
724 "PECI Agent 1 Calibration",
729 #define NCT6795_TEMP_MASK 0xbfffff7e
730 #define NCT6795_VIRT_TEMP_MASK 0x80000000
732 static const char *const nct6796_temp_label[] = {
751 "PCH_CHIP_CPU_MAX_TEMP",
761 "PECI Agent 0 Calibration",
762 "PECI Agent 1 Calibration",
767 #define NCT6796_TEMP_MASK 0xbfff0ffe
768 #define NCT6796_VIRT_TEMP_MASK 0x80000c00
770 static const char *const nct6798_temp_label[] = {
789 "PCH_CHIP_CPU_MAX_TEMP",
805 #define NCT6798_TEMP_MASK 0x8fff0ffe
806 #define NCT6798_VIRT_TEMP_MASK 0x80000c00
808 /* NCT6102D/NCT6106D specific data */
810 #define NCT6106_REG_VBAT 0x318
811 #define NCT6106_REG_DIODE 0x319
812 #define NCT6106_DIODE_MASK 0x01
814 static const u16 NCT6106_REG_IN_MAX[] = {
815 0x90, 0x92, 0x94, 0x96, 0x98, 0x9a, 0x9e, 0xa0, 0xa2 };
816 static const u16 NCT6106_REG_IN_MIN[] = {
817 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9f, 0xa1, 0xa3 };
818 static const u16 NCT6106_REG_IN[] = {
819 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x07, 0x08, 0x09 };
821 static const u16 NCT6106_REG_TEMP[] = { 0x10, 0x11, 0x12, 0x13, 0x14, 0x15 };
822 static const u16 NCT6106_REG_TEMP_MON[] = { 0x18, 0x19, 0x1a };
823 static const u16 NCT6106_REG_TEMP_HYST[] = {
824 0xc3, 0xc7, 0xcb, 0xcf, 0xd3, 0xd7 };
825 static const u16 NCT6106_REG_TEMP_OVER[] = {
826 0xc2, 0xc6, 0xca, 0xce, 0xd2, 0xd6 };
827 static const u16 NCT6106_REG_TEMP_CRIT_L[] = {
828 0xc0, 0xc4, 0xc8, 0xcc, 0xd0, 0xd4 };
829 static const u16 NCT6106_REG_TEMP_CRIT_H[] = {
830 0xc1, 0xc5, 0xc9, 0xcf, 0xd1, 0xd5 };
831 static const u16 NCT6106_REG_TEMP_OFFSET[] = { 0x311, 0x312, 0x313 };
832 static const u16 NCT6106_REG_TEMP_CONFIG[] = {
833 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc };
835 static const u16 NCT6106_REG_FAN[] = { 0x20, 0x22, 0x24 };
836 static const u16 NCT6106_REG_FAN_MIN[] = { 0xe0, 0xe2, 0xe4 };
837 static const u16 NCT6106_REG_FAN_PULSES[] = { 0xf6, 0xf6, 0xf6 };
838 static const u16 NCT6106_FAN_PULSE_SHIFT[] = { 0, 2, 4 };
840 static const u8 NCT6106_REG_PWM_MODE[] = { 0xf3, 0xf3, 0xf3 };
841 static const u8 NCT6106_PWM_MODE_MASK[] = { 0x01, 0x02, 0x04 };
842 static const u16 NCT6106_REG_PWM[] = { 0x119, 0x129, 0x139 };
843 static const u16 NCT6106_REG_PWM_READ[] = { 0x4a, 0x4b, 0x4c };
844 static const u16 NCT6106_REG_FAN_MODE[] = { 0x113, 0x123, 0x133 };
845 static const u16 NCT6106_REG_TEMP_SEL[] = { 0x110, 0x120, 0x130 };
846 static const u16 NCT6106_REG_TEMP_SOURCE[] = {
847 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5 };
849 static const u16 NCT6106_REG_CRITICAL_TEMP[] = { 0x11a, 0x12a, 0x13a };
850 static const u16 NCT6106_REG_CRITICAL_TEMP_TOLERANCE[] = {
851 0x11b, 0x12b, 0x13b };
853 static const u16 NCT6106_REG_CRITICAL_PWM_ENABLE[] = { 0x11c, 0x12c, 0x13c };
854 #define NCT6106_CRITICAL_PWM_ENABLE_MASK 0x10
855 static const u16 NCT6106_REG_CRITICAL_PWM[] = { 0x11d, 0x12d, 0x13d };
857 static const u16 NCT6106_REG_FAN_STEP_UP_TIME[] = { 0x114, 0x124, 0x134 };
858 static const u16 NCT6106_REG_FAN_STEP_DOWN_TIME[] = { 0x115, 0x125, 0x135 };
859 static const u16 NCT6106_REG_FAN_STOP_OUTPUT[] = { 0x116, 0x126, 0x136 };
860 static const u16 NCT6106_REG_FAN_START_OUTPUT[] = { 0x117, 0x127, 0x137 };
861 static const u16 NCT6106_REG_FAN_STOP_TIME[] = { 0x118, 0x128, 0x138 };
862 static const u16 NCT6106_REG_TOLERANCE_H[] = { 0x112, 0x122, 0x132 };
864 static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 };
866 static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 };
867 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 };
868 static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a };
869 static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c };
870 static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c };
871 static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d };
873 static const u16 NCT6106_REG_AUTO_TEMP[] = { 0x160, 0x170, 0x180 };
874 static const u16 NCT6106_REG_AUTO_PWM[] = { 0x164, 0x174, 0x184 };
876 static const u16 NCT6106_REG_ALARM[NUM_REG_ALARM] = {
877 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d };
879 static const s8 NCT6106_ALARM_BITS[] = {
880 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
881 9, -1, -1, -1, -1, -1, -1, /* in8..in14 */
883 32, 33, 34, -1, -1, /* fan1..fan5 */
884 -1, -1, -1, /* unused */
885 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
886 48, -1 /* intrusion0, intrusion1 */
889 static const u16 NCT6106_REG_BEEP[NUM_REG_BEEP] = {
890 0x3c0, 0x3c1, 0x3c2, 0x3c3, 0x3c4 };
892 static const s8 NCT6106_BEEP_BITS[] = {
893 0, 1, 2, 3, 4, 5, 7, 8, /* in0.. in7 */
894 9, 10, 11, 12, -1, -1, -1, /* in8..in14 */
895 32, /* global beep enable */
896 24, 25, 26, 27, 28, /* fan1..fan5 */
897 -1, -1, -1, /* unused */
898 16, 17, 18, 19, 20, 21, /* temp1..temp6 */
899 34, -1 /* intrusion0, intrusion1 */
902 static const u16 NCT6106_REG_TEMP_ALTERNATE[32] = {
908 static const u16 NCT6106_REG_TEMP_CRIT[32] = {
913 static enum pwm_enable reg_to_pwm_enable(int pwm, int mode)
915 if (mode == 0 && pwm == 255)
920 static int pwm_enable_to_reg(enum pwm_enable mode)
931 /* 1 is DC mode, output in ms */
932 static unsigned int step_time_from_reg(u8 reg, u8 mode)
934 return mode ? 400 * reg : 100 * reg;
937 static u8 step_time_to_reg(unsigned int msec, u8 mode)
939 return clamp_val((mode ? (msec + 200) / 400 :
940 (msec + 50) / 100), 1, 255);
943 static unsigned int fan_from_reg8(u16 reg, unsigned int divreg)
945 if (reg == 0 || reg == 255)
947 return 1350000U / (reg << divreg);
950 static unsigned int fan_from_reg13(u16 reg, unsigned int divreg)
952 if ((reg & 0xff1f) == 0xff1f)
955 reg = (reg & 0x1f) | ((reg & 0xff00) >> 3);
960 return 1350000U / reg;
963 static unsigned int fan_from_reg16(u16 reg, unsigned int divreg)
965 if (reg == 0 || reg == 0xffff)
969 * Even though the registers are 16 bit wide, the fan divisor
972 return 1350000U / (reg << divreg);
975 static unsigned int fan_from_reg_rpm(u16 reg, unsigned int divreg)
980 static u16 fan_to_reg(u32 fan, unsigned int divreg)
985 return (1350000U / fan) >> divreg;
988 static inline unsigned int
995 * Some of the voltage inputs have internal scaling, the tables below
996 * contain 8 (the ADC LSB in mV) * scaling factor * 100
998 static const u16 scale_in[15] = {
999 800, 800, 1600, 1600, 800, 800, 800, 1600, 1600, 800, 800, 800, 800,
1003 static inline long in_from_reg(u8 reg, u8 nr)
1005 return DIV_ROUND_CLOSEST(reg * scale_in[nr], 100);
1008 static inline u8 in_to_reg(u32 val, u8 nr)
1010 return clamp_val(DIV_ROUND_CLOSEST(val * 100, scale_in[nr]), 0, 255);
1014 * Data structures and manipulation thereof
1017 struct nct6775_data {
1018 int addr; /* IO base of hw monitor block */
1019 int sioreg; /* SIO register address */
1023 const struct attribute_group *groups[6];
1025 u16 reg_temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1026 * 3=temp_crit, 4=temp_lcrit
1028 u8 temp_src[NUM_TEMP];
1029 u16 reg_temp_config[NUM_TEMP];
1030 const char * const *temp_label;
1039 const s8 *ALARM_BITS;
1040 const s8 *BEEP_BITS;
1043 const u16 *REG_IN_MINMAX[2];
1045 const u16 *REG_TARGET;
1047 const u16 *REG_FAN_MODE;
1048 const u16 *REG_FAN_MIN;
1049 const u16 *REG_FAN_PULSES;
1050 const u16 *FAN_PULSE_SHIFT;
1051 const u16 *REG_FAN_TIME[3];
1053 const u16 *REG_TOLERANCE_H;
1055 const u8 *REG_PWM_MODE;
1056 const u8 *PWM_MODE_MASK;
1058 const u16 *REG_PWM[7]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1059 * [3]=pwm_max, [4]=pwm_step,
1060 * [5]=weight_duty_step, [6]=weight_duty_base
1062 const u16 *REG_PWM_READ;
1064 const u16 *REG_CRITICAL_PWM_ENABLE;
1065 u8 CRITICAL_PWM_ENABLE_MASK;
1066 const u16 *REG_CRITICAL_PWM;
1068 const u16 *REG_AUTO_TEMP;
1069 const u16 *REG_AUTO_PWM;
1071 const u16 *REG_CRITICAL_TEMP;
1072 const u16 *REG_CRITICAL_TEMP_TOLERANCE;
1074 const u16 *REG_TEMP_SOURCE; /* temp register sources */
1075 const u16 *REG_TEMP_SEL;
1076 const u16 *REG_WEIGHT_TEMP_SEL;
1077 const u16 *REG_WEIGHT_TEMP[3]; /* 0=base, 1=tolerance, 2=step */
1079 const u16 *REG_TEMP_OFFSET;
1081 const u16 *REG_ALARM;
1082 const u16 *REG_BEEP;
1084 unsigned int (*fan_from_reg)(u16 reg, unsigned int divreg);
1085 unsigned int (*fan_from_reg_min)(u16 reg, unsigned int divreg);
1087 struct mutex update_lock;
1088 bool valid; /* true if following fields are valid */
1089 unsigned long last_updated; /* In jiffies */
1091 /* Register values */
1092 u8 bank; /* current register bank */
1093 u8 in_num; /* number of in inputs we have */
1094 u8 in[15][3]; /* [0]=in, [1]=in_max, [2]=in_min */
1095 unsigned int rpm[NUM_FAN];
1096 u16 fan_min[NUM_FAN];
1097 u8 fan_pulses[NUM_FAN];
1098 u8 fan_div[NUM_FAN];
1100 u8 has_fan; /* some fan inputs can be disabled */
1101 u8 has_fan_min; /* some fans don't have min register */
1104 u8 num_temp_alarms; /* 2, 3, or 6 */
1105 u8 num_temp_beeps; /* 2, 3, or 6 */
1106 u8 temp_fixed_num; /* 3 or 6 */
1107 u8 temp_type[NUM_TEMP_FIXED];
1108 s8 temp_offset[NUM_TEMP_FIXED];
1109 s16 temp[5][NUM_TEMP]; /* 0=temp, 1=temp_over, 2=temp_hyst,
1110 * 3=temp_crit, 4=temp_lcrit */
1114 u8 pwm_num; /* number of pwm */
1115 u8 pwm_mode[NUM_FAN]; /* 0->DC variable voltage,
1116 * 1->PWM variable duty cycle
1118 enum pwm_enable pwm_enable[NUM_FAN];
1121 * 2->thermal cruise mode (also called SmartFan I)
1122 * 3->fan speed cruise mode
1124 * 5->enhanced variable thermal cruise (SmartFan IV)
1126 u8 pwm[7][NUM_FAN]; /* [0]=pwm, [1]=pwm_start, [2]=pwm_floor,
1127 * [3]=pwm_max, [4]=pwm_step,
1128 * [5]=weight_duty_step, [6]=weight_duty_base
1131 u8 target_temp[NUM_FAN];
1132 u8 target_temp_mask;
1133 u32 target_speed[NUM_FAN];
1134 u32 target_speed_tolerance[NUM_FAN];
1135 u8 speed_tolerance_limit;
1137 u8 temp_tolerance[2][NUM_FAN];
1140 u8 fan_time[3][NUM_FAN]; /* 0 = stop_time, 1 = step_up, 2 = step_down */
1142 /* Automatic fan speed control registers */
1144 u8 auto_pwm[NUM_FAN][7];
1145 u8 auto_temp[NUM_FAN][7];
1146 u8 pwm_temp_sel[NUM_FAN];
1147 u8 pwm_weight_temp_sel[NUM_FAN];
1148 u8 weight_temp[3][NUM_FAN]; /* 0->temp_step, 1->temp_step_tol,
1158 u16 have_temp_fixed;
1161 /* Remember extra register values over suspend/resume */
1168 struct nct6775_sio_data {
1173 struct sensor_device_template {
1174 struct device_attribute dev_attr;
1182 bool s2; /* true if both index and nr are used */
1185 struct sensor_device_attr_u {
1187 struct sensor_device_attribute a1;
1188 struct sensor_device_attribute_2 a2;
1193 #define __TEMPLATE_ATTR(_template, _mode, _show, _store) { \
1194 .attr = {.name = _template, .mode = _mode }, \
1199 #define SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, _index) \
1200 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1201 .u.index = _index, \
1204 #define SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1206 { .dev_attr = __TEMPLATE_ATTR(_template, _mode, _show, _store), \
1207 .u.s.index = _index, \
1211 #define SENSOR_TEMPLATE(_name, _template, _mode, _show, _store, _index) \
1212 static struct sensor_device_template sensor_dev_template_##_name \
1213 = SENSOR_DEVICE_TEMPLATE(_template, _mode, _show, _store, \
1216 #define SENSOR_TEMPLATE_2(_name, _template, _mode, _show, _store, \
1218 static struct sensor_device_template sensor_dev_template_##_name \
1219 = SENSOR_DEVICE_TEMPLATE_2(_template, _mode, _show, _store, \
1222 struct sensor_template_group {
1223 struct sensor_device_template **templates;
1224 umode_t (*is_visible)(struct kobject *, struct attribute *, int);
1228 static struct attribute_group *
1229 nct6775_create_attr_group(struct device *dev,
1230 const struct sensor_template_group *tg,
1233 struct attribute_group *group;
1234 struct sensor_device_attr_u *su;
1235 struct sensor_device_attribute *a;
1236 struct sensor_device_attribute_2 *a2;
1237 struct attribute **attrs;
1238 struct sensor_device_template **t;
1242 return ERR_PTR(-EINVAL);
1245 for (count = 0; *t; t++, count++)
1249 return ERR_PTR(-EINVAL);
1251 group = devm_kzalloc(dev, sizeof(*group), GFP_KERNEL);
1253 return ERR_PTR(-ENOMEM);
1255 attrs = devm_kcalloc(dev, repeat * count + 1, sizeof(*attrs),
1258 return ERR_PTR(-ENOMEM);
1260 su = devm_kzalloc(dev, array3_size(repeat, count, sizeof(*su)),
1263 return ERR_PTR(-ENOMEM);
1265 group->attrs = attrs;
1266 group->is_visible = tg->is_visible;
1268 for (i = 0; i < repeat; i++) {
1270 while (*t != NULL) {
1271 snprintf(su->name, sizeof(su->name),
1272 (*t)->dev_attr.attr.name, tg->base + i);
1275 sysfs_attr_init(&a2->dev_attr.attr);
1276 a2->dev_attr.attr.name = su->name;
1277 a2->nr = (*t)->u.s.nr + i;
1278 a2->index = (*t)->u.s.index;
1279 a2->dev_attr.attr.mode =
1280 (*t)->dev_attr.attr.mode;
1281 a2->dev_attr.show = (*t)->dev_attr.show;
1282 a2->dev_attr.store = (*t)->dev_attr.store;
1283 *attrs = &a2->dev_attr.attr;
1286 sysfs_attr_init(&a->dev_attr.attr);
1287 a->dev_attr.attr.name = su->name;
1288 a->index = (*t)->u.index + i;
1289 a->dev_attr.attr.mode =
1290 (*t)->dev_attr.attr.mode;
1291 a->dev_attr.show = (*t)->dev_attr.show;
1292 a->dev_attr.store = (*t)->dev_attr.store;
1293 *attrs = &a->dev_attr.attr;
1304 static bool is_word_sized(struct nct6775_data *data, u16 reg)
1306 switch (data->kind) {
1308 return reg == 0x20 || reg == 0x22 || reg == 0x24 ||
1309 reg == 0xe0 || reg == 0xe2 || reg == 0xe4 ||
1310 reg == 0x111 || reg == 0x121 || reg == 0x131;
1312 return (((reg & 0xff00) == 0x100 ||
1313 (reg & 0xff00) == 0x200) &&
1314 ((reg & 0x00ff) == 0x50 ||
1315 (reg & 0x00ff) == 0x53 ||
1316 (reg & 0x00ff) == 0x55)) ||
1317 (reg & 0xfff0) == 0x630 ||
1318 reg == 0x640 || reg == 0x642 ||
1320 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1321 reg == 0x73 || reg == 0x75 || reg == 0x77;
1323 return (((reg & 0xff00) == 0x100 ||
1324 (reg & 0xff00) == 0x200) &&
1325 ((reg & 0x00ff) == 0x50 ||
1326 (reg & 0x00ff) == 0x53 ||
1327 (reg & 0x00ff) == 0x55)) ||
1328 (reg & 0xfff0) == 0x630 ||
1330 reg == 0x640 || reg == 0x642 ||
1331 ((reg & 0xfff0) == 0x650 && (reg & 0x000f) >= 0x06) ||
1332 reg == 0x73 || reg == 0x75 || reg == 0x77;
1341 return reg == 0x150 || reg == 0x153 || reg == 0x155 ||
1342 (reg & 0xfff0) == 0x4c0 ||
1344 reg == 0x63a || reg == 0x63c || reg == 0x63e ||
1345 reg == 0x640 || reg == 0x642 || reg == 0x64a ||
1347 reg == 0x73 || reg == 0x75 || reg == 0x77 || reg == 0x79 ||
1348 reg == 0x7b || reg == 0x7d;
1354 * On older chips, only registers 0x50-0x5f are banked.
1355 * On more recent chips, all registers are banked.
1356 * Assume that is the case and set the bank number for each access.
1357 * Cache the bank number so it only needs to be set if it changes.
1359 static inline void nct6775_set_bank(struct nct6775_data *data, u16 reg)
1363 if (data->bank != bank) {
1364 outb_p(NCT6775_REG_BANK, data->addr + ADDR_REG_OFFSET);
1365 outb_p(bank, data->addr + DATA_REG_OFFSET);
1370 static u16 nct6775_read_value(struct nct6775_data *data, u16 reg)
1372 int res, word_sized = is_word_sized(data, reg);
1374 nct6775_set_bank(data, reg);
1375 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1376 res = inb_p(data->addr + DATA_REG_OFFSET);
1378 outb_p((reg & 0xff) + 1,
1379 data->addr + ADDR_REG_OFFSET);
1380 res = (res << 8) + inb_p(data->addr + DATA_REG_OFFSET);
1385 static int nct6775_write_value(struct nct6775_data *data, u16 reg, u16 value)
1387 int word_sized = is_word_sized(data, reg);
1389 nct6775_set_bank(data, reg);
1390 outb_p(reg & 0xff, data->addr + ADDR_REG_OFFSET);
1392 outb_p(value >> 8, data->addr + DATA_REG_OFFSET);
1393 outb_p((reg & 0xff) + 1,
1394 data->addr + ADDR_REG_OFFSET);
1396 outb_p(value & 0xff, data->addr + DATA_REG_OFFSET);
1400 /* We left-align 8-bit temperature values to make the code simpler */
1401 static u16 nct6775_read_temp(struct nct6775_data *data, u16 reg)
1405 res = nct6775_read_value(data, reg);
1406 if (!is_word_sized(data, reg))
1412 static int nct6775_write_temp(struct nct6775_data *data, u16 reg, u16 value)
1414 if (!is_word_sized(data, reg))
1416 return nct6775_write_value(data, reg, value);
1419 /* This function assumes that the caller holds data->update_lock */
1420 static void nct6775_write_fan_div(struct nct6775_data *data, int nr)
1426 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x70)
1427 | (data->fan_div[0] & 0x7);
1428 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1431 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV1) & 0x7)
1432 | ((data->fan_div[1] << 4) & 0x70);
1433 nct6775_write_value(data, NCT6775_REG_FANDIV1, reg);
1436 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x70)
1437 | (data->fan_div[2] & 0x7);
1438 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1441 reg = (nct6775_read_value(data, NCT6775_REG_FANDIV2) & 0x7)
1442 | ((data->fan_div[3] << 4) & 0x70);
1443 nct6775_write_value(data, NCT6775_REG_FANDIV2, reg);
1448 static void nct6775_write_fan_div_common(struct nct6775_data *data, int nr)
1450 if (data->kind == nct6775)
1451 nct6775_write_fan_div(data, nr);
1454 static void nct6775_update_fan_div(struct nct6775_data *data)
1458 i = nct6775_read_value(data, NCT6775_REG_FANDIV1);
1459 data->fan_div[0] = i & 0x7;
1460 data->fan_div[1] = (i & 0x70) >> 4;
1461 i = nct6775_read_value(data, NCT6775_REG_FANDIV2);
1462 data->fan_div[2] = i & 0x7;
1463 if (data->has_fan & BIT(3))
1464 data->fan_div[3] = (i & 0x70) >> 4;
1467 static void nct6775_update_fan_div_common(struct nct6775_data *data)
1469 if (data->kind == nct6775)
1470 nct6775_update_fan_div(data);
1473 static void nct6775_init_fan_div(struct nct6775_data *data)
1477 nct6775_update_fan_div_common(data);
1479 * For all fans, start with highest divider value if the divider
1480 * register is not initialized. This ensures that we get a
1481 * reading from the fan count register, even if it is not optimal.
1482 * We'll compute a better divider later on.
1484 for (i = 0; i < ARRAY_SIZE(data->fan_div); i++) {
1485 if (!(data->has_fan & BIT(i)))
1487 if (data->fan_div[i] == 0) {
1488 data->fan_div[i] = 7;
1489 nct6775_write_fan_div_common(data, i);
1494 static void nct6775_init_fan_common(struct device *dev,
1495 struct nct6775_data *data)
1500 if (data->has_fan_div)
1501 nct6775_init_fan_div(data);
1504 * If fan_min is not set (0), set it to 0xff to disable it. This
1505 * prevents the unnecessary warning when fanX_min is reported as 0.
1507 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
1508 if (data->has_fan_min & BIT(i)) {
1509 reg = nct6775_read_value(data, data->REG_FAN_MIN[i]);
1511 nct6775_write_value(data, data->REG_FAN_MIN[i],
1512 data->has_fan_div ? 0xff
1518 static void nct6775_select_fan_div(struct device *dev,
1519 struct nct6775_data *data, int nr, u16 reg)
1521 u8 fan_div = data->fan_div[nr];
1524 if (!data->has_fan_div)
1528 * If we failed to measure the fan speed, or the reported value is not
1529 * in the optimal range, and the clock divider can be modified,
1530 * let's try that for next time.
1532 if (reg == 0x00 && fan_div < 0x07)
1534 else if (reg != 0x00 && reg < 0x30 && fan_div > 0)
1537 if (fan_div != data->fan_div[nr]) {
1538 dev_dbg(dev, "Modifying fan%d clock divider from %u to %u\n",
1539 nr + 1, div_from_reg(data->fan_div[nr]),
1540 div_from_reg(fan_div));
1542 /* Preserve min limit if possible */
1543 if (data->has_fan_min & BIT(nr)) {
1544 fan_min = data->fan_min[nr];
1545 if (fan_div > data->fan_div[nr]) {
1546 if (fan_min != 255 && fan_min > 1)
1549 if (fan_min != 255) {
1555 if (fan_min != data->fan_min[nr]) {
1556 data->fan_min[nr] = fan_min;
1557 nct6775_write_value(data, data->REG_FAN_MIN[nr],
1561 data->fan_div[nr] = fan_div;
1562 nct6775_write_fan_div_common(data, nr);
1566 static void nct6775_update_pwm(struct device *dev)
1568 struct nct6775_data *data = dev_get_drvdata(dev);
1570 int fanmodecfg, reg;
1573 for (i = 0; i < data->pwm_num; i++) {
1574 if (!(data->has_pwm & BIT(i)))
1577 duty_is_dc = data->REG_PWM_MODE[i] &&
1578 (nct6775_read_value(data, data->REG_PWM_MODE[i])
1579 & data->PWM_MODE_MASK[i]);
1580 data->pwm_mode[i] = !duty_is_dc;
1582 fanmodecfg = nct6775_read_value(data, data->REG_FAN_MODE[i]);
1583 for (j = 0; j < ARRAY_SIZE(data->REG_PWM); j++) {
1584 if (data->REG_PWM[j] && data->REG_PWM[j][i]) {
1586 = nct6775_read_value(data,
1587 data->REG_PWM[j][i]);
1591 data->pwm_enable[i] = reg_to_pwm_enable(data->pwm[0][i],
1592 (fanmodecfg >> 4) & 7);
1594 if (!data->temp_tolerance[0][i] ||
1595 data->pwm_enable[i] != speed_cruise)
1596 data->temp_tolerance[0][i] = fanmodecfg & 0x0f;
1597 if (!data->target_speed_tolerance[i] ||
1598 data->pwm_enable[i] == speed_cruise) {
1599 u8 t = fanmodecfg & 0x0f;
1601 if (data->REG_TOLERANCE_H) {
1602 t |= (nct6775_read_value(data,
1603 data->REG_TOLERANCE_H[i]) & 0x70) >> 1;
1605 data->target_speed_tolerance[i] = t;
1608 data->temp_tolerance[1][i] =
1609 nct6775_read_value(data,
1610 data->REG_CRITICAL_TEMP_TOLERANCE[i]);
1612 reg = nct6775_read_value(data, data->REG_TEMP_SEL[i]);
1613 data->pwm_temp_sel[i] = reg & 0x1f;
1614 /* If fan can stop, report floor as 0 */
1616 data->pwm[2][i] = 0;
1618 if (!data->REG_WEIGHT_TEMP_SEL[i])
1621 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[i]);
1622 data->pwm_weight_temp_sel[i] = reg & 0x1f;
1623 /* If weight is disabled, report weight source as 0 */
1625 data->pwm_weight_temp_sel[i] = 0;
1627 /* Weight temp data */
1628 for (j = 0; j < ARRAY_SIZE(data->weight_temp); j++) {
1629 data->weight_temp[j][i]
1630 = nct6775_read_value(data,
1631 data->REG_WEIGHT_TEMP[j][i]);
1636 static void nct6775_update_pwm_limits(struct device *dev)
1638 struct nct6775_data *data = dev_get_drvdata(dev);
1643 for (i = 0; i < data->pwm_num; i++) {
1644 if (!(data->has_pwm & BIT(i)))
1647 for (j = 0; j < ARRAY_SIZE(data->fan_time); j++) {
1648 data->fan_time[j][i] =
1649 nct6775_read_value(data, data->REG_FAN_TIME[j][i]);
1652 reg_t = nct6775_read_value(data, data->REG_TARGET[i]);
1653 /* Update only in matching mode or if never updated */
1654 if (!data->target_temp[i] ||
1655 data->pwm_enable[i] == thermal_cruise)
1656 data->target_temp[i] = reg_t & data->target_temp_mask;
1657 if (!data->target_speed[i] ||
1658 data->pwm_enable[i] == speed_cruise) {
1659 if (data->REG_TOLERANCE_H) {
1660 reg_t |= (nct6775_read_value(data,
1661 data->REG_TOLERANCE_H[i]) & 0x0f) << 8;
1663 data->target_speed[i] = reg_t;
1666 for (j = 0; j < data->auto_pwm_num; j++) {
1667 data->auto_pwm[i][j] =
1668 nct6775_read_value(data,
1669 NCT6775_AUTO_PWM(data, i, j));
1670 data->auto_temp[i][j] =
1671 nct6775_read_value(data,
1672 NCT6775_AUTO_TEMP(data, i, j));
1675 /* critical auto_pwm temperature data */
1676 data->auto_temp[i][data->auto_pwm_num] =
1677 nct6775_read_value(data, data->REG_CRITICAL_TEMP[i]);
1679 switch (data->kind) {
1681 reg = nct6775_read_value(data,
1682 NCT6775_REG_CRITICAL_ENAB[i]);
1683 data->auto_pwm[i][data->auto_pwm_num] =
1684 (reg & 0x02) ? 0xff : 0x00;
1687 data->auto_pwm[i][data->auto_pwm_num] = 0xff;
1698 reg = nct6775_read_value(data,
1699 data->REG_CRITICAL_PWM_ENABLE[i]);
1700 if (reg & data->CRITICAL_PWM_ENABLE_MASK)
1701 reg = nct6775_read_value(data,
1702 data->REG_CRITICAL_PWM[i]);
1705 data->auto_pwm[i][data->auto_pwm_num] = reg;
1711 static struct nct6775_data *nct6775_update_device(struct device *dev)
1713 struct nct6775_data *data = dev_get_drvdata(dev);
1716 mutex_lock(&data->update_lock);
1718 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1720 /* Fan clock dividers */
1721 nct6775_update_fan_div_common(data);
1723 /* Measured voltages and limits */
1724 for (i = 0; i < data->in_num; i++) {
1725 if (!(data->have_in & BIT(i)))
1728 data->in[i][0] = nct6775_read_value(data,
1730 data->in[i][1] = nct6775_read_value(data,
1731 data->REG_IN_MINMAX[0][i]);
1732 data->in[i][2] = nct6775_read_value(data,
1733 data->REG_IN_MINMAX[1][i]);
1736 /* Measured fan speeds and limits */
1737 for (i = 0; i < ARRAY_SIZE(data->rpm); i++) {
1740 if (!(data->has_fan & BIT(i)))
1743 reg = nct6775_read_value(data, data->REG_FAN[i]);
1744 data->rpm[i] = data->fan_from_reg(reg,
1747 if (data->has_fan_min & BIT(i))
1748 data->fan_min[i] = nct6775_read_value(data,
1749 data->REG_FAN_MIN[i]);
1751 if (data->REG_FAN_PULSES[i]) {
1752 data->fan_pulses[i] =
1753 (nct6775_read_value(data,
1754 data->REG_FAN_PULSES[i])
1755 >> data->FAN_PULSE_SHIFT[i]) & 0x03;
1758 nct6775_select_fan_div(dev, data, i, reg);
1761 nct6775_update_pwm(dev);
1762 nct6775_update_pwm_limits(dev);
1764 /* Measured temperatures and limits */
1765 for (i = 0; i < NUM_TEMP; i++) {
1766 if (!(data->have_temp & BIT(i)))
1768 for (j = 0; j < ARRAY_SIZE(data->reg_temp); j++) {
1769 if (data->reg_temp[j][i])
1771 = nct6775_read_temp(data,
1772 data->reg_temp[j][i]);
1774 if (i >= NUM_TEMP_FIXED ||
1775 !(data->have_temp_fixed & BIT(i)))
1777 data->temp_offset[i]
1778 = nct6775_read_value(data, data->REG_TEMP_OFFSET[i]);
1782 for (i = 0; i < NUM_REG_ALARM; i++) {
1785 if (!data->REG_ALARM[i])
1787 alarm = nct6775_read_value(data, data->REG_ALARM[i]);
1788 data->alarms |= ((u64)alarm) << (i << 3);
1792 for (i = 0; i < NUM_REG_BEEP; i++) {
1795 if (!data->REG_BEEP[i])
1797 beep = nct6775_read_value(data, data->REG_BEEP[i]);
1798 data->beeps |= ((u64)beep) << (i << 3);
1801 data->last_updated = jiffies;
1805 mutex_unlock(&data->update_lock);
1810 * Sysfs callback functions
1813 show_in_reg(struct device *dev, struct device_attribute *attr, char *buf)
1815 struct nct6775_data *data = nct6775_update_device(dev);
1816 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1817 int index = sattr->index;
1820 return sprintf(buf, "%ld\n", in_from_reg(data->in[nr][index], nr));
1824 store_in_reg(struct device *dev, struct device_attribute *attr, const char *buf,
1827 struct nct6775_data *data = dev_get_drvdata(dev);
1828 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1829 int index = sattr->index;
1834 err = kstrtoul(buf, 10, &val);
1837 mutex_lock(&data->update_lock);
1838 data->in[nr][index] = in_to_reg(val, nr);
1839 nct6775_write_value(data, data->REG_IN_MINMAX[index - 1][nr],
1840 data->in[nr][index]);
1841 mutex_unlock(&data->update_lock);
1846 show_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1848 struct nct6775_data *data = nct6775_update_device(dev);
1849 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1850 int nr = data->ALARM_BITS[sattr->index];
1852 return sprintf(buf, "%u\n",
1853 (unsigned int)((data->alarms >> nr) & 0x01));
1856 static int find_temp_source(struct nct6775_data *data, int index, int count)
1858 int source = data->temp_src[index];
1861 for (nr = 0; nr < count; nr++) {
1864 src = nct6775_read_value(data,
1865 data->REG_TEMP_SOURCE[nr]) & 0x1f;
1873 show_temp_alarm(struct device *dev, struct device_attribute *attr, char *buf)
1875 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1876 struct nct6775_data *data = nct6775_update_device(dev);
1877 unsigned int alarm = 0;
1881 * For temperatures, there is no fixed mapping from registers to alarm
1882 * bits. Alarm bits are determined by the temperature source mapping.
1884 nr = find_temp_source(data, sattr->index, data->num_temp_alarms);
1886 int bit = data->ALARM_BITS[nr + TEMP_ALARM_BASE];
1888 alarm = (data->alarms >> bit) & 0x01;
1890 return sprintf(buf, "%u\n", alarm);
1894 show_beep(struct device *dev, struct device_attribute *attr, char *buf)
1896 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1897 struct nct6775_data *data = nct6775_update_device(dev);
1898 int nr = data->BEEP_BITS[sattr->index];
1900 return sprintf(buf, "%u\n",
1901 (unsigned int)((data->beeps >> nr) & 0x01));
1905 store_beep(struct device *dev, struct device_attribute *attr, const char *buf,
1908 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1909 struct nct6775_data *data = dev_get_drvdata(dev);
1910 int nr = data->BEEP_BITS[sattr->index];
1911 int regindex = nr >> 3;
1915 err = kstrtoul(buf, 10, &val);
1921 mutex_lock(&data->update_lock);
1923 data->beeps |= (1ULL << nr);
1925 data->beeps &= ~(1ULL << nr);
1926 nct6775_write_value(data, data->REG_BEEP[regindex],
1927 (data->beeps >> (regindex << 3)) & 0xff);
1928 mutex_unlock(&data->update_lock);
1933 show_temp_beep(struct device *dev, struct device_attribute *attr, char *buf)
1935 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
1936 struct nct6775_data *data = nct6775_update_device(dev);
1937 unsigned int beep = 0;
1941 * For temperatures, there is no fixed mapping from registers to beep
1942 * enable bits. Beep enable bits are determined by the temperature
1945 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1947 int bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1949 beep = (data->beeps >> bit) & 0x01;
1951 return sprintf(buf, "%u\n", beep);
1955 store_temp_beep(struct device *dev, struct device_attribute *attr,
1956 const char *buf, size_t count)
1958 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1959 struct nct6775_data *data = dev_get_drvdata(dev);
1960 int nr, bit, regindex;
1964 err = kstrtoul(buf, 10, &val);
1970 nr = find_temp_source(data, sattr->index, data->num_temp_beeps);
1974 bit = data->BEEP_BITS[nr + TEMP_ALARM_BASE];
1975 regindex = bit >> 3;
1977 mutex_lock(&data->update_lock);
1979 data->beeps |= (1ULL << bit);
1981 data->beeps &= ~(1ULL << bit);
1982 nct6775_write_value(data, data->REG_BEEP[regindex],
1983 (data->beeps >> (regindex << 3)) & 0xff);
1984 mutex_unlock(&data->update_lock);
1989 static umode_t nct6775_in_is_visible(struct kobject *kobj,
1990 struct attribute *attr, int index)
1992 struct device *dev = container_of(kobj, struct device, kobj);
1993 struct nct6775_data *data = dev_get_drvdata(dev);
1994 int in = index / 5; /* voltage index */
1996 if (!(data->have_in & BIT(in)))
2002 SENSOR_TEMPLATE_2(in_input, "in%d_input", S_IRUGO, show_in_reg, NULL, 0, 0);
2003 SENSOR_TEMPLATE(in_alarm, "in%d_alarm", S_IRUGO, show_alarm, NULL, 0);
2004 SENSOR_TEMPLATE(in_beep, "in%d_beep", S_IWUSR | S_IRUGO, show_beep, store_beep,
2006 SENSOR_TEMPLATE_2(in_min, "in%d_min", S_IWUSR | S_IRUGO, show_in_reg,
2007 store_in_reg, 0, 1);
2008 SENSOR_TEMPLATE_2(in_max, "in%d_max", S_IWUSR | S_IRUGO, show_in_reg,
2009 store_in_reg, 0, 2);
2012 * nct6775_in_is_visible uses the index into the following array
2013 * to determine if attributes should be created or not.
2014 * Any change in order or content must be matched.
2016 static struct sensor_device_template *nct6775_attributes_in_template[] = {
2017 &sensor_dev_template_in_input,
2018 &sensor_dev_template_in_alarm,
2019 &sensor_dev_template_in_beep,
2020 &sensor_dev_template_in_min,
2021 &sensor_dev_template_in_max,
2025 static const struct sensor_template_group nct6775_in_template_group = {
2026 .templates = nct6775_attributes_in_template,
2027 .is_visible = nct6775_in_is_visible,
2031 show_fan(struct device *dev, struct device_attribute *attr, char *buf)
2033 struct nct6775_data *data = nct6775_update_device(dev);
2034 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2035 int nr = sattr->index;
2037 return sprintf(buf, "%d\n", data->rpm[nr]);
2041 show_fan_min(struct device *dev, struct device_attribute *attr, char *buf)
2043 struct nct6775_data *data = nct6775_update_device(dev);
2044 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2045 int nr = sattr->index;
2047 return sprintf(buf, "%d\n",
2048 data->fan_from_reg_min(data->fan_min[nr],
2049 data->fan_div[nr]));
2053 show_fan_div(struct device *dev, struct device_attribute *attr, char *buf)
2055 struct nct6775_data *data = nct6775_update_device(dev);
2056 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2057 int nr = sattr->index;
2059 return sprintf(buf, "%u\n", div_from_reg(data->fan_div[nr]));
2063 store_fan_min(struct device *dev, struct device_attribute *attr,
2064 const char *buf, size_t count)
2066 struct nct6775_data *data = dev_get_drvdata(dev);
2067 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2068 int nr = sattr->index;
2074 err = kstrtoul(buf, 10, &val);
2078 mutex_lock(&data->update_lock);
2079 if (!data->has_fan_div) {
2080 /* NCT6776F or NCT6779D; we know this is a 13 bit register */
2086 val = 1350000U / val;
2087 val = (val & 0x1f) | ((val << 3) & 0xff00);
2089 data->fan_min[nr] = val;
2090 goto write_min; /* Leave fan divider alone */
2093 /* No min limit, alarm disabled */
2094 data->fan_min[nr] = 255;
2095 new_div = data->fan_div[nr]; /* No change */
2096 dev_info(dev, "fan%u low limit and alarm disabled\n", nr + 1);
2099 reg = 1350000U / val;
2100 if (reg >= 128 * 255) {
2102 * Speed below this value cannot possibly be represented,
2103 * even with the highest divider (128)
2105 data->fan_min[nr] = 254;
2106 new_div = 7; /* 128 == BIT(7) */
2108 "fan%u low limit %lu below minimum %u, set to minimum\n",
2109 nr + 1, val, data->fan_from_reg_min(254, 7));
2112 * Speed above this value cannot possibly be represented,
2113 * even with the lowest divider (1)
2115 data->fan_min[nr] = 1;
2116 new_div = 0; /* 1 == BIT(0) */
2118 "fan%u low limit %lu above maximum %u, set to maximum\n",
2119 nr + 1, val, data->fan_from_reg_min(1, 0));
2122 * Automatically pick the best divider, i.e. the one such
2123 * that the min limit will correspond to a register value
2124 * in the 96..192 range
2127 while (reg > 192 && new_div < 7) {
2131 data->fan_min[nr] = reg;
2136 * Write both the fan clock divider (if it changed) and the new
2137 * fan min (unconditionally)
2139 if (new_div != data->fan_div[nr]) {
2140 dev_dbg(dev, "fan%u clock divider changed from %u to %u\n",
2141 nr + 1, div_from_reg(data->fan_div[nr]),
2142 div_from_reg(new_div));
2143 data->fan_div[nr] = new_div;
2144 nct6775_write_fan_div_common(data, nr);
2145 /* Give the chip time to sample a new speed value */
2146 data->last_updated = jiffies;
2150 nct6775_write_value(data, data->REG_FAN_MIN[nr], data->fan_min[nr]);
2151 mutex_unlock(&data->update_lock);
2157 show_fan_pulses(struct device *dev, struct device_attribute *attr, char *buf)
2159 struct nct6775_data *data = nct6775_update_device(dev);
2160 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2161 int p = data->fan_pulses[sattr->index];
2163 return sprintf(buf, "%d\n", p ? : 4);
2167 store_fan_pulses(struct device *dev, struct device_attribute *attr,
2168 const char *buf, size_t count)
2170 struct nct6775_data *data = dev_get_drvdata(dev);
2171 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2172 int nr = sattr->index;
2177 err = kstrtoul(buf, 10, &val);
2184 mutex_lock(&data->update_lock);
2185 data->fan_pulses[nr] = val & 3;
2186 reg = nct6775_read_value(data, data->REG_FAN_PULSES[nr]);
2187 reg &= ~(0x03 << data->FAN_PULSE_SHIFT[nr]);
2188 reg |= (val & 3) << data->FAN_PULSE_SHIFT[nr];
2189 nct6775_write_value(data, data->REG_FAN_PULSES[nr], reg);
2190 mutex_unlock(&data->update_lock);
2195 static umode_t nct6775_fan_is_visible(struct kobject *kobj,
2196 struct attribute *attr, int index)
2198 struct device *dev = container_of(kobj, struct device, kobj);
2199 struct nct6775_data *data = dev_get_drvdata(dev);
2200 int fan = index / 6; /* fan index */
2201 int nr = index % 6; /* attribute index */
2203 if (!(data->has_fan & BIT(fan)))
2206 if (nr == 1 && data->ALARM_BITS[FAN_ALARM_BASE + fan] == -1)
2208 if (nr == 2 && data->BEEP_BITS[FAN_ALARM_BASE + fan] == -1)
2210 if (nr == 3 && !data->REG_FAN_PULSES[fan])
2212 if (nr == 4 && !(data->has_fan_min & BIT(fan)))
2214 if (nr == 5 && data->kind != nct6775)
2220 SENSOR_TEMPLATE(fan_input, "fan%d_input", S_IRUGO, show_fan, NULL, 0);
2221 SENSOR_TEMPLATE(fan_alarm, "fan%d_alarm", S_IRUGO, show_alarm, NULL,
2223 SENSOR_TEMPLATE(fan_beep, "fan%d_beep", S_IWUSR | S_IRUGO, show_beep,
2224 store_beep, FAN_ALARM_BASE);
2225 SENSOR_TEMPLATE(fan_pulses, "fan%d_pulses", S_IWUSR | S_IRUGO, show_fan_pulses,
2226 store_fan_pulses, 0);
2227 SENSOR_TEMPLATE(fan_min, "fan%d_min", S_IWUSR | S_IRUGO, show_fan_min,
2229 SENSOR_TEMPLATE(fan_div, "fan%d_div", S_IRUGO, show_fan_div, NULL, 0);
2232 * nct6775_fan_is_visible uses the index into the following array
2233 * to determine if attributes should be created or not.
2234 * Any change in order or content must be matched.
2236 static struct sensor_device_template *nct6775_attributes_fan_template[] = {
2237 &sensor_dev_template_fan_input,
2238 &sensor_dev_template_fan_alarm, /* 1 */
2239 &sensor_dev_template_fan_beep, /* 2 */
2240 &sensor_dev_template_fan_pulses,
2241 &sensor_dev_template_fan_min, /* 4 */
2242 &sensor_dev_template_fan_div, /* 5 */
2246 static const struct sensor_template_group nct6775_fan_template_group = {
2247 .templates = nct6775_attributes_fan_template,
2248 .is_visible = nct6775_fan_is_visible,
2253 show_temp_label(struct device *dev, struct device_attribute *attr, char *buf)
2255 struct nct6775_data *data = nct6775_update_device(dev);
2256 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2257 int nr = sattr->index;
2259 return sprintf(buf, "%s\n", data->temp_label[data->temp_src[nr]]);
2263 show_temp(struct device *dev, struct device_attribute *attr, char *buf)
2265 struct nct6775_data *data = nct6775_update_device(dev);
2266 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2268 int index = sattr->index;
2270 return sprintf(buf, "%d\n", LM75_TEMP_FROM_REG(data->temp[index][nr]));
2274 store_temp(struct device *dev, struct device_attribute *attr, const char *buf,
2277 struct nct6775_data *data = dev_get_drvdata(dev);
2278 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2280 int index = sattr->index;
2284 err = kstrtol(buf, 10, &val);
2288 mutex_lock(&data->update_lock);
2289 data->temp[index][nr] = LM75_TEMP_TO_REG(val);
2290 nct6775_write_temp(data, data->reg_temp[index][nr],
2291 data->temp[index][nr]);
2292 mutex_unlock(&data->update_lock);
2297 show_temp_offset(struct device *dev, struct device_attribute *attr, char *buf)
2299 struct nct6775_data *data = nct6775_update_device(dev);
2300 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2302 return sprintf(buf, "%d\n", data->temp_offset[sattr->index] * 1000);
2306 store_temp_offset(struct device *dev, struct device_attribute *attr,
2307 const char *buf, size_t count)
2309 struct nct6775_data *data = dev_get_drvdata(dev);
2310 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2311 int nr = sattr->index;
2315 err = kstrtol(buf, 10, &val);
2319 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), -128, 127);
2321 mutex_lock(&data->update_lock);
2322 data->temp_offset[nr] = val;
2323 nct6775_write_value(data, data->REG_TEMP_OFFSET[nr], val);
2324 mutex_unlock(&data->update_lock);
2330 show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
2332 struct nct6775_data *data = nct6775_update_device(dev);
2333 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2334 int nr = sattr->index;
2336 return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
2340 store_temp_type(struct device *dev, struct device_attribute *attr,
2341 const char *buf, size_t count)
2343 struct nct6775_data *data = nct6775_update_device(dev);
2344 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2345 int nr = sattr->index;
2348 u8 vbat, diode, vbit, dbit;
2350 err = kstrtoul(buf, 10, &val);
2354 if (val != 1 && val != 3 && val != 4)
2357 mutex_lock(&data->update_lock);
2359 data->temp_type[nr] = val;
2361 dbit = data->DIODE_MASK << nr;
2362 vbat = nct6775_read_value(data, data->REG_VBAT) & ~vbit;
2363 diode = nct6775_read_value(data, data->REG_DIODE) & ~dbit;
2365 case 1: /* CPU diode (diode, current mode) */
2369 case 3: /* diode, voltage mode */
2372 case 4: /* thermistor */
2375 nct6775_write_value(data, data->REG_VBAT, vbat);
2376 nct6775_write_value(data, data->REG_DIODE, diode);
2378 mutex_unlock(&data->update_lock);
2382 static umode_t nct6775_temp_is_visible(struct kobject *kobj,
2383 struct attribute *attr, int index)
2385 struct device *dev = container_of(kobj, struct device, kobj);
2386 struct nct6775_data *data = dev_get_drvdata(dev);
2387 int temp = index / 10; /* temp index */
2388 int nr = index % 10; /* attribute index */
2390 if (!(data->have_temp & BIT(temp)))
2393 if (nr == 1 && !data->temp_label)
2396 if (nr == 2 && find_temp_source(data, temp, data->num_temp_alarms) < 0)
2397 return 0; /* alarm */
2399 if (nr == 3 && find_temp_source(data, temp, data->num_temp_beeps) < 0)
2400 return 0; /* beep */
2402 if (nr == 4 && !data->reg_temp[1][temp]) /* max */
2405 if (nr == 5 && !data->reg_temp[2][temp]) /* max_hyst */
2408 if (nr == 6 && !data->reg_temp[3][temp]) /* crit */
2411 if (nr == 7 && !data->reg_temp[4][temp]) /* lcrit */
2414 /* offset and type only apply to fixed sensors */
2415 if (nr > 7 && !(data->have_temp_fixed & BIT(temp)))
2421 SENSOR_TEMPLATE_2(temp_input, "temp%d_input", S_IRUGO, show_temp, NULL, 0, 0);
2422 SENSOR_TEMPLATE(temp_label, "temp%d_label", S_IRUGO, show_temp_label, NULL, 0);
2423 SENSOR_TEMPLATE_2(temp_max, "temp%d_max", S_IRUGO | S_IWUSR, show_temp,
2425 SENSOR_TEMPLATE_2(temp_max_hyst, "temp%d_max_hyst", S_IRUGO | S_IWUSR,
2426 show_temp, store_temp, 0, 2);
2427 SENSOR_TEMPLATE_2(temp_crit, "temp%d_crit", S_IRUGO | S_IWUSR, show_temp,
2429 SENSOR_TEMPLATE_2(temp_lcrit, "temp%d_lcrit", S_IRUGO | S_IWUSR, show_temp,
2431 SENSOR_TEMPLATE(temp_offset, "temp%d_offset", S_IRUGO | S_IWUSR,
2432 show_temp_offset, store_temp_offset, 0);
2433 SENSOR_TEMPLATE(temp_type, "temp%d_type", S_IRUGO | S_IWUSR, show_temp_type,
2434 store_temp_type, 0);
2435 SENSOR_TEMPLATE(temp_alarm, "temp%d_alarm", S_IRUGO, show_temp_alarm, NULL, 0);
2436 SENSOR_TEMPLATE(temp_beep, "temp%d_beep", S_IRUGO | S_IWUSR, show_temp_beep,
2437 store_temp_beep, 0);
2440 * nct6775_temp_is_visible uses the index into the following array
2441 * to determine if attributes should be created or not.
2442 * Any change in order or content must be matched.
2444 static struct sensor_device_template *nct6775_attributes_temp_template[] = {
2445 &sensor_dev_template_temp_input,
2446 &sensor_dev_template_temp_label,
2447 &sensor_dev_template_temp_alarm, /* 2 */
2448 &sensor_dev_template_temp_beep, /* 3 */
2449 &sensor_dev_template_temp_max, /* 4 */
2450 &sensor_dev_template_temp_max_hyst, /* 5 */
2451 &sensor_dev_template_temp_crit, /* 6 */
2452 &sensor_dev_template_temp_lcrit, /* 7 */
2453 &sensor_dev_template_temp_offset, /* 8 */
2454 &sensor_dev_template_temp_type, /* 9 */
2458 static const struct sensor_template_group nct6775_temp_template_group = {
2459 .templates = nct6775_attributes_temp_template,
2460 .is_visible = nct6775_temp_is_visible,
2465 show_pwm_mode(struct device *dev, struct device_attribute *attr, char *buf)
2467 struct nct6775_data *data = nct6775_update_device(dev);
2468 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2470 return sprintf(buf, "%d\n", data->pwm_mode[sattr->index]);
2474 store_pwm_mode(struct device *dev, struct device_attribute *attr,
2475 const char *buf, size_t count)
2477 struct nct6775_data *data = dev_get_drvdata(dev);
2478 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2479 int nr = sattr->index;
2484 err = kstrtoul(buf, 10, &val);
2491 /* Setting DC mode (0) is not supported for all chips/channels */
2492 if (data->REG_PWM_MODE[nr] == 0) {
2498 mutex_lock(&data->update_lock);
2499 data->pwm_mode[nr] = val;
2500 reg = nct6775_read_value(data, data->REG_PWM_MODE[nr]);
2501 reg &= ~data->PWM_MODE_MASK[nr];
2503 reg |= data->PWM_MODE_MASK[nr];
2504 nct6775_write_value(data, data->REG_PWM_MODE[nr], reg);
2505 mutex_unlock(&data->update_lock);
2510 show_pwm(struct device *dev, struct device_attribute *attr, char *buf)
2512 struct nct6775_data *data = nct6775_update_device(dev);
2513 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2515 int index = sattr->index;
2519 * For automatic fan control modes, show current pwm readings.
2520 * Otherwise, show the configured value.
2522 if (index == 0 && data->pwm_enable[nr] > manual)
2523 pwm = nct6775_read_value(data, data->REG_PWM_READ[nr]);
2525 pwm = data->pwm[index][nr];
2527 return sprintf(buf, "%d\n", pwm);
2531 store_pwm(struct device *dev, struct device_attribute *attr, const char *buf,
2534 struct nct6775_data *data = dev_get_drvdata(dev);
2535 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2537 int index = sattr->index;
2539 int minval[7] = { 0, 1, 1, data->pwm[2][nr], 0, 0, 0 };
2541 = { 255, 255, data->pwm[3][nr] ? : 255, 255, 255, 255, 255 };
2545 err = kstrtoul(buf, 10, &val);
2548 val = clamp_val(val, minval[index], maxval[index]);
2550 mutex_lock(&data->update_lock);
2551 data->pwm[index][nr] = val;
2552 nct6775_write_value(data, data->REG_PWM[index][nr], val);
2553 if (index == 2) { /* floor: disable if val == 0 */
2554 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2558 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2560 mutex_unlock(&data->update_lock);
2564 /* Returns 0 if OK, -EINVAL otherwise */
2565 static int check_trip_points(struct nct6775_data *data, int nr)
2569 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2570 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
2573 for (i = 0; i < data->auto_pwm_num - 1; i++) {
2574 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
2577 /* validate critical temperature and pwm if enabled (pwm > 0) */
2578 if (data->auto_pwm[nr][data->auto_pwm_num]) {
2579 if (data->auto_temp[nr][data->auto_pwm_num - 1] >
2580 data->auto_temp[nr][data->auto_pwm_num] ||
2581 data->auto_pwm[nr][data->auto_pwm_num - 1] >
2582 data->auto_pwm[nr][data->auto_pwm_num])
2588 static void pwm_update_registers(struct nct6775_data *data, int nr)
2592 switch (data->pwm_enable[nr]) {
2597 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2598 reg = (reg & ~data->tolerance_mask) |
2599 (data->target_speed_tolerance[nr] & data->tolerance_mask);
2600 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2601 nct6775_write_value(data, data->REG_TARGET[nr],
2602 data->target_speed[nr] & 0xff);
2603 if (data->REG_TOLERANCE_H) {
2604 reg = (data->target_speed[nr] >> 8) & 0x0f;
2605 reg |= (data->target_speed_tolerance[nr] & 0x38) << 1;
2606 nct6775_write_value(data,
2607 data->REG_TOLERANCE_H[nr],
2611 case thermal_cruise:
2612 nct6775_write_value(data, data->REG_TARGET[nr],
2613 data->target_temp[nr]);
2616 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2617 reg = (reg & ~data->tolerance_mask) |
2618 data->temp_tolerance[0][nr];
2619 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2625 show_pwm_enable(struct device *dev, struct device_attribute *attr, char *buf)
2627 struct nct6775_data *data = nct6775_update_device(dev);
2628 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2630 return sprintf(buf, "%d\n", data->pwm_enable[sattr->index]);
2634 store_pwm_enable(struct device *dev, struct device_attribute *attr,
2635 const char *buf, size_t count)
2637 struct nct6775_data *data = dev_get_drvdata(dev);
2638 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2639 int nr = sattr->index;
2644 err = kstrtoul(buf, 10, &val);
2651 if (val == sf3 && data->kind != nct6775)
2654 if (val == sf4 && check_trip_points(data, nr)) {
2655 dev_err(dev, "Inconsistent trip points, not switching to SmartFan IV mode\n");
2656 dev_err(dev, "Adjust trip points and try again\n");
2660 mutex_lock(&data->update_lock);
2661 data->pwm_enable[nr] = val;
2664 * turn off pwm control: select manual mode, set pwm to maximum
2666 data->pwm[0][nr] = 255;
2667 nct6775_write_value(data, data->REG_PWM[0][nr], 255);
2669 pwm_update_registers(data, nr);
2670 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2672 reg |= pwm_enable_to_reg(val) << 4;
2673 nct6775_write_value(data, data->REG_FAN_MODE[nr], reg);
2674 mutex_unlock(&data->update_lock);
2679 show_pwm_temp_sel_common(struct nct6775_data *data, char *buf, int src)
2683 for (i = 0; i < NUM_TEMP; i++) {
2684 if (!(data->have_temp & BIT(i)))
2686 if (src == data->temp_src[i]) {
2692 return sprintf(buf, "%d\n", sel);
2696 show_pwm_temp_sel(struct device *dev, struct device_attribute *attr, char *buf)
2698 struct nct6775_data *data = nct6775_update_device(dev);
2699 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2700 int index = sattr->index;
2702 return show_pwm_temp_sel_common(data, buf, data->pwm_temp_sel[index]);
2706 store_pwm_temp_sel(struct device *dev, struct device_attribute *attr,
2707 const char *buf, size_t count)
2709 struct nct6775_data *data = nct6775_update_device(dev);
2710 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2711 int nr = sattr->index;
2715 err = kstrtoul(buf, 10, &val);
2718 if (val == 0 || val > NUM_TEMP)
2720 if (!(data->have_temp & BIT(val - 1)) || !data->temp_src[val - 1])
2723 mutex_lock(&data->update_lock);
2724 src = data->temp_src[val - 1];
2725 data->pwm_temp_sel[nr] = src;
2726 reg = nct6775_read_value(data, data->REG_TEMP_SEL[nr]);
2729 nct6775_write_value(data, data->REG_TEMP_SEL[nr], reg);
2730 mutex_unlock(&data->update_lock);
2736 show_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2739 struct nct6775_data *data = nct6775_update_device(dev);
2740 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2741 int index = sattr->index;
2743 return show_pwm_temp_sel_common(data, buf,
2744 data->pwm_weight_temp_sel[index]);
2748 store_pwm_weight_temp_sel(struct device *dev, struct device_attribute *attr,
2749 const char *buf, size_t count)
2751 struct nct6775_data *data = nct6775_update_device(dev);
2752 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2753 int nr = sattr->index;
2757 err = kstrtoul(buf, 10, &val);
2762 val = array_index_nospec(val, NUM_TEMP + 1);
2763 if (val && (!(data->have_temp & BIT(val - 1)) ||
2764 !data->temp_src[val - 1]))
2767 mutex_lock(&data->update_lock);
2769 src = data->temp_src[val - 1];
2770 data->pwm_weight_temp_sel[nr] = src;
2771 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2773 reg |= (src | 0x80);
2774 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2776 data->pwm_weight_temp_sel[nr] = 0;
2777 reg = nct6775_read_value(data, data->REG_WEIGHT_TEMP_SEL[nr]);
2779 nct6775_write_value(data, data->REG_WEIGHT_TEMP_SEL[nr], reg);
2781 mutex_unlock(&data->update_lock);
2787 show_target_temp(struct device *dev, struct device_attribute *attr, char *buf)
2789 struct nct6775_data *data = nct6775_update_device(dev);
2790 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2792 return sprintf(buf, "%d\n", data->target_temp[sattr->index] * 1000);
2796 store_target_temp(struct device *dev, struct device_attribute *attr,
2797 const char *buf, size_t count)
2799 struct nct6775_data *data = dev_get_drvdata(dev);
2800 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2801 int nr = sattr->index;
2805 err = kstrtoul(buf, 10, &val);
2809 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0,
2810 data->target_temp_mask);
2812 mutex_lock(&data->update_lock);
2813 data->target_temp[nr] = val;
2814 pwm_update_registers(data, nr);
2815 mutex_unlock(&data->update_lock);
2820 show_target_speed(struct device *dev, struct device_attribute *attr, char *buf)
2822 struct nct6775_data *data = nct6775_update_device(dev);
2823 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2824 int nr = sattr->index;
2826 return sprintf(buf, "%d\n",
2827 fan_from_reg16(data->target_speed[nr],
2828 data->fan_div[nr]));
2832 store_target_speed(struct device *dev, struct device_attribute *attr,
2833 const char *buf, size_t count)
2835 struct nct6775_data *data = dev_get_drvdata(dev);
2836 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2837 int nr = sattr->index;
2842 err = kstrtoul(buf, 10, &val);
2846 val = clamp_val(val, 0, 1350000U);
2847 speed = fan_to_reg(val, data->fan_div[nr]);
2849 mutex_lock(&data->update_lock);
2850 data->target_speed[nr] = speed;
2851 pwm_update_registers(data, nr);
2852 mutex_unlock(&data->update_lock);
2857 show_temp_tolerance(struct device *dev, struct device_attribute *attr,
2860 struct nct6775_data *data = nct6775_update_device(dev);
2861 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2863 int index = sattr->index;
2865 return sprintf(buf, "%d\n", data->temp_tolerance[index][nr] * 1000);
2869 store_temp_tolerance(struct device *dev, struct device_attribute *attr,
2870 const char *buf, size_t count)
2872 struct nct6775_data *data = dev_get_drvdata(dev);
2873 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2875 int index = sattr->index;
2879 err = kstrtoul(buf, 10, &val);
2883 /* Limit tolerance as needed */
2884 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, data->tolerance_mask);
2886 mutex_lock(&data->update_lock);
2887 data->temp_tolerance[index][nr] = val;
2889 pwm_update_registers(data, nr);
2891 nct6775_write_value(data,
2892 data->REG_CRITICAL_TEMP_TOLERANCE[nr],
2894 mutex_unlock(&data->update_lock);
2899 * Fan speed tolerance is a tricky beast, since the associated register is
2900 * a tick counter, but the value is reported and configured as rpm.
2901 * Compute resulting low and high rpm values and report the difference.
2902 * A fan speed tolerance only makes sense if a fan target speed has been
2903 * configured, so only display values other than 0 if that is the case.
2906 show_speed_tolerance(struct device *dev, struct device_attribute *attr,
2909 struct nct6775_data *data = nct6775_update_device(dev);
2910 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2911 int nr = sattr->index;
2912 int target = data->target_speed[nr];
2916 int low = target - data->target_speed_tolerance[nr];
2917 int high = target + data->target_speed_tolerance[nr];
2926 tolerance = (fan_from_reg16(low, data->fan_div[nr])
2927 - fan_from_reg16(high, data->fan_div[nr])) / 2;
2930 return sprintf(buf, "%d\n", tolerance);
2934 store_speed_tolerance(struct device *dev, struct device_attribute *attr,
2935 const char *buf, size_t count)
2937 struct nct6775_data *data = dev_get_drvdata(dev);
2938 struct sensor_device_attribute *sattr = to_sensor_dev_attr(attr);
2939 int nr = sattr->index;
2944 err = kstrtoul(buf, 10, &val);
2948 high = fan_from_reg16(data->target_speed[nr],
2949 data->fan_div[nr]) + val;
2950 low = fan_from_reg16(data->target_speed[nr],
2951 data->fan_div[nr]) - val;
2957 val = (fan_to_reg(low, data->fan_div[nr]) -
2958 fan_to_reg(high, data->fan_div[nr])) / 2;
2960 /* Limit tolerance as needed */
2961 val = clamp_val(val, 0, data->speed_tolerance_limit);
2963 mutex_lock(&data->update_lock);
2964 data->target_speed_tolerance[nr] = val;
2965 pwm_update_registers(data, nr);
2966 mutex_unlock(&data->update_lock);
2970 SENSOR_TEMPLATE_2(pwm, "pwm%d", S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 0);
2971 SENSOR_TEMPLATE(pwm_mode, "pwm%d_mode", S_IWUSR | S_IRUGO, show_pwm_mode,
2973 SENSOR_TEMPLATE(pwm_enable, "pwm%d_enable", S_IWUSR | S_IRUGO, show_pwm_enable,
2974 store_pwm_enable, 0);
2975 SENSOR_TEMPLATE(pwm_temp_sel, "pwm%d_temp_sel", S_IWUSR | S_IRUGO,
2976 show_pwm_temp_sel, store_pwm_temp_sel, 0);
2977 SENSOR_TEMPLATE(pwm_target_temp, "pwm%d_target_temp", S_IWUSR | S_IRUGO,
2978 show_target_temp, store_target_temp, 0);
2979 SENSOR_TEMPLATE(fan_target, "fan%d_target", S_IWUSR | S_IRUGO,
2980 show_target_speed, store_target_speed, 0);
2981 SENSOR_TEMPLATE(fan_tolerance, "fan%d_tolerance", S_IWUSR | S_IRUGO,
2982 show_speed_tolerance, store_speed_tolerance, 0);
2984 /* Smart Fan registers */
2987 show_weight_temp(struct device *dev, struct device_attribute *attr, char *buf)
2989 struct nct6775_data *data = nct6775_update_device(dev);
2990 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
2992 int index = sattr->index;
2994 return sprintf(buf, "%d\n", data->weight_temp[index][nr] * 1000);
2998 store_weight_temp(struct device *dev, struct device_attribute *attr,
2999 const char *buf, size_t count)
3001 struct nct6775_data *data = dev_get_drvdata(dev);
3002 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3004 int index = sattr->index;
3008 err = kstrtoul(buf, 10, &val);
3012 val = clamp_val(DIV_ROUND_CLOSEST(val, 1000), 0, 255);
3014 mutex_lock(&data->update_lock);
3015 data->weight_temp[index][nr] = val;
3016 nct6775_write_value(data, data->REG_WEIGHT_TEMP[index][nr], val);
3017 mutex_unlock(&data->update_lock);
3021 SENSOR_TEMPLATE(pwm_weight_temp_sel, "pwm%d_weight_temp_sel", S_IWUSR | S_IRUGO,
3022 show_pwm_weight_temp_sel, store_pwm_weight_temp_sel, 0);
3023 SENSOR_TEMPLATE_2(pwm_weight_temp_step, "pwm%d_weight_temp_step",
3024 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 0);
3025 SENSOR_TEMPLATE_2(pwm_weight_temp_step_tol, "pwm%d_weight_temp_step_tol",
3026 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 1);
3027 SENSOR_TEMPLATE_2(pwm_weight_temp_step_base, "pwm%d_weight_temp_step_base",
3028 S_IWUSR | S_IRUGO, show_weight_temp, store_weight_temp, 0, 2);
3029 SENSOR_TEMPLATE_2(pwm_weight_duty_step, "pwm%d_weight_duty_step",
3030 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 5);
3031 SENSOR_TEMPLATE_2(pwm_weight_duty_base, "pwm%d_weight_duty_base",
3032 S_IWUSR | S_IRUGO, show_pwm, store_pwm, 0, 6);
3035 show_fan_time(struct device *dev, struct device_attribute *attr, char *buf)
3037 struct nct6775_data *data = nct6775_update_device(dev);
3038 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3040 int index = sattr->index;
3042 return sprintf(buf, "%d\n",
3043 step_time_from_reg(data->fan_time[index][nr],
3044 data->pwm_mode[nr]));
3048 store_fan_time(struct device *dev, struct device_attribute *attr,
3049 const char *buf, size_t count)
3051 struct nct6775_data *data = dev_get_drvdata(dev);
3052 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3054 int index = sattr->index;
3058 err = kstrtoul(buf, 10, &val);
3062 val = step_time_to_reg(val, data->pwm_mode[nr]);
3063 mutex_lock(&data->update_lock);
3064 data->fan_time[index][nr] = val;
3065 nct6775_write_value(data, data->REG_FAN_TIME[index][nr], val);
3066 mutex_unlock(&data->update_lock);
3071 show_auto_pwm(struct device *dev, struct device_attribute *attr, char *buf)
3073 struct nct6775_data *data = nct6775_update_device(dev);
3074 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3076 return sprintf(buf, "%d\n", data->auto_pwm[sattr->nr][sattr->index]);
3080 store_auto_pwm(struct device *dev, struct device_attribute *attr,
3081 const char *buf, size_t count)
3083 struct nct6775_data *data = dev_get_drvdata(dev);
3084 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3086 int point = sattr->index;
3091 err = kstrtoul(buf, 10, &val);
3097 if (point == data->auto_pwm_num) {
3098 if (data->kind != nct6775 && !val)
3100 if (data->kind != nct6779 && val)
3104 mutex_lock(&data->update_lock);
3105 data->auto_pwm[nr][point] = val;
3106 if (point < data->auto_pwm_num) {
3107 nct6775_write_value(data,
3108 NCT6775_AUTO_PWM(data, nr, point),
3109 data->auto_pwm[nr][point]);
3111 switch (data->kind) {
3113 /* disable if needed (pwm == 0) */
3114 reg = nct6775_read_value(data,
3115 NCT6775_REG_CRITICAL_ENAB[nr]);
3120 nct6775_write_value(data, NCT6775_REG_CRITICAL_ENAB[nr],
3124 break; /* always enabled, nothing to do */
3134 nct6775_write_value(data, data->REG_CRITICAL_PWM[nr],
3136 reg = nct6775_read_value(data,
3137 data->REG_CRITICAL_PWM_ENABLE[nr]);
3139 reg &= ~data->CRITICAL_PWM_ENABLE_MASK;
3141 reg |= data->CRITICAL_PWM_ENABLE_MASK;
3142 nct6775_write_value(data,
3143 data->REG_CRITICAL_PWM_ENABLE[nr],
3148 mutex_unlock(&data->update_lock);
3153 show_auto_temp(struct device *dev, struct device_attribute *attr, char *buf)
3155 struct nct6775_data *data = nct6775_update_device(dev);
3156 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3158 int point = sattr->index;
3161 * We don't know for sure if the temperature is signed or unsigned.
3162 * Assume it is unsigned.
3164 return sprintf(buf, "%d\n", data->auto_temp[nr][point] * 1000);
3168 store_auto_temp(struct device *dev, struct device_attribute *attr,
3169 const char *buf, size_t count)
3171 struct nct6775_data *data = dev_get_drvdata(dev);
3172 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
3174 int point = sattr->index;
3178 err = kstrtoul(buf, 10, &val);
3184 mutex_lock(&data->update_lock);
3185 data->auto_temp[nr][point] = DIV_ROUND_CLOSEST(val, 1000);
3186 if (point < data->auto_pwm_num) {
3187 nct6775_write_value(data,
3188 NCT6775_AUTO_TEMP(data, nr, point),
3189 data->auto_temp[nr][point]);
3191 nct6775_write_value(data, data->REG_CRITICAL_TEMP[nr],
3192 data->auto_temp[nr][point]);
3194 mutex_unlock(&data->update_lock);
3198 static umode_t nct6775_pwm_is_visible(struct kobject *kobj,
3199 struct attribute *attr, int index)
3201 struct device *dev = container_of(kobj, struct device, kobj);
3202 struct nct6775_data *data = dev_get_drvdata(dev);
3203 int pwm = index / 36; /* pwm index */
3204 int nr = index % 36; /* attribute index */
3206 if (!(data->has_pwm & BIT(pwm)))
3209 if ((nr >= 14 && nr <= 18) || nr == 21) /* weight */
3210 if (!data->REG_WEIGHT_TEMP_SEL[pwm])
3212 if (nr == 19 && data->REG_PWM[3] == NULL) /* pwm_max */
3214 if (nr == 20 && data->REG_PWM[4] == NULL) /* pwm_step */
3216 if (nr == 21 && data->REG_PWM[6] == NULL) /* weight_duty_base */
3219 if (nr >= 22 && nr <= 35) { /* auto point */
3220 int api = (nr - 22) / 2; /* auto point index */
3222 if (api > data->auto_pwm_num)
3228 SENSOR_TEMPLATE_2(pwm_stop_time, "pwm%d_stop_time", S_IWUSR | S_IRUGO,
3229 show_fan_time, store_fan_time, 0, 0);
3230 SENSOR_TEMPLATE_2(pwm_step_up_time, "pwm%d_step_up_time", S_IWUSR | S_IRUGO,
3231 show_fan_time, store_fan_time, 0, 1);
3232 SENSOR_TEMPLATE_2(pwm_step_down_time, "pwm%d_step_down_time", S_IWUSR | S_IRUGO,
3233 show_fan_time, store_fan_time, 0, 2);
3234 SENSOR_TEMPLATE_2(pwm_start, "pwm%d_start", S_IWUSR | S_IRUGO, show_pwm,
3236 SENSOR_TEMPLATE_2(pwm_floor, "pwm%d_floor", S_IWUSR | S_IRUGO, show_pwm,
3238 SENSOR_TEMPLATE_2(pwm_temp_tolerance, "pwm%d_temp_tolerance", S_IWUSR | S_IRUGO,
3239 show_temp_tolerance, store_temp_tolerance, 0, 0);
3240 SENSOR_TEMPLATE_2(pwm_crit_temp_tolerance, "pwm%d_crit_temp_tolerance",
3241 S_IWUSR | S_IRUGO, show_temp_tolerance, store_temp_tolerance,
3244 SENSOR_TEMPLATE_2(pwm_max, "pwm%d_max", S_IWUSR | S_IRUGO, show_pwm, store_pwm,
3247 SENSOR_TEMPLATE_2(pwm_step, "pwm%d_step", S_IWUSR | S_IRUGO, show_pwm,
3250 SENSOR_TEMPLATE_2(pwm_auto_point1_pwm, "pwm%d_auto_point1_pwm",
3251 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 0);
3252 SENSOR_TEMPLATE_2(pwm_auto_point1_temp, "pwm%d_auto_point1_temp",
3253 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 0);
3255 SENSOR_TEMPLATE_2(pwm_auto_point2_pwm, "pwm%d_auto_point2_pwm",
3256 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 1);
3257 SENSOR_TEMPLATE_2(pwm_auto_point2_temp, "pwm%d_auto_point2_temp",
3258 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 1);
3260 SENSOR_TEMPLATE_2(pwm_auto_point3_pwm, "pwm%d_auto_point3_pwm",
3261 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 2);
3262 SENSOR_TEMPLATE_2(pwm_auto_point3_temp, "pwm%d_auto_point3_temp",
3263 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 2);
3265 SENSOR_TEMPLATE_2(pwm_auto_point4_pwm, "pwm%d_auto_point4_pwm",
3266 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 3);
3267 SENSOR_TEMPLATE_2(pwm_auto_point4_temp, "pwm%d_auto_point4_temp",
3268 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 3);
3270 SENSOR_TEMPLATE_2(pwm_auto_point5_pwm, "pwm%d_auto_point5_pwm",
3271 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 4);
3272 SENSOR_TEMPLATE_2(pwm_auto_point5_temp, "pwm%d_auto_point5_temp",
3273 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 4);
3275 SENSOR_TEMPLATE_2(pwm_auto_point6_pwm, "pwm%d_auto_point6_pwm",
3276 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 5);
3277 SENSOR_TEMPLATE_2(pwm_auto_point6_temp, "pwm%d_auto_point6_temp",
3278 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 5);
3280 SENSOR_TEMPLATE_2(pwm_auto_point7_pwm, "pwm%d_auto_point7_pwm",
3281 S_IWUSR | S_IRUGO, show_auto_pwm, store_auto_pwm, 0, 6);
3282 SENSOR_TEMPLATE_2(pwm_auto_point7_temp, "pwm%d_auto_point7_temp",
3283 S_IWUSR | S_IRUGO, show_auto_temp, store_auto_temp, 0, 6);
3286 * nct6775_pwm_is_visible uses the index into the following array
3287 * to determine if attributes should be created or not.
3288 * Any change in order or content must be matched.
3290 static struct sensor_device_template *nct6775_attributes_pwm_template[] = {
3291 &sensor_dev_template_pwm,
3292 &sensor_dev_template_pwm_mode,
3293 &sensor_dev_template_pwm_enable,
3294 &sensor_dev_template_pwm_temp_sel,
3295 &sensor_dev_template_pwm_temp_tolerance,
3296 &sensor_dev_template_pwm_crit_temp_tolerance,
3297 &sensor_dev_template_pwm_target_temp,
3298 &sensor_dev_template_fan_target,
3299 &sensor_dev_template_fan_tolerance,
3300 &sensor_dev_template_pwm_stop_time,
3301 &sensor_dev_template_pwm_step_up_time,
3302 &sensor_dev_template_pwm_step_down_time,
3303 &sensor_dev_template_pwm_start,
3304 &sensor_dev_template_pwm_floor,
3305 &sensor_dev_template_pwm_weight_temp_sel, /* 14 */
3306 &sensor_dev_template_pwm_weight_temp_step,
3307 &sensor_dev_template_pwm_weight_temp_step_tol,
3308 &sensor_dev_template_pwm_weight_temp_step_base,
3309 &sensor_dev_template_pwm_weight_duty_step, /* 18 */
3310 &sensor_dev_template_pwm_max, /* 19 */
3311 &sensor_dev_template_pwm_step, /* 20 */
3312 &sensor_dev_template_pwm_weight_duty_base, /* 21 */
3313 &sensor_dev_template_pwm_auto_point1_pwm, /* 22 */
3314 &sensor_dev_template_pwm_auto_point1_temp,
3315 &sensor_dev_template_pwm_auto_point2_pwm,
3316 &sensor_dev_template_pwm_auto_point2_temp,
3317 &sensor_dev_template_pwm_auto_point3_pwm,
3318 &sensor_dev_template_pwm_auto_point3_temp,
3319 &sensor_dev_template_pwm_auto_point4_pwm,
3320 &sensor_dev_template_pwm_auto_point4_temp,
3321 &sensor_dev_template_pwm_auto_point5_pwm,
3322 &sensor_dev_template_pwm_auto_point5_temp,
3323 &sensor_dev_template_pwm_auto_point6_pwm,
3324 &sensor_dev_template_pwm_auto_point6_temp,
3325 &sensor_dev_template_pwm_auto_point7_pwm,
3326 &sensor_dev_template_pwm_auto_point7_temp, /* 35 */
3331 static const struct sensor_template_group nct6775_pwm_template_group = {
3332 .templates = nct6775_attributes_pwm_template,
3333 .is_visible = nct6775_pwm_is_visible,
3338 cpu0_vid_show(struct device *dev, struct device_attribute *attr, char *buf)
3340 struct nct6775_data *data = dev_get_drvdata(dev);
3342 return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
3345 static DEVICE_ATTR_RO(cpu0_vid);
3347 /* Case open detection */
3350 clear_caseopen(struct device *dev, struct device_attribute *attr,
3351 const char *buf, size_t count)
3353 struct nct6775_data *data = dev_get_drvdata(dev);
3354 int nr = to_sensor_dev_attr(attr)->index - INTRUSION_ALARM_BASE;
3359 if (kstrtoul(buf, 10, &val) || val != 0)
3362 mutex_lock(&data->update_lock);
3365 * Use CR registers to clear caseopen status.
3366 * The CR registers are the same for all chips, and not all chips
3367 * support clearing the caseopen status through "regular" registers.
3369 ret = superio_enter(data->sioreg);
3375 superio_select(data->sioreg, NCT6775_LD_ACPI);
3376 reg = superio_inb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr]);
3377 reg |= NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3378 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3379 reg &= ~NCT6775_CR_CASEOPEN_CLR_MASK[nr];
3380 superio_outb(data->sioreg, NCT6775_REG_CR_CASEOPEN_CLR[nr], reg);
3381 superio_exit(data->sioreg);
3383 data->valid = false; /* Force cache refresh */
3385 mutex_unlock(&data->update_lock);
3389 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IWUSR | S_IRUGO, show_alarm,
3390 clear_caseopen, INTRUSION_ALARM_BASE);
3391 static SENSOR_DEVICE_ATTR(intrusion1_alarm, S_IWUSR | S_IRUGO, show_alarm,
3392 clear_caseopen, INTRUSION_ALARM_BASE + 1);
3393 static SENSOR_DEVICE_ATTR(intrusion0_beep, S_IWUSR | S_IRUGO, show_beep,
3394 store_beep, INTRUSION_ALARM_BASE);
3395 static SENSOR_DEVICE_ATTR(intrusion1_beep, S_IWUSR | S_IRUGO, show_beep,
3396 store_beep, INTRUSION_ALARM_BASE + 1);
3397 static SENSOR_DEVICE_ATTR(beep_enable, S_IWUSR | S_IRUGO, show_beep,
3398 store_beep, BEEP_ENABLE_BASE);
3400 static umode_t nct6775_other_is_visible(struct kobject *kobj,
3401 struct attribute *attr, int index)
3403 struct device *dev = container_of(kobj, struct device, kobj);
3404 struct nct6775_data *data = dev_get_drvdata(dev);
3406 if (index == 0 && !data->have_vid)
3409 if (index == 1 || index == 2) {
3410 if (data->ALARM_BITS[INTRUSION_ALARM_BASE + index - 1] < 0)
3414 if (index == 3 || index == 4) {
3415 if (data->BEEP_BITS[INTRUSION_ALARM_BASE + index - 3] < 0)
3423 * nct6775_other_is_visible uses the index into the following array
3424 * to determine if attributes should be created or not.
3425 * Any change in order or content must be matched.
3427 static struct attribute *nct6775_attributes_other[] = {
3428 &dev_attr_cpu0_vid.attr, /* 0 */
3429 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, /* 1 */
3430 &sensor_dev_attr_intrusion1_alarm.dev_attr.attr, /* 2 */
3431 &sensor_dev_attr_intrusion0_beep.dev_attr.attr, /* 3 */
3432 &sensor_dev_attr_intrusion1_beep.dev_attr.attr, /* 4 */
3433 &sensor_dev_attr_beep_enable.dev_attr.attr, /* 5 */
3438 static const struct attribute_group nct6775_group_other = {
3439 .attrs = nct6775_attributes_other,
3440 .is_visible = nct6775_other_is_visible,
3443 static inline void nct6775_init_device(struct nct6775_data *data)
3448 /* Start monitoring if needed */
3449 if (data->REG_CONFIG) {
3450 tmp = nct6775_read_value(data, data->REG_CONFIG);
3452 nct6775_write_value(data, data->REG_CONFIG, tmp | 0x01);
3455 /* Enable temperature sensors if needed */
3456 for (i = 0; i < NUM_TEMP; i++) {
3457 if (!(data->have_temp & BIT(i)))
3459 if (!data->reg_temp_config[i])
3461 tmp = nct6775_read_value(data, data->reg_temp_config[i]);
3463 nct6775_write_value(data, data->reg_temp_config[i],
3467 /* Enable VBAT monitoring if needed */
3468 tmp = nct6775_read_value(data, data->REG_VBAT);
3470 nct6775_write_value(data, data->REG_VBAT, tmp | 0x01);
3472 diode = nct6775_read_value(data, data->REG_DIODE);
3474 for (i = 0; i < data->temp_fixed_num; i++) {
3475 if (!(data->have_temp_fixed & BIT(i)))
3477 if ((tmp & (data->DIODE_MASK << i))) /* diode */
3479 = 3 - ((diode >> i) & data->DIODE_MASK);
3480 else /* thermistor */
3481 data->temp_type[i] = 4;
3486 nct6775_check_fan_inputs(struct nct6775_data *data)
3488 bool fan3pin = false, fan4pin = false, fan4min = false;
3489 bool fan5pin = false, fan6pin = false, fan7pin = false;
3490 bool pwm3pin = false, pwm4pin = false, pwm5pin = false;
3491 bool pwm6pin = false, pwm7pin = false;
3492 int sioreg = data->sioreg;
3494 /* Store SIO_REG_ENABLE for use during resume */
3495 superio_select(sioreg, NCT6775_LD_HWM);
3496 data->sio_reg_enable = superio_inb(sioreg, SIO_REG_ENABLE);
3498 /* fan4 and fan5 share some pins with the GPIO and serial flash */
3499 if (data->kind == nct6775) {
3500 int cr2c = superio_inb(sioreg, 0x2c);
3502 fan3pin = cr2c & BIT(6);
3503 pwm3pin = cr2c & BIT(7);
3505 /* On NCT6775, fan4 shares pins with the fdc interface */
3506 fan4pin = !(superio_inb(sioreg, 0x2A) & 0x80);
3507 } else if (data->kind == nct6776) {
3508 bool gpok = superio_inb(sioreg, 0x27) & 0x80;
3509 const char *board_vendor, *board_name;
3511 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
3512 board_name = dmi_get_system_info(DMI_BOARD_NAME);
3514 if (board_name && board_vendor &&
3515 !strcmp(board_vendor, "ASRock")) {
3517 * Auxiliary fan monitoring is not enabled on ASRock
3518 * Z77 Pro4-M if booted in UEFI Ultra-FastBoot mode.
3519 * Observed with BIOS version 2.00.
3521 if (!strcmp(board_name, "Z77 Pro4-M")) {
3522 if ((data->sio_reg_enable & 0xe0) != 0xe0) {
3523 data->sio_reg_enable |= 0xe0;
3524 superio_outb(sioreg, SIO_REG_ENABLE,
3525 data->sio_reg_enable);
3530 if (data->sio_reg_enable & 0x80)
3533 fan3pin = !(superio_inb(sioreg, 0x24) & 0x40);
3535 if (data->sio_reg_enable & 0x40)
3538 fan4pin = superio_inb(sioreg, 0x1C) & 0x01;
3540 if (data->sio_reg_enable & 0x20)
3543 fan5pin = superio_inb(sioreg, 0x1C) & 0x02;
3547 } else if (data->kind == nct6106) {
3548 int cr24 = superio_inb(sioreg, 0x24);
3550 fan3pin = !(cr24 & 0x80);
3551 pwm3pin = cr24 & 0x08;
3554 * NCT6779D, NCT6791D, NCT6792D, NCT6793D, NCT6795D, NCT6796D,
3555 * NCT6797D, NCT6798D
3557 int cr1a = superio_inb(sioreg, 0x1a);
3558 int cr1b = superio_inb(sioreg, 0x1b);
3559 int cr1c = superio_inb(sioreg, 0x1c);
3560 int cr1d = superio_inb(sioreg, 0x1d);
3561 int cr2a = superio_inb(sioreg, 0x2a);
3562 int cr2b = superio_inb(sioreg, 0x2b);
3563 int cr2d = superio_inb(sioreg, 0x2d);
3564 int cr2f = superio_inb(sioreg, 0x2f);
3565 bool dsw_en = cr2f & BIT(3);
3566 bool ddr4_en = cr2f & BIT(4);
3571 superio_select(sioreg, NCT6775_LD_12);
3572 cre0 = superio_inb(sioreg, 0xe0);
3573 creb = superio_inb(sioreg, 0xeb);
3574 cred = superio_inb(sioreg, 0xed);
3576 fan3pin = !(cr1c & BIT(5));
3577 fan4pin = !(cr1c & BIT(6));
3578 fan5pin = !(cr1c & BIT(7));
3580 pwm3pin = !(cr1c & BIT(0));
3581 pwm4pin = !(cr1c & BIT(1));
3582 pwm5pin = !(cr1c & BIT(2));
3584 switch (data->kind) {
3586 fan6pin = cr2d & BIT(1);
3587 pwm6pin = cr2d & BIT(0);
3590 fan6pin = !dsw_en && (cr2d & BIT(1));
3591 pwm6pin = !dsw_en && (cr2d & BIT(0));
3594 fan5pin |= cr1b & BIT(5);
3595 fan5pin |= creb & BIT(5);
3597 fan6pin = creb & BIT(3);
3599 pwm5pin |= cr2d & BIT(7);
3600 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3602 pwm6pin = !dsw_en && (cr2d & BIT(0));
3603 pwm6pin |= creb & BIT(2);
3606 fan5pin |= cr1b & BIT(5);
3607 fan5pin |= creb & BIT(5);
3609 fan6pin = (cr2a & BIT(4)) &&
3610 (!dsw_en || (cred & BIT(4)));
3611 fan6pin |= creb & BIT(3);
3613 pwm5pin |= cr2d & BIT(7);
3614 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3616 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3617 pwm6pin |= creb & BIT(2);
3620 fan5pin |= cr1b & BIT(5);
3621 fan5pin |= (cre0 & BIT(3)) && !(cr1b & BIT(0));
3622 fan5pin |= creb & BIT(5);
3624 fan6pin = (cr2a & BIT(4)) &&
3625 (!dsw_en || (cred & BIT(4)));
3626 fan6pin |= creb & BIT(3);
3628 fan7pin = !(cr2b & BIT(2));
3630 pwm5pin |= cr2d & BIT(7);
3631 pwm5pin |= (cre0 & BIT(4)) && !(cr1b & BIT(0));
3632 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3634 pwm6pin = (cr2a & BIT(3)) && (cred & BIT(2));
3635 pwm6pin |= creb & BIT(2);
3637 pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3640 fan5pin |= !ddr4_en && (cr1b & BIT(5));
3641 fan5pin |= creb & BIT(5);
3643 fan6pin = cr2a & BIT(4);
3644 fan6pin |= creb & BIT(3);
3646 fan7pin = cr1a & BIT(1);
3648 pwm5pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3649 pwm5pin |= !ddr4_en && (cr2d & BIT(7));
3651 pwm6pin = creb & BIT(2);
3652 pwm6pin |= cred & BIT(2);
3654 pwm7pin = cr1d & BIT(4);
3657 fan6pin = !(cr1b & BIT(0)) && (cre0 & BIT(3));
3658 fan6pin |= cr2a & BIT(4);
3659 fan6pin |= creb & BIT(5);
3661 fan7pin = cr1b & BIT(5);
3662 fan7pin |= !(cr2b & BIT(2));
3663 fan7pin |= creb & BIT(3);
3665 pwm6pin = !(cr1b & BIT(0)) && (cre0 & BIT(4));
3666 pwm6pin |= !(cred & BIT(2)) && (cr2a & BIT(3));
3667 pwm6pin |= (creb & BIT(4)) && !(cr2a & BIT(0));
3669 pwm7pin = !(cr1d & (BIT(2) | BIT(3)));
3670 pwm7pin |= cr2d & BIT(7);
3671 pwm7pin |= creb & BIT(2);
3673 default: /* NCT6779D */
3680 /* fan 1 and 2 (0x03) are always present */
3681 data->has_fan = 0x03 | (fan3pin << 2) | (fan4pin << 3) |
3682 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3683 data->has_fan_min = 0x03 | (fan3pin << 2) | (fan4min << 3) |
3684 (fan5pin << 4) | (fan6pin << 5) | (fan7pin << 6);
3685 data->has_pwm = 0x03 | (pwm3pin << 2) | (pwm4pin << 3) |
3686 (pwm5pin << 4) | (pwm6pin << 5) | (pwm7pin << 6);
3689 static void add_temp_sensors(struct nct6775_data *data, const u16 *regp,
3690 int *available, int *mask)
3695 for (i = 0; i < data->pwm_num && *available; i++) {
3700 src = nct6775_read_value(data, regp[i]);
3702 if (!src || (*mask & BIT(src)))
3704 if (!(data->temp_mask & BIT(src)))
3707 index = __ffs(*available);
3708 nct6775_write_value(data, data->REG_TEMP_SOURCE[index], src);
3709 *available &= ~BIT(index);
3714 static int nct6775_probe(struct platform_device *pdev)
3716 struct device *dev = &pdev->dev;
3717 struct nct6775_sio_data *sio_data = dev_get_platdata(dev);
3718 struct nct6775_data *data;
3719 struct resource *res;
3721 int src, mask, available;
3722 const u16 *reg_temp, *reg_temp_over, *reg_temp_hyst, *reg_temp_config;
3723 const u16 *reg_temp_mon, *reg_temp_alternate, *reg_temp_crit;
3724 const u16 *reg_temp_crit_l = NULL, *reg_temp_crit_h = NULL;
3725 int num_reg_temp, num_reg_temp_mon;
3727 struct attribute_group *group;
3728 struct device *hwmon_dev;
3729 int num_attr_groups = 0;
3731 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3732 if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH,
3736 data = devm_kzalloc(&pdev->dev, sizeof(struct nct6775_data),
3741 data->kind = sio_data->kind;
3742 data->sioreg = sio_data->sioreg;
3743 data->addr = res->start;
3744 mutex_init(&data->update_lock);
3745 data->name = nct6775_device_names[data->kind];
3746 data->bank = 0xff; /* Force initial bank selection */
3747 platform_set_drvdata(pdev, data);
3749 switch (data->kind) {
3753 data->auto_pwm_num = 4;
3754 data->temp_fixed_num = 3;
3755 data->num_temp_alarms = 6;
3756 data->num_temp_beeps = 6;
3758 data->fan_from_reg = fan_from_reg13;
3759 data->fan_from_reg_min = fan_from_reg13;
3761 data->temp_label = nct6776_temp_label;
3762 data->temp_mask = NCT6776_TEMP_MASK;
3763 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3765 data->REG_VBAT = NCT6106_REG_VBAT;
3766 data->REG_DIODE = NCT6106_REG_DIODE;
3767 data->DIODE_MASK = NCT6106_DIODE_MASK;
3768 data->REG_VIN = NCT6106_REG_IN;
3769 data->REG_IN_MINMAX[0] = NCT6106_REG_IN_MIN;
3770 data->REG_IN_MINMAX[1] = NCT6106_REG_IN_MAX;
3771 data->REG_TARGET = NCT6106_REG_TARGET;
3772 data->REG_FAN = NCT6106_REG_FAN;
3773 data->REG_FAN_MODE = NCT6106_REG_FAN_MODE;
3774 data->REG_FAN_MIN = NCT6106_REG_FAN_MIN;
3775 data->REG_FAN_PULSES = NCT6106_REG_FAN_PULSES;
3776 data->FAN_PULSE_SHIFT = NCT6106_FAN_PULSE_SHIFT;
3777 data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME;
3778 data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME;
3779 data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME;
3780 data->REG_PWM[0] = NCT6106_REG_PWM;
3781 data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT;
3782 data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT;
3783 data->REG_PWM[5] = NCT6106_REG_WEIGHT_DUTY_STEP;
3784 data->REG_PWM[6] = NCT6106_REG_WEIGHT_DUTY_BASE;
3785 data->REG_PWM_READ = NCT6106_REG_PWM_READ;
3786 data->REG_PWM_MODE = NCT6106_REG_PWM_MODE;
3787 data->PWM_MODE_MASK = NCT6106_PWM_MODE_MASK;
3788 data->REG_AUTO_TEMP = NCT6106_REG_AUTO_TEMP;
3789 data->REG_AUTO_PWM = NCT6106_REG_AUTO_PWM;
3790 data->REG_CRITICAL_TEMP = NCT6106_REG_CRITICAL_TEMP;
3791 data->REG_CRITICAL_TEMP_TOLERANCE
3792 = NCT6106_REG_CRITICAL_TEMP_TOLERANCE;
3793 data->REG_CRITICAL_PWM_ENABLE = NCT6106_REG_CRITICAL_PWM_ENABLE;
3794 data->CRITICAL_PWM_ENABLE_MASK
3795 = NCT6106_CRITICAL_PWM_ENABLE_MASK;
3796 data->REG_CRITICAL_PWM = NCT6106_REG_CRITICAL_PWM;
3797 data->REG_TEMP_OFFSET = NCT6106_REG_TEMP_OFFSET;
3798 data->REG_TEMP_SOURCE = NCT6106_REG_TEMP_SOURCE;
3799 data->REG_TEMP_SEL = NCT6106_REG_TEMP_SEL;
3800 data->REG_WEIGHT_TEMP_SEL = NCT6106_REG_WEIGHT_TEMP_SEL;
3801 data->REG_WEIGHT_TEMP[0] = NCT6106_REG_WEIGHT_TEMP_STEP;
3802 data->REG_WEIGHT_TEMP[1] = NCT6106_REG_WEIGHT_TEMP_STEP_TOL;
3803 data->REG_WEIGHT_TEMP[2] = NCT6106_REG_WEIGHT_TEMP_BASE;
3804 data->REG_ALARM = NCT6106_REG_ALARM;
3805 data->ALARM_BITS = NCT6106_ALARM_BITS;
3806 data->REG_BEEP = NCT6106_REG_BEEP;
3807 data->BEEP_BITS = NCT6106_BEEP_BITS;
3809 reg_temp = NCT6106_REG_TEMP;
3810 reg_temp_mon = NCT6106_REG_TEMP_MON;
3811 num_reg_temp = ARRAY_SIZE(NCT6106_REG_TEMP);
3812 num_reg_temp_mon = ARRAY_SIZE(NCT6106_REG_TEMP_MON);
3813 reg_temp_over = NCT6106_REG_TEMP_OVER;
3814 reg_temp_hyst = NCT6106_REG_TEMP_HYST;
3815 reg_temp_config = NCT6106_REG_TEMP_CONFIG;
3816 reg_temp_alternate = NCT6106_REG_TEMP_ALTERNATE;
3817 reg_temp_crit = NCT6106_REG_TEMP_CRIT;
3818 reg_temp_crit_l = NCT6106_REG_TEMP_CRIT_L;
3819 reg_temp_crit_h = NCT6106_REG_TEMP_CRIT_H;
3825 data->auto_pwm_num = 6;
3826 data->has_fan_div = true;
3827 data->temp_fixed_num = 3;
3828 data->num_temp_alarms = 3;
3829 data->num_temp_beeps = 3;
3831 data->ALARM_BITS = NCT6775_ALARM_BITS;
3832 data->BEEP_BITS = NCT6775_BEEP_BITS;
3834 data->fan_from_reg = fan_from_reg16;
3835 data->fan_from_reg_min = fan_from_reg8;
3836 data->target_temp_mask = 0x7f;
3837 data->tolerance_mask = 0x0f;
3838 data->speed_tolerance_limit = 15;
3840 data->temp_label = nct6775_temp_label;
3841 data->temp_mask = NCT6775_TEMP_MASK;
3842 data->virt_temp_mask = NCT6775_VIRT_TEMP_MASK;
3844 data->REG_CONFIG = NCT6775_REG_CONFIG;
3845 data->REG_VBAT = NCT6775_REG_VBAT;
3846 data->REG_DIODE = NCT6775_REG_DIODE;
3847 data->DIODE_MASK = NCT6775_DIODE_MASK;
3848 data->REG_VIN = NCT6775_REG_IN;
3849 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3850 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3851 data->REG_TARGET = NCT6775_REG_TARGET;
3852 data->REG_FAN = NCT6775_REG_FAN;
3853 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3854 data->REG_FAN_MIN = NCT6775_REG_FAN_MIN;
3855 data->REG_FAN_PULSES = NCT6775_REG_FAN_PULSES;
3856 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3857 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3858 data->REG_FAN_TIME[1] = NCT6775_REG_FAN_STEP_UP_TIME;
3859 data->REG_FAN_TIME[2] = NCT6775_REG_FAN_STEP_DOWN_TIME;
3860 data->REG_PWM[0] = NCT6775_REG_PWM;
3861 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3862 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3863 data->REG_PWM[3] = NCT6775_REG_FAN_MAX_OUTPUT;
3864 data->REG_PWM[4] = NCT6775_REG_FAN_STEP_OUTPUT;
3865 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3866 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3867 data->REG_PWM_MODE = NCT6775_REG_PWM_MODE;
3868 data->PWM_MODE_MASK = NCT6775_PWM_MODE_MASK;
3869 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3870 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3871 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3872 data->REG_CRITICAL_TEMP_TOLERANCE
3873 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3874 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3875 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3876 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3877 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3878 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3879 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3880 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3881 data->REG_ALARM = NCT6775_REG_ALARM;
3882 data->REG_BEEP = NCT6775_REG_BEEP;
3884 reg_temp = NCT6775_REG_TEMP;
3885 reg_temp_mon = NCT6775_REG_TEMP_MON;
3886 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3887 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3888 reg_temp_over = NCT6775_REG_TEMP_OVER;
3889 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3890 reg_temp_config = NCT6775_REG_TEMP_CONFIG;
3891 reg_temp_alternate = NCT6775_REG_TEMP_ALTERNATE;
3892 reg_temp_crit = NCT6775_REG_TEMP_CRIT;
3898 data->auto_pwm_num = 4;
3899 data->has_fan_div = false;
3900 data->temp_fixed_num = 3;
3901 data->num_temp_alarms = 3;
3902 data->num_temp_beeps = 6;
3904 data->ALARM_BITS = NCT6776_ALARM_BITS;
3905 data->BEEP_BITS = NCT6776_BEEP_BITS;
3907 data->fan_from_reg = fan_from_reg13;
3908 data->fan_from_reg_min = fan_from_reg13;
3909 data->target_temp_mask = 0xff;
3910 data->tolerance_mask = 0x07;
3911 data->speed_tolerance_limit = 63;
3913 data->temp_label = nct6776_temp_label;
3914 data->temp_mask = NCT6776_TEMP_MASK;
3915 data->virt_temp_mask = NCT6776_VIRT_TEMP_MASK;
3917 data->REG_CONFIG = NCT6775_REG_CONFIG;
3918 data->REG_VBAT = NCT6775_REG_VBAT;
3919 data->REG_DIODE = NCT6775_REG_DIODE;
3920 data->DIODE_MASK = NCT6775_DIODE_MASK;
3921 data->REG_VIN = NCT6775_REG_IN;
3922 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3923 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3924 data->REG_TARGET = NCT6775_REG_TARGET;
3925 data->REG_FAN = NCT6775_REG_FAN;
3926 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
3927 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
3928 data->REG_FAN_PULSES = NCT6776_REG_FAN_PULSES;
3929 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
3930 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
3931 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
3932 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
3933 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
3934 data->REG_PWM[0] = NCT6775_REG_PWM;
3935 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
3936 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
3937 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
3938 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
3939 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
3940 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
3941 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
3942 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
3943 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
3944 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
3945 data->REG_CRITICAL_TEMP_TOLERANCE
3946 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
3947 data->REG_TEMP_OFFSET = NCT6775_REG_TEMP_OFFSET;
3948 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
3949 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
3950 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
3951 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
3952 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
3953 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
3954 data->REG_ALARM = NCT6775_REG_ALARM;
3955 data->REG_BEEP = NCT6776_REG_BEEP;
3957 reg_temp = NCT6775_REG_TEMP;
3958 reg_temp_mon = NCT6775_REG_TEMP_MON;
3959 num_reg_temp = ARRAY_SIZE(NCT6775_REG_TEMP);
3960 num_reg_temp_mon = ARRAY_SIZE(NCT6775_REG_TEMP_MON);
3961 reg_temp_over = NCT6775_REG_TEMP_OVER;
3962 reg_temp_hyst = NCT6775_REG_TEMP_HYST;
3963 reg_temp_config = NCT6776_REG_TEMP_CONFIG;
3964 reg_temp_alternate = NCT6776_REG_TEMP_ALTERNATE;
3965 reg_temp_crit = NCT6776_REG_TEMP_CRIT;
3971 data->auto_pwm_num = 4;
3972 data->has_fan_div = false;
3973 data->temp_fixed_num = 6;
3974 data->num_temp_alarms = 2;
3975 data->num_temp_beeps = 2;
3977 data->ALARM_BITS = NCT6779_ALARM_BITS;
3978 data->BEEP_BITS = NCT6779_BEEP_BITS;
3980 data->fan_from_reg = fan_from_reg_rpm;
3981 data->fan_from_reg_min = fan_from_reg13;
3982 data->target_temp_mask = 0xff;
3983 data->tolerance_mask = 0x07;
3984 data->speed_tolerance_limit = 63;
3986 data->temp_label = nct6779_temp_label;
3987 data->temp_mask = NCT6779_TEMP_MASK;
3988 data->virt_temp_mask = NCT6779_VIRT_TEMP_MASK;
3990 data->REG_CONFIG = NCT6775_REG_CONFIG;
3991 data->REG_VBAT = NCT6775_REG_VBAT;
3992 data->REG_DIODE = NCT6775_REG_DIODE;
3993 data->DIODE_MASK = NCT6775_DIODE_MASK;
3994 data->REG_VIN = NCT6779_REG_IN;
3995 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
3996 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
3997 data->REG_TARGET = NCT6775_REG_TARGET;
3998 data->REG_FAN = NCT6779_REG_FAN;
3999 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4000 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4001 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4002 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4003 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4004 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4005 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4006 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4007 data->REG_PWM[0] = NCT6775_REG_PWM;
4008 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4009 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4010 data->REG_PWM[5] = NCT6775_REG_WEIGHT_DUTY_STEP;
4011 data->REG_PWM[6] = NCT6776_REG_WEIGHT_DUTY_BASE;
4012 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4013 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4014 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4015 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4016 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4017 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4018 data->REG_CRITICAL_TEMP_TOLERANCE
4019 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4020 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4021 data->CRITICAL_PWM_ENABLE_MASK
4022 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4023 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4024 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4025 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4026 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4027 data->REG_WEIGHT_TEMP_SEL = NCT6775_REG_WEIGHT_TEMP_SEL;
4028 data->REG_WEIGHT_TEMP[0] = NCT6775_REG_WEIGHT_TEMP_STEP;
4029 data->REG_WEIGHT_TEMP[1] = NCT6775_REG_WEIGHT_TEMP_STEP_TOL;
4030 data->REG_WEIGHT_TEMP[2] = NCT6775_REG_WEIGHT_TEMP_BASE;
4031 data->REG_ALARM = NCT6779_REG_ALARM;
4032 data->REG_BEEP = NCT6776_REG_BEEP;
4034 reg_temp = NCT6779_REG_TEMP;
4035 reg_temp_mon = NCT6779_REG_TEMP_MON;
4036 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4037 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4038 reg_temp_over = NCT6779_REG_TEMP_OVER;
4039 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4040 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4041 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4042 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4053 data->pwm_num = (data->kind == nct6796 ||
4054 data->kind == nct6797 ||
4055 data->kind == nct6798) ? 7 : 6;
4056 data->auto_pwm_num = 4;
4057 data->has_fan_div = false;
4058 data->temp_fixed_num = 6;
4059 data->num_temp_alarms = 2;
4060 data->num_temp_beeps = 2;
4062 data->ALARM_BITS = NCT6791_ALARM_BITS;
4063 data->BEEP_BITS = NCT6779_BEEP_BITS;
4065 data->fan_from_reg = fan_from_reg_rpm;
4066 data->fan_from_reg_min = fan_from_reg13;
4067 data->target_temp_mask = 0xff;
4068 data->tolerance_mask = 0x07;
4069 data->speed_tolerance_limit = 63;
4071 switch (data->kind) {
4074 data->temp_label = nct6779_temp_label;
4075 data->temp_mask = NCT6791_TEMP_MASK;
4076 data->virt_temp_mask = NCT6791_VIRT_TEMP_MASK;
4079 data->temp_label = nct6792_temp_label;
4080 data->temp_mask = NCT6792_TEMP_MASK;
4081 data->virt_temp_mask = NCT6792_VIRT_TEMP_MASK;
4084 data->temp_label = nct6793_temp_label;
4085 data->temp_mask = NCT6793_TEMP_MASK;
4086 data->virt_temp_mask = NCT6793_VIRT_TEMP_MASK;
4090 data->temp_label = nct6795_temp_label;
4091 data->temp_mask = NCT6795_TEMP_MASK;
4092 data->virt_temp_mask = NCT6795_VIRT_TEMP_MASK;
4095 data->temp_label = nct6796_temp_label;
4096 data->temp_mask = NCT6796_TEMP_MASK;
4097 data->virt_temp_mask = NCT6796_VIRT_TEMP_MASK;
4100 data->temp_label = nct6798_temp_label;
4101 data->temp_mask = NCT6798_TEMP_MASK;
4102 data->virt_temp_mask = NCT6798_VIRT_TEMP_MASK;
4106 data->REG_CONFIG = NCT6775_REG_CONFIG;
4107 data->REG_VBAT = NCT6775_REG_VBAT;
4108 data->REG_DIODE = NCT6775_REG_DIODE;
4109 data->DIODE_MASK = NCT6775_DIODE_MASK;
4110 data->REG_VIN = NCT6779_REG_IN;
4111 data->REG_IN_MINMAX[0] = NCT6775_REG_IN_MIN;
4112 data->REG_IN_MINMAX[1] = NCT6775_REG_IN_MAX;
4113 data->REG_TARGET = NCT6775_REG_TARGET;
4114 data->REG_FAN = NCT6779_REG_FAN;
4115 data->REG_FAN_MODE = NCT6775_REG_FAN_MODE;
4116 data->REG_FAN_MIN = NCT6776_REG_FAN_MIN;
4117 data->REG_FAN_PULSES = NCT6779_REG_FAN_PULSES;
4118 data->FAN_PULSE_SHIFT = NCT6775_FAN_PULSE_SHIFT;
4119 data->REG_FAN_TIME[0] = NCT6775_REG_FAN_STOP_TIME;
4120 data->REG_FAN_TIME[1] = NCT6776_REG_FAN_STEP_UP_TIME;
4121 data->REG_FAN_TIME[2] = NCT6776_REG_FAN_STEP_DOWN_TIME;
4122 data->REG_TOLERANCE_H = NCT6776_REG_TOLERANCE_H;
4123 data->REG_PWM[0] = NCT6775_REG_PWM;
4124 data->REG_PWM[1] = NCT6775_REG_FAN_START_OUTPUT;
4125 data->REG_PWM[2] = NCT6775_REG_FAN_STOP_OUTPUT;
4126 data->REG_PWM[5] = NCT6791_REG_WEIGHT_DUTY_STEP;
4127 data->REG_PWM[6] = NCT6791_REG_WEIGHT_DUTY_BASE;
4128 data->REG_PWM_READ = NCT6775_REG_PWM_READ;
4129 data->REG_PWM_MODE = NCT6776_REG_PWM_MODE;
4130 data->PWM_MODE_MASK = NCT6776_PWM_MODE_MASK;
4131 data->REG_AUTO_TEMP = NCT6775_REG_AUTO_TEMP;
4132 data->REG_AUTO_PWM = NCT6775_REG_AUTO_PWM;
4133 data->REG_CRITICAL_TEMP = NCT6775_REG_CRITICAL_TEMP;
4134 data->REG_CRITICAL_TEMP_TOLERANCE
4135 = NCT6775_REG_CRITICAL_TEMP_TOLERANCE;
4136 data->REG_CRITICAL_PWM_ENABLE = NCT6779_REG_CRITICAL_PWM_ENABLE;
4137 data->CRITICAL_PWM_ENABLE_MASK
4138 = NCT6779_CRITICAL_PWM_ENABLE_MASK;
4139 data->REG_CRITICAL_PWM = NCT6779_REG_CRITICAL_PWM;
4140 data->REG_TEMP_OFFSET = NCT6779_REG_TEMP_OFFSET;
4141 data->REG_TEMP_SOURCE = NCT6775_REG_TEMP_SOURCE;
4142 data->REG_TEMP_SEL = NCT6775_REG_TEMP_SEL;
4143 data->REG_WEIGHT_TEMP_SEL = NCT6791_REG_WEIGHT_TEMP_SEL;
4144 data->REG_WEIGHT_TEMP[0] = NCT6791_REG_WEIGHT_TEMP_STEP;
4145 data->REG_WEIGHT_TEMP[1] = NCT6791_REG_WEIGHT_TEMP_STEP_TOL;
4146 data->REG_WEIGHT_TEMP[2] = NCT6791_REG_WEIGHT_TEMP_BASE;
4147 data->REG_ALARM = NCT6791_REG_ALARM;
4148 if (data->kind == nct6791)
4149 data->REG_BEEP = NCT6776_REG_BEEP;
4151 data->REG_BEEP = NCT6792_REG_BEEP;
4153 reg_temp = NCT6779_REG_TEMP;
4154 num_reg_temp = ARRAY_SIZE(NCT6779_REG_TEMP);
4155 if (data->kind == nct6791) {
4156 reg_temp_mon = NCT6779_REG_TEMP_MON;
4157 num_reg_temp_mon = ARRAY_SIZE(NCT6779_REG_TEMP_MON);
4159 reg_temp_mon = NCT6792_REG_TEMP_MON;
4160 num_reg_temp_mon = ARRAY_SIZE(NCT6792_REG_TEMP_MON);
4162 reg_temp_over = NCT6779_REG_TEMP_OVER;
4163 reg_temp_hyst = NCT6779_REG_TEMP_HYST;
4164 reg_temp_config = NCT6779_REG_TEMP_CONFIG;
4165 reg_temp_alternate = NCT6779_REG_TEMP_ALTERNATE;
4166 reg_temp_crit = NCT6779_REG_TEMP_CRIT;
4172 data->have_in = BIT(data->in_num) - 1;
4173 data->have_temp = 0;
4176 * On some boards, not all available temperature sources are monitored,
4177 * even though some of the monitoring registers are unused.
4178 * Get list of unused monitoring registers, then detect if any fan
4179 * controls are configured to use unmonitored temperature sources.
4180 * If so, assign the unmonitored temperature sources to available
4181 * monitoring registers.
4185 for (i = 0; i < num_reg_temp; i++) {
4186 if (reg_temp[i] == 0)
4189 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4190 if (!src || (mask & BIT(src)))
4191 available |= BIT(i);
4197 * Now find unmonitored temperature registers and enable monitoring
4198 * if additional monitoring registers are available.
4200 add_temp_sensors(data, data->REG_TEMP_SEL, &available, &mask);
4201 add_temp_sensors(data, data->REG_WEIGHT_TEMP_SEL, &available, &mask);
4204 s = NUM_TEMP_FIXED; /* First dynamic temperature attribute */
4205 for (i = 0; i < num_reg_temp; i++) {
4206 if (reg_temp[i] == 0)
4209 src = nct6775_read_value(data, data->REG_TEMP_SOURCE[i]) & 0x1f;
4210 if (!src || (mask & BIT(src)))
4213 if (!(data->temp_mask & BIT(src))) {
4215 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4216 src, i, data->REG_TEMP_SOURCE[i], reg_temp[i]);
4222 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4223 if (src <= data->temp_fixed_num) {
4224 data->have_temp |= BIT(src - 1);
4225 data->have_temp_fixed |= BIT(src - 1);
4226 data->reg_temp[0][src - 1] = reg_temp[i];
4227 data->reg_temp[1][src - 1] = reg_temp_over[i];
4228 data->reg_temp[2][src - 1] = reg_temp_hyst[i];
4229 if (reg_temp_crit_h && reg_temp_crit_h[i])
4230 data->reg_temp[3][src - 1] = reg_temp_crit_h[i];
4231 else if (reg_temp_crit[src - 1])
4232 data->reg_temp[3][src - 1]
4233 = reg_temp_crit[src - 1];
4234 if (reg_temp_crit_l && reg_temp_crit_l[i])
4235 data->reg_temp[4][src - 1] = reg_temp_crit_l[i];
4236 data->reg_temp_config[src - 1] = reg_temp_config[i];
4237 data->temp_src[src - 1] = src;
4244 /* Use dynamic index for other sources */
4245 data->have_temp |= BIT(s);
4246 data->reg_temp[0][s] = reg_temp[i];
4247 data->reg_temp[1][s] = reg_temp_over[i];
4248 data->reg_temp[2][s] = reg_temp_hyst[i];
4249 data->reg_temp_config[s] = reg_temp_config[i];
4250 if (reg_temp_crit_h && reg_temp_crit_h[i])
4251 data->reg_temp[3][s] = reg_temp_crit_h[i];
4252 else if (reg_temp_crit[src - 1])
4253 data->reg_temp[3][s] = reg_temp_crit[src - 1];
4254 if (reg_temp_crit_l && reg_temp_crit_l[i])
4255 data->reg_temp[4][s] = reg_temp_crit_l[i];
4257 data->temp_src[s] = src;
4262 * Repeat with temperatures used for fan control.
4263 * This set of registers does not support limits.
4265 for (i = 0; i < num_reg_temp_mon; i++) {
4266 if (reg_temp_mon[i] == 0)
4269 src = nct6775_read_value(data, data->REG_TEMP_SEL[i]) & 0x1f;
4273 if (!(data->temp_mask & BIT(src))) {
4275 "Invalid temperature source %d at index %d, source register 0x%x, temp register 0x%x\n",
4276 src, i, data->REG_TEMP_SEL[i],
4282 * For virtual temperature sources, the 'virtual' temperature
4283 * for each fan reflects a different temperature, and there
4284 * are no duplicates.
4286 if (!(data->virt_temp_mask & BIT(src))) {
4287 if (mask & BIT(src))
4292 /* Use fixed index for SYSTIN(1), CPUTIN(2), AUXTIN(3) */
4293 if (src <= data->temp_fixed_num) {
4294 if (data->have_temp & BIT(src - 1))
4296 data->have_temp |= BIT(src - 1);
4297 data->have_temp_fixed |= BIT(src - 1);
4298 data->reg_temp[0][src - 1] = reg_temp_mon[i];
4299 data->temp_src[src - 1] = src;
4306 /* Use dynamic index for other sources */
4307 data->have_temp |= BIT(s);
4308 data->reg_temp[0][s] = reg_temp_mon[i];
4309 data->temp_src[s] = src;
4313 #ifdef USE_ALTERNATE
4315 * Go through the list of alternate temp registers and enable
4317 * The temperature is already monitored if the respective bit in <mask>
4320 for (i = 0; i < 31; i++) {
4321 if (!(data->temp_mask & BIT(i + 1)))
4323 if (!reg_temp_alternate[i])
4325 if (mask & BIT(i + 1))
4327 if (i < data->temp_fixed_num) {
4328 if (data->have_temp & BIT(i))
4330 data->have_temp |= BIT(i);
4331 data->have_temp_fixed |= BIT(i);
4332 data->reg_temp[0][i] = reg_temp_alternate[i];
4333 if (i < num_reg_temp) {
4334 data->reg_temp[1][i] = reg_temp_over[i];
4335 data->reg_temp[2][i] = reg_temp_hyst[i];
4337 data->temp_src[i] = i + 1;
4341 if (s >= NUM_TEMP) /* Abort if no more space */
4344 data->have_temp |= BIT(s);
4345 data->reg_temp[0][s] = reg_temp_alternate[i];
4346 data->temp_src[s] = i + 1;
4349 #endif /* USE_ALTERNATE */
4351 /* Initialize the chip */
4352 nct6775_init_device(data);
4354 err = superio_enter(sio_data->sioreg);
4358 cr2a = superio_inb(sio_data->sioreg, 0x2a);
4359 switch (data->kind) {
4361 data->have_vid = (cr2a & 0x40);
4364 data->have_vid = (cr2a & 0x60) == 0x40;
4380 * We can get the VID input values directly at logical device D 0xe3.
4382 if (data->have_vid) {
4383 superio_select(sio_data->sioreg, NCT6775_LD_VID);
4384 data->vid = superio_inb(sio_data->sioreg, 0xe3);
4385 data->vrm = vid_which_vrm();
4391 superio_select(sio_data->sioreg, NCT6775_LD_HWM);
4392 tmp = superio_inb(sio_data->sioreg,
4393 NCT6775_REG_CR_FAN_DEBOUNCE);
4394 switch (data->kind) {
4415 superio_outb(sio_data->sioreg, NCT6775_REG_CR_FAN_DEBOUNCE,
4417 dev_info(&pdev->dev, "Enabled fan debounce for chip %s\n",
4421 nct6775_check_fan_inputs(data);
4423 superio_exit(sio_data->sioreg);
4425 /* Read fan clock dividers immediately */
4426 nct6775_init_fan_common(dev, data);
4428 /* Register sysfs hooks */
4429 group = nct6775_create_attr_group(dev, &nct6775_pwm_template_group,
4432 return PTR_ERR(group);
4434 data->groups[num_attr_groups++] = group;
4436 group = nct6775_create_attr_group(dev, &nct6775_in_template_group,
4437 fls(data->have_in));
4439 return PTR_ERR(group);
4441 data->groups[num_attr_groups++] = group;
4443 group = nct6775_create_attr_group(dev, &nct6775_fan_template_group,
4444 fls(data->has_fan));
4446 return PTR_ERR(group);
4448 data->groups[num_attr_groups++] = group;
4450 group = nct6775_create_attr_group(dev, &nct6775_temp_template_group,
4451 fls(data->have_temp));
4453 return PTR_ERR(group);
4455 data->groups[num_attr_groups++] = group;
4456 data->groups[num_attr_groups++] = &nct6775_group_other;
4458 hwmon_dev = devm_hwmon_device_register_with_groups(dev, data->name,
4459 data, data->groups);
4460 return PTR_ERR_OR_ZERO(hwmon_dev);
4463 static void nct6791_enable_io_mapping(int sioaddr)
4467 val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE);
4469 pr_info("Enabling hardware monitor logical device mappings.\n");
4470 superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE,
4475 static int __maybe_unused nct6775_suspend(struct device *dev)
4477 struct nct6775_data *data = nct6775_update_device(dev);
4479 mutex_lock(&data->update_lock);
4480 data->vbat = nct6775_read_value(data, data->REG_VBAT);
4481 if (data->kind == nct6775) {
4482 data->fandiv1 = nct6775_read_value(data, NCT6775_REG_FANDIV1);
4483 data->fandiv2 = nct6775_read_value(data, NCT6775_REG_FANDIV2);
4485 mutex_unlock(&data->update_lock);
4490 static int __maybe_unused nct6775_resume(struct device *dev)
4492 struct nct6775_data *data = dev_get_drvdata(dev);
4493 int sioreg = data->sioreg;
4497 mutex_lock(&data->update_lock);
4498 data->bank = 0xff; /* Force initial bank selection */
4500 err = superio_enter(sioreg);
4504 superio_select(sioreg, NCT6775_LD_HWM);
4505 reg = superio_inb(sioreg, SIO_REG_ENABLE);
4506 if (reg != data->sio_reg_enable)
4507 superio_outb(sioreg, SIO_REG_ENABLE, data->sio_reg_enable);
4509 if (data->kind == nct6791 || data->kind == nct6792 ||
4510 data->kind == nct6793 || data->kind == nct6795 ||
4511 data->kind == nct6796)
4512 nct6791_enable_io_mapping(sioreg);
4514 superio_exit(sioreg);
4516 /* Restore limits */
4517 for (i = 0; i < data->in_num; i++) {
4518 if (!(data->have_in & BIT(i)))
4521 nct6775_write_value(data, data->REG_IN_MINMAX[0][i],
4523 nct6775_write_value(data, data->REG_IN_MINMAX[1][i],
4527 for (i = 0; i < ARRAY_SIZE(data->fan_min); i++) {
4528 if (!(data->has_fan_min & BIT(i)))
4531 nct6775_write_value(data, data->REG_FAN_MIN[i],
4535 for (i = 0; i < NUM_TEMP; i++) {
4536 if (!(data->have_temp & BIT(i)))
4539 for (j = 1; j < ARRAY_SIZE(data->reg_temp); j++)
4540 if (data->reg_temp[j][i])
4541 nct6775_write_temp(data, data->reg_temp[j][i],
4545 /* Restore other settings */
4546 nct6775_write_value(data, data->REG_VBAT, data->vbat);
4547 if (data->kind == nct6775) {
4548 nct6775_write_value(data, NCT6775_REG_FANDIV1, data->fandiv1);
4549 nct6775_write_value(data, NCT6775_REG_FANDIV2, data->fandiv2);
4553 /* Force re-reading all values */
4554 data->valid = false;
4555 mutex_unlock(&data->update_lock);
4560 static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume);
4562 static struct platform_driver nct6775_driver = {
4565 .pm = &nct6775_dev_pm_ops,
4567 .probe = nct6775_probe,
4570 /* nct6775_find() looks for a '627 in the Super-I/O config space */
4571 static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data)
4577 err = superio_enter(sioaddr);
4581 val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) |
4582 superio_inb(sioaddr, SIO_REG_DEVID + 1);
4583 if (force_id && val != 0xffff)
4586 switch (val & SIO_ID_MASK) {
4587 case SIO_NCT6106_ID:
4588 sio_data->kind = nct6106;
4590 case SIO_NCT6775_ID:
4591 sio_data->kind = nct6775;
4593 case SIO_NCT6776_ID:
4594 sio_data->kind = nct6776;
4596 case SIO_NCT6779_ID:
4597 sio_data->kind = nct6779;
4599 case SIO_NCT6791_ID:
4600 sio_data->kind = nct6791;
4602 case SIO_NCT6792_ID:
4603 sio_data->kind = nct6792;
4605 case SIO_NCT6793_ID:
4606 sio_data->kind = nct6793;
4608 case SIO_NCT6795_ID:
4609 sio_data->kind = nct6795;
4611 case SIO_NCT6796_ID:
4612 sio_data->kind = nct6796;
4614 case SIO_NCT6797_ID:
4615 sio_data->kind = nct6797;
4617 case SIO_NCT6798_ID:
4618 sio_data->kind = nct6798;
4622 pr_debug("unsupported chip ID: 0x%04x\n", val);
4623 superio_exit(sioaddr);
4627 /* We have a known chip, find the HWM I/O address */
4628 superio_select(sioaddr, NCT6775_LD_HWM);
4629 val = (superio_inb(sioaddr, SIO_REG_ADDR) << 8)
4630 | superio_inb(sioaddr, SIO_REG_ADDR + 1);
4631 addr = val & IOREGION_ALIGNMENT;
4633 pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n");
4634 superio_exit(sioaddr);
4638 /* Activate logical device if needed */
4639 val = superio_inb(sioaddr, SIO_REG_ENABLE);
4640 if (!(val & 0x01)) {
4641 pr_warn("Forcibly enabling Super-I/O. Sensor is probably unusable.\n");
4642 superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
4645 if (sio_data->kind == nct6791 || sio_data->kind == nct6792 ||
4646 sio_data->kind == nct6793 || sio_data->kind == nct6795 ||
4647 sio_data->kind == nct6796)
4648 nct6791_enable_io_mapping(sioaddr);
4650 superio_exit(sioaddr);
4651 pr_info("Found %s or compatible chip at %#x:%#x\n",
4652 nct6775_sio_names[sio_data->kind], sioaddr, addr);
4653 sio_data->sioreg = sioaddr;
4659 * when Super-I/O functions move to a separate file, the Super-I/O
4660 * bus will manage the lifetime of the device and this module will only keep
4661 * track of the nct6775 driver. But since we use platform_device_alloc(), we
4662 * must keep track of the device
4664 static struct platform_device *pdev[2];
4666 static int __init sensors_nct6775_init(void)
4671 struct resource res;
4672 struct nct6775_sio_data sio_data;
4673 int sioaddr[2] = { 0x2e, 0x4e };
4675 err = platform_driver_register(&nct6775_driver);
4680 * initialize sio_data->kind and sio_data->sioreg.
4682 * when Super-I/O functions move to a separate file, the Super-I/O
4683 * driver will probe 0x2e and 0x4e and auto-detect the presence of a
4684 * nct6775 hardware monitor, and call probe()
4686 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4687 address = nct6775_find(sioaddr[i], &sio_data);
4693 pdev[i] = platform_device_alloc(DRVNAME, address);
4696 goto exit_device_unregister;
4699 err = platform_device_add_data(pdev[i], &sio_data,
4700 sizeof(struct nct6775_sio_data));
4702 goto exit_device_put;
4704 memset(&res, 0, sizeof(res));
4706 res.start = address + IOREGION_OFFSET;
4707 res.end = address + IOREGION_OFFSET + IOREGION_LENGTH - 1;
4708 res.flags = IORESOURCE_IO;
4710 err = acpi_check_resource_conflict(&res);
4712 platform_device_put(pdev[i]);
4717 err = platform_device_add_resources(pdev[i], &res, 1);
4719 goto exit_device_put;
4721 /* platform_device_add calls probe() */
4722 err = platform_device_add(pdev[i]);
4724 goto exit_device_put;
4728 goto exit_unregister;
4734 platform_device_put(pdev[i]);
4735 exit_device_unregister:
4738 platform_device_unregister(pdev[i]);
4741 platform_driver_unregister(&nct6775_driver);
4745 static void __exit sensors_nct6775_exit(void)
4749 for (i = 0; i < ARRAY_SIZE(pdev); i++) {
4751 platform_device_unregister(pdev[i]);
4753 platform_driver_unregister(&nct6775_driver);
4756 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
4757 MODULE_DESCRIPTION("Driver for NCT6775F and compatible chips");
4758 MODULE_LICENSE("GPL");
4760 module_init(sensors_nct6775_init);
4761 module_exit(sensors_nct6775_exit);