1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
5 * Copyright (c) 2015 Kontron
6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
8 * Copyright (c) 2019 Advantech
9 * Author: Amy.Shih <amy.shih@advantech.com.tw>
12 #include <linux/module.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/mutex.h>
17 #include <linux/hwmon.h>
19 #define VENDOR_ID_REG 0x7A /* Any bank */
20 #define NUVOTON_ID 0x50
21 #define CHIP_ID_REG 0x7B /* Any bank */
22 #define NCT7904_ID 0xC5
23 #define DEVICE_ID_REG 0x7C /* Any bank */
25 #define BANK_SEL_REG 0xFF
33 #define FANIN_MAX 12 /* Counted from 1 */
34 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB,
35 LTD (not a voltage), VSEN17..19 */
36 #define FANCTL_MAX 4 /* Counted from 1 */
37 #define TCPU_MAX 8 /* Counted from 1 */
38 #define TEMP_MAX 4 /* Counted from 1 */
40 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
41 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
42 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
43 #define FANIN_CTRL0_REG 0x24
44 #define FANIN_CTRL1_REG 0x25
45 #define DTS_T_CTRL0_REG 0x26
46 #define DTS_T_CTRL1_REG 0x27
47 #define VT_ADC_MD_REG 0x2E
49 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
50 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
51 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
52 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
53 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */
54 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */
55 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */
56 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */
57 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */
59 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
60 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */
61 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
62 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */
63 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */
64 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */
65 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */
66 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */
67 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */
68 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */
69 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
70 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
71 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
72 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */
73 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */
74 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
75 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
76 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */
77 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */
79 #define PRTS_REG 0x03 /* Bank 2 */
80 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */
81 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */
82 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */
83 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */
85 #define ENABLE_TSI BIT(1)
87 static const unsigned short normal_i2c[] = {
88 0x2d, 0x2e, I2C_CLIENT_END
92 struct i2c_client *client;
93 struct mutex bank_lock;
98 u8 fan_mode[FANCTL_MAX];
101 u8 temp_mode; /* 0: TR mode, 1: TD mode */
104 /* Access functions */
105 static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
109 mutex_lock(&data->bank_lock);
110 if (data->bank_sel == bank)
112 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
114 data->bank_sel = bank;
120 static inline void nct7904_bank_release(struct nct7904_data *data)
122 mutex_unlock(&data->bank_lock);
125 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
126 static int nct7904_read_reg(struct nct7904_data *data,
127 unsigned int bank, unsigned int reg)
129 struct i2c_client *client = data->client;
132 ret = nct7904_bank_lock(data, bank);
134 ret = i2c_smbus_read_byte_data(client, reg);
136 nct7904_bank_release(data);
141 * Read 2-byte register. Returns register in big-endian format or
144 static int nct7904_read_reg16(struct nct7904_data *data,
145 unsigned int bank, unsigned int reg)
147 struct i2c_client *client = data->client;
150 ret = nct7904_bank_lock(data, bank);
152 ret = i2c_smbus_read_byte_data(client, reg);
155 ret = i2c_smbus_read_byte_data(client, reg + 1);
161 nct7904_bank_release(data);
165 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
166 static int nct7904_write_reg(struct nct7904_data *data,
167 unsigned int bank, unsigned int reg, u8 val)
169 struct i2c_client *client = data->client;
172 ret = nct7904_bank_lock(data, bank);
174 ret = i2c_smbus_write_byte_data(client, reg, val);
176 nct7904_bank_release(data);
180 static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
183 struct nct7904_data *data = dev_get_drvdata(dev);
184 unsigned int cnt, rpm;
188 case hwmon_fan_input:
189 ret = nct7904_read_reg16(data, BANK_0,
190 FANIN1_HV_REG + channel * 2);
193 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
201 ret = nct7904_read_reg16(data, BANK_1,
202 FANIN1_HV_HL_REG + channel * 2);
205 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
212 case hwmon_fan_alarm:
213 ret = nct7904_read_reg(data, BANK_0,
214 SMI_STS5_REG + (channel >> 3));
217 *val = (ret >> (channel & 0x07)) & 1;
224 static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
226 const struct nct7904_data *data = _data;
229 case hwmon_fan_input:
230 case hwmon_fan_alarm:
231 if (data->fanin_mask & (1 << channel))
235 if (data->fanin_mask & (1 << channel))
245 static u8 nct7904_chan_to_index[] = {
247 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
251 static int nct7904_read_in(struct device *dev, u32 attr, int channel,
254 struct nct7904_data *data = dev_get_drvdata(dev);
255 int ret, volt, index;
257 index = nct7904_chan_to_index[channel];
261 ret = nct7904_read_reg16(data, BANK_0,
262 VSEN1_HV_REG + index * 2);
265 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
267 volt *= 2; /* 0.002V scale */
269 volt *= 6; /* 0.006V scale */
273 ret = nct7904_read_reg16(data, BANK_1,
274 VSEN1_HV_LL_REG + index * 4);
277 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
279 volt *= 2; /* 0.002V scale */
281 volt *= 6; /* 0.006V scale */
285 ret = nct7904_read_reg16(data, BANK_1,
286 VSEN1_HV_HL_REG + index * 4);
289 volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
291 volt *= 2; /* 0.002V scale */
293 volt *= 6; /* 0.006V scale */
297 ret = nct7904_read_reg(data, BANK_0,
298 SMI_STS1_REG + (index >> 3));
301 *val = (ret >> (index & 0x07)) & 1;
308 static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
310 const struct nct7904_data *data = _data;
311 int index = nct7904_chan_to_index[channel];
316 if (channel > 0 && (data->vsen_mask & BIT(index)))
321 if (channel > 0 && (data->vsen_mask & BIT(index)))
331 static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
334 struct nct7904_data *data = dev_get_drvdata(dev);
336 unsigned int reg1, reg2, reg3;
339 case hwmon_temp_input:
341 ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
342 else if (channel < 5)
343 ret = nct7904_read_reg16(data, BANK_0,
344 TEMP_CH1_HV_REG + channel * 4);
346 ret = nct7904_read_reg16(data, BANK_0,
347 T_CPU1_HV_REG + (channel - 5)
351 temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
352 *val = sign_extend32(temp, 10) * 125;
354 case hwmon_temp_alarm:
356 ret = nct7904_read_reg(data, BANK_0,
360 *val = (ret >> 1) & 1;
361 } else if (channel < 4) {
362 ret = nct7904_read_reg(data, BANK_0,
366 *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
368 if ((channel - 5) < 4) {
369 ret = nct7904_read_reg(data, BANK_0,
371 ((channel - 5) >> 3));
374 *val = (ret >> ((channel - 5) & 0x07)) & 1;
376 ret = nct7904_read_reg(data, BANK_0,
378 ((channel - 5) >> 3));
381 *val = (ret >> (((channel - 5) & 0x07) - 4))
386 case hwmon_temp_type:
388 if ((data->tcpu_mask >> channel) & 0x01) {
389 if ((data->temp_mode >> channel) & 0x01)
397 if ((data->has_dts >> (channel - 5)) & 0x01) {
398 if (data->enable_dts & ENABLE_TSI)
408 reg1 = LTD_HV_LL_REG;
409 reg2 = TEMP_CH1_W_REG;
410 reg3 = DTS_T_CPU1_W_REG;
412 case hwmon_temp_max_hyst:
413 reg1 = LTD_LV_LL_REG;
414 reg2 = TEMP_CH1_WH_REG;
415 reg3 = DTS_T_CPU1_WH_REG;
417 case hwmon_temp_crit:
418 reg1 = LTD_HV_HL_REG;
419 reg2 = TEMP_CH1_C_REG;
420 reg3 = DTS_T_CPU1_C_REG;
422 case hwmon_temp_crit_hyst:
423 reg1 = LTD_LV_HL_REG;
424 reg2 = TEMP_CH1_CH_REG;
425 reg3 = DTS_T_CPU1_CH_REG;
432 ret = nct7904_read_reg(data, BANK_1, reg1);
433 else if (channel < 5)
434 ret = nct7904_read_reg(data, BANK_1,
437 ret = nct7904_read_reg(data, BANK_1,
438 reg3 + (channel - 5) * 4);
446 static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
448 const struct nct7904_data *data = _data;
451 case hwmon_temp_input:
452 case hwmon_temp_alarm:
453 case hwmon_temp_type:
455 if (data->tcpu_mask & BIT(channel))
458 if (data->has_dts & BIT(channel - 5))
463 case hwmon_temp_max_hyst:
464 case hwmon_temp_crit:
465 case hwmon_temp_crit_hyst:
467 if (data->tcpu_mask & BIT(channel))
470 if (data->has_dts & BIT(channel - 5))
481 static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
484 struct nct7904_data *data = dev_get_drvdata(dev);
488 case hwmon_pwm_input:
489 ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
494 case hwmon_pwm_enable:
495 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
506 static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
509 struct nct7904_data *data = dev_get_drvdata(dev);
511 unsigned int reg1, reg2, reg3;
513 val = clamp_val(val / 1000, -128, 127);
517 reg1 = LTD_HV_LL_REG;
518 reg2 = TEMP_CH1_W_REG;
519 reg3 = DTS_T_CPU1_W_REG;
521 case hwmon_temp_max_hyst:
522 reg1 = LTD_LV_LL_REG;
523 reg2 = TEMP_CH1_WH_REG;
524 reg3 = DTS_T_CPU1_WH_REG;
526 case hwmon_temp_crit:
527 reg1 = LTD_HV_HL_REG;
528 reg2 = TEMP_CH1_C_REG;
529 reg3 = DTS_T_CPU1_C_REG;
531 case hwmon_temp_crit_hyst:
532 reg1 = LTD_LV_HL_REG;
533 reg2 = TEMP_CH1_CH_REG;
534 reg3 = DTS_T_CPU1_CH_REG;
540 ret = nct7904_write_reg(data, BANK_1, reg1, val);
541 else if (channel < 5)
542 ret = nct7904_write_reg(data, BANK_1,
543 reg2 + channel * 8, val);
545 ret = nct7904_write_reg(data, BANK_1,
546 reg3 + (channel - 5) * 4, val);
551 static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
554 struct nct7904_data *data = dev_get_drvdata(dev);
563 val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
564 tmp = (val >> 5) & 0xff;
565 ret = nct7904_write_reg(data, BANK_1,
566 FANIN1_HV_HL_REG + channel * 2, tmp);
570 ret = nct7904_write_reg(data, BANK_1,
571 FANIN1_LV_HL_REG + channel * 2, tmp);
578 static int nct7904_write_in(struct device *dev, u32 attr, int channel,
581 struct nct7904_data *data = dev_get_drvdata(dev);
584 index = nct7904_chan_to_index[channel];
587 val = val / 2; /* 0.002V scale */
589 val = val / 6; /* 0.006V scale */
591 val = clamp_val(val, 0, 0x7ff);
595 tmp = nct7904_read_reg(data, BANK_1,
596 VSEN1_LV_LL_REG + index * 4);
601 ret = nct7904_write_reg(data, BANK_1,
602 VSEN1_LV_LL_REG + index * 4, tmp);
605 tmp = nct7904_read_reg(data, BANK_1,
606 VSEN1_HV_LL_REG + index * 4);
609 tmp = (val >> 3) & 0xff;
610 ret = nct7904_write_reg(data, BANK_1,
611 VSEN1_HV_LL_REG + index * 4, tmp);
614 tmp = nct7904_read_reg(data, BANK_1,
615 VSEN1_LV_HL_REG + index * 4);
620 ret = nct7904_write_reg(data, BANK_1,
621 VSEN1_LV_HL_REG + index * 4, tmp);
624 tmp = nct7904_read_reg(data, BANK_1,
625 VSEN1_HV_HL_REG + index * 4);
628 tmp = (val >> 3) & 0xff;
629 ret = nct7904_write_reg(data, BANK_1,
630 VSEN1_HV_HL_REG + index * 4, tmp);
637 static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
640 struct nct7904_data *data = dev_get_drvdata(dev);
644 case hwmon_pwm_input:
645 if (val < 0 || val > 255)
647 ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
650 case hwmon_pwm_enable:
651 if (val < 1 || val > 2 ||
652 (val == 2 && !data->fan_mode[channel]))
654 ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
655 val == 2 ? data->fan_mode[channel] : 0);
662 static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
665 case hwmon_pwm_input:
666 case hwmon_pwm_enable:
673 static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
674 u32 attr, int channel, long *val)
678 return nct7904_read_in(dev, attr, channel, val);
680 return nct7904_read_fan(dev, attr, channel, val);
682 return nct7904_read_pwm(dev, attr, channel, val);
684 return nct7904_read_temp(dev, attr, channel, val);
690 static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
691 u32 attr, int channel, long val)
695 return nct7904_write_in(dev, attr, channel, val);
697 return nct7904_write_fan(dev, attr, channel, val);
699 return nct7904_write_pwm(dev, attr, channel, val);
701 return nct7904_write_temp(dev, attr, channel, val);
707 static umode_t nct7904_is_visible(const void *data,
708 enum hwmon_sensor_types type,
709 u32 attr, int channel)
713 return nct7904_in_is_visible(data, attr, channel);
715 return nct7904_fan_is_visible(data, attr, channel);
717 return nct7904_pwm_is_visible(data, attr, channel);
719 return nct7904_temp_is_visible(data, attr, channel);
725 /* Return 0 if detection is successful, -ENODEV otherwise */
726 static int nct7904_detect(struct i2c_client *client,
727 struct i2c_board_info *info)
729 struct i2c_adapter *adapter = client->adapter;
731 if (!i2c_check_functionality(adapter,
732 I2C_FUNC_SMBUS_READ_BYTE |
733 I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
736 /* Determine the chip type. */
737 if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
738 i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
739 (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
740 (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
743 strlcpy(info->type, "nct7904", I2C_NAME_SIZE);
748 static const struct hwmon_channel_info *nct7904_info[] = {
749 HWMON_CHANNEL_INFO(in,
750 /* dummy, skipped in is_visible */
751 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
753 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
755 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
757 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
759 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
761 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
763 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
765 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
767 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
769 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
771 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
773 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
775 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
777 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
779 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
781 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
783 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
785 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
787 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
789 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
791 HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
793 HWMON_CHANNEL_INFO(fan,
794 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
795 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
796 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
797 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
798 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
799 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
800 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
801 HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
802 HWMON_CHANNEL_INFO(pwm,
803 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
804 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
805 HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
806 HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
807 HWMON_CHANNEL_INFO(temp,
808 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
809 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
811 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
812 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
814 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
815 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
817 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
818 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
820 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
821 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
823 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
824 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
826 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
827 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
829 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
830 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
832 HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
833 HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
838 static const struct hwmon_ops nct7904_hwmon_ops = {
839 .is_visible = nct7904_is_visible,
840 .read = nct7904_read,
841 .write = nct7904_write,
844 static const struct hwmon_chip_info nct7904_chip_info = {
845 .ops = &nct7904_hwmon_ops,
846 .info = nct7904_info,
849 static int nct7904_probe(struct i2c_client *client,
850 const struct i2c_device_id *id)
852 struct nct7904_data *data;
853 struct device *hwmon_dev;
854 struct device *dev = &client->dev;
859 data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
863 data->client = client;
864 mutex_init(&data->bank_lock);
867 /* Setup sensor groups. */
868 /* FANIN attributes */
869 ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
872 data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
877 * Note: voltage sensors overlap with external temperature
878 * sensors. So, if we ever decide to support the latter
879 * we will have to adjust 'vsen_mask' accordingly.
882 ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
884 mask = (ret >> 8) | ((ret & 0xff) << 8);
885 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
888 data->vsen_mask = mask;
890 /* CPU_TEMP attributes */
891 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
895 if ((ret & 0x6) == 0x6)
896 data->tcpu_mask |= 1; /* TR1 */
897 if ((ret & 0x18) == 0x18)
898 data->tcpu_mask |= 2; /* TR2 */
899 if ((ret & 0x20) == 0x20)
900 data->tcpu_mask |= 4; /* TR3 */
901 if ((ret & 0x80) == 0x80)
902 data->tcpu_mask |= 8; /* TR4 */
905 ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
908 if ((ret & 0x02) == 0x02)
909 data->tcpu_mask |= 0x10;
911 /* Multi-Function detecting for Volt and TR/TD */
912 ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
917 for (i = 0; i < 4; i++) {
918 val = (ret & (0x03 << i)) >> (i * 2);
921 data->tcpu_mask &= ~bit;
922 else if (val == 0x1 || val == 0x2)
923 data->temp_mode |= bit;
927 ret = nct7904_read_reg(data, BANK_2, PFE_REG);
931 data->enable_dts = 1; /* Enable DTS & PECI */
933 ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
937 data->enable_dts = 0x3; /* Enable DTS & TSI */
940 /* Check DTS enable status */
941 if (data->enable_dts) {
942 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
945 data->has_dts = ret & 0xF;
946 if (data->enable_dts & ENABLE_TSI) {
947 ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
950 data->has_dts |= (ret & 0xF) << 4;
954 for (i = 0; i < FANCTL_MAX; i++) {
955 ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
958 data->fan_mode[i] = ret;
962 devm_hwmon_device_register_with_info(dev, client->name, data,
963 &nct7904_chip_info, NULL);
964 return PTR_ERR_OR_ZERO(hwmon_dev);
967 static const struct i2c_device_id nct7904_id[] = {
971 MODULE_DEVICE_TABLE(i2c, nct7904_id);
973 static struct i2c_driver nct7904_driver = {
974 .class = I2C_CLASS_HWMON,
978 .probe = nct7904_probe,
979 .id_table = nct7904_id,
980 .detect = nct7904_detect,
981 .address_list = normal_i2c,
984 module_i2c_driver(nct7904_driver);
986 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
987 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
988 MODULE_LICENSE("GPL");