1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Embedded Trace Buffer driver
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/device.h>
13 #include <linux/err.h>
15 #include <linux/miscdevice.h>
16 #include <linux/uaccess.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/seq_file.h>
21 #include <linux/coresight.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
24 #include <linux/circ_buf.h>
26 #include <linux/perf_event.h>
29 #include "coresight-priv.h"
30 #include "coresight-etm-perf.h"
32 #define ETB_RAM_DEPTH_REG 0x004
33 #define ETB_STATUS_REG 0x00c
34 #define ETB_RAM_READ_DATA_REG 0x010
35 #define ETB_RAM_READ_POINTER 0x014
36 #define ETB_RAM_WRITE_POINTER 0x018
38 #define ETB_CTL_REG 0x020
39 #define ETB_RWD_REG 0x024
40 #define ETB_FFSR 0x300
41 #define ETB_FFCR 0x304
42 #define ETB_ITMISCOP0 0xee0
43 #define ETB_ITTRFLINACK 0xee4
44 #define ETB_ITTRFLIN 0xee8
45 #define ETB_ITATBDATA0 0xeeC
46 #define ETB_ITATBCTR2 0xef0
47 #define ETB_ITATBCTR1 0xef4
48 #define ETB_ITATBCTR0 0xef8
50 /* register description */
52 #define ETB_STATUS_RAM_FULL BIT(0)
54 #define ETB_CTL_CAPT_EN BIT(0)
56 #define ETB_FFCR_EN_FTC BIT(0)
57 #define ETB_FFCR_FON_MAN BIT(6)
58 #define ETB_FFCR_STOP_FI BIT(12)
59 #define ETB_FFCR_STOP_TRIGGER BIT(13)
61 #define ETB_FFCR_BIT 6
62 #define ETB_FFSR_BIT 1
63 #define ETB_FRAME_SIZE_WORDS 4
66 * struct etb_drvdata - specifics associated to an ETB component
67 * @base: memory mapped base address for this component.
68 * @dev: the device entity associated to this component.
69 * @atclk: optional clock for the core parts of the ETB.
70 * @csdev: component vitals needed by the framework.
71 * @miscdev: specifics to handle "/dev/xyz.etb" entry.
72 * @spinlock: only one at a time pls.
73 * @reading: synchronise user space access to etb buffer.
74 * @buf: area of memory where ETB buffer content gets sent.
75 * @mode: this ETB is being used.
76 * @buffer_depth: size of @buf.
77 * @trigger_cntr: amount of words to store after a trigger.
83 struct coresight_device *csdev;
84 struct miscdevice miscdev;
93 static int etb_set_buffer(struct coresight_device *csdev,
94 struct perf_output_handle *handle);
96 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata)
100 pm_runtime_get_sync(drvdata->dev);
102 /* RO registers don't need locking */
103 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG);
105 pm_runtime_put(drvdata->dev);
109 static void __etb_enable_hw(struct etb_drvdata *drvdata)
114 CS_UNLOCK(drvdata->base);
116 depth = drvdata->buffer_depth;
117 /* reset write RAM pointer address */
118 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
119 /* clear entire RAM buffer */
120 for (i = 0; i < depth; i++)
121 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG);
123 /* reset write RAM pointer address */
124 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
125 /* reset read RAM pointer address */
126 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
128 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG);
129 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER,
130 drvdata->base + ETB_FFCR);
131 /* ETB trace capture enable */
132 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG);
134 CS_LOCK(drvdata->base);
137 static int etb_enable_hw(struct etb_drvdata *drvdata)
139 int rc = coresight_claim_device(drvdata->base);
144 __etb_enable_hw(drvdata);
148 static int etb_enable_sysfs(struct coresight_device *csdev)
152 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
154 spin_lock_irqsave(&drvdata->spinlock, flags);
156 /* Don't messup with perf sessions. */
157 if (drvdata->mode == CS_MODE_PERF) {
162 /* Nothing to do, the tracer is already enabled. */
163 if (drvdata->mode == CS_MODE_SYSFS)
166 ret = etb_enable_hw(drvdata);
168 drvdata->mode = CS_MODE_SYSFS;
171 spin_unlock_irqrestore(&drvdata->spinlock, flags);
175 static int etb_enable_perf(struct coresight_device *csdev, void *data)
179 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
181 spin_lock_irqsave(&drvdata->spinlock, flags);
183 /* No need to continue if the component is already in use. */
184 if (drvdata->mode != CS_MODE_DISABLED) {
190 * We don't have an internal state to clean up if we fail to setup
191 * the perf buffer. So we can perform the step before we turn the
192 * ETB on and leave without cleaning up.
194 ret = etb_set_buffer(csdev, (struct perf_output_handle *)data);
198 ret = etb_enable_hw(drvdata);
200 drvdata->mode = CS_MODE_PERF;
203 spin_unlock_irqrestore(&drvdata->spinlock, flags);
207 static int etb_enable(struct coresight_device *csdev, u32 mode, void *data)
210 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
214 ret = etb_enable_sysfs(csdev);
217 ret = etb_enable_perf(csdev, data);
227 dev_dbg(drvdata->dev, "ETB enabled\n");
231 static void __etb_disable_hw(struct etb_drvdata *drvdata)
235 CS_UNLOCK(drvdata->base);
237 ffcr = readl_relaxed(drvdata->base + ETB_FFCR);
238 /* stop formatter when a stop has completed */
239 ffcr |= ETB_FFCR_STOP_FI;
240 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
241 /* manually generate a flush of the system */
242 ffcr |= ETB_FFCR_FON_MAN;
243 writel_relaxed(ffcr, drvdata->base + ETB_FFCR);
245 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) {
246 dev_err(drvdata->dev,
247 "timeout while waiting for completion of Manual Flush\n");
250 /* disable trace capture */
251 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG);
253 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) {
254 dev_err(drvdata->dev,
255 "timeout while waiting for Formatter to Stop\n");
258 CS_LOCK(drvdata->base);
261 static void etb_dump_hw(struct etb_drvdata *drvdata)
266 u32 read_data, depth;
267 u32 read_ptr, write_ptr;
268 u32 frame_off, frame_endoff;
270 CS_UNLOCK(drvdata->base);
272 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
273 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
275 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS;
276 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off;
278 dev_err(drvdata->dev,
279 "write_ptr: %lu not aligned to formatter frame size\n",
280 (unsigned long)write_ptr);
281 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n",
282 (unsigned long)frame_off, (unsigned long)frame_endoff);
283 write_ptr += frame_endoff;
286 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG)
287 & ETB_STATUS_RAM_FULL) == 0) {
288 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
290 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER);
294 depth = drvdata->buffer_depth;
295 buf_ptr = drvdata->buf;
296 for (i = 0; i < depth; i++) {
297 read_data = readl_relaxed(drvdata->base +
298 ETB_RAM_READ_DATA_REG);
299 *(u32 *)buf_ptr = read_data;
304 coresight_insert_barrier_packet(drvdata->buf);
307 buf_ptr -= (frame_endoff * 4);
308 for (i = 0; i < frame_endoff; i++) {
316 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
318 CS_LOCK(drvdata->base);
321 static void etb_disable_hw(struct etb_drvdata *drvdata)
323 __etb_disable_hw(drvdata);
324 etb_dump_hw(drvdata);
325 coresight_disclaim_device(drvdata->base);
328 static void etb_disable(struct coresight_device *csdev)
330 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
333 spin_lock_irqsave(&drvdata->spinlock, flags);
335 /* Disable the ETB only if it needs to */
336 if (drvdata->mode != CS_MODE_DISABLED) {
337 etb_disable_hw(drvdata);
338 drvdata->mode = CS_MODE_DISABLED;
340 spin_unlock_irqrestore(&drvdata->spinlock, flags);
342 dev_dbg(drvdata->dev, "ETB disabled\n");
345 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
346 void **pages, int nr_pages, bool overwrite)
349 struct cs_buffers *buf;
352 cpu = smp_processor_id();
353 node = cpu_to_node(cpu);
355 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
359 buf->snapshot = overwrite;
360 buf->nr_pages = nr_pages;
361 buf->data_pages = pages;
366 static void etb_free_buffer(void *config)
368 struct cs_buffers *buf = config;
373 static int etb_set_buffer(struct coresight_device *csdev,
374 struct perf_output_handle *handle)
378 struct cs_buffers *buf = etm_perf_sink_config(handle);
383 /* wrap head around to the amount of space we have */
384 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1);
386 /* find the page to write to */
387 buf->cur = head / PAGE_SIZE;
389 /* and offset within that page */
390 buf->offset = head % PAGE_SIZE;
392 local_set(&buf->data_size, 0);
397 static unsigned long etb_update_buffer(struct coresight_device *csdev,
398 struct perf_output_handle *handle,
405 u32 read_ptr, write_ptr, capacity;
406 u32 status, read_data;
407 unsigned long offset, to_read;
408 struct cs_buffers *buf = sink_config;
409 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
414 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS;
416 __etb_disable_hw(drvdata);
417 CS_UNLOCK(drvdata->base);
419 /* unit is in words, not bytes */
420 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER);
421 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER);
424 * Entries should be aligned to the frame size. If they are not
425 * go back to the last alignment point to give decoding tools a
426 * chance to fix things.
428 if (write_ptr % ETB_FRAME_SIZE_WORDS) {
429 dev_err(drvdata->dev,
430 "write_ptr: %lu not aligned to formatter frame size\n",
431 (unsigned long)write_ptr);
433 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1);
438 * Get a hold of the status register and see if a wrap around
439 * has occurred. If so adjust things accordingly. Otherwise
440 * start at the beginning and go until the write pointer has
443 status = readl_relaxed(drvdata->base + ETB_STATUS_REG);
444 if (status & ETB_STATUS_RAM_FULL) {
447 read_ptr = write_ptr;
449 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth);
450 to_read *= ETB_FRAME_SIZE_WORDS;
454 * Make sure we don't overwrite data that hasn't been consumed yet.
455 * It is entirely possible that the HW buffer has more data than the
456 * ring buffer can currently handle. If so adjust the start address
457 * to take only the last traces.
459 * In snapshot mode we are looking to get the latest traces only and as
460 * such, we don't care about not overwriting data that hasn't been
461 * processed by user space.
463 if (!buf->snapshot && to_read > handle->size) {
464 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1);
466 /* The new read pointer must be frame size aligned */
467 to_read = handle->size & mask;
469 * Move the RAM read pointer up, keeping in mind that
470 * everything is in frame size units.
472 read_ptr = (write_ptr + drvdata->buffer_depth) -
473 to_read / ETB_FRAME_SIZE_WORDS;
474 /* Wrap around if need be*/
475 if (read_ptr > (drvdata->buffer_depth - 1))
476 read_ptr -= drvdata->buffer_depth;
477 /* let the decoder know we've skipped ahead */
482 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
484 /* finally tell HW where we want to start reading from */
485 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER);
488 offset = buf->offset;
489 barrier = barrier_pkt;
491 for (i = 0; i < to_read; i += 4) {
492 buf_ptr = buf->data_pages[cur] + offset;
493 read_data = readl_relaxed(drvdata->base +
494 ETB_RAM_READ_DATA_REG);
495 if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) {
496 read_data = *barrier;
500 *(u32 *)buf_ptr = read_data;
504 if (offset >= PAGE_SIZE) {
507 /* wrap around at the end of the buffer */
508 cur &= buf->nr_pages - 1;
512 /* reset ETB buffer for next run */
513 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER);
514 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER);
517 * In snapshot mode we have to update the handle->head to point
518 * to the new location.
521 handle->head = (cur * PAGE_SIZE) + offset;
522 to_read = buf->nr_pages << PAGE_SHIFT;
524 __etb_enable_hw(drvdata);
525 CS_LOCK(drvdata->base);
530 static const struct coresight_ops_sink etb_sink_ops = {
531 .enable = etb_enable,
532 .disable = etb_disable,
533 .alloc_buffer = etb_alloc_buffer,
534 .free_buffer = etb_free_buffer,
535 .update_buffer = etb_update_buffer,
538 static const struct coresight_ops etb_cs_ops = {
539 .sink_ops = &etb_sink_ops,
542 static void etb_dump(struct etb_drvdata *drvdata)
546 spin_lock_irqsave(&drvdata->spinlock, flags);
547 if (drvdata->mode == CS_MODE_SYSFS) {
548 __etb_disable_hw(drvdata);
549 etb_dump_hw(drvdata);
550 __etb_enable_hw(drvdata);
552 spin_unlock_irqrestore(&drvdata->spinlock, flags);
554 dev_dbg(drvdata->dev, "ETB dumped\n");
557 static int etb_open(struct inode *inode, struct file *file)
559 struct etb_drvdata *drvdata = container_of(file->private_data,
560 struct etb_drvdata, miscdev);
562 if (local_cmpxchg(&drvdata->reading, 0, 1))
565 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
569 static ssize_t etb_read(struct file *file, char __user *data,
570 size_t len, loff_t *ppos)
573 struct etb_drvdata *drvdata = container_of(file->private_data,
574 struct etb_drvdata, miscdev);
578 depth = drvdata->buffer_depth;
579 if (*ppos + len > depth * 4)
580 len = depth * 4 - *ppos;
582 if (copy_to_user(data, drvdata->buf + *ppos, len)) {
583 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
589 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
590 __func__, len, (int)(depth * 4 - *ppos));
594 static int etb_release(struct inode *inode, struct file *file)
596 struct etb_drvdata *drvdata = container_of(file->private_data,
597 struct etb_drvdata, miscdev);
598 local_set(&drvdata->reading, 0);
600 dev_dbg(drvdata->dev, "%s: released\n", __func__);
604 static const struct file_operations etb_fops = {
605 .owner = THIS_MODULE,
608 .release = etb_release,
612 #define coresight_etb10_reg(name, offset) \
613 coresight_simple_reg32(struct etb_drvdata, name, offset)
615 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG);
616 coresight_etb10_reg(sts, ETB_STATUS_REG);
617 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER);
618 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER);
619 coresight_etb10_reg(trg, ETB_TRG);
620 coresight_etb10_reg(ctl, ETB_CTL_REG);
621 coresight_etb10_reg(ffsr, ETB_FFSR);
622 coresight_etb10_reg(ffcr, ETB_FFCR);
624 static struct attribute *coresight_etb_mgmt_attrs[] = {
636 static ssize_t trigger_cntr_show(struct device *dev,
637 struct device_attribute *attr, char *buf)
639 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
640 unsigned long val = drvdata->trigger_cntr;
642 return sprintf(buf, "%#lx\n", val);
645 static ssize_t trigger_cntr_store(struct device *dev,
646 struct device_attribute *attr,
647 const char *buf, size_t size)
651 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent);
653 ret = kstrtoul(buf, 16, &val);
657 drvdata->trigger_cntr = val;
660 static DEVICE_ATTR_RW(trigger_cntr);
662 static struct attribute *coresight_etb_attrs[] = {
663 &dev_attr_trigger_cntr.attr,
667 static const struct attribute_group coresight_etb_group = {
668 .attrs = coresight_etb_attrs,
671 static const struct attribute_group coresight_etb_mgmt_group = {
672 .attrs = coresight_etb_mgmt_attrs,
676 const struct attribute_group *coresight_etb_groups[] = {
677 &coresight_etb_group,
678 &coresight_etb_mgmt_group,
682 static int etb_probe(struct amba_device *adev, const struct amba_id *id)
686 struct device *dev = &adev->dev;
687 struct coresight_platform_data *pdata = NULL;
688 struct etb_drvdata *drvdata;
689 struct resource *res = &adev->res;
690 struct coresight_desc desc = { 0 };
691 struct device_node *np = adev->dev.of_node;
694 pdata = of_get_coresight_platform_data(dev, np);
696 return PTR_ERR(pdata);
697 adev->dev.platform_data = pdata;
700 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
704 drvdata->dev = &adev->dev;
705 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
706 if (!IS_ERR(drvdata->atclk)) {
707 ret = clk_prepare_enable(drvdata->atclk);
711 dev_set_drvdata(dev, drvdata);
713 /* validity for the resource is already checked by the AMBA core */
714 base = devm_ioremap_resource(dev, res);
716 return PTR_ERR(base);
718 drvdata->base = base;
720 spin_lock_init(&drvdata->spinlock);
722 drvdata->buffer_depth = etb_get_buffer_depth(drvdata);
723 pm_runtime_put(&adev->dev);
725 if (drvdata->buffer_depth & 0x80000000)
728 drvdata->buf = devm_kcalloc(dev,
729 drvdata->buffer_depth, 4, GFP_KERNEL);
733 desc.type = CORESIGHT_DEV_TYPE_SINK;
734 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
735 desc.ops = &etb_cs_ops;
738 desc.groups = coresight_etb_groups;
739 drvdata->csdev = coresight_register(&desc);
740 if (IS_ERR(drvdata->csdev))
741 return PTR_ERR(drvdata->csdev);
743 drvdata->miscdev.name = pdata->name;
744 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
745 drvdata->miscdev.fops = &etb_fops;
746 ret = misc_register(&drvdata->miscdev);
748 goto err_misc_register;
753 coresight_unregister(drvdata->csdev);
758 static int etb_runtime_suspend(struct device *dev)
760 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
762 if (drvdata && !IS_ERR(drvdata->atclk))
763 clk_disable_unprepare(drvdata->atclk);
768 static int etb_runtime_resume(struct device *dev)
770 struct etb_drvdata *drvdata = dev_get_drvdata(dev);
772 if (drvdata && !IS_ERR(drvdata->atclk))
773 clk_prepare_enable(drvdata->atclk);
779 static const struct dev_pm_ops etb_dev_pm_ops = {
780 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL)
783 static const struct amba_id etb_ids[] = {
791 static struct amba_driver etb_driver = {
793 .name = "coresight-etb10",
794 .owner = THIS_MODULE,
795 .pm = &etb_dev_pm_ops,
796 .suppress_bind_attrs = true,
802 builtin_amba_driver(etb_driver);