1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Program Flow Trace driver
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
14 #include <linux/err.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/cpu.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/clk.h>
30 #include <linux/perf_event.h>
31 #include <asm/sections.h>
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
40 static int boot_enable;
41 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
43 /* The number of ETM/PTM currently registered */
45 static struct etm_drvdata *etmdrvdata[NR_CPUS];
47 static enum cpuhp_state hp_online;
50 * Memory mapped writes to clear os lock are not supported on some processors
51 * and OS lock must be unlocked before any memory mapped access on such
52 * processors, otherwise memory mapped reads/writes will be invalid.
54 static void etm_os_unlock(struct etm_drvdata *drvdata)
56 /* Writing any value to ETMOSLAR unlocks the trace registers */
57 etm_writel(drvdata, 0x0, ETMOSLAR);
58 drvdata->os_unlock = true;
62 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
66 /* Ensure pending cp14 accesses complete before setting pwrdwn */
69 etmcr = etm_readl(drvdata, ETMCR);
70 etmcr |= ETMCR_PWD_DWN;
71 etm_writel(drvdata, etmcr, ETMCR);
74 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
78 etmcr = etm_readl(drvdata, ETMCR);
79 etmcr &= ~ETMCR_PWD_DWN;
80 etm_writel(drvdata, etmcr, ETMCR);
81 /* Ensure pwrup completes before subsequent cp14 accesses */
86 static void etm_set_pwrup(struct etm_drvdata *drvdata)
90 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
91 etmpdcr |= ETMPDCR_PWD_UP;
92 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
93 /* Ensure pwrup completes before subsequent cp14 accesses */
98 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
102 /* Ensure pending cp14 accesses complete before clearing pwrup */
105 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
106 etmpdcr &= ~ETMPDCR_PWD_UP;
107 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
111 * coresight_timeout_etm - loop until a bit has changed to a specific state.
112 * @drvdata: etm's private data structure.
113 * @offset: address of a register, starting from @addr.
114 * @position: the position of the bit of interest.
115 * @value: the value the bit should have.
117 * Basically the same as @coresight_timeout except for the register access
118 * method where we have to account for CP14 configurations.
120 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
121 * TIMEOUT_US has elapsed, which ever happens first.
124 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
125 int position, int value)
130 for (i = TIMEOUT_US; i > 0; i--) {
131 val = etm_readl(drvdata, offset);
132 /* Waiting on the bit to go from 0 to 1 */
134 if (val & BIT(position))
136 /* Waiting on the bit to go from 1 to 0 */
138 if (!(val & BIT(position)))
143 * Delay is arbitrary - the specification doesn't say how long
144 * we are expected to wait. Extra check required to make sure
145 * we don't wait needlessly on the last iteration.
155 static void etm_set_prog(struct etm_drvdata *drvdata)
159 etmcr = etm_readl(drvdata, ETMCR);
160 etmcr |= ETMCR_ETM_PRG;
161 etm_writel(drvdata, etmcr, ETMCR);
163 * Recommended by spec for cp14 accesses to ensure etmcr write is
164 * complete before polling etmsr
167 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
168 dev_err(drvdata->dev,
169 "%s: timeout observed when probing at offset %#x\n",
174 static void etm_clr_prog(struct etm_drvdata *drvdata)
178 etmcr = etm_readl(drvdata, ETMCR);
179 etmcr &= ~ETMCR_ETM_PRG;
180 etm_writel(drvdata, etmcr, ETMCR);
182 * Recommended by spec for cp14 accesses to ensure etmcr write is
183 * complete before polling etmsr
186 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
187 dev_err(drvdata->dev,
188 "%s: timeout observed when probing at offset %#x\n",
193 void etm_set_default(struct etm_config *config)
197 if (WARN_ON_ONCE(!config))
201 * Taken verbatim from the TRM:
203 * To trace all memory:
204 * set bit [24] in register 0x009, the ETMTECR1, to 1
205 * set all other bits in register 0x009, the ETMTECR1, to 0
206 * set all bits in register 0x007, the ETMTECR2, to 0
207 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
209 config->enable_ctrl1 = BIT(24);
210 config->enable_ctrl2 = 0x0;
211 config->enable_event = ETM_HARD_WIRE_RES_A;
213 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
214 config->enable_event = ETM_HARD_WIRE_RES_A;
216 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
220 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
221 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
222 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
224 for (i = 0; i < ETM_MAX_CNTR; i++) {
225 config->cntr_rld_val[i] = 0x0;
226 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
227 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
228 config->cntr_val[i] = 0x0;
231 config->seq_curr_state = 0x0;
232 config->ctxid_idx = 0x0;
233 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
234 config->ctxid_pid[i] = 0x0;
236 config->ctxid_mask = 0x0;
237 /* Setting default to 1024 as per TRM recommendation */
238 config->sync_freq = 0x400;
241 void etm_config_trace_mode(struct etm_config *config)
247 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
249 /* excluding kernel AND user space doesn't make sense */
250 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
253 /* nothing to do if neither flags are set */
254 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
257 flags = (1 << 0 | /* instruction execute */
258 3 << 3 | /* ARM instruction */
259 0 << 5 | /* No data value comparison */
260 0 << 7 | /* No exact mach */
261 0 << 8); /* Ignore context ID */
263 /* No need to worry about single address comparators. */
264 config->enable_ctrl2 = 0x0;
266 /* Bit 0 is address range comparator 1 */
267 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
271 * ETMACTRn[13,11] == Non-secure state comparison control
272 * ETMACTRn[12,10] == Secure state comparison control
274 * b00 == Match in all modes in this state
275 * b01 == Do not match in any more in this state
276 * b10 == Match in all modes excepts user mode in this state
277 * b11 == Match only in user mode in this state
280 /* Tracing in secure mode is not supported at this time */
281 flags |= (0 << 12 | 1 << 10);
283 if (mode & ETM_MODE_EXCL_USER) {
284 /* exclude user, match all modes except user mode */
285 flags |= (1 << 13 | 0 << 11);
287 /* exclude kernel, match only in user mode */
288 flags |= (1 << 13 | 1 << 11);
292 * The ETMEEVR register is already set to "hard wire A". As such
293 * all there is to do is setup an address comparator that spans
294 * the entire address range and configure the state and mode bits.
296 config->addr_val[0] = (u32) 0x0;
297 config->addr_val[1] = (u32) ~0x0;
298 config->addr_acctype[0] = flags;
299 config->addr_acctype[1] = flags;
300 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
301 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
304 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
305 ETMCR_TIMESTAMP_EN | \
308 static int etm_parse_event_config(struct etm_drvdata *drvdata,
309 struct perf_event *event)
311 struct etm_config *config = &drvdata->config;
312 struct perf_event_attr *attr = &event->attr;
317 /* Clear configuration from previous run */
318 memset(config, 0, sizeof(struct etm_config));
320 if (attr->exclude_kernel)
321 config->mode = ETM_MODE_EXCL_KERN;
323 if (attr->exclude_user)
324 config->mode = ETM_MODE_EXCL_USER;
326 /* Always start from the default config */
327 etm_set_default(config);
330 * By default the tracers are configured to trace the whole address
331 * range. Narrow the field only if requested by user space.
334 etm_config_trace_mode(config);
337 * At this time only cycle accurate, return stack and timestamp
338 * options are available.
340 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
343 config->ctrl = attr->config;
346 * Possible to have cores with PTM (supports ret stack) and ETM
347 * (never has ret stack) on the same SoC. So if we have a request
348 * for return stack that can't be honoured on this core then
349 * clear the bit - trace will still continue normally
351 if ((config->ctrl & ETMCR_RETURN_STACK) &&
352 !(drvdata->etmccer & ETMCCER_RETSTACK))
353 config->ctrl &= ~ETMCR_RETURN_STACK;
358 static int etm_enable_hw(struct etm_drvdata *drvdata)
362 struct etm_config *config = &drvdata->config;
364 CS_UNLOCK(drvdata->base);
366 rc = coresight_claim_device_unlocked(drvdata->base);
371 etm_clr_pwrdwn(drvdata);
372 /* Apply power to trace registers */
373 etm_set_pwrup(drvdata);
374 /* Make sure all registers are accessible */
375 etm_os_unlock(drvdata);
377 etm_set_prog(drvdata);
379 etmcr = etm_readl(drvdata, ETMCR);
380 /* Clear setting from a previous run if need be */
381 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
382 etmcr |= drvdata->port_size;
383 etmcr |= ETMCR_ETM_EN;
384 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
385 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
386 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
387 etm_writel(drvdata, config->enable_event, ETMTEEVR);
388 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
389 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
390 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
391 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
392 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
394 for (i = 0; i < drvdata->nr_cntr; i++) {
395 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
396 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
397 etm_writel(drvdata, config->cntr_rld_event[i],
399 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
401 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
402 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
403 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
404 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
405 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
406 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
407 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
408 for (i = 0; i < drvdata->nr_ext_out; i++)
409 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
410 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
411 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
412 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
413 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
414 /* No external input selected */
415 etm_writel(drvdata, 0x0, ETMEXTINSELR);
416 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
417 /* No auxiliary control selected */
418 etm_writel(drvdata, 0x0, ETMAUXCR);
419 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
420 /* No VMID comparator value selected */
421 etm_writel(drvdata, 0x0, ETMVMIDCVR);
423 etm_clr_prog(drvdata);
426 CS_LOCK(drvdata->base);
428 dev_dbg(drvdata->dev, "cpu: %d enable smp call done: %d\n",
433 struct etm_enable_arg {
434 struct etm_drvdata *drvdata;
438 static void etm_enable_hw_smp_call(void *info)
440 struct etm_enable_arg *arg = info;
444 arg->rc = etm_enable_hw(arg->drvdata);
447 static int etm_cpu_id(struct coresight_device *csdev)
449 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
454 int etm_get_trace_id(struct etm_drvdata *drvdata)
462 if (!local_read(&drvdata->mode))
463 return drvdata->traceid;
465 pm_runtime_get_sync(drvdata->dev);
467 spin_lock_irqsave(&drvdata->spinlock, flags);
469 CS_UNLOCK(drvdata->base);
470 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
471 CS_LOCK(drvdata->base);
473 spin_unlock_irqrestore(&drvdata->spinlock, flags);
474 pm_runtime_put(drvdata->dev);
481 static int etm_trace_id(struct coresight_device *csdev)
483 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
485 return etm_get_trace_id(drvdata);
488 static int etm_enable_perf(struct coresight_device *csdev,
489 struct perf_event *event)
491 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
493 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
496 /* Configure the tracer based on the session's specifics */
497 etm_parse_event_config(drvdata, event);
499 return etm_enable_hw(drvdata);
502 static int etm_enable_sysfs(struct coresight_device *csdev)
504 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
505 struct etm_enable_arg arg = { 0 };
508 spin_lock(&drvdata->spinlock);
511 * Configure the ETM only if the CPU is online. If it isn't online
512 * hw configuration will take place on the local CPU during bring up.
514 if (cpu_online(drvdata->cpu)) {
515 arg.drvdata = drvdata;
516 ret = smp_call_function_single(drvdata->cpu,
517 etm_enable_hw_smp_call, &arg, 1);
521 drvdata->sticky_enable = true;
526 spin_unlock(&drvdata->spinlock);
529 dev_dbg(drvdata->dev, "ETM tracing enabled\n");
533 static int etm_enable(struct coresight_device *csdev,
534 struct perf_event *event, u32 mode)
538 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
540 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
542 /* Someone is already using the tracer */
548 ret = etm_enable_sysfs(csdev);
551 ret = etm_enable_perf(csdev, event);
557 /* The tracer didn't start */
559 local_set(&drvdata->mode, CS_MODE_DISABLED);
564 static void etm_disable_hw(void *info)
567 struct etm_drvdata *drvdata = info;
568 struct etm_config *config = &drvdata->config;
570 CS_UNLOCK(drvdata->base);
571 etm_set_prog(drvdata);
573 /* Read back sequencer and counters for post trace analysis */
574 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
576 for (i = 0; i < drvdata->nr_cntr; i++)
577 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
579 etm_set_pwrdwn(drvdata);
580 coresight_disclaim_device_unlocked(drvdata->base);
582 CS_LOCK(drvdata->base);
584 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
587 static void etm_disable_perf(struct coresight_device *csdev)
589 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
591 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
594 CS_UNLOCK(drvdata->base);
596 /* Setting the prog bit disables tracing immediately */
597 etm_set_prog(drvdata);
600 * There is no way to know when the tracer will be used again so
601 * power down the tracer.
603 etm_set_pwrdwn(drvdata);
604 coresight_disclaim_device_unlocked(drvdata->base);
606 CS_LOCK(drvdata->base);
609 static void etm_disable_sysfs(struct coresight_device *csdev)
611 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
614 * Taking hotplug lock here protects from clocks getting disabled
615 * with tracing being left on (crash scenario) if user disable occurs
616 * after cpu online mask indicates the cpu is offline but before the
617 * DYING hotplug callback is serviced by the ETM driver.
620 spin_lock(&drvdata->spinlock);
623 * Executing etm_disable_hw on the cpu whose ETM is being disabled
624 * ensures that register writes occur when cpu is powered.
626 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
628 spin_unlock(&drvdata->spinlock);
631 dev_dbg(drvdata->dev, "ETM tracing disabled\n");
634 static void etm_disable(struct coresight_device *csdev,
635 struct perf_event *event)
638 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
641 * For as long as the tracer isn't disabled another entity can't
642 * change its status. As such we can read the status here without
643 * fearing it will change under us.
645 mode = local_read(&drvdata->mode);
648 case CS_MODE_DISABLED:
651 etm_disable_sysfs(csdev);
654 etm_disable_perf(csdev);
662 local_set(&drvdata->mode, CS_MODE_DISABLED);
665 static const struct coresight_ops_source etm_source_ops = {
666 .cpu_id = etm_cpu_id,
667 .trace_id = etm_trace_id,
668 .enable = etm_enable,
669 .disable = etm_disable,
672 static const struct coresight_ops etm_cs_ops = {
673 .source_ops = &etm_source_ops,
676 static int etm_online_cpu(unsigned int cpu)
678 if (!etmdrvdata[cpu])
681 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
682 coresight_enable(etmdrvdata[cpu]->csdev);
686 static int etm_starting_cpu(unsigned int cpu)
688 if (!etmdrvdata[cpu])
691 spin_lock(&etmdrvdata[cpu]->spinlock);
692 if (!etmdrvdata[cpu]->os_unlock) {
693 etm_os_unlock(etmdrvdata[cpu]);
694 etmdrvdata[cpu]->os_unlock = true;
697 if (local_read(&etmdrvdata[cpu]->mode))
698 etm_enable_hw(etmdrvdata[cpu]);
699 spin_unlock(&etmdrvdata[cpu]->spinlock);
703 static int etm_dying_cpu(unsigned int cpu)
705 if (!etmdrvdata[cpu])
708 spin_lock(&etmdrvdata[cpu]->spinlock);
709 if (local_read(&etmdrvdata[cpu]->mode))
710 etm_disable_hw(etmdrvdata[cpu]);
711 spin_unlock(&etmdrvdata[cpu]->spinlock);
715 static bool etm_arch_supported(u8 arch)
732 static void etm_init_arch_data(void *info)
736 struct etm_drvdata *drvdata = info;
738 /* Make sure all registers are accessible */
739 etm_os_unlock(drvdata);
741 CS_UNLOCK(drvdata->base);
743 /* First dummy read */
744 (void)etm_readl(drvdata, ETMPDSR);
745 /* Provide power to ETM: ETMPDCR[3] == 1 */
746 etm_set_pwrup(drvdata);
748 * Clear power down bit since when this bit is set writes to
749 * certain registers might be ignored.
751 etm_clr_pwrdwn(drvdata);
753 * Set prog bit. It will be set from reset but this is included to
756 etm_set_prog(drvdata);
758 /* Find all capabilities */
759 etmidr = etm_readl(drvdata, ETMIDR);
760 drvdata->arch = BMVAL(etmidr, 4, 11);
761 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
763 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
764 etmccr = etm_readl(drvdata, ETMCCR);
765 drvdata->etmccr = etmccr;
766 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
767 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
768 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
769 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
770 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
772 etm_set_pwrdwn(drvdata);
773 etm_clr_pwrup(drvdata);
774 CS_LOCK(drvdata->base);
777 static void etm_init_trace_id(struct etm_drvdata *drvdata)
779 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
782 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
786 struct device *dev = &adev->dev;
787 struct coresight_platform_data *pdata = NULL;
788 struct etm_drvdata *drvdata;
789 struct resource *res = &adev->res;
790 struct coresight_desc desc = { 0 };
791 struct device_node *np = adev->dev.of_node;
793 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
798 pdata = of_get_coresight_platform_data(dev, np);
800 return PTR_ERR(pdata);
802 adev->dev.platform_data = pdata;
803 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
806 drvdata->dev = &adev->dev;
807 dev_set_drvdata(dev, drvdata);
809 /* Validity for the resource is already checked by the AMBA core */
810 base = devm_ioremap_resource(dev, res);
812 return PTR_ERR(base);
814 drvdata->base = base;
816 spin_lock_init(&drvdata->spinlock);
818 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
819 if (!IS_ERR(drvdata->atclk)) {
820 ret = clk_prepare_enable(drvdata->atclk);
825 drvdata->cpu = pdata ? pdata->cpu : 0;
828 etmdrvdata[drvdata->cpu] = drvdata;
830 if (smp_call_function_single(drvdata->cpu,
831 etm_init_arch_data, drvdata, 1))
832 dev_err(dev, "ETM arch init failed\n");
835 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
836 "arm/coresight:starting",
837 etm_starting_cpu, etm_dying_cpu);
838 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
839 "arm/coresight:online",
840 etm_online_cpu, NULL);
842 goto err_arch_supported;
847 if (etm_arch_supported(drvdata->arch) == false) {
849 goto err_arch_supported;
852 etm_init_trace_id(drvdata);
853 etm_set_default(&drvdata->config);
855 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
856 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
857 desc.ops = &etm_cs_ops;
860 desc.groups = coresight_etm_groups;
861 drvdata->csdev = coresight_register(&desc);
862 if (IS_ERR(drvdata->csdev)) {
863 ret = PTR_ERR(drvdata->csdev);
864 goto err_arch_supported;
867 ret = etm_perf_symlink(drvdata->csdev, true);
869 coresight_unregister(drvdata->csdev);
870 goto err_arch_supported;
873 pm_runtime_put(&adev->dev);
874 dev_info(dev, "%s initialized\n", (char *)id->data);
876 coresight_enable(drvdata->csdev);
877 drvdata->boot_enable = true;
883 if (--etm_count == 0) {
884 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
886 cpuhp_remove_state_nocalls(hp_online);
892 static int etm_runtime_suspend(struct device *dev)
894 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
896 if (drvdata && !IS_ERR(drvdata->atclk))
897 clk_disable_unprepare(drvdata->atclk);
902 static int etm_runtime_resume(struct device *dev)
904 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
906 if (drvdata && !IS_ERR(drvdata->atclk))
907 clk_prepare_enable(drvdata->atclk);
913 static const struct dev_pm_ops etm_dev_pm_ops = {
914 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
917 static const struct amba_id etm_ids[] = {
923 { /* ETM 3.5 - Cortex-A5 */
943 { /* PTM 1.1 Qualcomm */
951 static struct amba_driver etm_driver = {
953 .name = "coresight-etm3x",
954 .owner = THIS_MODULE,
955 .pm = &etm_dev_pm_ops,
956 .suppress_bind_attrs = true,
961 builtin_amba_driver(etm_driver);