drivers/hwtracing/coresight/coresight-priv.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _CORESIGHT_PRIV_H
   7 #define _CORESIGHT_PRIV_H
   8
   9 #include <linux/bitops.h>
  10 #include <linux/io.h>
  11 #include <linux/coresight.h>
  12 #include <linux/pm_runtime.h>
  13
  14 /*
  15  * Coresight management registers (0xf00-0xfcc)
  16  * 0xfa0 - 0xfa4: Management    registers in PFTv1.0
  17  *                Trace         registers in PFTv1.1
  18  */
  19 #define CORESIGHT_ITCTRL        0xf00
  20 #define CORESIGHT_CLAIMSET      0xfa0
  21 #define CORESIGHT_CLAIMCLR      0xfa4
  22 #define CORESIGHT_LAR           0xfb0
  23 #define CORESIGHT_LSR           0xfb4
  24 #define CORESIGHT_AUTHSTATUS    0xfb8
  25 #define CORESIGHT_DEVID         0xfc8
  26 #define CORESIGHT_DEVTYPE       0xfcc
  27
  28
  29 /*
  30  * Coresight device CLAIM protocol.
  31  * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
  32  */
  33 #define CORESIGHT_CLAIM_SELF_HOSTED     BIT(1)
  34
  35 #define TIMEOUT_US              100
  36 #define BMVAL(val, lsb, msb)    ((val & GENMASK(msb, lsb)) >> lsb)
  37
  38 #define ETM_MODE_EXCL_KERN      BIT(30)
  39 #define ETM_MODE_EXCL_USER      BIT(31)
  40
  41 typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
  42 #define __coresight_simple_func(type, func, name, lo_off, hi_off)       \
  43 static ssize_t name##_show(struct device *_dev,                         \
  44                            struct device_attribute *attr, char *buf)    \
  45 {                                                                       \
  46         type *drvdata = dev_get_drvdata(_dev->parent);                  \
  47         coresight_read_fn fn = func;                                    \
  48         u64 val;                                                        \
  49         pm_runtime_get_sync(_dev->parent);                              \
  50         if (fn)                                                         \
  51                 val = (u64)fn(_dev->parent, lo_off);                    \
  52         else                                                            \
  53                 val = coresight_read_reg_pair(drvdata->base,            \
  54                                                  lo_off, hi_off);       \
  55         pm_runtime_put_sync(_dev->parent);                              \
  56         return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val);              \
  57 }                                                                       \
  58 static DEVICE_ATTR_RO(name)
  59
  60 #define coresight_simple_func(type, func, name, offset)                 \
  61         __coresight_simple_func(type, func, name, offset, -1)
  62 #define coresight_simple_reg32(type, name, offset)                      \
  63         __coresight_simple_func(type, NULL, name, offset, -1)
  64 #define coresight_simple_reg64(type, name, lo_off, hi_off)              \
  65         __coresight_simple_func(type, NULL, name, lo_off, hi_off)
  66
  67 extern const u32 barrier_pkt[4];
  68 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(barrier_pkt))
  69
  70 enum etm_addr_type {
  71         ETM_ADDR_TYPE_NONE,
  72         ETM_ADDR_TYPE_SINGLE,
  73         ETM_ADDR_TYPE_RANGE,
  74         ETM_ADDR_TYPE_START,
  75         ETM_ADDR_TYPE_STOP,
  76 };
  77
  78 enum cs_mode {
  79         CS_MODE_DISABLED,
  80         CS_MODE_SYSFS,
  81         CS_MODE_PERF,
  82 };
  83
  84 /**
  85  * struct cs_buffer - keep track of a recording session' specifics
  86  * @cur:        index of the current buffer
  87  * @nr_pages:   max number of pages granted to us
  88  * @offset:     offset within the current buffer
  89  * @data_size:  how much we collected in this run
  90  * @snapshot:   is this run in snapshot mode
  91  * @data_pages: a handle the ring buffer
  92  */
  93 struct cs_buffers {
  94         unsigned int            cur;
  95         unsigned int            nr_pages;
  96         unsigned long           offset;
  97         local_t                 data_size;
  98         bool                    snapshot;
  99         void                    **data_pages;
 100 };
 101
 102 static inline void coresight_insert_barrier_packet(void *buf)
 103 {
 104         if (buf)
 105                 memcpy(buf, barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
 106 }
 107
 108
 109 static inline void CS_LOCK(void __iomem *addr)
 110 {
 111         do {
 112                 /* Wait for things to settle */
 113                 mb();
 114                 writel_relaxed(0x0, addr + CORESIGHT_LAR);
 115         } while (0);
 116 }
 117
 118 static inline void CS_UNLOCK(void __iomem *addr)
 119 {
 120         do {
 121                 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
 122                 /* Make sure everyone has seen this */
 123                 mb();
 124         } while (0);
 125 }
 126
 127 static inline u64
 128 coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
 129 {
 130         u64 val;
 131
 132         val = readl_relaxed(addr + lo_offset);
 133         val |= (hi_offset < 0) ? 0 :
 134                (u64)readl_relaxed(addr + hi_offset) << 32;
 135         return val;
 136 }
 137
 138 static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
 139                                                  s32 lo_offset, s32 hi_offset)
 140 {
 141         writel_relaxed((u32)val, addr + lo_offset);
 142         if (hi_offset >= 0)
 143                 writel_relaxed((u32)(val >> 32), addr + hi_offset);
 144 }
 145
 146 void coresight_disable_path(struct list_head *path);
 147 int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
 148 struct coresight_device *coresight_get_sink(struct list_head *path);
 149 struct coresight_device *coresight_get_enabled_sink(bool reset);
 150 struct coresight_device *coresight_get_sink_by_id(u32 id);
 151 struct list_head *coresight_build_path(struct coresight_device *csdev,
 152                                        struct coresight_device *sink);
 153 void coresight_release_path(struct list_head *path);
 154
 155 #ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
 156 extern int etm_readl_cp14(u32 off, unsigned int *val);
 157 extern int etm_writel_cp14(u32 off, u32 val);
 158 #else
 159 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
 160 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
 161 #endif
 162
 163 #endif