1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 * Description: CoreSight Trace Memory Controller driver
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/device.h>
11 #include <linux/idr.h>
13 #include <linux/err.h>
15 #include <linux/miscdevice.h>
16 #include <linux/mutex.h>
17 #include <linux/property.h>
18 #include <linux/uaccess.h>
19 #include <linux/slab.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/spinlock.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/coresight.h>
25 #include <linux/amba/bus.h>
27 #include "coresight-priv.h"
28 #include "coresight-tmc.h"
30 DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb");
31 DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf");
32 DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr");
34 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
36 /* Ensure formatter, unformatter and hardware fifo are empty */
37 if (coresight_timeout(drvdata->base,
38 TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
39 dev_err(&drvdata->csdev->dev,
40 "timeout while waiting for TMC to be Ready\n");
44 void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
48 ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
49 ffcr |= TMC_FFCR_STOP_ON_FLUSH;
50 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
51 ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
52 writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
53 /* Ensure flush completes */
54 if (coresight_timeout(drvdata->base,
55 TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
56 dev_err(&drvdata->csdev->dev,
57 "timeout while waiting for completion of Manual Flush\n");
60 tmc_wait_for_tmcready(drvdata);
63 void tmc_enable_hw(struct tmc_drvdata *drvdata)
65 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
68 void tmc_disable_hw(struct tmc_drvdata *drvdata)
70 writel_relaxed(0x0, drvdata->base + TMC_CTL);
73 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
78 * When moving RRP or an offset address forward, the new values must
79 * be byte-address aligned to the width of the trace memory databus
80 * _and_ to a frame boundary (16 byte), whichever is the biggest. For
81 * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
82 * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
85 switch (drvdata->memwidth) {
86 case TMC_MEM_INTF_WIDTH_32BITS:
88 case TMC_MEM_INTF_WIDTH_64BITS:
90 case TMC_MEM_INTF_WIDTH_128BITS:
91 mask = GENMASK(31, 4);
93 case TMC_MEM_INTF_WIDTH_256BITS:
94 mask = GENMASK(31, 5);
101 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
105 switch (drvdata->config_type) {
106 case TMC_CONFIG_TYPE_ETB:
107 case TMC_CONFIG_TYPE_ETF:
108 ret = tmc_read_prepare_etb(drvdata);
110 case TMC_CONFIG_TYPE_ETR:
111 ret = tmc_read_prepare_etr(drvdata);
118 dev_dbg(&drvdata->csdev->dev, "TMC read start\n");
123 static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
127 switch (drvdata->config_type) {
128 case TMC_CONFIG_TYPE_ETB:
129 case TMC_CONFIG_TYPE_ETF:
130 ret = tmc_read_unprepare_etb(drvdata);
132 case TMC_CONFIG_TYPE_ETR:
133 ret = tmc_read_unprepare_etr(drvdata);
140 dev_dbg(&drvdata->csdev->dev, "TMC read end\n");
145 static int tmc_open(struct inode *inode, struct file *file)
148 struct tmc_drvdata *drvdata = container_of(file->private_data,
149 struct tmc_drvdata, miscdev);
151 ret = tmc_read_prepare(drvdata);
155 nonseekable_open(inode, file);
157 dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
161 static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
162 loff_t pos, size_t len, char **bufpp)
164 switch (drvdata->config_type) {
165 case TMC_CONFIG_TYPE_ETB:
166 case TMC_CONFIG_TYPE_ETF:
167 return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
168 case TMC_CONFIG_TYPE_ETR:
169 return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
175 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
180 struct tmc_drvdata *drvdata = container_of(file->private_data,
181 struct tmc_drvdata, miscdev);
182 actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
186 if (copy_to_user(data, bufp, actual)) {
187 dev_dbg(&drvdata->csdev->dev,
188 "%s: copy_to_user failed\n", __func__);
193 dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
198 static int tmc_release(struct inode *inode, struct file *file)
201 struct tmc_drvdata *drvdata = container_of(file->private_data,
202 struct tmc_drvdata, miscdev);
204 ret = tmc_read_unprepare(drvdata);
208 dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
212 static const struct file_operations tmc_fops = {
213 .owner = THIS_MODULE,
216 .release = tmc_release,
220 static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
222 enum tmc_mem_intf_width memwidth;
225 * Excerpt from the TRM:
227 * DEVID::MEMWIDTH[10:8]
228 * 0x2 Memory interface databus is 32 bits wide.
229 * 0x3 Memory interface databus is 64 bits wide.
230 * 0x4 Memory interface databus is 128 bits wide.
231 * 0x5 Memory interface databus is 256 bits wide.
233 switch (BMVAL(devid, 8, 10)) {
235 memwidth = TMC_MEM_INTF_WIDTH_32BITS;
238 memwidth = TMC_MEM_INTF_WIDTH_64BITS;
241 memwidth = TMC_MEM_INTF_WIDTH_128BITS;
244 memwidth = TMC_MEM_INTF_WIDTH_256BITS;
253 #define coresight_tmc_reg(name, offset) \
254 coresight_simple_reg32(struct tmc_drvdata, name, offset)
255 #define coresight_tmc_reg64(name, lo_off, hi_off) \
256 coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
258 coresight_tmc_reg(rsz, TMC_RSZ);
259 coresight_tmc_reg(sts, TMC_STS);
260 coresight_tmc_reg(trg, TMC_TRG);
261 coresight_tmc_reg(ctl, TMC_CTL);
262 coresight_tmc_reg(ffsr, TMC_FFSR);
263 coresight_tmc_reg(ffcr, TMC_FFCR);
264 coresight_tmc_reg(mode, TMC_MODE);
265 coresight_tmc_reg(pscr, TMC_PSCR);
266 coresight_tmc_reg(axictl, TMC_AXICTL);
267 coresight_tmc_reg(authstatus, TMC_AUTHSTATUS);
268 coresight_tmc_reg(devid, CORESIGHT_DEVID);
269 coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
270 coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
271 coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
273 static struct attribute *coresight_tmc_mgmt_attrs[] = {
284 &dev_attr_devid.attr,
286 &dev_attr_axictl.attr,
287 &dev_attr_authstatus.attr,
291 static ssize_t trigger_cntr_show(struct device *dev,
292 struct device_attribute *attr, char *buf)
294 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
295 unsigned long val = drvdata->trigger_cntr;
297 return sprintf(buf, "%#lx\n", val);
300 static ssize_t trigger_cntr_store(struct device *dev,
301 struct device_attribute *attr,
302 const char *buf, size_t size)
306 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
308 ret = kstrtoul(buf, 16, &val);
312 drvdata->trigger_cntr = val;
315 static DEVICE_ATTR_RW(trigger_cntr);
317 static ssize_t buffer_size_show(struct device *dev,
318 struct device_attribute *attr, char *buf)
320 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
322 return sprintf(buf, "%#x\n", drvdata->size);
325 static ssize_t buffer_size_store(struct device *dev,
326 struct device_attribute *attr,
327 const char *buf, size_t size)
331 struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
333 /* Only permitted for TMC-ETRs */
334 if (drvdata->config_type != TMC_CONFIG_TYPE_ETR)
337 ret = kstrtoul(buf, 0, &val);
340 /* The buffer size should be page aligned */
341 if (val & (PAGE_SIZE - 1))
347 static DEVICE_ATTR_RW(buffer_size);
349 static struct attribute *coresight_tmc_attrs[] = {
350 &dev_attr_trigger_cntr.attr,
351 &dev_attr_buffer_size.attr,
355 static const struct attribute_group coresight_tmc_group = {
356 .attrs = coresight_tmc_attrs,
359 static const struct attribute_group coresight_tmc_mgmt_group = {
360 .attrs = coresight_tmc_mgmt_attrs,
364 const struct attribute_group *coresight_tmc_groups[] = {
365 &coresight_tmc_group,
366 &coresight_tmc_mgmt_group,
370 static inline bool tmc_etr_can_use_sg(struct device *dev)
372 return fwnode_property_present(dev->fwnode, "arm,scatter-gather");
375 static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
377 u32 auth = readl_relaxed(drvdata->base + TMC_AUTHSTATUS);
379 return (auth & TMC_AUTH_NSID_MASK) == 0x3;
382 /* Detect and initialise the capabilities of a TMC ETR */
383 static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
387 struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
389 if (!tmc_etr_has_non_secure_access(drvdata))
392 /* Set the unadvertised capabilities */
393 tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
395 if (!(devid & TMC_DEVID_NOSCAT) && tmc_etr_can_use_sg(parent))
396 tmc_etr_set_cap(drvdata, TMC_ETR_SG);
398 /* Check if the AXI address width is available */
399 if (devid & TMC_DEVID_AXIAW_VALID)
400 dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
401 TMC_DEVID_AXIAW_MASK);
404 * Unless specified in the device configuration, ETR uses a 40-bit
405 * AXI master in place of the embedded SRAM of ETB/ETF.
413 dev_info(parent, "Detected dma mask %dbits\n", dma_mask);
419 rc = dma_set_mask_and_coherent(parent, DMA_BIT_MASK(dma_mask));
421 dev_err(parent, "Failed to setup DMA mask: %d\n", rc);
425 static u32 tmc_etr_get_default_buffer_size(struct device *dev)
429 if (fwnode_property_read_u32(dev->fwnode, "arm,buffer-size", &size))
434 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
439 struct device *dev = &adev->dev;
440 struct coresight_platform_data *pdata = NULL;
441 struct tmc_drvdata *drvdata;
442 struct resource *res = &adev->res;
443 struct coresight_desc desc = { 0 };
444 struct coresight_dev_list *dev_list = NULL;
447 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
451 dev_set_drvdata(dev, drvdata);
453 /* Validity for the resource is already checked by the AMBA core */
454 base = devm_ioremap_resource(dev, res);
460 drvdata->base = base;
462 spin_lock_init(&drvdata->spinlock);
464 devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
465 drvdata->config_type = BMVAL(devid, 6, 7);
466 drvdata->memwidth = tmc_get_memwidth(devid);
467 /* This device is not associated with a session */
470 if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
471 drvdata->size = tmc_etr_get_default_buffer_size(dev);
473 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
476 desc.groups = coresight_tmc_groups;
478 switch (drvdata->config_type) {
479 case TMC_CONFIG_TYPE_ETB:
480 desc.type = CORESIGHT_DEV_TYPE_SINK;
481 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
482 desc.ops = &tmc_etb_cs_ops;
483 dev_list = &etb_devs;
485 case TMC_CONFIG_TYPE_ETR:
486 desc.type = CORESIGHT_DEV_TYPE_SINK;
487 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
488 desc.ops = &tmc_etr_cs_ops;
489 ret = tmc_etr_setup_caps(dev, devid,
490 coresight_get_uci_data(id));
493 idr_init(&drvdata->idr);
494 mutex_init(&drvdata->idr_mutex);
495 dev_list = &etr_devs;
497 case TMC_CONFIG_TYPE_ETF:
498 desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
499 desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
500 desc.ops = &tmc_etf_cs_ops;
501 dev_list = &etf_devs;
504 pr_err("%s: Unsupported TMC config\n", desc.name);
509 desc.name = coresight_alloc_device_name(dev_list, dev);
515 pdata = coresight_get_platform_data(dev);
517 ret = PTR_ERR(pdata);
520 adev->dev.platform_data = pdata;
523 drvdata->csdev = coresight_register(&desc);
524 if (IS_ERR(drvdata->csdev)) {
525 ret = PTR_ERR(drvdata->csdev);
529 drvdata->miscdev.name = desc.name;
530 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
531 drvdata->miscdev.fops = &tmc_fops;
532 ret = misc_register(&drvdata->miscdev);
534 coresight_unregister(drvdata->csdev);
536 pm_runtime_put(&adev->dev);
541 static const struct amba_id tmc_ids[] = {
542 CS_AMBA_ID(0x000bb961),
543 /* Coresight SoC 600 TMC-ETR/ETS */
544 CS_AMBA_ID_DATA(0x000bb9e8, (unsigned long)CORESIGHT_SOC_600_ETR_CAPS),
545 /* Coresight SoC 600 TMC-ETB */
546 CS_AMBA_ID(0x000bb9e9),
547 /* Coresight SoC 600 TMC-ETF */
548 CS_AMBA_ID(0x000bb9ea),
552 static struct amba_driver tmc_driver = {
554 .name = "coresight-tmc",
555 .owner = THIS_MODULE,
556 .suppress_bind_attrs = true,
561 builtin_amba_driver(tmc_driver);