drivers/i2c/busses/i2c-aspeed.c

   1 /*
   2  *  Aspeed 24XX/25XX I2C Controller.
   3  *
   4  *  Copyright (C) 2012-2017 ASPEED Technology Inc.
   5  *  Copyright 2017 IBM Corporation
   6  *  Copyright 2017 Google, Inc.
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/clk.h>
  14 #include <linux/completion.h>
  15 #include <linux/err.h>
  16 #include <linux/errno.h>
  17 #include <linux/i2c.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/irq.h>
  22 #include <linux/irqchip/chained_irq.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/reset.h>
  31 #include <linux/slab.h>
  32
  33 /* I2C Register */
  34 #define ASPEED_I2C_FUN_CTRL_REG                         0x00
  35 #define ASPEED_I2C_AC_TIMING_REG1                       0x04
  36 #define ASPEED_I2C_AC_TIMING_REG2                       0x08
  37 #define ASPEED_I2C_INTR_CTRL_REG                        0x0c
  38 #define ASPEED_I2C_INTR_STS_REG                         0x10
  39 #define ASPEED_I2C_CMD_REG                              0x14
  40 #define ASPEED_I2C_DEV_ADDR_REG                         0x18
  41 #define ASPEED_I2C_BYTE_BUF_REG                         0x20
  42
  43 /* Global Register Definition */
  44 /* 0x00 : I2C Interrupt Status Register  */
  45 /* 0x08 : I2C Interrupt Target Assignment  */
  46
  47 /* Device Register Definition */
  48 /* 0x00 : I2CD Function Control Register  */
  49 #define ASPEED_I2CD_MULTI_MASTER_DIS                    BIT(15)
  50 #define ASPEED_I2CD_SDA_DRIVE_1T_EN                     BIT(8)
  51 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN                   BIT(7)
  52 #define ASPEED_I2CD_M_HIGH_SPEED_EN                     BIT(6)
  53 #define ASPEED_I2CD_SLAVE_EN                            BIT(1)
  54 #define ASPEED_I2CD_MASTER_EN                           BIT(0)
  55
  56 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
  57 #define ASPEED_I2CD_TIME_TBUF_MASK                      GENMASK(31, 28)
  58 #define ASPEED_I2CD_TIME_THDSTA_MASK                    GENMASK(27, 24)
  59 #define ASPEED_I2CD_TIME_TACST_MASK                     GENMASK(23, 20)
  60 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT                 16
  61 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK                  GENMASK(19, 16)
  62 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT                  12
  63 #define ASPEED_I2CD_TIME_SCL_LOW_MASK                   GENMASK(15, 12)
  64 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK              GENMASK(3, 0)
  65 #define ASPEED_I2CD_TIME_SCL_REG_MAX                    GENMASK(3, 0)
  66 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
  67 #define ASPEED_NO_TIMEOUT_CTRL                          0
  68
  69 /* 0x0c : I2CD Interrupt Control Register &
  70  * 0x10 : I2CD Interrupt Status Register
  71  *
  72  * These share bit definitions, so use the same values for the enable &
  73  * status bits.
  74  */
  75 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT                 BIT(14)
  76 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE               BIT(13)
  77 #define ASPEED_I2CD_INTR_SLAVE_MATCH                    BIT(7)
  78 #define ASPEED_I2CD_INTR_SCL_TIMEOUT                    BIT(6)
  79 #define ASPEED_I2CD_INTR_ABNORMAL                       BIT(5)
  80 #define ASPEED_I2CD_INTR_NORMAL_STOP                    BIT(4)
  81 #define ASPEED_I2CD_INTR_ARBIT_LOSS                     BIT(3)
  82 #define ASPEED_I2CD_INTR_RX_DONE                        BIT(2)
  83 #define ASPEED_I2CD_INTR_TX_NAK                         BIT(1)
  84 #define ASPEED_I2CD_INTR_TX_ACK                         BIT(0)
  85 #define ASPEED_I2CD_INTR_MASTER_ERRORS                                         \
  86                 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |                             \
  87                  ASPEED_I2CD_INTR_SCL_TIMEOUT |                                \
  88                  ASPEED_I2CD_INTR_ABNORMAL |                                   \
  89                  ASPEED_I2CD_INTR_ARBIT_LOSS)
  90 #define ASPEED_I2CD_INTR_ALL                                                   \
  91                 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |                             \
  92                  ASPEED_I2CD_INTR_BUS_RECOVER_DONE |                           \
  93                  ASPEED_I2CD_INTR_SCL_TIMEOUT |                                \
  94                  ASPEED_I2CD_INTR_ABNORMAL |                                   \
  95                  ASPEED_I2CD_INTR_NORMAL_STOP |                                \
  96                  ASPEED_I2CD_INTR_ARBIT_LOSS |                                 \
  97                  ASPEED_I2CD_INTR_RX_DONE |                                    \
  98                  ASPEED_I2CD_INTR_TX_NAK |                                     \
  99                  ASPEED_I2CD_INTR_TX_ACK)
 100
 101 /* 0x14 : I2CD Command/Status Register   */
 102 #define ASPEED_I2CD_SCL_LINE_STS                        BIT(18)
 103 #define ASPEED_I2CD_SDA_LINE_STS                        BIT(17)
 104 #define ASPEED_I2CD_BUS_BUSY_STS                        BIT(16)
 105 #define ASPEED_I2CD_BUS_RECOVER_CMD                     BIT(11)
 106
 107 /* Command Bit */
 108 #define ASPEED_I2CD_M_STOP_CMD                          BIT(5)
 109 #define ASPEED_I2CD_M_S_RX_CMD_LAST                     BIT(4)
 110 #define ASPEED_I2CD_M_RX_CMD                            BIT(3)
 111 #define ASPEED_I2CD_S_TX_CMD                            BIT(2)
 112 #define ASPEED_I2CD_M_TX_CMD                            BIT(1)
 113 #define ASPEED_I2CD_M_START_CMD                         BIT(0)
 114
 115 /* 0x18 : I2CD Slave Device Address Register   */
 116 #define ASPEED_I2CD_DEV_ADDR_MASK                       GENMASK(6, 0)
 117
 118 enum aspeed_i2c_master_state {
 119         ASPEED_I2C_MASTER_INACTIVE,
 120         ASPEED_I2C_MASTER_START,
 121         ASPEED_I2C_MASTER_TX_FIRST,
 122         ASPEED_I2C_MASTER_TX,
 123         ASPEED_I2C_MASTER_RX_FIRST,
 124         ASPEED_I2C_MASTER_RX,
 125         ASPEED_I2C_MASTER_STOP,
 126 };
 127
 128 enum aspeed_i2c_slave_state {
 129         ASPEED_I2C_SLAVE_STOP,
 130         ASPEED_I2C_SLAVE_START,
 131         ASPEED_I2C_SLAVE_READ_REQUESTED,
 132         ASPEED_I2C_SLAVE_READ_PROCESSED,
 133         ASPEED_I2C_SLAVE_WRITE_REQUESTED,
 134         ASPEED_I2C_SLAVE_WRITE_RECEIVED,
 135 };
 136
 137 struct aspeed_i2c_bus {
 138         struct i2c_adapter              adap;
 139         struct device                   *dev;
 140         void __iomem                    *base;
 141         struct reset_control            *rst;
 142         /* Synchronizes I/O mem access to base. */
 143         spinlock_t                      lock;
 144         struct completion               cmd_complete;
 145         u32                             (*get_clk_reg_val)(struct device *dev,
 146                                                            u32 divisor);
 147         unsigned long                   parent_clk_frequency;
 148         u32                             bus_frequency;
 149         /* Transaction state. */
 150         enum aspeed_i2c_master_state    master_state;
 151         struct i2c_msg                  *msgs;
 152         size_t                          buf_index;
 153         size_t                          msgs_index;
 154         size_t                          msgs_count;
 155         bool                            send_stop;
 156         int                             cmd_err;
 157         /* Protected only by i2c_lock_bus */
 158         int                             master_xfer_result;
 159 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 160         struct i2c_client               *slave;
 161         enum aspeed_i2c_slave_state     slave_state;
 162 #endif /* CONFIG_I2C_SLAVE */
 163 };
 164
 165 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
 166
 167 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
 168 {
 169         unsigned long time_left, flags;
 170         int ret = 0;
 171         u32 command;
 172
 173         spin_lock_irqsave(&bus->lock, flags);
 174         command = readl(bus->base + ASPEED_I2C_CMD_REG);
 175
 176         if (command & ASPEED_I2CD_SDA_LINE_STS) {
 177                 /* Bus is idle: no recovery needed. */
 178                 if (command & ASPEED_I2CD_SCL_LINE_STS)
 179                         goto out;
 180                 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
 181                         command);
 182
 183                 reinit_completion(&bus->cmd_complete);
 184                 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
 185                 spin_unlock_irqrestore(&bus->lock, flags);
 186
 187                 time_left = wait_for_completion_timeout(
 188                                 &bus->cmd_complete, bus->adap.timeout);
 189
 190                 spin_lock_irqsave(&bus->lock, flags);
 191                 if (time_left == 0)
 192                         goto reset_out;
 193                 else if (bus->cmd_err)
 194                         goto reset_out;
 195                 /* Recovery failed. */
 196                 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
 197                            ASPEED_I2CD_SCL_LINE_STS))
 198                         goto reset_out;
 199         /* Bus error. */
 200         } else {
 201                 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
 202                         command);
 203
 204                 reinit_completion(&bus->cmd_complete);
 205                 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
 206                 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
 207                        bus->base + ASPEED_I2C_CMD_REG);
 208                 spin_unlock_irqrestore(&bus->lock, flags);
 209
 210                 time_left = wait_for_completion_timeout(
 211                                 &bus->cmd_complete, bus->adap.timeout);
 212
 213                 spin_lock_irqsave(&bus->lock, flags);
 214                 if (time_left == 0)
 215                         goto reset_out;
 216                 else if (bus->cmd_err)
 217                         goto reset_out;
 218                 /* Recovery failed. */
 219                 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
 220                            ASPEED_I2CD_SDA_LINE_STS))
 221                         goto reset_out;
 222         }
 223
 224 out:
 225         spin_unlock_irqrestore(&bus->lock, flags);
 226
 227         return ret;
 228
 229 reset_out:
 230         spin_unlock_irqrestore(&bus->lock, flags);
 231
 232         return aspeed_i2c_reset(bus);
 233 }
 234
 235 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 236 static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
 237 {
 238         u32 command, irq_handled = 0;
 239         struct i2c_client *slave = bus->slave;
 240         u8 value;
 241
 242         if (!slave)
 243                 return 0;
 244
 245         command = readl(bus->base + ASPEED_I2C_CMD_REG);
 246
 247         /* Slave was requested, restart state machine. */
 248         if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
 249                 irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
 250                 bus->slave_state = ASPEED_I2C_SLAVE_START;
 251         }
 252
 253         /* Slave is not currently active, irq was for someone else. */
 254         if (bus->slave_state == ASPEED_I2C_SLAVE_STOP)
 255                 return irq_handled;
 256
 257         dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
 258                 irq_status, command);
 259
 260         /* Slave was sent something. */
 261         if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
 262                 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
 263                 /* Handle address frame. */
 264                 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
 265                         if (value & 0x1)
 266                                 bus->slave_state =
 267                                                 ASPEED_I2C_SLAVE_READ_REQUESTED;
 268                         else
 269                                 bus->slave_state =
 270                                                 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
 271                 }
 272                 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
 273         }
 274
 275         /* Slave was asked to stop. */
 276         if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
 277                 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
 278                 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
 279         }
 280         if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
 281                 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
 282                 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
 283         }
 284         if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
 285                 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
 286
 287         switch (bus->slave_state) {
 288         case ASPEED_I2C_SLAVE_READ_REQUESTED:
 289                 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
 290                         dev_err(bus->dev, "Unexpected ACK on read request.\n");
 291                 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
 292                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
 293                 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
 294                 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
 295                 break;
 296         case ASPEED_I2C_SLAVE_READ_PROCESSED:
 297                 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
 298                         dev_err(bus->dev,
 299                                 "Expected ACK after processed read.\n");
 300                 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
 301                 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
 302                 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
 303                 break;
 304         case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
 305                 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
 306                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
 307                 break;
 308         case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
 309                 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
 310                 break;
 311         case ASPEED_I2C_SLAVE_STOP:
 312                 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
 313                 break;
 314         default:
 315                 dev_err(bus->dev, "unhandled slave_state: %d\n",
 316                         bus->slave_state);
 317                 break;
 318         }
 319
 320         return irq_handled;
 321 }
 322 #endif /* CONFIG_I2C_SLAVE */
 323
 324 /* precondition: bus.lock has been acquired. */
 325 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
 326 {
 327         u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
 328         struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
 329         u8 slave_addr = i2c_8bit_addr_from_msg(msg);
 330
 331         bus->master_state = ASPEED_I2C_MASTER_START;
 332         bus->buf_index = 0;
 333
 334         if (msg->flags & I2C_M_RD) {
 335                 command |= ASPEED_I2CD_M_RX_CMD;
 336                 /* Need to let the hardware know to NACK after RX. */
 337                 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
 338                         command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
 339         }
 340
 341         writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
 342         writel(command, bus->base + ASPEED_I2C_CMD_REG);
 343 }
 344
 345 /* precondition: bus.lock has been acquired. */
 346 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
 347 {
 348         bus->master_state = ASPEED_I2C_MASTER_STOP;
 349         writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
 350 }
 351
 352 /* precondition: bus.lock has been acquired. */
 353 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
 354 {
 355         if (bus->msgs_index + 1 < bus->msgs_count) {
 356                 bus->msgs_index++;
 357                 aspeed_i2c_do_start(bus);
 358         } else {
 359                 aspeed_i2c_do_stop(bus);
 360         }
 361 }
 362
 363 static int aspeed_i2c_is_irq_error(u32 irq_status)
 364 {
 365         if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
 366                 return -EAGAIN;
 367         if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
 368                           ASPEED_I2CD_INTR_SCL_TIMEOUT))
 369                 return -EBUSY;
 370         if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
 371                 return -EPROTO;
 372
 373         return 0;
 374 }
 375
 376 static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
 377 {
 378         u32 irq_handled = 0, command = 0;
 379         struct i2c_msg *msg;
 380         u8 recv_byte;
 381         int ret;
 382
 383         if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
 384                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
 385                 irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
 386                 goto out_complete;
 387         } else {
 388                 /* Master is not currently active, irq was for someone else. */
 389                 if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE)
 390                         goto out_no_complete;
 391         }
 392
 393         /*
 394          * We encountered an interrupt that reports an error: the hardware
 395          * should clear the command queue effectively taking us back to the
 396          * INACTIVE state.
 397          */
 398         ret = aspeed_i2c_is_irq_error(irq_status);
 399         if (ret) {
 400                 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
 401                         irq_status);
 402                 bus->cmd_err = ret;
 403                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
 404                 irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
 405                 goto out_complete;
 406         }
 407
 408         /* We are in an invalid state; reset bus to a known state. */
 409         if (!bus->msgs) {
 410                 dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
 411                         irq_status);
 412                 bus->cmd_err = -EIO;
 413                 if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
 414                     bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
 415                         aspeed_i2c_do_stop(bus);
 416                 goto out_no_complete;
 417         }
 418         msg = &bus->msgs[bus->msgs_index];
 419
 420         /*
 421          * START is a special case because we still have to handle a subsequent
 422          * TX or RX immediately after we handle it, so we handle it here and
 423          * then update the state and handle the new state below.
 424          */
 425         if (bus->master_state == ASPEED_I2C_MASTER_START) {
 426                 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
 427                         if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
 428                                 bus->cmd_err = -ENXIO;
 429                                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
 430                                 goto out_complete;
 431                         }
 432                         pr_devel("no slave present at %02x\n", msg->addr);
 433                         irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
 434                         bus->cmd_err = -ENXIO;
 435                         aspeed_i2c_do_stop(bus);
 436                         goto out_no_complete;
 437                 }
 438                 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
 439                 if (msg->len == 0) { /* SMBUS_QUICK */
 440                         aspeed_i2c_do_stop(bus);
 441                         goto out_no_complete;
 442                 }
 443                 if (msg->flags & I2C_M_RD)
 444                         bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
 445                 else
 446                         bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
 447         }
 448
 449         switch (bus->master_state) {
 450         case ASPEED_I2C_MASTER_TX:
 451                 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
 452                         dev_dbg(bus->dev, "slave NACKed TX\n");
 453                         irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
 454                         goto error_and_stop;
 455                 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
 456                         dev_err(bus->dev, "slave failed to ACK TX\n");
 457                         goto error_and_stop;
 458                 }
 459                 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
 460                 /* fall through */
 461         case ASPEED_I2C_MASTER_TX_FIRST:
 462                 if (bus->buf_index < msg->len) {
 463                         bus->master_state = ASPEED_I2C_MASTER_TX;
 464                         writel(msg->buf[bus->buf_index++],
 465                                bus->base + ASPEED_I2C_BYTE_BUF_REG);
 466                         writel(ASPEED_I2CD_M_TX_CMD,
 467                                bus->base + ASPEED_I2C_CMD_REG);
 468                 } else {
 469                         aspeed_i2c_next_msg_or_stop(bus);
 470                 }
 471                 goto out_no_complete;
 472         case ASPEED_I2C_MASTER_RX_FIRST:
 473                 /* RX may not have completed yet (only address cycle) */
 474                 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
 475                         goto out_no_complete;
 476                 /* fall through */
 477         case ASPEED_I2C_MASTER_RX:
 478                 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
 479                         dev_err(bus->dev, "master failed to RX\n");
 480                         goto error_and_stop;
 481                 }
 482                 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
 483
 484                 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
 485                 msg->buf[bus->buf_index++] = recv_byte;
 486
 487                 if (msg->flags & I2C_M_RECV_LEN) {
 488                         if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
 489                                 bus->cmd_err = -EPROTO;
 490                                 aspeed_i2c_do_stop(bus);
 491                                 goto out_no_complete;
 492                         }
 493                         msg->len = recv_byte +
 494                                         ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
 495                         msg->flags &= ~I2C_M_RECV_LEN;
 496                 }
 497
 498                 if (bus->buf_index < msg->len) {
 499                         bus->master_state = ASPEED_I2C_MASTER_RX;
 500                         command = ASPEED_I2CD_M_RX_CMD;
 501                         if (bus->buf_index + 1 == msg->len)
 502                                 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
 503                         writel(command, bus->base + ASPEED_I2C_CMD_REG);
 504                 } else {
 505                         aspeed_i2c_next_msg_or_stop(bus);
 506                 }
 507                 goto out_no_complete;
 508         case ASPEED_I2C_MASTER_STOP:
 509                 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
 510                         dev_err(bus->dev,
 511                                 "master failed to STOP. irq_status:0x%x\n",
 512                                 irq_status);
 513                         bus->cmd_err = -EIO;
 514                         /* Do not STOP as we have already tried. */
 515                 } else {
 516                         irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
 517                 }
 518
 519                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
 520                 goto out_complete;
 521         case ASPEED_I2C_MASTER_INACTIVE:
 522                 dev_err(bus->dev,
 523                         "master received interrupt 0x%08x, but is inactive\n",
 524                         irq_status);
 525                 bus->cmd_err = -EIO;
 526                 /* Do not STOP as we should be inactive. */
 527                 goto out_complete;
 528         default:
 529                 WARN(1, "unknown master state\n");
 530                 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
 531                 bus->cmd_err = -EINVAL;
 532                 goto out_complete;
 533         }
 534 error_and_stop:
 535         bus->cmd_err = -EIO;
 536         aspeed_i2c_do_stop(bus);
 537         goto out_no_complete;
 538 out_complete:
 539         bus->msgs = NULL;
 540         if (bus->cmd_err)
 541                 bus->master_xfer_result = bus->cmd_err;
 542         else
 543                 bus->master_xfer_result = bus->msgs_index + 1;
 544         complete(&bus->cmd_complete);
 545 out_no_complete:
 546         return irq_handled;
 547 }
 548
 549 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
 550 {
 551         struct aspeed_i2c_bus *bus = dev_id;
 552         u32 irq_received, irq_remaining, irq_handled;
 553
 554         spin_lock(&bus->lock);
 555         irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
 556         /* Ack all interrupts except for Rx done */
 557         writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
 558                bus->base + ASPEED_I2C_INTR_STS_REG);
 559         irq_remaining = irq_received;
 560
 561 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 562         /*
 563          * In most cases, interrupt bits will be set one by one, although
 564          * multiple interrupt bits could be set at the same time. It's also
 565          * possible that master interrupt bits could be set along with slave
 566          * interrupt bits. Each case needs to be handled using corresponding
 567          * handlers depending on the current state.
 568          */
 569         if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
 570                 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
 571                 irq_remaining &= ~irq_handled;
 572                 if (irq_remaining)
 573                         irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
 574         } else {
 575                 irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
 576                 irq_remaining &= ~irq_handled;
 577                 if (irq_remaining)
 578                         irq_handled |= aspeed_i2c_master_irq(bus,
 579                                                              irq_remaining);
 580         }
 581 #else
 582         irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
 583 #endif /* CONFIG_I2C_SLAVE */
 584
 585         irq_remaining &= ~irq_handled;
 586         if (irq_remaining)
 587                 dev_err(bus->dev,
 588                         "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
 589                         irq_received, irq_handled);
 590
 591         /* Ack Rx done */
 592         if (irq_received & ASPEED_I2CD_INTR_RX_DONE)
 593                 writel(ASPEED_I2CD_INTR_RX_DONE,
 594                        bus->base + ASPEED_I2C_INTR_STS_REG);
 595         spin_unlock(&bus->lock);
 596         return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
 597 }
 598
 599 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
 600                                   struct i2c_msg *msgs, int num)
 601 {
 602         struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
 603         unsigned long time_left, flags;
 604         int ret = 0;
 605
 606         spin_lock_irqsave(&bus->lock, flags);
 607         bus->cmd_err = 0;
 608
 609         /* If bus is busy, attempt recovery. We assume a single master
 610          * environment.
 611          */
 612         if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
 613                 spin_unlock_irqrestore(&bus->lock, flags);
 614                 ret = aspeed_i2c_recover_bus(bus);
 615                 if (ret)
 616                         return ret;
 617                 spin_lock_irqsave(&bus->lock, flags);
 618         }
 619
 620         bus->cmd_err = 0;
 621         bus->msgs = msgs;
 622         bus->msgs_index = 0;
 623         bus->msgs_count = num;
 624
 625         reinit_completion(&bus->cmd_complete);
 626         aspeed_i2c_do_start(bus);
 627         spin_unlock_irqrestore(&bus->lock, flags);
 628
 629         time_left = wait_for_completion_timeout(&bus->cmd_complete,
 630                                                 bus->adap.timeout);
 631
 632         if (time_left == 0)
 633                 return -ETIMEDOUT;
 634         else
 635                 return bus->master_xfer_result;
 636 }
 637
 638 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
 639 {
 640         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
 641 }
 642
 643 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 644 /* precondition: bus.lock has been acquired. */
 645 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
 646 {
 647         u32 addr_reg_val, func_ctrl_reg_val;
 648
 649         /* Set slave addr. */
 650         addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
 651         addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
 652         addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
 653         writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
 654
 655         /* Turn on slave mode. */
 656         func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
 657         func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
 658         writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
 659 }
 660
 661 static int aspeed_i2c_reg_slave(struct i2c_client *client)
 662 {
 663         struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
 664         unsigned long flags;
 665
 666         spin_lock_irqsave(&bus->lock, flags);
 667         if (bus->slave) {
 668                 spin_unlock_irqrestore(&bus->lock, flags);
 669                 return -EINVAL;
 670         }
 671
 672         __aspeed_i2c_reg_slave(bus, client->addr);
 673
 674         bus->slave = client;
 675         bus->slave_state = ASPEED_I2C_SLAVE_STOP;
 676         spin_unlock_irqrestore(&bus->lock, flags);
 677
 678         return 0;
 679 }
 680
 681 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
 682 {
 683         struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
 684         u32 func_ctrl_reg_val;
 685         unsigned long flags;
 686
 687         spin_lock_irqsave(&bus->lock, flags);
 688         if (!bus->slave) {
 689                 spin_unlock_irqrestore(&bus->lock, flags);
 690                 return -EINVAL;
 691         }
 692
 693         /* Turn off slave mode. */
 694         func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
 695         func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
 696         writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
 697
 698         bus->slave = NULL;
 699         spin_unlock_irqrestore(&bus->lock, flags);
 700
 701         return 0;
 702 }
 703 #endif /* CONFIG_I2C_SLAVE */
 704
 705 static const struct i2c_algorithm aspeed_i2c_algo = {
 706         .master_xfer    = aspeed_i2c_master_xfer,
 707         .functionality  = aspeed_i2c_functionality,
 708 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 709         .reg_slave      = aspeed_i2c_reg_slave,
 710         .unreg_slave    = aspeed_i2c_unreg_slave,
 711 #endif /* CONFIG_I2C_SLAVE */
 712 };
 713
 714 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
 715                                       u32 clk_high_low_mask,
 716                                       u32 divisor)
 717 {
 718         u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
 719
 720         /*
 721          * SCL_high and SCL_low represent a value 1 greater than what is stored
 722          * since a zero divider is meaningless. Thus, the max value each can
 723          * store is every bit set + 1. Since SCL_high and SCL_low are added
 724          * together (see below), the max value of both is the max value of one
 725          * them times two.
 726          */
 727         clk_high_low_max = (clk_high_low_mask + 1) * 2;
 728
 729         /*
 730          * The actual clock frequency of SCL is:
 731          *      SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
 732          *               = APB_freq / divisor
 733          * where base_freq is a programmable clock divider; its value is
 734          *      base_freq = 1 << base_clk_divisor
 735          * SCL_high is the number of base_freq clock cycles that SCL stays high
 736          * and SCL_low is the number of base_freq clock cycles that SCL stays
 737          * low for a period of SCL.
 738          * The actual register has a minimum SCL_high and SCL_low minimum of 1;
 739          * thus, they start counting at zero. So
 740          *      SCL_high = clk_high + 1
 741          *      SCL_low  = clk_low + 1
 742          * Thus,
 743          *      SCL_freq = APB_freq /
 744          *              ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
 745          * The documentation recommends clk_high >= clk_high_max / 2 and
 746          * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
 747          * gives us the following solution:
 748          */
 749         base_clk_divisor = divisor > clk_high_low_max ?
 750                         ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
 751
 752         if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
 753                 base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
 754                 clk_low = clk_high_low_mask;
 755                 clk_high = clk_high_low_mask;
 756                 dev_err(dev,
 757                         "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
 758                         divisor, (1 << base_clk_divisor) * clk_high_low_max);
 759         } else {
 760                 tmp = (divisor + (1 << base_clk_divisor) - 1)
 761                                 >> base_clk_divisor;
 762                 clk_low = tmp / 2;
 763                 clk_high = tmp - clk_low;
 764
 765                 if (clk_high)
 766                         clk_high--;
 767
 768                 if (clk_low)
 769                         clk_low--;
 770         }
 771
 772
 773         return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
 774                 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
 775                         | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
 776                            & ASPEED_I2CD_TIME_SCL_LOW_MASK)
 777                         | (base_clk_divisor
 778                            & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
 779 }
 780
 781 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
 782 {
 783         /*
 784          * clk_high and clk_low are each 3 bits wide, so each can hold a max
 785          * value of 8 giving a clk_high_low_max of 16.
 786          */
 787         return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
 788 }
 789
 790 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
 791 {
 792         /*
 793          * clk_high and clk_low are each 4 bits wide, so each can hold a max
 794          * value of 16 giving a clk_high_low_max of 32.
 795          */
 796         return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
 797 }
 798
 799 /* precondition: bus.lock has been acquired. */
 800 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
 801 {
 802         u32 divisor, clk_reg_val;
 803
 804         divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
 805         clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
 806         clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
 807                         ASPEED_I2CD_TIME_THDSTA_MASK |
 808                         ASPEED_I2CD_TIME_TACST_MASK);
 809         clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
 810         writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
 811         writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
 812
 813         return 0;
 814 }
 815
 816 /* precondition: bus.lock has been acquired. */
 817 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
 818                              struct platform_device *pdev)
 819 {
 820         u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
 821         int ret;
 822
 823         /* Disable everything. */
 824         writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
 825
 826         ret = aspeed_i2c_init_clk(bus);
 827         if (ret < 0)
 828                 return ret;
 829
 830         if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
 831                 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
 832
 833         /* Enable Master Mode */
 834         writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
 835                bus->base + ASPEED_I2C_FUN_CTRL_REG);
 836
 837 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 838         /* If slave has already been registered, re-enable it. */
 839         if (bus->slave)
 840                 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
 841 #endif /* CONFIG_I2C_SLAVE */
 842
 843         /* Set interrupt generation of I2C controller */
 844         writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
 845
 846         return 0;
 847 }
 848
 849 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
 850 {
 851         struct platform_device *pdev = to_platform_device(bus->dev);
 852         unsigned long flags;
 853         int ret;
 854
 855         spin_lock_irqsave(&bus->lock, flags);
 856
 857         /* Disable and ack all interrupts. */
 858         writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
 859         writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
 860
 861         ret = aspeed_i2c_init(bus, pdev);
 862
 863         spin_unlock_irqrestore(&bus->lock, flags);
 864
 865         return ret;
 866 }
 867
 868 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
 869         {
 870                 .compatible = "aspeed,ast2400-i2c-bus",
 871                 .data = aspeed_i2c_24xx_get_clk_reg_val,
 872         },
 873         {
 874                 .compatible = "aspeed,ast2500-i2c-bus",
 875                 .data = aspeed_i2c_25xx_get_clk_reg_val,
 876         },
 877         { },
 878 };
 879 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
 880
 881 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
 882 {
 883         const struct of_device_id *match;
 884         struct aspeed_i2c_bus *bus;
 885         struct clk *parent_clk;
 886         struct resource *res;
 887         int irq, ret;
 888
 889         bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
 890         if (!bus)
 891                 return -ENOMEM;
 892
 893         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 894         bus->base = devm_ioremap_resource(&pdev->dev, res);
 895         if (IS_ERR(bus->base))
 896                 return PTR_ERR(bus->base);
 897
 898         parent_clk = devm_clk_get(&pdev->dev, NULL);
 899         if (IS_ERR(parent_clk))
 900                 return PTR_ERR(parent_clk);
 901         bus->parent_clk_frequency = clk_get_rate(parent_clk);
 902         /* We just need the clock rate, we don't actually use the clk object. */
 903         devm_clk_put(&pdev->dev, parent_clk);
 904
 905         bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
 906         if (IS_ERR(bus->rst)) {
 907                 dev_err(&pdev->dev,
 908                         "missing or invalid reset controller device tree entry\n");
 909                 return PTR_ERR(bus->rst);
 910         }
 911         reset_control_deassert(bus->rst);
 912
 913         ret = of_property_read_u32(pdev->dev.of_node,
 914                                    "bus-frequency", &bus->bus_frequency);
 915         if (ret < 0) {
 916                 dev_err(&pdev->dev,
 917                         "Could not read bus-frequency property\n");
 918                 bus->bus_frequency = 100000;
 919         }
 920
 921         match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
 922         if (!match)
 923                 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
 924         else
 925                 bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
 926                                 match->data;
 927
 928         /* Initialize the I2C adapter */
 929         spin_lock_init(&bus->lock);
 930         init_completion(&bus->cmd_complete);
 931         bus->adap.owner = THIS_MODULE;
 932         bus->adap.retries = 0;
 933         bus->adap.timeout = 5 * HZ;
 934         bus->adap.algo = &aspeed_i2c_algo;
 935         bus->adap.dev.parent = &pdev->dev;
 936         bus->adap.dev.of_node = pdev->dev.of_node;
 937         strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
 938         i2c_set_adapdata(&bus->adap, bus);
 939
 940         bus->dev = &pdev->dev;
 941
 942         /* Clean up any left over interrupt state. */
 943         writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
 944         writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
 945         /*
 946          * bus.lock does not need to be held because the interrupt handler has
 947          * not been enabled yet.
 948          */
 949         ret = aspeed_i2c_init(bus, pdev);
 950         if (ret < 0)
 951                 return ret;
 952
 953         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 954         ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
 955                                0, dev_name(&pdev->dev), bus);
 956         if (ret < 0)
 957                 return ret;
 958
 959         ret = i2c_add_adapter(&bus->adap);
 960         if (ret < 0)
 961                 return ret;
 962
 963         platform_set_drvdata(pdev, bus);
 964
 965         dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
 966                  bus->adap.nr, irq);
 967
 968         return 0;
 969 }
 970
 971 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
 972 {
 973         struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
 974         unsigned long flags;
 975
 976         spin_lock_irqsave(&bus->lock, flags);
 977
 978         /* Disable everything. */
 979         writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
 980         writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
 981
 982         spin_unlock_irqrestore(&bus->lock, flags);
 983
 984         reset_control_assert(bus->rst);
 985
 986         i2c_del_adapter(&bus->adap);
 987
 988         return 0;
 989 }
 990
 991 static struct platform_driver aspeed_i2c_bus_driver = {
 992         .probe          = aspeed_i2c_probe_bus,
 993         .remove         = aspeed_i2c_remove_bus,
 994         .driver         = {
 995                 .name           = "aspeed-i2c-bus",
 996                 .of_match_table = aspeed_i2c_bus_of_table,
 997         },
 998 };
 999 module_platform_driver(aspeed_i2c_bus_driver);
1000
1001 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
1002 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
1003 MODULE_LICENSE("GPL v2");