2 * Aspeed 24XX/25XX I2C Controller.
4 * Copyright (C) 2012-2017 ASPEED Technology Inc.
5 * Copyright 2017 IBM Corporation
6 * Copyright 2017 Google, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip/chained_irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
34 #define ASPEED_I2C_FUN_CTRL_REG 0x00
35 #define ASPEED_I2C_AC_TIMING_REG1 0x04
36 #define ASPEED_I2C_AC_TIMING_REG2 0x08
37 #define ASPEED_I2C_INTR_CTRL_REG 0x0c
38 #define ASPEED_I2C_INTR_STS_REG 0x10
39 #define ASPEED_I2C_CMD_REG 0x14
40 #define ASPEED_I2C_DEV_ADDR_REG 0x18
41 #define ASPEED_I2C_BYTE_BUF_REG 0x20
43 /* Global Register Definition */
44 /* 0x00 : I2C Interrupt Status Register */
45 /* 0x08 : I2C Interrupt Target Assignment */
47 /* Device Register Definition */
48 /* 0x00 : I2CD Function Control Register */
49 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15)
50 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8)
51 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7)
52 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6)
53 #define ASPEED_I2CD_SLAVE_EN BIT(1)
54 #define ASPEED_I2CD_MASTER_EN BIT(0)
56 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */
57 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28)
58 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24)
59 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20)
60 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16
61 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16)
62 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12
63 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12)
64 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0)
65 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0)
66 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */
67 #define ASPEED_NO_TIMEOUT_CTRL 0
69 /* 0x0c : I2CD Interrupt Control Register &
70 * 0x10 : I2CD Interrupt Status Register
72 * These share bit definitions, so use the same values for the enable &
75 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14)
76 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13)
77 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7)
78 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6)
79 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5)
80 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4)
81 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3)
82 #define ASPEED_I2CD_INTR_RX_DONE BIT(2)
83 #define ASPEED_I2CD_INTR_TX_NAK BIT(1)
84 #define ASPEED_I2CD_INTR_TX_ACK BIT(0)
85 #define ASPEED_I2CD_INTR_MASTER_ERRORS \
86 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
87 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
88 ASPEED_I2CD_INTR_ABNORMAL | \
89 ASPEED_I2CD_INTR_ARBIT_LOSS)
90 #define ASPEED_I2CD_INTR_ALL \
91 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \
92 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \
93 ASPEED_I2CD_INTR_SCL_TIMEOUT | \
94 ASPEED_I2CD_INTR_ABNORMAL | \
95 ASPEED_I2CD_INTR_NORMAL_STOP | \
96 ASPEED_I2CD_INTR_ARBIT_LOSS | \
97 ASPEED_I2CD_INTR_RX_DONE | \
98 ASPEED_I2CD_INTR_TX_NAK | \
99 ASPEED_I2CD_INTR_TX_ACK)
101 /* 0x14 : I2CD Command/Status Register */
102 #define ASPEED_I2CD_SCL_LINE_STS BIT(18)
103 #define ASPEED_I2CD_SDA_LINE_STS BIT(17)
104 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16)
105 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11)
108 #define ASPEED_I2CD_M_STOP_CMD BIT(5)
109 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4)
110 #define ASPEED_I2CD_M_RX_CMD BIT(3)
111 #define ASPEED_I2CD_S_TX_CMD BIT(2)
112 #define ASPEED_I2CD_M_TX_CMD BIT(1)
113 #define ASPEED_I2CD_M_START_CMD BIT(0)
115 /* 0x18 : I2CD Slave Device Address Register */
116 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0)
118 enum aspeed_i2c_master_state {
119 ASPEED_I2C_MASTER_INACTIVE,
120 ASPEED_I2C_MASTER_START,
121 ASPEED_I2C_MASTER_TX_FIRST,
122 ASPEED_I2C_MASTER_TX,
123 ASPEED_I2C_MASTER_RX_FIRST,
124 ASPEED_I2C_MASTER_RX,
125 ASPEED_I2C_MASTER_STOP,
128 enum aspeed_i2c_slave_state {
129 ASPEED_I2C_SLAVE_STOP,
130 ASPEED_I2C_SLAVE_START,
131 ASPEED_I2C_SLAVE_READ_REQUESTED,
132 ASPEED_I2C_SLAVE_READ_PROCESSED,
133 ASPEED_I2C_SLAVE_WRITE_REQUESTED,
134 ASPEED_I2C_SLAVE_WRITE_RECEIVED,
137 struct aspeed_i2c_bus {
138 struct i2c_adapter adap;
141 struct reset_control *rst;
142 /* Synchronizes I/O mem access to base. */
144 struct completion cmd_complete;
145 u32 (*get_clk_reg_val)(struct device *dev,
147 unsigned long parent_clk_frequency;
149 /* Transaction state. */
150 enum aspeed_i2c_master_state master_state;
151 struct i2c_msg *msgs;
157 /* Protected only by i2c_lock_bus */
158 int master_xfer_result;
159 #if IS_ENABLED(CONFIG_I2C_SLAVE)
160 struct i2c_client *slave;
161 enum aspeed_i2c_slave_state slave_state;
162 #endif /* CONFIG_I2C_SLAVE */
165 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus);
167 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus)
169 unsigned long time_left, flags;
173 spin_lock_irqsave(&bus->lock, flags);
174 command = readl(bus->base + ASPEED_I2C_CMD_REG);
176 if (command & ASPEED_I2CD_SDA_LINE_STS) {
177 /* Bus is idle: no recovery needed. */
178 if (command & ASPEED_I2CD_SCL_LINE_STS)
180 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n",
183 reinit_completion(&bus->cmd_complete);
184 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
185 spin_unlock_irqrestore(&bus->lock, flags);
187 time_left = wait_for_completion_timeout(
188 &bus->cmd_complete, bus->adap.timeout);
190 spin_lock_irqsave(&bus->lock, flags);
193 else if (bus->cmd_err)
195 /* Recovery failed. */
196 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
197 ASPEED_I2CD_SCL_LINE_STS))
201 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n",
204 reinit_completion(&bus->cmd_complete);
205 /* Writes 1 to 8 SCL clock cycles until SDA is released. */
206 writel(ASPEED_I2CD_BUS_RECOVER_CMD,
207 bus->base + ASPEED_I2C_CMD_REG);
208 spin_unlock_irqrestore(&bus->lock, flags);
210 time_left = wait_for_completion_timeout(
211 &bus->cmd_complete, bus->adap.timeout);
213 spin_lock_irqsave(&bus->lock, flags);
216 else if (bus->cmd_err)
218 /* Recovery failed. */
219 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) &
220 ASPEED_I2CD_SDA_LINE_STS))
225 spin_unlock_irqrestore(&bus->lock, flags);
230 spin_unlock_irqrestore(&bus->lock, flags);
232 return aspeed_i2c_reset(bus);
235 #if IS_ENABLED(CONFIG_I2C_SLAVE)
236 static u32 aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
238 u32 command, irq_handled = 0;
239 struct i2c_client *slave = bus->slave;
245 command = readl(bus->base + ASPEED_I2C_CMD_REG);
247 /* Slave was requested, restart state machine. */
248 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) {
249 irq_handled |= ASPEED_I2CD_INTR_SLAVE_MATCH;
250 bus->slave_state = ASPEED_I2C_SLAVE_START;
253 /* Slave is not currently active, irq was for someone else. */
254 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP)
257 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n",
258 irq_status, command);
260 /* Slave was sent something. */
261 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) {
262 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
263 /* Handle address frame. */
264 if (bus->slave_state == ASPEED_I2C_SLAVE_START) {
267 ASPEED_I2C_SLAVE_READ_REQUESTED;
270 ASPEED_I2C_SLAVE_WRITE_REQUESTED;
272 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
275 /* Slave was asked to stop. */
276 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) {
277 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
278 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
280 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) {
281 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
282 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
284 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
285 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
287 switch (bus->slave_state) {
288 case ASPEED_I2C_SLAVE_READ_REQUESTED:
289 if (irq_status & ASPEED_I2CD_INTR_TX_ACK)
290 dev_err(bus->dev, "Unexpected ACK on read request.\n");
291 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED;
292 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
293 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
294 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
296 case ASPEED_I2C_SLAVE_READ_PROCESSED:
297 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK))
299 "Expected ACK after processed read.\n");
300 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
301 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG);
302 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG);
304 case ASPEED_I2C_SLAVE_WRITE_REQUESTED:
305 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED;
306 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
308 case ASPEED_I2C_SLAVE_WRITE_RECEIVED:
309 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value);
311 case ASPEED_I2C_SLAVE_STOP:
312 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
315 dev_err(bus->dev, "unhandled slave_state: %d\n",
322 #endif /* CONFIG_I2C_SLAVE */
324 /* precondition: bus.lock has been acquired. */
325 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus)
327 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD;
328 struct i2c_msg *msg = &bus->msgs[bus->msgs_index];
329 u8 slave_addr = i2c_8bit_addr_from_msg(msg);
331 bus->master_state = ASPEED_I2C_MASTER_START;
334 if (msg->flags & I2C_M_RD) {
335 command |= ASPEED_I2CD_M_RX_CMD;
336 /* Need to let the hardware know to NACK after RX. */
337 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
338 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
341 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG);
342 writel(command, bus->base + ASPEED_I2C_CMD_REG);
345 /* precondition: bus.lock has been acquired. */
346 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus)
348 bus->master_state = ASPEED_I2C_MASTER_STOP;
349 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG);
352 /* precondition: bus.lock has been acquired. */
353 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus)
355 if (bus->msgs_index + 1 < bus->msgs_count) {
357 aspeed_i2c_do_start(bus);
359 aspeed_i2c_do_stop(bus);
363 static int aspeed_i2c_is_irq_error(u32 irq_status)
365 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS)
367 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT |
368 ASPEED_I2CD_INTR_SCL_TIMEOUT))
370 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL))
376 static u32 aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus, u32 irq_status)
378 u32 irq_handled = 0, command = 0;
383 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) {
384 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
385 irq_handled |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE;
388 /* Master is not currently active, irq was for someone else. */
389 if (bus->master_state == ASPEED_I2C_MASTER_INACTIVE)
390 goto out_no_complete;
394 * We encountered an interrupt that reports an error: the hardware
395 * should clear the command queue effectively taking us back to the
398 ret = aspeed_i2c_is_irq_error(irq_status);
400 dev_dbg(bus->dev, "received error interrupt: 0x%08x\n",
403 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
404 irq_handled |= (irq_status & ASPEED_I2CD_INTR_MASTER_ERRORS);
408 /* We are in an invalid state; reset bus to a known state. */
410 dev_err(bus->dev, "bus in unknown state. irq_status: 0x%x\n",
413 if (bus->master_state != ASPEED_I2C_MASTER_STOP &&
414 bus->master_state != ASPEED_I2C_MASTER_INACTIVE)
415 aspeed_i2c_do_stop(bus);
416 goto out_no_complete;
418 msg = &bus->msgs[bus->msgs_index];
421 * START is a special case because we still have to handle a subsequent
422 * TX or RX immediately after we handle it, so we handle it here and
423 * then update the state and handle the new state below.
425 if (bus->master_state == ASPEED_I2C_MASTER_START) {
426 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
427 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_NAK))) {
428 bus->cmd_err = -ENXIO;
429 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
432 pr_devel("no slave present at %02x\n", msg->addr);
433 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
434 bus->cmd_err = -ENXIO;
435 aspeed_i2c_do_stop(bus);
436 goto out_no_complete;
438 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
439 if (msg->len == 0) { /* SMBUS_QUICK */
440 aspeed_i2c_do_stop(bus);
441 goto out_no_complete;
443 if (msg->flags & I2C_M_RD)
444 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST;
446 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST;
449 switch (bus->master_state) {
450 case ASPEED_I2C_MASTER_TX:
451 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) {
452 dev_dbg(bus->dev, "slave NACKed TX\n");
453 irq_handled |= ASPEED_I2CD_INTR_TX_NAK;
455 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) {
456 dev_err(bus->dev, "slave failed to ACK TX\n");
459 irq_handled |= ASPEED_I2CD_INTR_TX_ACK;
461 case ASPEED_I2C_MASTER_TX_FIRST:
462 if (bus->buf_index < msg->len) {
463 bus->master_state = ASPEED_I2C_MASTER_TX;
464 writel(msg->buf[bus->buf_index++],
465 bus->base + ASPEED_I2C_BYTE_BUF_REG);
466 writel(ASPEED_I2CD_M_TX_CMD,
467 bus->base + ASPEED_I2C_CMD_REG);
469 aspeed_i2c_next_msg_or_stop(bus);
471 goto out_no_complete;
472 case ASPEED_I2C_MASTER_RX_FIRST:
473 /* RX may not have completed yet (only address cycle) */
474 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE))
475 goto out_no_complete;
477 case ASPEED_I2C_MASTER_RX:
478 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) {
479 dev_err(bus->dev, "master failed to RX\n");
482 irq_handled |= ASPEED_I2CD_INTR_RX_DONE;
484 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8;
485 msg->buf[bus->buf_index++] = recv_byte;
487 if (msg->flags & I2C_M_RECV_LEN) {
488 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) {
489 bus->cmd_err = -EPROTO;
490 aspeed_i2c_do_stop(bus);
491 goto out_no_complete;
493 msg->len = recv_byte +
494 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1);
495 msg->flags &= ~I2C_M_RECV_LEN;
498 if (bus->buf_index < msg->len) {
499 bus->master_state = ASPEED_I2C_MASTER_RX;
500 command = ASPEED_I2CD_M_RX_CMD;
501 if (bus->buf_index + 1 == msg->len)
502 command |= ASPEED_I2CD_M_S_RX_CMD_LAST;
503 writel(command, bus->base + ASPEED_I2C_CMD_REG);
505 aspeed_i2c_next_msg_or_stop(bus);
507 goto out_no_complete;
508 case ASPEED_I2C_MASTER_STOP:
509 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) {
511 "master failed to STOP. irq_status:0x%x\n",
514 /* Do not STOP as we have already tried. */
516 irq_handled |= ASPEED_I2CD_INTR_NORMAL_STOP;
519 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
521 case ASPEED_I2C_MASTER_INACTIVE:
523 "master received interrupt 0x%08x, but is inactive\n",
526 /* Do not STOP as we should be inactive. */
529 WARN(1, "unknown master state\n");
530 bus->master_state = ASPEED_I2C_MASTER_INACTIVE;
531 bus->cmd_err = -EINVAL;
536 aspeed_i2c_do_stop(bus);
537 goto out_no_complete;
541 bus->master_xfer_result = bus->cmd_err;
543 bus->master_xfer_result = bus->msgs_index + 1;
544 complete(&bus->cmd_complete);
549 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id)
551 struct aspeed_i2c_bus *bus = dev_id;
552 u32 irq_received, irq_remaining, irq_handled;
554 spin_lock(&bus->lock);
555 irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
556 /* Ack all interrupts except for Rx done */
557 writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE,
558 bus->base + ASPEED_I2C_INTR_STS_REG);
559 irq_remaining = irq_received;
561 #if IS_ENABLED(CONFIG_I2C_SLAVE)
563 * In most cases, interrupt bits will be set one by one, although
564 * multiple interrupt bits could be set at the same time. It's also
565 * possible that master interrupt bits could be set along with slave
566 * interrupt bits. Each case needs to be handled using corresponding
567 * handlers depending on the current state.
569 if (bus->master_state != ASPEED_I2C_MASTER_INACTIVE) {
570 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
571 irq_remaining &= ~irq_handled;
573 irq_handled |= aspeed_i2c_slave_irq(bus, irq_remaining);
575 irq_handled = aspeed_i2c_slave_irq(bus, irq_remaining);
576 irq_remaining &= ~irq_handled;
578 irq_handled |= aspeed_i2c_master_irq(bus,
582 irq_handled = aspeed_i2c_master_irq(bus, irq_remaining);
583 #endif /* CONFIG_I2C_SLAVE */
585 irq_remaining &= ~irq_handled;
588 "irq handled != irq. expected 0x%08x, but was 0x%08x\n",
589 irq_received, irq_handled);
592 if (irq_received & ASPEED_I2CD_INTR_RX_DONE)
593 writel(ASPEED_I2CD_INTR_RX_DONE,
594 bus->base + ASPEED_I2C_INTR_STS_REG);
595 spin_unlock(&bus->lock);
596 return irq_remaining ? IRQ_NONE : IRQ_HANDLED;
599 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap,
600 struct i2c_msg *msgs, int num)
602 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap);
603 unsigned long time_left, flags;
606 spin_lock_irqsave(&bus->lock, flags);
609 /* If bus is busy, attempt recovery. We assume a single master
612 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) {
613 spin_unlock_irqrestore(&bus->lock, flags);
614 ret = aspeed_i2c_recover_bus(bus);
617 spin_lock_irqsave(&bus->lock, flags);
623 bus->msgs_count = num;
625 reinit_completion(&bus->cmd_complete);
626 aspeed_i2c_do_start(bus);
627 spin_unlock_irqrestore(&bus->lock, flags);
629 time_left = wait_for_completion_timeout(&bus->cmd_complete,
635 return bus->master_xfer_result;
638 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap)
640 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
643 #if IS_ENABLED(CONFIG_I2C_SLAVE)
644 /* precondition: bus.lock has been acquired. */
645 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr)
647 u32 addr_reg_val, func_ctrl_reg_val;
649 /* Set slave addr. */
650 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG);
651 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK;
652 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK;
653 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG);
655 /* Turn on slave mode. */
656 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
657 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN;
658 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
661 static int aspeed_i2c_reg_slave(struct i2c_client *client)
663 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
666 spin_lock_irqsave(&bus->lock, flags);
668 spin_unlock_irqrestore(&bus->lock, flags);
672 __aspeed_i2c_reg_slave(bus, client->addr);
675 bus->slave_state = ASPEED_I2C_SLAVE_STOP;
676 spin_unlock_irqrestore(&bus->lock, flags);
681 static int aspeed_i2c_unreg_slave(struct i2c_client *client)
683 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter);
684 u32 func_ctrl_reg_val;
687 spin_lock_irqsave(&bus->lock, flags);
689 spin_unlock_irqrestore(&bus->lock, flags);
693 /* Turn off slave mode. */
694 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG);
695 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN;
696 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG);
699 spin_unlock_irqrestore(&bus->lock, flags);
703 #endif /* CONFIG_I2C_SLAVE */
705 static const struct i2c_algorithm aspeed_i2c_algo = {
706 .master_xfer = aspeed_i2c_master_xfer,
707 .functionality = aspeed_i2c_functionality,
708 #if IS_ENABLED(CONFIG_I2C_SLAVE)
709 .reg_slave = aspeed_i2c_reg_slave,
710 .unreg_slave = aspeed_i2c_unreg_slave,
711 #endif /* CONFIG_I2C_SLAVE */
714 static u32 aspeed_i2c_get_clk_reg_val(struct device *dev,
715 u32 clk_high_low_mask,
718 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
721 * SCL_high and SCL_low represent a value 1 greater than what is stored
722 * since a zero divider is meaningless. Thus, the max value each can
723 * store is every bit set + 1. Since SCL_high and SCL_low are added
724 * together (see below), the max value of both is the max value of one
727 clk_high_low_max = (clk_high_low_mask + 1) * 2;
730 * The actual clock frequency of SCL is:
731 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low))
732 * = APB_freq / divisor
733 * where base_freq is a programmable clock divider; its value is
734 * base_freq = 1 << base_clk_divisor
735 * SCL_high is the number of base_freq clock cycles that SCL stays high
736 * and SCL_low is the number of base_freq clock cycles that SCL stays
737 * low for a period of SCL.
738 * The actual register has a minimum SCL_high and SCL_low minimum of 1;
739 * thus, they start counting at zero. So
740 * SCL_high = clk_high + 1
741 * SCL_low = clk_low + 1
743 * SCL_freq = APB_freq /
744 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
745 * The documentation recommends clk_high >= clk_high_max / 2 and
746 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
747 * gives us the following solution:
749 base_clk_divisor = divisor > clk_high_low_max ?
750 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
752 if (base_clk_divisor > ASPEED_I2CD_TIME_BASE_DIVISOR_MASK) {
753 base_clk_divisor = ASPEED_I2CD_TIME_BASE_DIVISOR_MASK;
754 clk_low = clk_high_low_mask;
755 clk_high = clk_high_low_mask;
757 "clamping clock divider: divider requested, %u, is greater than largest possible divider, %u.\n",
758 divisor, (1 << base_clk_divisor) * clk_high_low_max);
760 tmp = (divisor + (1 << base_clk_divisor) - 1)
763 clk_high = tmp - clk_low;
773 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
774 & ASPEED_I2CD_TIME_SCL_HIGH_MASK)
775 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
776 & ASPEED_I2CD_TIME_SCL_LOW_MASK)
778 & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
781 static u32 aspeed_i2c_24xx_get_clk_reg_val(struct device *dev, u32 divisor)
784 * clk_high and clk_low are each 3 bits wide, so each can hold a max
785 * value of 8 giving a clk_high_low_max of 16.
787 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(2, 0), divisor);
790 static u32 aspeed_i2c_25xx_get_clk_reg_val(struct device *dev, u32 divisor)
793 * clk_high and clk_low are each 4 bits wide, so each can hold a max
794 * value of 16 giving a clk_high_low_max of 32.
796 return aspeed_i2c_get_clk_reg_val(dev, GENMASK(3, 0), divisor);
799 /* precondition: bus.lock has been acquired. */
800 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
802 u32 divisor, clk_reg_val;
804 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
805 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);
806 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |
807 ASPEED_I2CD_TIME_THDSTA_MASK |
808 ASPEED_I2CD_TIME_TACST_MASK);
809 clk_reg_val |= bus->get_clk_reg_val(bus->dev, divisor);
810 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
811 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
816 /* precondition: bus.lock has been acquired. */
817 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus,
818 struct platform_device *pdev)
820 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN;
823 /* Disable everything. */
824 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
826 ret = aspeed_i2c_init_clk(bus);
830 if (!of_property_read_bool(pdev->dev.of_node, "multi-master"))
831 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS;
833 /* Enable Master Mode */
834 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg,
835 bus->base + ASPEED_I2C_FUN_CTRL_REG);
837 #if IS_ENABLED(CONFIG_I2C_SLAVE)
838 /* If slave has already been registered, re-enable it. */
840 __aspeed_i2c_reg_slave(bus, bus->slave->addr);
841 #endif /* CONFIG_I2C_SLAVE */
843 /* Set interrupt generation of I2C controller */
844 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG);
849 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
851 struct platform_device *pdev = to_platform_device(bus->dev);
855 spin_lock_irqsave(&bus->lock, flags);
857 /* Disable and ack all interrupts. */
858 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
859 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
861 ret = aspeed_i2c_init(bus, pdev);
863 spin_unlock_irqrestore(&bus->lock, flags);
868 static const struct of_device_id aspeed_i2c_bus_of_table[] = {
870 .compatible = "aspeed,ast2400-i2c-bus",
871 .data = aspeed_i2c_24xx_get_clk_reg_val,
874 .compatible = "aspeed,ast2500-i2c-bus",
875 .data = aspeed_i2c_25xx_get_clk_reg_val,
879 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
881 static int aspeed_i2c_probe_bus(struct platform_device *pdev)
883 const struct of_device_id *match;
884 struct aspeed_i2c_bus *bus;
885 struct clk *parent_clk;
886 struct resource *res;
889 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
893 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
894 bus->base = devm_ioremap_resource(&pdev->dev, res);
895 if (IS_ERR(bus->base))
896 return PTR_ERR(bus->base);
898 parent_clk = devm_clk_get(&pdev->dev, NULL);
899 if (IS_ERR(parent_clk))
900 return PTR_ERR(parent_clk);
901 bus->parent_clk_frequency = clk_get_rate(parent_clk);
902 /* We just need the clock rate, we don't actually use the clk object. */
903 devm_clk_put(&pdev->dev, parent_clk);
905 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
906 if (IS_ERR(bus->rst)) {
908 "missing or invalid reset controller device tree entry\n");
909 return PTR_ERR(bus->rst);
911 reset_control_deassert(bus->rst);
913 ret = of_property_read_u32(pdev->dev.of_node,
914 "bus-frequency", &bus->bus_frequency);
917 "Could not read bus-frequency property\n");
918 bus->bus_frequency = 100000;
921 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
923 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
925 bus->get_clk_reg_val = (u32 (*)(struct device *, u32))
928 /* Initialize the I2C adapter */
929 spin_lock_init(&bus->lock);
930 init_completion(&bus->cmd_complete);
931 bus->adap.owner = THIS_MODULE;
932 bus->adap.retries = 0;
933 bus->adap.timeout = 5 * HZ;
934 bus->adap.algo = &aspeed_i2c_algo;
935 bus->adap.dev.parent = &pdev->dev;
936 bus->adap.dev.of_node = pdev->dev.of_node;
937 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name));
938 i2c_set_adapdata(&bus->adap, bus);
940 bus->dev = &pdev->dev;
942 /* Clean up any left over interrupt state. */
943 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
944 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG);
946 * bus.lock does not need to be held because the interrupt handler has
947 * not been enabled yet.
949 ret = aspeed_i2c_init(bus, pdev);
953 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
954 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq,
955 0, dev_name(&pdev->dev), bus);
959 ret = i2c_add_adapter(&bus->adap);
963 platform_set_drvdata(pdev, bus);
965 dev_info(bus->dev, "i2c bus %d registered, irq %d\n",
971 static int aspeed_i2c_remove_bus(struct platform_device *pdev)
973 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev);
976 spin_lock_irqsave(&bus->lock, flags);
978 /* Disable everything. */
979 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG);
980 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG);
982 spin_unlock_irqrestore(&bus->lock, flags);
984 reset_control_assert(bus->rst);
986 i2c_del_adapter(&bus->adap);
991 static struct platform_driver aspeed_i2c_bus_driver = {
992 .probe = aspeed_i2c_probe_bus,
993 .remove = aspeed_i2c_remove_bus,
995 .name = "aspeed-i2c-bus",
996 .of_match_table = aspeed_i2c_bus_of_table,
999 module_platform_driver(aspeed_i2c_bus_driver);
1001 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>");
1002 MODULE_DESCRIPTION("Aspeed I2C Bus Driver");
1003 MODULE_LICENSE("GPL v2");