2 * Copyright (C) 2014 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/version.h>
30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
31 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per
32 * data register whereas STB SoCs use 4 byte per data register transfer,
33 * account for this difference in total count per transaction and mask to
36 #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0))
37 #define BSC_CNT_REG1_SHIFT 0
39 /* BSC CTL register field definitions */
40 #define BSC_CTL_REG_DTF_MASK 0x00000003
41 #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030
42 #define BSC_CTL_REG_SCL_SEL_SHIFT 4
43 #define BSC_CTL_REG_INT_EN_MASK 0x00000040
44 #define BSC_CTL_REG_INT_EN_SHIFT 6
45 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080
47 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */
48 #define BSC_IIC_EN_RESTART_MASK 0x00000040
49 #define BSC_IIC_EN_NOSTART_MASK 0x00000020
50 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010
51 #define BSC_IIC_EN_NOACK_MASK 0x00000004
52 #define BSC_IIC_EN_INTRP_MASK 0x00000002
53 #define BSC_IIC_EN_ENABLE_MASK 0x00000001
55 /* BSC_CTLHI control register field definitions */
56 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080
57 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040
58 #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002
59 #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001
61 #define I2C_TIMEOUT 100 /* msecs */
63 /* Condition mask used for non combined transfer */
64 #define COND_RESTART BSC_IIC_EN_RESTART_MASK
65 #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK
66 #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK
67 #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP)
69 /* BSC data transfer direction */
70 #define DTF_WR_MASK 0x00000000
71 #define DTF_RD_MASK 0x00000001
72 /* BSC data transfer direction combined format */
73 #define DTF_RD_WR_MASK 0x00000002
74 #define DTF_WR_RD_MASK 0x00000003
76 #define INT_ENABLE true
77 #define INT_DISABLE false
79 /* BSC block register map structure to cache fields to be written */
81 u32 chip_address; /* slave address */
82 u32 data_in[N_DATA_REGS]; /* tx data buffer*/
83 u32 cnt_reg; /* rx/tx data length */
84 u32 ctl_reg; /* control register */
85 u32 iic_enable; /* xfer enable and status */
86 u32 data_out[N_DATA_REGS]; /* rx data buffer */
87 u32 ctlhi_reg; /* more control fields */
88 u32 scl_param; /* reserved */
91 struct bsc_clk_param {
104 static char const *cmd_string[] = {
107 [CMD_WR_NOACK] = "WR NOACK",
108 [CMD_RD_NOACK] = "RD NOACK",
122 static const struct bsc_clk_param bsc_clk[] = {
125 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
130 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
135 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
140 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
145 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,
146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
150 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,
151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
155 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,
156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
160 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,
161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
165 struct brcmstb_i2c_dev {
166 struct device *device;
169 struct bsc_regs *bsc_regmap;
170 struct i2c_adapter adapter;
171 struct completion done;
176 /* register accessors for both be and le cpu arch */
177 #ifdef CONFIG_CPU_BIG_ENDIAN
178 #define __bsc_readl(_reg) ioread32be(_reg)
179 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg)
181 #define __bsc_readl(_reg) ioread32(_reg)
182 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg)
185 #define bsc_readl(_dev, _reg) \
186 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg))
188 #define bsc_writel(_dev, _val, _reg) \
189 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg))
191 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev)
193 return (N_DATA_REGS * dev->data_regsz);
196 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev)
198 return dev->data_regsz;
201 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev,
206 /* Enable BSC CTL interrupt line */
207 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;
209 /* Disable BSC CTL interrupt line */
210 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;
213 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
216 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)
218 struct brcmstb_i2c_dev *dev = devid;
219 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg);
220 u32 status_iic_intrp = bsc_readl(dev, iic_enable);
222 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n",
223 status_bsc_ctl, status_iic_intrp);
225 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))
228 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
229 complete(&dev->done);
231 dev_dbg(dev->device, "isr handled");
235 /* Wait for device to be ready */
236 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)
238 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
240 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {
241 if (time_after(jiffies, timeout))
248 /* i2c xfer completion function, handles both irq and polling mode */
249 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev)
252 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);
255 if (!wait_for_completion_timeout(&dev->done, timeout))
258 /* we are in polling mode */
260 unsigned long time_left = jiffies + timeout;
263 bsc_intrp = bsc_readl(dev, iic_enable) &
264 BSC_IIC_EN_INTRP_MASK;
265 if (time_after(jiffies, time_left)) {
270 } while (!bsc_intrp);
273 if (dev->irq < 0 || ret == -ETIMEDOUT)
274 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
279 /* Set xfer START/STOP conditions for subsequent transfer */
280 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,
283 u32 regval = dev->bsc_regmap->iic_enable;
285 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;
288 /* Send I2C request check completion */
289 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,
290 enum bsc_xfer_cmd cmd)
293 struct bsc_regs *pi2creg = dev->bsc_regmap;
295 /* Make sure the hardware is ready */
296 rc = brcmstb_i2c_wait_if_busy(dev);
300 /* only if we are in interrupt mode */
302 reinit_completion(&dev->done);
304 /* enable BSC CTL interrupt line */
305 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE);
307 /* initiate transfer by setting iic_enable */
308 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;
309 bsc_writel(dev, pi2creg->iic_enable, iic_enable);
311 /* Wait for transaction to finish or timeout */
312 rc = brcmstb_i2c_wait_for_completion(dev);
314 dev_dbg(dev->device, "intr timeout for cmd %s\n",
319 if ((CMD_RD || CMD_WR) &&
320 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {
322 dev_dbg(dev->device, "controller received NOACK intr for %s\n",
327 bsc_writel(dev, 0, cnt_reg);
328 bsc_writel(dev, 0, iic_enable);
333 /* Actual data transfer through the BSC master */
334 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,
335 u8 *buf, unsigned int len,
336 struct i2c_msg *pmsg)
338 int cnt, byte, i, rc;
339 enum bsc_xfer_cmd cmd;
341 struct bsc_regs *pi2creg = dev->bsc_regmap;
342 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK;
343 int data_regsz = brcmstb_i2c_get_data_regsz(dev);
345 /* see if the transaction needs to check NACK conditions */
347 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK
349 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;
351 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;
352 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;
354 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);
356 /* set data transfer direction */
357 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;
358 if (cmd == CMD_WR || cmd == CMD_WR_NOACK)
359 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;
361 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;
363 /* set the read/write length */
364 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) &
365 (len << BSC_CNT_REG1_SHIFT), cnt_reg);
367 /* Write data into data_in register */
369 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) {
370 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
373 for (byte = 0; byte < data_regsz; byte++) {
374 word >>= BITS_PER_BYTE;
375 if ((cnt + byte) < len)
376 word |= buf[cnt + byte] <<
377 (BITS_PER_BYTE * (data_regsz - 1));
379 bsc_writel(dev, word, data_in[i]);
383 /* Initiate xfer, the function will return on completion */
384 rc = brcmstb_send_i2c_cmd(dev, cmd);
387 dev_dbg(dev->device, "%s failure", cmd_string[cmd]);
391 /* Read data from data_out register */
392 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) {
393 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) {
394 u32 data = bsc_readl(dev, data_out[i]);
396 for (byte = 0; byte < data_regsz &&
397 (byte + cnt) < len; byte++) {
398 buf[cnt + byte] = data & 0xff;
399 data >>= BITS_PER_BYTE;
407 /* Write a single byte of data to the i2c bus */
408 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,
409 u8 *buf, unsigned int nak_expected)
411 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;
413 bsc_writel(dev, 1, cnt_reg);
414 bsc_writel(dev, *buf, data_in);
416 return brcmstb_send_i2c_cmd(dev, cmd);
419 /* Send i2c address */
420 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,
425 if (msg->flags & I2C_M_TEN) {
426 /* First byte is 11110XX0 where XX is upper 2 bits */
427 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
428 bsc_writel(dev, addr, chip_address);
430 /* Second byte is the remaining 8 bits */
431 addr = msg->addr & 0xFF;
432 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
435 if (msg->flags & I2C_M_RD) {
436 /* For read, send restart without stop condition */
437 brcmstb_set_i2c_start_stop(dev, COND_RESTART
439 /* Then re-send the first byte with the read bit set */
440 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
441 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)
446 addr = i2c_8bit_addr_from_msg(msg);
448 bsc_writel(dev, addr, chip_address);
454 /* Master transfer function */
455 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,
456 struct i2c_msg msgs[], int num)
458 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);
459 struct i2c_msg *pmsg;
465 int xfersz = brcmstb_i2c_get_xfersz(dev);
466 u32 cond, cond_per_msg;
468 /* Loop through all messages */
469 for (i = 0; i < num; i++) {
475 "msg# %d/%d flg %x buf %x len %d\n", i,
476 num - 1, pmsg->flags,
477 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len);
479 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))
480 cond = ~COND_START_STOP;
482 cond = COND_RESTART | COND_NOSTOP;
484 brcmstb_set_i2c_start_stop(dev, cond);
486 /* Send slave address */
487 if (!(pmsg->flags & I2C_M_NOSTART)) {
488 rc = brcmstb_i2c_do_addr(dev, pmsg);
491 "NACK for addr %2.2x msg#%d rc = %d\n",
499 /* Perform data transfer */
501 bytes_to_xfer = min(len, xfersz);
505 cond_per_msg = cond_per_msg &
506 ~(COND_RESTART | COND_NOSTOP);
510 cond_per_msg = (cond_per_msg & ~COND_RESTART) |
514 brcmstb_set_i2c_start_stop(dev, cond_per_msg);
516 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,
517 bytes_to_xfer, pmsg);
521 len -= bytes_to_xfer;
522 tmp_buf += bytes_to_xfer;
524 cond_per_msg = COND_NOSTART | COND_NOSTOP;
534 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)
536 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR
537 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;
540 static const struct i2c_algorithm brcmstb_i2c_algo = {
541 .master_xfer = brcmstb_i2c_xfer,
542 .functionality = brcmstb_i2c_functionality,
545 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)
547 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk);
548 u32 clk_freq_hz = dev->clk_freq_hz;
550 for (i = 0; i < num_speeds; i++) {
551 if (bsc_clk[i].hz == clk_freq_hz) {
552 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK
553 | BSC_CTL_REG_DIV_CLK_MASK);
554 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |
555 bsc_clk[i].div_mask);
556 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);
561 /* in case we did not get find a valid speed */
562 if (i == num_speeds) {
563 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>
564 BSC_CTL_REG_SCL_SEL_SHIFT;
565 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n",
570 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)
572 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32))
573 /* set 4 byte data in/out xfers */
574 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;
576 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK;
578 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);
580 brcmstb_i2c_set_bus_speed(dev);
583 static int brcmstb_i2c_probe(struct platform_device *pdev)
586 struct brcmstb_i2c_dev *dev;
587 struct i2c_adapter *adap;
588 struct resource *iomem;
589 const char *int_name;
591 /* Allocate memory for private data structure */
592 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
596 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL);
597 if (!dev->bsc_regmap)
600 platform_set_drvdata(pdev, dev);
601 dev->device = &pdev->dev;
602 init_completion(&dev->done);
604 /* Map hardware registers */
605 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
606 dev->base = devm_ioremap_resource(dev->device, iomem);
607 if (IS_ERR(dev->base)) {
612 rc = of_property_read_string(dev->device->of_node, "interrupt-names",
617 /* Get the interrupt number */
618 dev->irq = platform_get_irq(pdev, 0);
620 /* disable the bsc interrupt line */
621 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE);
623 /* register the ISR handler */
624 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,
626 int_name ? int_name : pdev->name,
630 dev_dbg(dev->device, "falling back to polling mode");
634 if (of_property_read_u32(dev->device->of_node,
635 "clock-frequency", &dev->clk_freq_hz)) {
636 dev_warn(dev->device, "setting clock-frequency@%dHz\n",
638 dev->clk_freq_hz = bsc_clk[0].hz;
641 /* set the data in/out register size for compatible SoCs */
642 if (of_device_is_compatible(dev->device->of_node,
643 "brcmstb,brcmper-i2c"))
644 dev->data_regsz = sizeof(u8);
646 dev->data_regsz = sizeof(u32);
648 brcmstb_i2c_set_bsc_reg_defaults(dev);
650 /* Add the i2c adapter */
651 adap = &dev->adapter;
652 i2c_set_adapdata(adap, dev);
653 adap->owner = THIS_MODULE;
654 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name));
656 strlcat(adap->name, int_name, sizeof(adap->name));
657 adap->algo = &brcmstb_i2c_algo;
658 adap->dev.parent = &pdev->dev;
659 adap->dev.of_node = pdev->dev.of_node;
660 rc = i2c_add_adapter(adap);
664 dev_info(dev->device, "%s@%dhz registered in %s mode\n",
665 int_name ? int_name : " ", dev->clk_freq_hz,
666 (dev->irq >= 0) ? "interrupt" : "polling");
674 static int brcmstb_i2c_remove(struct platform_device *pdev)
676 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);
678 i2c_del_adapter(&dev->adapter);
682 #ifdef CONFIG_PM_SLEEP
683 static int brcmstb_i2c_suspend(struct device *dev)
685 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
687 i2c_mark_adapter_suspended(&i2c_dev->adapter);
691 static int brcmstb_i2c_resume(struct device *dev)
693 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);
695 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev);
696 i2c_mark_adapter_resumed(&i2c_dev->adapter);
702 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,
705 static const struct of_device_id brcmstb_i2c_of_match[] = {
706 {.compatible = "brcm,brcmstb-i2c"},
707 {.compatible = "brcm,brcmper-i2c"},
710 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);
712 static struct platform_driver brcmstb_i2c_driver = {
714 .name = "brcmstb-i2c",
715 .of_match_table = brcmstb_i2c_of_match,
716 .pm = &brcmstb_i2c_pm,
718 .probe = brcmstb_i2c_probe,
719 .remove = brcmstb_i2c_remove,
721 module_platform_driver(brcmstb_i2c_driver);
723 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>");
724 MODULE_DESCRIPTION("Broadcom Settop I2C Driver");
725 MODULE_LICENSE("GPL v2");