drivers/i2c/busses/i2c-designware-master.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/errno.h>
  27 #include <linux/export.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/i2c.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/module.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/reset.h>
  35
  36 #include "i2c-designware-core.h"
  37
  38 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  39 {
  40         /* Configure Tx/Rx FIFO threshold levels */
  41         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  42         dw_writel(dev, 0, DW_IC_RX_TL);
  43
  44         /* Configure the I2C master */
  45         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  46 }
  47
  48 /**
  49  * i2c_dw_init() - Initialize the designware I2C master hardware
  50  * @dev: device private data
  51  *
  52  * This functions configures and enables the I2C master.
  53  * This function is called during I2C init function, and in case of timeout at
  54  * run time.
  55  */
  56 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
  57 {
  58         u32 ic_clk = i2c_dw_clk_rate(dev);
  59         u32 hcnt, lcnt;
  60         u32 reg, comp_param1;
  61         u32 sda_falling_time, scl_falling_time;
  62         int ret;
  63
  64         ret = i2c_dw_acquire_lock(dev);
  65         if (ret)
  66                 return ret;
  67
  68         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  69
  70         /* Disable the adapter */
  71         __i2c_dw_disable(dev);
  72
  73         /* Set standard and fast speed deviders for high/low periods */
  74
  75         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
  76         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
  77
  78         /* Set SCL timing parameters for standard-mode */
  79         if (dev->ss_hcnt && dev->ss_lcnt) {
  80                 hcnt = dev->ss_hcnt;
  81                 lcnt = dev->ss_lcnt;
  82         } else {
  83                 hcnt = i2c_dw_scl_hcnt(ic_clk,
  84                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  85                                         sda_falling_time,
  86                                         0,      /* 0: DW default, 1: Ideal */
  87                                         0);     /* No offset */
  88                 lcnt = i2c_dw_scl_lcnt(ic_clk,
  89                                         4700,   /* tLOW = 4.7 us */
  90                                         scl_falling_time,
  91                                         0);     /* No offset */
  92         }
  93         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
  94         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
  95         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
  96
  97         /* Set SCL timing parameters for fast-mode or fast-mode plus */
  98         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
  99                 hcnt = dev->fp_hcnt;
 100                 lcnt = dev->fp_lcnt;
 101         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 102                 hcnt = dev->fs_hcnt;
 103                 lcnt = dev->fs_lcnt;
 104         } else {
 105                 hcnt = i2c_dw_scl_hcnt(ic_clk,
 106                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 107                                         sda_falling_time,
 108                                         0,      /* 0: DW default, 1: Ideal */
 109                                         0);     /* No offset */
 110                 lcnt = i2c_dw_scl_lcnt(ic_clk,
 111                                         1300,   /* tLOW = 1.3 us */
 112                                         scl_falling_time,
 113                                         0);     /* No offset */
 114         }
 115         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 116         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 117         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 118
 119         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 120                 DW_IC_CON_SPEED_HIGH) {
 121                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 122                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 123                         dev_err(dev->dev, "High Speed not supported!\n");
 124                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 125                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 126                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 127                         hcnt = dev->hs_hcnt;
 128                         lcnt = dev->hs_lcnt;
 129                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 130                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 131                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 132                                 hcnt, lcnt);
 133                 }
 134         }
 135
 136         /* Configure SDA Hold Time if required */
 137         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 138         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 139                 if (!dev->sda_hold_time) {
 140                         /* Keep previous hold time setting if no one set it */
 141                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 142                 }
 143                 /*
 144                  * Workaround for avoiding TX arbitration lost in case I2C
 145                  * slave pulls SDA down "too quickly" after falling egde of
 146                  * SCL by enabling non-zero SDA RX hold. Specification says it
 147                  * extends incoming SDA low to high transition while SCL is
 148                  * high but it apprears to help also above issue.
 149                  */
 150                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 151                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 152                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 153         } else if (dev->sda_hold_time) {
 154                 dev_warn(dev->dev,
 155                         "Hardware too old to adjust SDA hold time.\n");
 156         }
 157
 158         i2c_dw_configure_fifo_master(dev);
 159         i2c_dw_release_lock(dev);
 160
 161         return 0;
 162 }
 163
 164 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 165 {
 166         struct i2c_msg *msgs = dev->msgs;
 167         u32 ic_con, ic_tar = 0;
 168
 169         /* Disable the adapter */
 170         __i2c_dw_disable(dev);
 171
 172         /* If the slave address is ten bit address, enable 10BITADDR */
 173         ic_con = dw_readl(dev, DW_IC_CON);
 174         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 175                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 176                 /*
 177                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 178                  * mode has to be enabled via bit 12 of IC_TAR register.
 179                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 180                  * detected from registers.
 181                  */
 182                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 183         } else {
 184                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 185         }
 186
 187         dw_writel(dev, ic_con, DW_IC_CON);
 188
 189         /*
 190          * Set the slave (target) address and enable 10-bit addressing mode
 191          * if applicable.
 192          */
 193         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 194
 195         /* Enforce disabled interrupts (due to HW issues) */
 196         i2c_dw_disable_int(dev);
 197
 198         /* Enable the adapter */
 199         __i2c_dw_enable(dev);
 200
 201         /* Dummy read to avoid the register getting stuck on Bay Trail */
 202         dw_readl(dev, DW_IC_ENABLE_STATUS);
 203
 204         /* Clear and enable interrupts */
 205         dw_readl(dev, DW_IC_CLR_INTR);
 206         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 207 }
 208
 209 /*
 210  * Initiate (and continue) low level master read/write transaction.
 211  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 212  * messages into the tx buffer.  Even if the size of i2c_msg data is
 213  * longer than the size of the tx buffer, it handles everything.
 214  */
 215 static void
 216 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 217 {
 218         struct i2c_msg *msgs = dev->msgs;
 219         u32 intr_mask;
 220         int tx_limit, rx_limit;
 221         u32 addr = msgs[dev->msg_write_idx].addr;
 222         u32 buf_len = dev->tx_buf_len;
 223         u8 *buf = dev->tx_buf;
 224         bool need_restart = false;
 225
 226         intr_mask = DW_IC_INTR_MASTER_MASK;
 227
 228         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 229                 u32 flags = msgs[dev->msg_write_idx].flags;
 230
 231                 /*
 232                  * If target address has changed, we need to
 233                  * reprogram the target address in the I2C
 234                  * adapter when we are done with this transfer.
 235                  */
 236                 if (msgs[dev->msg_write_idx].addr != addr) {
 237                         dev_err(dev->dev,
 238                                 "%s: invalid target address\n", __func__);
 239                         dev->msg_err = -EINVAL;
 240                         break;
 241                 }
 242
 243                 if (msgs[dev->msg_write_idx].len == 0) {
 244                         dev_err(dev->dev,
 245                                 "%s: invalid message length\n", __func__);
 246                         dev->msg_err = -EINVAL;
 247                         break;
 248                 }
 249
 250                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 251                         /* new i2c_msg */
 252                         buf = msgs[dev->msg_write_idx].buf;
 253                         buf_len = msgs[dev->msg_write_idx].len;
 254
 255                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 256                          * IC_RESTART_EN are set, we must manually
 257                          * set restart bit between messages.
 258                          */
 259                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 260                                         (dev->msg_write_idx > 0))
 261                                 need_restart = true;
 262                 }
 263
 264                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 265                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 266
 267                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 268                         u32 cmd = 0;
 269
 270                         /*
 271                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 272                          * manually set the stop bit. However, it cannot be
 273                          * detected from the registers so we set it always
 274                          * when writing/reading the last byte.
 275                          */
 276
 277                         /*
 278                          * i2c-core always sets the buffer length of
 279                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 280                          * be adjusted when receiving the first byte.
 281                          * Thus we can't stop the transaction here.
 282                          */
 283                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 284                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 285                                 cmd |= BIT(9);
 286
 287                         if (need_restart) {
 288                                 cmd |= BIT(10);
 289                                 need_restart = false;
 290                         }
 291
 292                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 293
 294                                 /* Avoid rx buffer overrun */
 295                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 296                                         break;
 297
 298                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 299                                 rx_limit--;
 300                                 dev->rx_outstanding++;
 301                         } else
 302                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 303                         tx_limit--; buf_len--;
 304                 }
 305
 306                 dev->tx_buf = buf;
 307                 dev->tx_buf_len = buf_len;
 308
 309                 /*
 310                  * Because we don't know the buffer length in the
 311                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 312                  * the transaction here.
 313                  */
 314                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 315                         /* more bytes to be written */
 316                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 317                         break;
 318                 } else
 319                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 320         }
 321
 322         /*
 323          * If i2c_msg index search is completed, we don't need TX_EMPTY
 324          * interrupt any more.
 325          */
 326         if (dev->msg_write_idx == dev->msgs_num)
 327                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 328
 329         if (dev->msg_err)
 330                 intr_mask = 0;
 331
 332         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 333 }
 334
 335 static u8
 336 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 337 {
 338         struct i2c_msg *msgs = dev->msgs;
 339         u32 flags = msgs[dev->msg_read_idx].flags;
 340
 341         /*
 342          * Adjust the buffer length and mask the flag
 343          * after receiving the first byte.
 344          */
 345         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 346         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 347         msgs[dev->msg_read_idx].len = len;
 348         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 349
 350         return len;
 351 }
 352
 353 static void
 354 i2c_dw_read(struct dw_i2c_dev *dev)
 355 {
 356         struct i2c_msg *msgs = dev->msgs;
 357         int rx_valid;
 358
 359         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 360                 u32 len;
 361                 u8 *buf;
 362
 363                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 364                         continue;
 365
 366                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 367                         len = msgs[dev->msg_read_idx].len;
 368                         buf = msgs[dev->msg_read_idx].buf;
 369                 } else {
 370                         len = dev->rx_buf_len;
 371                         buf = dev->rx_buf;
 372                 }
 373
 374                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 375
 376                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 377                         u32 flags = msgs[dev->msg_read_idx].flags;
 378
 379                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 380                         /* Ensure length byte is a valid value */
 381                         if (flags & I2C_M_RECV_LEN &&
 382                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 383                                 len = i2c_dw_recv_len(dev, *buf);
 384                         }
 385                         buf++;
 386                         dev->rx_outstanding--;
 387                 }
 388
 389                 if (len > 0) {
 390                         dev->status |= STATUS_READ_IN_PROGRESS;
 391                         dev->rx_buf_len = len;
 392                         dev->rx_buf = buf;
 393                         return;
 394                 } else
 395                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 396         }
 397 }
 398
 399 /*
 400  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 401  */
 402 static int
 403 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 404 {
 405         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 406         int ret;
 407
 408         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 409
 410         pm_runtime_get_sync(dev->dev);
 411
 412         reinit_completion(&dev->cmd_complete);
 413         dev->msgs = msgs;
 414         dev->msgs_num = num;
 415         dev->cmd_err = 0;
 416         dev->msg_write_idx = 0;
 417         dev->msg_read_idx = 0;
 418         dev->msg_err = 0;
 419         dev->status = STATUS_IDLE;
 420         dev->abort_source = 0;
 421         dev->rx_outstanding = 0;
 422
 423         ret = i2c_dw_acquire_lock(dev);
 424         if (ret)
 425                 goto done_nolock;
 426
 427         ret = i2c_dw_wait_bus_not_busy(dev);
 428         if (ret < 0)
 429                 goto done;
 430
 431         /* Start the transfers */
 432         i2c_dw_xfer_init(dev);
 433
 434         /* Wait for tx to complete */
 435         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 436                 dev_err(dev->dev, "controller timed out\n");
 437                 /* i2c_dw_init implicitly disables the adapter */
 438                 i2c_recover_bus(&dev->adapter);
 439                 i2c_dw_init_master(dev);
 440                 ret = -ETIMEDOUT;
 441                 goto done;
 442         }
 443
 444         /*
 445          * We must disable the adapter before returning and signaling the end
 446          * of the current transfer. Otherwise the hardware might continue
 447          * generating interrupts which in turn causes a race condition with
 448          * the following transfer.  Needs some more investigation if the
 449          * additional interrupts are a hardware bug or this driver doesn't
 450          * handle them correctly yet.
 451          */
 452         __i2c_dw_disable_nowait(dev);
 453
 454         if (dev->msg_err) {
 455                 ret = dev->msg_err;
 456                 goto done;
 457         }
 458
 459         /* No error */
 460         if (likely(!dev->cmd_err && !dev->status)) {
 461                 ret = num;
 462                 goto done;
 463         }
 464
 465         /* We have an error */
 466         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 467                 ret = i2c_dw_handle_tx_abort(dev);
 468                 goto done;
 469         }
 470
 471         if (dev->status)
 472                 dev_err(dev->dev,
 473                         "transfer terminated early - interrupt latency too high?\n");
 474
 475         ret = -EIO;
 476
 477 done:
 478         i2c_dw_release_lock(dev);
 479
 480 done_nolock:
 481         pm_runtime_mark_last_busy(dev->dev);
 482         pm_runtime_put_autosuspend(dev->dev);
 483
 484         return ret;
 485 }
 486
 487 static const struct i2c_algorithm i2c_dw_algo = {
 488         .master_xfer = i2c_dw_xfer,
 489         .functionality = i2c_dw_func,
 490 };
 491
 492 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 493 {
 494         u32 stat;
 495
 496         /*
 497          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 498          * Ths unmasked raw version of interrupt status bits are available
 499          * in the IC_RAW_INTR_STAT register.
 500          *
 501          * That is,
 502          *   stat = dw_readl(IC_INTR_STAT);
 503          * equals to,
 504          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 505          *
 506          * The raw version might be useful for debugging purposes.
 507          */
 508         stat = dw_readl(dev, DW_IC_INTR_STAT);
 509
 510         /*
 511          * Do not use the IC_CLR_INTR register to clear interrupts, or
 512          * you'll miss some interrupts, triggered during the period from
 513          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 514          *
 515          * Instead, use the separately-prepared IC_CLR_* registers.
 516          */
 517         if (stat & DW_IC_INTR_RX_UNDER)
 518                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 519         if (stat & DW_IC_INTR_RX_OVER)
 520                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 521         if (stat & DW_IC_INTR_TX_OVER)
 522                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 523         if (stat & DW_IC_INTR_RD_REQ)
 524                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 525         if (stat & DW_IC_INTR_TX_ABRT) {
 526                 /*
 527                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 528                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 529                  */
 530                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 531                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 532         }
 533         if (stat & DW_IC_INTR_RX_DONE)
 534                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 535         if (stat & DW_IC_INTR_ACTIVITY)
 536                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 537         if (stat & DW_IC_INTR_STOP_DET)
 538                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 539         if (stat & DW_IC_INTR_START_DET)
 540                 dw_readl(dev, DW_IC_CLR_START_DET);
 541         if (stat & DW_IC_INTR_GEN_CALL)
 542                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 543
 544         return stat;
 545 }
 546
 547 /*
 548  * Interrupt service routine. This gets called whenever an I2C master interrupt
 549  * occurs.
 550  */
 551 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 552 {
 553         u32 stat;
 554
 555         stat = i2c_dw_read_clear_intrbits(dev);
 556         if (stat & DW_IC_INTR_TX_ABRT) {
 557                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 558                 dev->status = STATUS_IDLE;
 559
 560                 /*
 561                  * Anytime TX_ABRT is set, the contents of the tx/rx
 562                  * buffers are flushed. Make sure to skip them.
 563                  */
 564                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 565                 goto tx_aborted;
 566         }
 567
 568         if (stat & DW_IC_INTR_RX_FULL)
 569                 i2c_dw_read(dev);
 570
 571         if (stat & DW_IC_INTR_TX_EMPTY)
 572                 i2c_dw_xfer_msg(dev);
 573
 574         /*
 575          * No need to modify or disable the interrupt mask here.
 576          * i2c_dw_xfer_msg() will take care of it according to
 577          * the current transmit status.
 578          */
 579
 580 tx_aborted:
 581         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 582                 complete(&dev->cmd_complete);
 583         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 584                 /* Workaround to trigger pending interrupt */
 585                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 586                 i2c_dw_disable_int(dev);
 587                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 588         }
 589
 590         return 0;
 591 }
 592
 593 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 594 {
 595         struct dw_i2c_dev *dev = dev_id;
 596         u32 stat, enabled;
 597
 598         enabled = dw_readl(dev, DW_IC_ENABLE);
 599         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 600         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 601         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 602                 return IRQ_NONE;
 603
 604         i2c_dw_irq_handler_master(dev);
 605
 606         return IRQ_HANDLED;
 607 }
 608
 609 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 610 {
 611         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 612
 613         i2c_dw_disable(dev);
 614         reset_control_assert(dev->rst);
 615         i2c_dw_prepare_clk(dev, false);
 616 }
 617
 618 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 619 {
 620         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 621
 622         i2c_dw_prepare_clk(dev, true);
 623         reset_control_deassert(dev->rst);
 624         i2c_dw_init_master(dev);
 625 }
 626
 627 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 628 {
 629         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 630         struct i2c_adapter *adap = &dev->adapter;
 631         struct gpio_desc *gpio;
 632         int r;
 633
 634         gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
 635         if (IS_ERR(gpio)) {
 636                 r = PTR_ERR(gpio);
 637                 if (r == -ENOENT || r == -ENOSYS)
 638                         return 0;
 639                 return r;
 640         }
 641         rinfo->scl_gpiod = gpio;
 642
 643         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 644         if (IS_ERR(gpio))
 645                 return PTR_ERR(gpio);
 646         rinfo->sda_gpiod = gpio;
 647
 648         rinfo->recover_bus = i2c_generic_scl_recovery;
 649         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 650         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 651         adap->bus_recovery_info = rinfo;
 652
 653         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 654                  rinfo->sda_gpiod ? ",sda" : "");
 655
 656         return 0;
 657 }
 658
 659 int i2c_dw_probe(struct dw_i2c_dev *dev)
 660 {
 661         struct i2c_adapter *adap = &dev->adapter;
 662         unsigned long irq_flags;
 663         int ret;
 664
 665         init_completion(&dev->cmd_complete);
 666
 667         dev->init = i2c_dw_init_master;
 668         dev->disable = i2c_dw_disable;
 669         dev->disable_int = i2c_dw_disable_int;
 670
 671         ret = i2c_dw_set_reg_access(dev);
 672         if (ret)
 673                 return ret;
 674
 675         ret = dev->init(dev);
 676         if (ret)
 677                 return ret;
 678
 679         snprintf(adap->name, sizeof(adap->name),
 680                  "Synopsys DesignWare I2C adapter");
 681         adap->retries = 3;
 682         adap->algo = &i2c_dw_algo;
 683         adap->dev.parent = dev->dev;
 684         i2c_set_adapdata(adap, dev);
 685
 686         if (dev->pm_disabled) {
 687                 dev_pm_syscore_device(dev->dev, true);
 688                 irq_flags = IRQF_NO_SUSPEND;
 689         } else {
 690                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 691         }
 692
 693         i2c_dw_disable_int(dev);
 694         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 695                                dev_name(dev->dev), dev);
 696         if (ret) {
 697                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 698                         dev->irq, ret);
 699                 return ret;
 700         }
 701
 702         ret = i2c_dw_init_recovery_info(dev);
 703         if (ret)
 704                 return ret;
 705
 706         /*
 707          * Increment PM usage count during adapter registration in order to
 708          * avoid possible spurious runtime suspend when adapter device is
 709          * registered to the device core and immediate resume in case bus has
 710          * registered I2C slaves that do I2C transfers in their probe.
 711          */
 712         pm_runtime_get_noresume(dev->dev);
 713         ret = i2c_add_numbered_adapter(adap);
 714         if (ret)
 715                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 716         pm_runtime_put_noidle(dev->dev);
 717
 718         return ret;
 719 }
 720 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 721
 722 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 723 MODULE_LICENSE("GPL");