1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/i2c.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/pci.h>
17 #include <linux/mutex.h>
18 #include <linux/ktime.h>
19 #include <linux/slab.h>
21 #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
22 #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
23 #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
24 #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
25 #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
27 #define PCH_I2CSADR 0x00 /* I2C slave address register */
28 #define PCH_I2CCTL 0x04 /* I2C control register */
29 #define PCH_I2CSR 0x08 /* I2C status register */
30 #define PCH_I2CDR 0x0C /* I2C data register */
31 #define PCH_I2CMON 0x10 /* I2C bus monitor register */
32 #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
33 #define PCH_I2CMOD 0x18 /* I2C mode register */
34 #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
35 #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
36 #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
37 #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
38 #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
39 #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
40 #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
41 #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
42 #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
43 #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
44 #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
45 #define PCH_I2CTMR 0x48 /* I2C timer register */
46 #define PCH_I2CSRST 0xFC /* I2C reset register */
47 #define PCH_I2CNF 0xF8 /* I2C noise filter register */
49 #define BUS_IDLE_TIMEOUT 20
50 #define PCH_I2CCTL_I2CMEN 0x0080
51 #define TEN_BIT_ADDR_DEFAULT 0xF000
52 #define TEN_BIT_ADDR_MASK 0xF0
53 #define PCH_START 0x0020
54 #define PCH_RESTART 0x0004
55 #define PCH_ESR_START 0x0001
56 #define PCH_BUFF_START 0x1
57 #define PCH_REPSTART 0x0004
58 #define PCH_ACK 0x0008
59 #define PCH_GETACK 0x0001
62 #define I2CMCF_BIT 0x0080
63 #define I2CMIF_BIT 0x0002
64 #define I2CMAL_BIT 0x0010
65 #define I2CBMFI_BIT 0x0001
66 #define I2CBMAL_BIT 0x0002
67 #define I2CBMNA_BIT 0x0004
68 #define I2CBMTO_BIT 0x0008
69 #define I2CBMIS_BIT 0x0010
70 #define I2CESRFI_BIT 0X0001
71 #define I2CESRTO_BIT 0x0002
72 #define I2CESRFIIE_BIT 0x1
73 #define I2CESRTOIE_BIT 0x2
74 #define I2CBMDZ_BIT 0x0040
75 #define I2CBMAG_BIT 0x0020
76 #define I2CMBB_BIT 0x0020
77 #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
78 I2CBMTO_BIT | I2CBMIS_BIT)
79 #define I2C_ADDR_MSK 0xFF
80 #define I2C_MSB_2B_MSK 0x300
81 #define FAST_MODE_CLK 400
82 #define FAST_MODE_EN 0x0001
83 #define SUB_ADDR_LEN_MAX 4
84 #define BUF_LEN_MAX 32
85 #define PCH_BUFFER_MODE 0x1
86 #define EEPROM_SW_RST_MODE 0x0002
87 #define NORMAL_INTR_ENBL 0x0300
88 #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
89 #define EEPROM_RST_INTR_DISBL 0x0
90 #define BUFFER_MODE_INTR_ENBL 0x001F
91 #define BUFFER_MODE_INTR_DISBL 0x0
92 #define NORMAL_MODE 0x0
93 #define BUFFER_MODE 0x1
94 #define EEPROM_SR_MODE 0x2
95 #define I2C_TX_MODE 0x0010
96 #define PCH_BUF_TX 0xFFF7
97 #define PCH_BUF_RD 0x0008
98 #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
99 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
100 #define I2CMAL_EVENT 0x0001
101 #define I2CMCF_EVENT 0x0002
102 #define I2CBMFI_EVENT 0x0004
103 #define I2CBMAL_EVENT 0x0008
104 #define I2CBMNA_EVENT 0x0010
105 #define I2CBMTO_EVENT 0x0020
106 #define I2CBMIS_EVENT 0x0040
107 #define I2CESRFI_EVENT 0x0080
108 #define I2CESRTO_EVENT 0x0100
109 #define PCI_DEVICE_ID_PCH_I2C 0x8817
111 #define pch_dbg(adap, fmt, arg...) \
112 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
114 #define pch_err(adap, fmt, arg...) \
115 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
117 #define pch_pci_err(pdev, fmt, arg...) \
118 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
120 #define pch_pci_dbg(pdev, fmt, arg...) \
121 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
124 Set the number of I2C instance max
125 Intel EG20T PCH : 1ch
126 LAPIS Semiconductor ML7213 IOH : 2ch
127 LAPIS Semiconductor ML7831 IOH : 1ch
129 #define PCH_I2C_MAX_DEV 2
132 * struct i2c_algo_pch_data - for I2C driver functionalities
133 * @pch_adapter: stores the reference to i2c_adapter structure
134 * @p_adapter_info: stores the reference to adapter_info structure
135 * @pch_base_address: specifies the remapped base address
136 * @pch_buff_mode_en: specifies if buffer mode is enabled
137 * @pch_event_flag: specifies occurrence of interrupt events
138 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
140 struct i2c_algo_pch_data {
141 struct i2c_adapter pch_adapter;
142 struct adapter_info *p_adapter_info;
143 void __iomem *pch_base_address;
144 int pch_buff_mode_en;
146 bool pch_i2c_xfer_in_progress;
150 * struct adapter_info - This structure holds the adapter information for the
152 * @pch_data: stores a list of i2c_algo_pch_data
153 * @pch_i2c_suspended: specifies whether the system is suspended or not
154 * perhaps with more lines and words.
155 * @ch_num: specifies the number of i2c instance
157 * pch_data has as many elements as maximum I2C channels
159 struct adapter_info {
160 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
161 bool pch_i2c_suspended;
166 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
167 static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
168 static wait_queue_head_t pch_event;
169 static DEFINE_MUTEX(pch_mutex);
171 /* Definition for ML7213 by LAPIS Semiconductor */
172 #define PCI_DEVICE_ID_ML7213_I2C 0x802D
173 #define PCI_DEVICE_ID_ML7223_I2C 0x8010
174 #define PCI_DEVICE_ID_ML7831_I2C 0x8817
176 static const struct pci_device_id pch_pcidev_id[] = {
177 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
178 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
179 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
180 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
184 static irqreturn_t pch_i2c_handler(int irq, void *pData);
186 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
189 val = ioread32(addr + offset);
191 iowrite32(val, addr + offset);
194 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
197 val = ioread32(addr + offset);
199 iowrite32(val, addr + offset);
203 * pch_i2c_init() - hardware initialization of I2C module
204 * @adap: Pointer to struct i2c_algo_pch_data.
206 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
208 void __iomem *p = adap->pch_base_address;
213 /* reset I2C controller */
214 iowrite32(0x01, p + PCH_I2CSRST);
216 iowrite32(0x0, p + PCH_I2CSRST);
218 /* Initialize I2C registers */
219 iowrite32(0x21, p + PCH_I2CNF);
221 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
223 if (pch_i2c_speed != 400)
226 reg_value = PCH_I2CCTL_I2CMEN;
227 if (pch_i2c_speed == FAST_MODE_CLK) {
228 reg_value |= FAST_MODE_EN;
229 pch_dbg(adap, "Fast mode enabled\n");
232 if (pch_clk > PCH_MAX_CLK)
235 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
236 /* Set transfer speed in I2CBC */
237 iowrite32(pch_i2cbc, p + PCH_I2CBC);
239 pch_i2ctmr = (pch_clk) / 8;
240 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
242 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
243 iowrite32(reg_value, p + PCH_I2CCTL);
246 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
247 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
249 init_waitqueue_head(&pch_event);
253 * pch_i2c_wait_for_bus_idle() - check the status of bus.
254 * @adap: Pointer to struct i2c_algo_pch_data.
255 * @timeout: waiting time counter (ms).
257 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
260 void __iomem *p = adap->pch_base_address;
262 unsigned long end = jiffies + msecs_to_jiffies(timeout);
264 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
265 if (time_after(jiffies, end)) {
266 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
267 pch_err(adap, "%s: Timeout Error.return%d\n",
275 /* Retry after some usecs */
278 /* Wait a bit more without consuming CPU */
279 usleep_range(20, 1000);
288 * pch_i2c_start() - Generate I2C start condition in normal mode.
289 * @adap: Pointer to struct i2c_algo_pch_data.
291 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
293 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
295 void __iomem *p = adap->pch_base_address;
296 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
297 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
301 * pch_i2c_stop() - generate stop condition in normal mode.
302 * @adap: Pointer to struct i2c_algo_pch_data.
304 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
306 void __iomem *p = adap->pch_base_address;
307 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
308 /* clear the start bit */
309 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
312 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
315 void __iomem *p = adap->pch_base_address;
317 ret = wait_event_timeout(pch_event,
318 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
320 pch_err(adap, "%s:wait-event timeout\n", __func__);
321 adap->pch_event_flag = 0;
327 if (adap->pch_event_flag & I2C_ERROR_MASK) {
328 pch_err(adap, "Lost Arbitration\n");
329 adap->pch_event_flag = 0;
330 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
331 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
336 adap->pch_event_flag = 0;
338 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
339 pch_dbg(adap, "Receive NACK for slave address setting\n");
347 * pch_i2c_repstart() - generate repeated start condition in normal mode
348 * @adap: Pointer to struct i2c_algo_pch_data.
350 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
352 void __iomem *p = adap->pch_base_address;
353 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
354 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
358 * pch_i2c_writebytes() - write data to I2C bus in normal mode
359 * @i2c_adap: Pointer to the struct i2c_adapter.
360 * @last: specifies whether last message or not.
361 * In the case of compound mode it will be 1 for last message,
363 * @first: specifies whether first message or not.
364 * 1 for first message otherwise 0.
366 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
367 struct i2c_msg *msgs, u32 last, u32 first)
369 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
377 void __iomem *p = adap->pch_base_address;
383 /* enable master tx */
384 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
386 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
390 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
394 if (msgs->flags & I2C_M_TEN) {
395 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
396 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
400 rtn = pch_i2c_wait_for_check_xfer(adap);
404 addr_8_lsb = (addr & I2C_ADDR_MSK);
405 iowrite32(addr_8_lsb, p + PCH_I2CDR);
407 /* set 7 bit slave address and R/W bit as 0 */
408 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
413 rtn = pch_i2c_wait_for_check_xfer(adap);
417 for (wrcount = 0; wrcount < length; ++wrcount) {
418 /* write buffer value to I2C data register */
419 iowrite32(buf[wrcount], p + PCH_I2CDR);
420 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
422 rtn = pch_i2c_wait_for_check_xfer(adap);
426 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
427 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
430 /* check if this is the last message */
434 pch_i2c_repstart(adap);
436 pch_dbg(adap, "return=%d\n", wrcount);
442 * pch_i2c_sendack() - send ACK
443 * @adap: Pointer to struct i2c_algo_pch_data.
445 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
447 void __iomem *p = adap->pch_base_address;
448 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
449 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
453 * pch_i2c_sendnack() - send NACK
454 * @adap: Pointer to struct i2c_algo_pch_data.
456 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
458 void __iomem *p = adap->pch_base_address;
459 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
460 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
464 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
465 * @adap: Pointer to struct i2c_algo_pch_data.
467 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
469 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
471 void __iomem *p = adap->pch_base_address;
472 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
473 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
477 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
478 * @i2c_adap: Pointer to the struct i2c_adapter.
479 * @msgs: Pointer to i2c_msg structure.
480 * @last: specifies whether last message or not.
481 * @first: specifies whether first message or not.
483 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
486 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
494 void __iomem *p = adap->pch_base_address;
501 /* enable master reception */
502 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
505 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
509 if (msgs->flags & I2C_M_TEN) {
510 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
511 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
515 rtn = pch_i2c_wait_for_check_xfer(adap);
519 addr_8_lsb = (addr & I2C_ADDR_MSK);
520 iowrite32(addr_8_lsb, p + PCH_I2CDR);
522 pch_i2c_restart(adap);
524 rtn = pch_i2c_wait_for_check_xfer(adap);
528 addr_2_msb |= I2C_RD;
529 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
531 /* 7 address bits + R/W bit */
532 iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
535 /* check if it is the first message */
539 rtn = pch_i2c_wait_for_check_xfer(adap);
545 ioread32(p + PCH_I2CDR); /* Dummy read needs */
551 pch_i2c_sendack(adap);
554 for (loop = 1, read_index = 0; loop < length; loop++) {
555 buf[read_index] = ioread32(p + PCH_I2CDR);
560 rtn = pch_i2c_wait_for_check_xfer(adap);
565 pch_i2c_sendnack(adap);
567 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
572 rtn = pch_i2c_wait_for_check_xfer(adap);
579 pch_i2c_repstart(adap);
581 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
589 * pch_i2c_cb() - Interrupt handler Call back function
590 * @adap: Pointer to struct i2c_algo_pch_data.
592 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
595 void __iomem *p = adap->pch_base_address;
597 sts = ioread32(p + PCH_I2CSR);
598 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
599 if (sts & I2CMAL_BIT)
600 adap->pch_event_flag |= I2CMAL_EVENT;
602 if (sts & I2CMCF_BIT)
603 adap->pch_event_flag |= I2CMCF_EVENT;
605 /* clear the applicable bits */
606 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
608 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
614 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
616 * @pData: cookie passed back to the handler function.
618 static irqreturn_t pch_i2c_handler(int irq, void *pData)
623 struct adapter_info *adap_info = pData;
627 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
628 p = adap_info->pch_data[i].pch_base_address;
629 mode = ioread32(p + PCH_I2CMOD);
630 mode &= BUFFER_MODE | EEPROM_SR_MODE;
631 if (mode != NORMAL_MODE) {
632 pch_err(adap_info->pch_data,
633 "I2C-%d mode(%d) is not supported\n", mode, i);
636 reg_val = ioread32(p + PCH_I2CSR);
637 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
638 pch_i2c_cb(&adap_info->pch_data[i]);
643 return flag ? IRQ_HANDLED : IRQ_NONE;
647 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
648 * @i2c_adap: Pointer to the struct i2c_adapter.
649 * @msgs: Pointer to i2c_msg structure.
650 * @num: number of messages.
652 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
653 struct i2c_msg *msgs, s32 num)
655 struct i2c_msg *pmsg;
660 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
662 ret = mutex_lock_interruptible(&pch_mutex);
666 if (adap->p_adapter_info->pch_i2c_suspended) {
667 mutex_unlock(&pch_mutex);
671 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
672 adap->p_adapter_info->pch_i2c_suspended);
673 /* transfer not completed */
674 adap->pch_i2c_xfer_in_progress = true;
676 for (i = 0; i < num && ret >= 0; i++) {
678 pmsg->flags |= adap->pch_buff_mode_en;
679 status = pmsg->flags;
681 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
683 if ((status & (I2C_M_RD)) != false) {
684 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
687 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
692 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
694 mutex_unlock(&pch_mutex);
696 return (ret < 0) ? ret : num;
700 * pch_i2c_func() - return the functionality of the I2C driver
701 * @adap: Pointer to struct i2c_algo_pch_data.
703 static u32 pch_i2c_func(struct i2c_adapter *adap)
705 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
708 static const struct i2c_algorithm pch_algorithm = {
709 .master_xfer = pch_i2c_xfer,
710 .functionality = pch_i2c_func
714 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
715 * @adap: Pointer to struct i2c_algo_pch_data.
717 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
719 void __iomem *p = adap->pch_base_address;
721 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
723 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
725 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
728 static int pch_i2c_probe(struct pci_dev *pdev,
729 const struct pci_device_id *id)
731 void __iomem *base_addr;
734 struct adapter_info *adap_info;
735 struct i2c_adapter *pch_adap;
737 pch_pci_dbg(pdev, "Entered.\n");
739 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
740 if (adap_info == NULL)
743 ret = pci_enable_device(pdev);
745 pch_pci_err(pdev, "pci_enable_device FAILED\n");
749 ret = pci_request_regions(pdev, KBUILD_MODNAME);
751 pch_pci_err(pdev, "pci_request_regions FAILED\n");
755 base_addr = pci_iomap(pdev, 1, 0);
757 if (base_addr == NULL) {
758 pch_pci_err(pdev, "pci_iomap FAILED\n");
763 /* Set the number of I2C channel instance */
764 adap_info->ch_num = id->driver_data;
766 for (i = 0; i < adap_info->ch_num; i++) {
767 pch_adap = &adap_info->pch_data[i].pch_adapter;
768 adap_info->pch_i2c_suspended = false;
770 adap_info->pch_data[i].p_adapter_info = adap_info;
772 pch_adap->owner = THIS_MODULE;
773 pch_adap->class = I2C_CLASS_HWMON;
774 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
775 pch_adap->algo = &pch_algorithm;
776 pch_adap->algo_data = &adap_info->pch_data[i];
778 /* base_addr + offset; */
779 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
781 pch_adap->dev.of_node = pdev->dev.of_node;
782 pch_adap->dev.parent = &pdev->dev;
785 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
786 KBUILD_MODNAME, adap_info);
788 pch_pci_err(pdev, "request_irq FAILED\n");
789 goto err_request_irq;
792 for (i = 0; i < adap_info->ch_num; i++) {
793 pch_adap = &adap_info->pch_data[i].pch_adapter;
795 pch_i2c_init(&adap_info->pch_data[i]);
798 ret = i2c_add_numbered_adapter(pch_adap);
800 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
801 goto err_add_adapter;
805 pci_set_drvdata(pdev, adap_info);
806 pch_pci_dbg(pdev, "returns %d.\n", ret);
810 for (j = 0; j < i; j++)
811 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
812 free_irq(pdev->irq, adap_info);
814 pci_iounmap(pdev, base_addr);
816 pci_release_regions(pdev);
818 pci_disable_device(pdev);
824 static void pch_i2c_remove(struct pci_dev *pdev)
827 struct adapter_info *adap_info = pci_get_drvdata(pdev);
829 free_irq(pdev->irq, adap_info);
831 for (i = 0; i < adap_info->ch_num; i++) {
832 pch_i2c_disbl_int(&adap_info->pch_data[i]);
833 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
836 if (adap_info->pch_data[0].pch_base_address)
837 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
839 for (i = 0; i < adap_info->ch_num; i++)
840 adap_info->pch_data[i].pch_base_address = NULL;
842 pci_release_regions(pdev);
844 pci_disable_device(pdev);
849 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
853 struct adapter_info *adap_info = pci_get_drvdata(pdev);
854 void __iomem *p = adap_info->pch_data[0].pch_base_address;
856 adap_info->pch_i2c_suspended = true;
858 for (i = 0; i < adap_info->ch_num; i++) {
859 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
860 /* Wait until all channel transfers are completed */
865 /* Disable the i2c interrupts */
866 for (i = 0; i < adap_info->ch_num; i++)
867 pch_i2c_disbl_int(&adap_info->pch_data[i]);
869 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
870 "invoked function pch_i2c_disbl_int successfully\n",
871 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
872 ioread32(p + PCH_I2CESRSTA));
874 ret = pci_save_state(pdev);
877 pch_pci_err(pdev, "pci_save_state\n");
881 pci_enable_wake(pdev, PCI_D3hot, 0);
882 pci_disable_device(pdev);
883 pci_set_power_state(pdev, pci_choose_state(pdev, state));
888 static int pch_i2c_resume(struct pci_dev *pdev)
891 struct adapter_info *adap_info = pci_get_drvdata(pdev);
893 pci_set_power_state(pdev, PCI_D0);
894 pci_restore_state(pdev);
896 if (pci_enable_device(pdev) < 0) {
897 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
901 pci_enable_wake(pdev, PCI_D3hot, 0);
903 for (i = 0; i < adap_info->ch_num; i++)
904 pch_i2c_init(&adap_info->pch_data[i]);
906 adap_info->pch_i2c_suspended = false;
911 #define pch_i2c_suspend NULL
912 #define pch_i2c_resume NULL
915 static struct pci_driver pch_pcidriver = {
916 .name = KBUILD_MODNAME,
917 .id_table = pch_pcidev_id,
918 .probe = pch_i2c_probe,
919 .remove = pch_i2c_remove,
920 .suspend = pch_i2c_suspend,
921 .resume = pch_i2c_resume
924 module_pci_driver(pch_pcidriver);
926 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
927 MODULE_LICENSE("GPL");
928 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
929 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
930 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));