2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
68 * Features supported by this driver:
72 * Block process call transaction no
73 * I2C block read transaction yes (doesn't use the block buffer)
75 * Interrupt processing yes
77 * See the file Documentation/i2c/busses/i2c-i801 for details.
80 #include <linux/interrupt.h>
81 #include <linux/module.h>
82 #include <linux/pci.h>
83 #include <linux/kernel.h>
84 #include <linux/stddef.h>
85 #include <linux/delay.h>
86 #include <linux/ioport.h>
87 #include <linux/init.h>
88 #include <linux/i2c.h>
89 #include <linux/acpi.h>
91 #include <linux/dmi.h>
92 #include <linux/slab.h>
93 #include <linux/wait.h>
94 #include <linux/err.h>
95 #include <linux/platform_device.h>
96 #include <linux/platform_data/itco_wdt.h>
97 #include <linux/pm_runtime.h>
99 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
101 #include <linux/gpio.h>
102 #include <linux/i2c-mux-gpio.h>
105 /* I801 SMBus address offsets */
106 #define SMBHSTSTS(p) (0 + (p)->smba)
107 #define SMBHSTCNT(p) (2 + (p)->smba)
108 #define SMBHSTCMD(p) (3 + (p)->smba)
109 #define SMBHSTADD(p) (4 + (p)->smba)
110 #define SMBHSTDAT0(p) (5 + (p)->smba)
111 #define SMBHSTDAT1(p) (6 + (p)->smba)
112 #define SMBBLKDAT(p) (7 + (p)->smba)
113 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
114 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
115 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
117 /* PCI Address Constants */
119 #define SMBPCICTL 0x004
120 #define SMBPCISTS 0x006
121 #define SMBHSTCFG 0x040
122 #define TCOBASE 0x050
125 #define ACPIBASE 0x040
126 #define ACPIBASE_SMI_OFF 0x030
127 #define ACPICTRL 0x044
128 #define ACPICTRL_EN 0x080
130 #define SBREG_BAR 0x10
131 #define SBREG_SMBCTRL 0xc6000c
133 /* Host status bits for SMBPCISTS */
134 #define SMBPCISTS_INTS 0x08
136 /* Control bits for SMBPCICTL */
137 #define SMBPCICTL_INTDIS 0x0400
139 /* Host configuration bits for SMBHSTCFG */
140 #define SMBHSTCFG_HST_EN 1
141 #define SMBHSTCFG_SMB_SMI_EN 2
142 #define SMBHSTCFG_I2C_EN 4
144 /* TCO configuration bits for TCOCTL */
145 #define TCOCTL_EN 0x0100
147 /* Auxiliary control register bits, ICH4+ only */
148 #define SMBAUXCTL_CRC 1
149 #define SMBAUXCTL_E32B 2
152 #define MAX_RETRIES 400
154 /* I801 command constants */
155 #define I801_QUICK 0x00
156 #define I801_BYTE 0x04
157 #define I801_BYTE_DATA 0x08
158 #define I801_WORD_DATA 0x0C
159 #define I801_PROC_CALL 0x10 /* unimplemented */
160 #define I801_BLOCK_DATA 0x14
161 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
163 /* I801 Host Control register bits */
164 #define SMBHSTCNT_INTREN 0x01
165 #define SMBHSTCNT_KILL 0x02
166 #define SMBHSTCNT_LAST_BYTE 0x20
167 #define SMBHSTCNT_START 0x40
168 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
170 /* I801 Hosts Status register bits */
171 #define SMBHSTSTS_BYTE_DONE 0x80
172 #define SMBHSTSTS_INUSE_STS 0x40
173 #define SMBHSTSTS_SMBALERT_STS 0x20
174 #define SMBHSTSTS_FAILED 0x10
175 #define SMBHSTSTS_BUS_ERR 0x08
176 #define SMBHSTSTS_DEV_ERR 0x04
177 #define SMBHSTSTS_INTR 0x02
178 #define SMBHSTSTS_HOST_BUSY 0x01
180 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
183 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
186 /* Older devices have their ID defined in <linux/pci_ids.h> */
187 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
188 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
189 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
191 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
194 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
195 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
196 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
197 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
198 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
199 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
200 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
201 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
202 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
203 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
205 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
206 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
207 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
208 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
209 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
210 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
211 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
213 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
215 struct i801_mux_config {
220 unsigned gpios[2]; /* Relative to gpio_chip->base */
225 struct i2c_adapter adapter;
227 unsigned char original_hstcfg;
228 struct pci_dev *pci_dev;
229 unsigned int features;
232 wait_queue_head_t waitq;
235 /* Command state used by isr for byte-by-byte block transactions */
242 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
244 const struct i801_mux_config *mux_drvdata;
245 struct platform_device *mux_pdev;
247 struct platform_device *tco_pdev;
250 * If set to true the host controller registers are reserved for
251 * ACPI AML use. Protected by acpi_lock.
254 struct mutex acpi_lock;
257 #define FEATURE_SMBUS_PEC (1 << 0)
258 #define FEATURE_BLOCK_BUFFER (1 << 1)
259 #define FEATURE_BLOCK_PROC (1 << 2)
260 #define FEATURE_I2C_BLOCK_READ (1 << 3)
261 #define FEATURE_IRQ (1 << 4)
262 /* Not really a feature, but it's convenient to handle it as such */
263 #define FEATURE_IDF (1 << 15)
264 #define FEATURE_TCO (1 << 16)
266 static const char *i801_feature_names[] = {
269 "Block process call",
274 static unsigned int disable_features;
275 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
276 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
277 "\t\t 0x01 disable SMBus PEC\n"
278 "\t\t 0x02 disable the block buffer\n"
279 "\t\t 0x08 disable the I2C block read functionality\n"
280 "\t\t 0x10 don't use interrupts ");
282 /* Make sure the SMBus host is ready to start transmitting.
283 Return 0 if it is, -EBUSY if it is not. */
284 static int i801_check_pre(struct i801_priv *priv)
288 status = inb_p(SMBHSTSTS(priv));
289 if (status & SMBHSTSTS_HOST_BUSY) {
290 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
294 status &= STATUS_FLAGS;
296 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
298 outb_p(status, SMBHSTSTS(priv));
299 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
301 dev_err(&priv->pci_dev->dev,
302 "Failed clearing status flags (%02x)\n",
312 * Convert the status register to an error code, and clear it.
313 * Note that status only contains the bits we want to clear, not the
314 * actual register value.
316 static int i801_check_post(struct i801_priv *priv, int status)
321 * If the SMBus is still busy, we give up
322 * Note: This timeout condition only happens when using polling
323 * transactions. For interrupt operation, NAK/timeout is indicated by
326 if (unlikely(status < 0)) {
327 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
328 /* try to stop the current command */
329 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
330 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
332 usleep_range(1000, 2000);
333 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
336 /* Check if it worked */
337 status = inb_p(SMBHSTSTS(priv));
338 if ((status & SMBHSTSTS_HOST_BUSY) ||
339 !(status & SMBHSTSTS_FAILED))
340 dev_err(&priv->pci_dev->dev,
341 "Failed terminating the transaction\n");
342 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
346 if (status & SMBHSTSTS_FAILED) {
348 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
350 if (status & SMBHSTSTS_DEV_ERR) {
352 dev_dbg(&priv->pci_dev->dev, "No response\n");
354 if (status & SMBHSTSTS_BUS_ERR) {
356 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
359 /* Clear status flags except BYTE_DONE, to be cleared by caller */
360 outb_p(status, SMBHSTSTS(priv));
365 /* Wait for BUSY being cleared and either INTR or an error flag being set */
366 static int i801_wait_intr(struct i801_priv *priv)
371 /* We will always wait for a fraction of a second! */
373 usleep_range(250, 500);
374 status = inb_p(SMBHSTSTS(priv));
375 } while (((status & SMBHSTSTS_HOST_BUSY) ||
376 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
377 (timeout++ < MAX_RETRIES));
379 if (timeout > MAX_RETRIES) {
380 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
383 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
386 /* Wait for either BYTE_DONE or an error flag being set */
387 static int i801_wait_byte_done(struct i801_priv *priv)
392 /* We will always wait for a fraction of a second! */
394 usleep_range(250, 500);
395 status = inb_p(SMBHSTSTS(priv));
396 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
397 (timeout++ < MAX_RETRIES));
399 if (timeout > MAX_RETRIES) {
400 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
403 return status & STATUS_ERROR_FLAGS;
406 static int i801_transaction(struct i801_priv *priv, int xact)
410 const struct i2c_adapter *adap = &priv->adapter;
412 result = i801_check_pre(priv);
416 if (priv->features & FEATURE_IRQ) {
417 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
419 result = wait_event_timeout(priv->waitq,
420 (status = priv->status),
424 dev_warn(&priv->pci_dev->dev,
425 "Timeout waiting for interrupt!\n");
428 return i801_check_post(priv, status);
431 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
432 * SMBSCMD are passed in xact */
433 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
435 status = i801_wait_intr(priv);
436 return i801_check_post(priv, status);
439 static int i801_block_transaction_by_block(struct i801_priv *priv,
440 union i2c_smbus_data *data,
441 char read_write, int hwpec)
446 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
448 /* Use 32-byte buffer to process this transaction */
449 if (read_write == I2C_SMBUS_WRITE) {
450 len = data->block[0];
451 outb_p(len, SMBHSTDAT0(priv));
452 for (i = 0; i < len; i++)
453 outb_p(data->block[i+1], SMBBLKDAT(priv));
456 status = i801_transaction(priv, I801_BLOCK_DATA |
457 (hwpec ? SMBHSTCNT_PEC_EN : 0));
461 if (read_write == I2C_SMBUS_READ) {
462 len = inb_p(SMBHSTDAT0(priv));
463 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
466 data->block[0] = len;
467 for (i = 0; i < len; i++)
468 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
473 static void i801_isr_byte_done(struct i801_priv *priv)
476 /* For SMBus block reads, length is received with first byte */
477 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
478 (priv->count == 0)) {
479 priv->len = inb_p(SMBHSTDAT0(priv));
480 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
481 dev_err(&priv->pci_dev->dev,
482 "Illegal SMBus block read size %d\n",
485 priv->len = I2C_SMBUS_BLOCK_MAX;
487 dev_dbg(&priv->pci_dev->dev,
488 "SMBus block read size is %d\n",
491 priv->data[-1] = priv->len;
495 if (priv->count < priv->len)
496 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
498 dev_dbg(&priv->pci_dev->dev,
499 "Discarding extra byte on block read\n");
501 /* Set LAST_BYTE for last byte of read transaction */
502 if (priv->count == priv->len - 1)
503 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
505 } else if (priv->count < priv->len - 1) {
506 /* Write next byte, except for IRQ after last byte */
507 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
510 /* Clear BYTE_DONE to continue with next byte */
511 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
515 * There are two kinds of interrupts:
517 * 1) i801 signals transaction completion with one of these interrupts:
519 * DEV_ERR - Invalid command, NAK or communication timeout
520 * BUS_ERR - SMI# transaction collision
521 * FAILED - transaction was canceled due to a KILL request
522 * When any of these occur, update ->status and wake up the waitq.
523 * ->status must be cleared before kicking off the next transaction.
525 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
526 * occurs for each byte of a byte-by-byte to prepare the next byte.
528 static irqreturn_t i801_isr(int irq, void *dev_id)
530 struct i801_priv *priv = dev_id;
534 /* Confirm this is our interrupt */
535 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
536 if (!(pcists & SMBPCISTS_INTS))
539 status = inb_p(SMBHSTSTS(priv));
540 if (status & SMBHSTSTS_BYTE_DONE)
541 i801_isr_byte_done(priv);
544 * Clear irq sources and report transaction result.
545 * ->status must be cleared before the next transaction is started.
547 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
549 outb_p(status, SMBHSTSTS(priv));
550 priv->status |= status;
551 wake_up(&priv->waitq);
558 * For "byte-by-byte" block transactions:
559 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
560 * I2C read uses cmd=I801_I2C_BLOCK_DATA
562 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
563 union i2c_smbus_data *data,
564 char read_write, int command,
571 const struct i2c_adapter *adap = &priv->adapter;
573 result = i801_check_pre(priv);
577 len = data->block[0];
579 if (read_write == I2C_SMBUS_WRITE) {
580 outb_p(len, SMBHSTDAT0(priv));
581 outb_p(data->block[1], SMBBLKDAT(priv));
584 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
585 read_write == I2C_SMBUS_READ)
586 smbcmd = I801_I2C_BLOCK_DATA;
588 smbcmd = I801_BLOCK_DATA;
590 if (priv->features & FEATURE_IRQ) {
591 priv->is_read = (read_write == I2C_SMBUS_READ);
592 if (len == 1 && priv->is_read)
593 smbcmd |= SMBHSTCNT_LAST_BYTE;
594 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
597 priv->data = &data->block[1];
599 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
600 result = wait_event_timeout(priv->waitq,
601 (status = priv->status),
605 dev_warn(&priv->pci_dev->dev,
606 "Timeout waiting for interrupt!\n");
609 return i801_check_post(priv, status);
612 for (i = 1; i <= len; i++) {
613 if (i == len && read_write == I2C_SMBUS_READ)
614 smbcmd |= SMBHSTCNT_LAST_BYTE;
615 outb_p(smbcmd, SMBHSTCNT(priv));
618 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
621 status = i801_wait_byte_done(priv);
625 if (i == 1 && read_write == I2C_SMBUS_READ
626 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
627 len = inb_p(SMBHSTDAT0(priv));
628 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
629 dev_err(&priv->pci_dev->dev,
630 "Illegal SMBus block read size %d\n",
633 while (inb_p(SMBHSTSTS(priv)) &
635 outb_p(SMBHSTSTS_BYTE_DONE,
637 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
640 data->block[0] = len;
643 /* Retrieve/store value in SMBBLKDAT */
644 if (read_write == I2C_SMBUS_READ)
645 data->block[i] = inb_p(SMBBLKDAT(priv));
646 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
647 outb_p(data->block[i+1], SMBBLKDAT(priv));
649 /* signals SMBBLKDAT ready */
650 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
653 status = i801_wait_intr(priv);
655 return i801_check_post(priv, status);
658 static int i801_set_block_buffer_mode(struct i801_priv *priv)
660 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
661 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
666 /* Block transaction function */
667 static int i801_block_transaction(struct i801_priv *priv,
668 union i2c_smbus_data *data, char read_write,
669 int command, int hwpec)
674 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
675 if (read_write == I2C_SMBUS_WRITE) {
676 /* set I2C_EN bit in configuration register */
677 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
678 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
679 hostc | SMBHSTCFG_I2C_EN);
680 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
681 dev_err(&priv->pci_dev->dev,
682 "I2C block read is unsupported!\n");
687 if (read_write == I2C_SMBUS_WRITE
688 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
689 if (data->block[0] < 1)
691 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
692 data->block[0] = I2C_SMBUS_BLOCK_MAX;
694 data->block[0] = 32; /* max for SMBus block reads */
697 /* Experience has shown that the block buffer can only be used for
698 SMBus (not I2C) block transactions, even though the datasheet
699 doesn't mention this limitation. */
700 if ((priv->features & FEATURE_BLOCK_BUFFER)
701 && command != I2C_SMBUS_I2C_BLOCK_DATA
702 && i801_set_block_buffer_mode(priv) == 0)
703 result = i801_block_transaction_by_block(priv, data,
706 result = i801_block_transaction_byte_by_byte(priv, data,
710 if (command == I2C_SMBUS_I2C_BLOCK_DATA
711 && read_write == I2C_SMBUS_WRITE) {
712 /* restore saved configuration register value */
713 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
718 /* Return negative errno on error. */
719 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
720 unsigned short flags, char read_write, u8 command,
721 int size, union i2c_smbus_data *data)
725 int ret = 0, xact = 0;
726 struct i801_priv *priv = i2c_get_adapdata(adap);
728 mutex_lock(&priv->acpi_lock);
729 if (priv->acpi_reserved) {
730 mutex_unlock(&priv->acpi_lock);
734 pm_runtime_get_sync(&priv->pci_dev->dev);
736 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
737 && size != I2C_SMBUS_QUICK
738 && size != I2C_SMBUS_I2C_BLOCK_DATA;
741 case I2C_SMBUS_QUICK:
742 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
747 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
749 if (read_write == I2C_SMBUS_WRITE)
750 outb_p(command, SMBHSTCMD(priv));
753 case I2C_SMBUS_BYTE_DATA:
754 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
756 outb_p(command, SMBHSTCMD(priv));
757 if (read_write == I2C_SMBUS_WRITE)
758 outb_p(data->byte, SMBHSTDAT0(priv));
759 xact = I801_BYTE_DATA;
761 case I2C_SMBUS_WORD_DATA:
762 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
764 outb_p(command, SMBHSTCMD(priv));
765 if (read_write == I2C_SMBUS_WRITE) {
766 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
767 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
769 xact = I801_WORD_DATA;
771 case I2C_SMBUS_BLOCK_DATA:
772 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
774 outb_p(command, SMBHSTCMD(priv));
777 case I2C_SMBUS_I2C_BLOCK_DATA:
778 /* NB: page 240 of ICH5 datasheet shows that the R/#W
779 * bit should be cleared here, even when reading */
780 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
781 if (read_write == I2C_SMBUS_READ) {
782 /* NB: page 240 of ICH5 datasheet also shows
783 * that DATA1 is the cmd field when reading */
784 outb_p(command, SMBHSTDAT1(priv));
786 outb_p(command, SMBHSTCMD(priv));
790 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
796 if (hwpec) /* enable/disable hardware PEC */
797 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
799 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
803 ret = i801_block_transaction(priv, data, read_write, size,
806 ret = i801_transaction(priv, xact);
808 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
809 time, so we forcibly disable it after every transaction. Turn off
810 E32B for the same reason. */
812 outb_p(inb_p(SMBAUXCTL(priv)) &
813 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
819 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
822 switch (xact & 0x7f) {
823 case I801_BYTE: /* Result put in SMBHSTDAT0 */
825 data->byte = inb_p(SMBHSTDAT0(priv));
828 data->word = inb_p(SMBHSTDAT0(priv)) +
829 (inb_p(SMBHSTDAT1(priv)) << 8);
834 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
835 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
836 mutex_unlock(&priv->acpi_lock);
841 static u32 i801_func(struct i2c_adapter *adapter)
843 struct i801_priv *priv = i2c_get_adapdata(adapter);
845 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
846 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
847 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
848 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
849 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
850 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
853 static const struct i2c_algorithm smbus_algorithm = {
854 .smbus_xfer = i801_access,
855 .functionality = i801_func,
858 static const struct pci_device_id i801_ids[] = {
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
868 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
869 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
870 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
871 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
872 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
873 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
874 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
875 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
876 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
878 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
879 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
880 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
881 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
882 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
883 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
884 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
885 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
886 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
887 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
888 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
889 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
890 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
891 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
892 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
893 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
894 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
895 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
896 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
897 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
898 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
899 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
903 MODULE_DEVICE_TABLE(pci, i801_ids);
905 #if defined CONFIG_X86 && defined CONFIG_DMI
906 static unsigned char apanel_addr;
908 /* Scan the system ROM for the signature "FJKEYINF" */
909 static __init const void __iomem *bios_signature(const void __iomem *bios)
912 const unsigned char signature[] = "FJKEYINF";
914 for (offset = 0; offset < 0x10000; offset += 0x10) {
915 if (check_signature(bios + offset, signature,
916 sizeof(signature)-1))
917 return bios + offset;
922 static void __init input_apanel_init(void)
925 const void __iomem *p;
927 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
928 p = bios_signature(bios);
930 /* just use the first address */
931 apanel_addr = readb(p + 8 + 3) >> 1;
936 struct dmi_onboard_device_info {
939 unsigned short i2c_addr;
940 const char *i2c_type;
943 static const struct dmi_onboard_device_info dmi_devices[] = {
944 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
945 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
946 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
949 static void dmi_check_onboard_device(u8 type, const char *name,
950 struct i2c_adapter *adap)
953 struct i2c_board_info info;
955 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
956 /* & ~0x80, ignore enabled/disabled bit */
957 if ((type & ~0x80) != dmi_devices[i].type)
959 if (strcasecmp(name, dmi_devices[i].name))
962 memset(&info, 0, sizeof(struct i2c_board_info));
963 info.addr = dmi_devices[i].i2c_addr;
964 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
965 i2c_new_device(adap, &info);
970 /* We use our own function to check for onboard devices instead of
971 dmi_find_device() as some buggy BIOS's have the devices we are interested
972 in marked as disabled */
973 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
980 count = (dm->length - sizeof(struct dmi_header)) / 2;
981 for (i = 0; i < count; i++) {
982 const u8 *d = (char *)(dm + 1) + (i * 2);
983 const char *name = ((char *) dm) + dm->length;
990 while (s > 0 && name[0]) {
991 name += strlen(name) + 1;
994 if (name[0] == 0) /* Bogus string reference */
997 dmi_check_onboard_device(type, name, adap);
1001 /* Register optional slaves */
1002 static void i801_probe_optional_slaves(struct i801_priv *priv)
1004 /* Only register slaves on main SMBus channel */
1005 if (priv->features & FEATURE_IDF)
1009 struct i2c_board_info info;
1011 memset(&info, 0, sizeof(struct i2c_board_info));
1012 info.addr = apanel_addr;
1013 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1014 i2c_new_device(&priv->adapter, &info);
1017 if (dmi_name_in_vendors("FUJITSU"))
1018 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1021 static void __init input_apanel_init(void) {}
1022 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1023 #endif /* CONFIG_X86 && CONFIG_DMI */
1025 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1027 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1028 .gpio_chip = "gpio_ich",
1029 .values = { 0x02, 0x03 },
1031 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1032 .gpios = { 52, 53 },
1036 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1037 .gpio_chip = "gpio_ich",
1038 .values = { 0x02, 0x03, 0x01 },
1040 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1041 .gpios = { 52, 53 },
1045 static const struct dmi_system_id mux_dmi_table[] = {
1048 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1049 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1051 .driver_data = &i801_mux_config_asus_z8_d12,
1055 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1056 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1058 .driver_data = &i801_mux_config_asus_z8_d12,
1062 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1063 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1065 .driver_data = &i801_mux_config_asus_z8_d12,
1069 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1070 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1072 .driver_data = &i801_mux_config_asus_z8_d12,
1076 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1077 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1079 .driver_data = &i801_mux_config_asus_z8_d12,
1083 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1084 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1086 .driver_data = &i801_mux_config_asus_z8_d12,
1090 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1091 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1093 .driver_data = &i801_mux_config_asus_z8_d18,
1097 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1098 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1100 .driver_data = &i801_mux_config_asus_z8_d18,
1104 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1105 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1107 .driver_data = &i801_mux_config_asus_z8_d12,
1112 /* Setup multiplexing if needed */
1113 static int i801_add_mux(struct i801_priv *priv)
1115 struct device *dev = &priv->adapter.dev;
1116 const struct i801_mux_config *mux_config;
1117 struct i2c_mux_gpio_platform_data gpio_data;
1120 if (!priv->mux_drvdata)
1122 mux_config = priv->mux_drvdata;
1124 /* Prepare the platform data */
1125 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1126 gpio_data.parent = priv->adapter.nr;
1127 gpio_data.values = mux_config->values;
1128 gpio_data.n_values = mux_config->n_values;
1129 gpio_data.classes = mux_config->classes;
1130 gpio_data.gpio_chip = mux_config->gpio_chip;
1131 gpio_data.gpios = mux_config->gpios;
1132 gpio_data.n_gpios = mux_config->n_gpios;
1133 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1135 /* Register the mux device */
1136 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1137 PLATFORM_DEVID_AUTO, &gpio_data,
1138 sizeof(struct i2c_mux_gpio_platform_data));
1139 if (IS_ERR(priv->mux_pdev)) {
1140 err = PTR_ERR(priv->mux_pdev);
1141 priv->mux_pdev = NULL;
1142 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1149 static void i801_del_mux(struct i801_priv *priv)
1152 platform_device_unregister(priv->mux_pdev);
1155 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1157 const struct dmi_system_id *id;
1158 const struct i801_mux_config *mux_config;
1159 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1162 id = dmi_first_match(mux_dmi_table);
1164 /* Remove branch classes from trunk */
1165 mux_config = id->driver_data;
1166 for (i = 0; i < mux_config->n_values; i++)
1167 class &= ~mux_config->classes[i];
1169 /* Remember for later */
1170 priv->mux_drvdata = mux_config;
1176 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1177 static inline void i801_del_mux(struct i801_priv *priv) { }
1179 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1181 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1185 static const struct itco_wdt_platform_data tco_platform_data = {
1186 .name = "Intel PCH",
1190 static DEFINE_SPINLOCK(p2sb_spinlock);
1192 static void i801_add_tco(struct i801_priv *priv)
1194 struct pci_dev *pci_dev = priv->pci_dev;
1195 struct resource tco_res[3], *res;
1196 struct platform_device *pdev;
1198 u32 tco_base, tco_ctl;
1199 u32 base_addr, ctrl_val;
1202 if (!(priv->features & FEATURE_TCO))
1205 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1206 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1207 if (!(tco_ctl & TCOCTL_EN))
1210 memset(tco_res, 0, sizeof(tco_res));
1212 res = &tco_res[ICH_RES_IO_TCO];
1213 res->start = tco_base & ~1;
1214 res->end = res->start + 32 - 1;
1215 res->flags = IORESOURCE_IO;
1218 * Power Management registers.
1220 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1221 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1223 res = &tco_res[ICH_RES_IO_SMI];
1224 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1225 res->end = res->start + 3;
1226 res->flags = IORESOURCE_IO;
1229 * Enable the ACPI I/O space.
1231 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1232 ctrl_val |= ACPICTRL_EN;
1233 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1236 * We must access the NO_REBOOT bit over the Primary to Sideband
1237 * bridge (P2SB). The BIOS prevents the P2SB device from being
1238 * enumerated by the PCI subsystem, so we need to unhide/hide it
1239 * to lookup the P2SB BAR.
1241 spin_lock(&p2sb_spinlock);
1243 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1245 /* Unhide the P2SB device */
1246 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1248 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1249 base64_addr = base_addr & 0xfffffff0;
1251 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1252 base64_addr |= (u64)base_addr << 32;
1254 /* Hide the P2SB device */
1255 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1256 spin_unlock(&p2sb_spinlock);
1258 res = &tco_res[ICH_RES_MEM_OFF];
1259 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1260 res->end = res->start + 3;
1261 res->flags = IORESOURCE_MEM;
1263 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1264 tco_res, 3, &tco_platform_data,
1265 sizeof(tco_platform_data));
1267 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1271 priv->tco_pdev = pdev;
1276 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1277 u64 *value, void *handler_context, void *region_context)
1279 struct i801_priv *priv = handler_context;
1280 struct pci_dev *pdev = priv->pci_dev;
1284 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1285 * further access from the driver itself. This device is now owned
1286 * by the system firmware.
1288 mutex_lock(&priv->acpi_lock);
1290 if (!priv->acpi_reserved) {
1291 priv->acpi_reserved = true;
1293 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1294 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1297 * BIOS is accessing the host controller so prevent it from
1298 * suspending automatically from now on.
1300 pm_runtime_get_sync(&pdev->dev);
1303 if ((function & ACPI_IO_MASK) == ACPI_READ)
1304 status = acpi_os_read_port(address, (u32 *)value, bits);
1306 status = acpi_os_write_port(address, (u32)*value, bits);
1308 mutex_unlock(&priv->acpi_lock);
1313 static int i801_acpi_probe(struct i801_priv *priv)
1315 struct acpi_device *adev;
1318 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1320 status = acpi_install_address_space_handler(adev->handle,
1321 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1323 if (ACPI_SUCCESS(status))
1327 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1330 static void i801_acpi_remove(struct i801_priv *priv)
1332 struct acpi_device *adev;
1334 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1338 acpi_remove_address_space_handler(adev->handle,
1339 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1341 mutex_lock(&priv->acpi_lock);
1342 if (priv->acpi_reserved)
1343 pm_runtime_put(&priv->pci_dev->dev);
1344 mutex_unlock(&priv->acpi_lock);
1347 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1348 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1351 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1355 struct i801_priv *priv;
1357 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1361 i2c_set_adapdata(&priv->adapter, priv);
1362 priv->adapter.owner = THIS_MODULE;
1363 priv->adapter.class = i801_get_adapter_class(priv);
1364 priv->adapter.algo = &smbus_algorithm;
1365 priv->adapter.dev.parent = &dev->dev;
1366 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1367 priv->adapter.retries = 3;
1368 mutex_init(&priv->acpi_lock);
1370 priv->pci_dev = dev;
1371 switch (dev->device) {
1372 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1373 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1374 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1375 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1376 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1377 priv->features |= FEATURE_I2C_BLOCK_READ;
1378 priv->features |= FEATURE_IRQ;
1379 priv->features |= FEATURE_SMBUS_PEC;
1380 priv->features |= FEATURE_BLOCK_BUFFER;
1381 priv->features |= FEATURE_TCO;
1384 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1385 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1386 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1387 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1388 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1389 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1390 priv->features |= FEATURE_IDF;
1393 priv->features |= FEATURE_I2C_BLOCK_READ;
1394 priv->features |= FEATURE_IRQ;
1396 case PCI_DEVICE_ID_INTEL_82801DB_3:
1397 priv->features |= FEATURE_SMBUS_PEC;
1398 priv->features |= FEATURE_BLOCK_BUFFER;
1400 case PCI_DEVICE_ID_INTEL_82801CA_3:
1401 case PCI_DEVICE_ID_INTEL_82801BA_2:
1402 case PCI_DEVICE_ID_INTEL_82801AB_3:
1403 case PCI_DEVICE_ID_INTEL_82801AA_3:
1407 /* Disable features on user request */
1408 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1409 if (priv->features & disable_features & (1 << i))
1410 dev_notice(&dev->dev, "%s disabled by user\n",
1411 i801_feature_names[i]);
1413 priv->features &= ~disable_features;
1415 err = pcim_enable_device(dev);
1417 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1421 pcim_pin_device(dev);
1423 /* Determine the address of the SMBus area */
1424 priv->smba = pci_resource_start(dev, SMBBAR);
1427 "SMBus base address uninitialized, upgrade BIOS\n");
1431 if (i801_acpi_probe(priv))
1434 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1435 dev_driver_string(&dev->dev));
1438 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1440 (unsigned long long)pci_resource_end(dev, SMBBAR));
1441 i801_acpi_remove(priv);
1445 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1446 priv->original_hstcfg = temp;
1447 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1448 if (!(temp & SMBHSTCFG_HST_EN)) {
1449 dev_info(&dev->dev, "Enabling SMBus device\n");
1450 temp |= SMBHSTCFG_HST_EN;
1452 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1454 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1455 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1456 /* Disable SMBus interrupt feature if SMBus using SMI# */
1457 priv->features &= ~FEATURE_IRQ;
1460 /* Clear special mode bits */
1461 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1462 outb_p(inb_p(SMBAUXCTL(priv)) &
1463 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1465 /* Default timeout in interrupt mode: 200 ms */
1466 priv->adapter.timeout = HZ / 5;
1468 if (priv->features & FEATURE_IRQ) {
1471 /* Complain if an interrupt is already pending */
1472 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1473 if (pcists & SMBPCISTS_INTS)
1474 dev_warn(&dev->dev, "An interrupt is pending!\n");
1476 /* Check if interrupts have been disabled */
1477 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1478 if (pcictl & SMBPCICTL_INTDIS) {
1479 dev_info(&dev->dev, "Interrupts are disabled\n");
1480 priv->features &= ~FEATURE_IRQ;
1484 if (priv->features & FEATURE_IRQ) {
1485 init_waitqueue_head(&priv->waitq);
1487 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1489 dev_driver_string(&dev->dev), priv);
1491 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1493 priv->features &= ~FEATURE_IRQ;
1496 dev_info(&dev->dev, "SMBus using %s\n",
1497 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1501 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1502 "SMBus I801 adapter at %04lx", priv->smba);
1503 err = i2c_add_adapter(&priv->adapter);
1505 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1506 i801_acpi_remove(priv);
1510 i801_probe_optional_slaves(priv);
1511 /* We ignore errors - multiplexing is optional */
1514 pci_set_drvdata(dev, priv);
1516 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1517 pm_runtime_use_autosuspend(&dev->dev);
1518 pm_runtime_put_autosuspend(&dev->dev);
1519 pm_runtime_allow(&dev->dev);
1524 static void i801_remove(struct pci_dev *dev)
1526 struct i801_priv *priv = pci_get_drvdata(dev);
1528 pm_runtime_forbid(&dev->dev);
1529 pm_runtime_get_noresume(&dev->dev);
1532 i2c_del_adapter(&priv->adapter);
1533 i801_acpi_remove(priv);
1534 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1536 platform_device_unregister(priv->tco_pdev);
1539 * do not call pci_disable_device(dev) since it can cause hard hangs on
1540 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1545 static int i801_suspend(struct device *dev)
1547 struct pci_dev *pci_dev = to_pci_dev(dev);
1548 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1550 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1554 static int i801_resume(struct device *dev)
1560 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1563 static struct pci_driver i801_driver = {
1564 .name = "i801_smbus",
1565 .id_table = i801_ids,
1566 .probe = i801_probe,
1567 .remove = i801_remove,
1573 static int __init i2c_i801_init(void)
1575 if (dmi_name_in_vendors("FUJITSU"))
1576 input_apanel_init();
1577 return pci_register_driver(&i801_driver);
1580 static void __exit i2c_i801_exit(void)
1582 pci_unregister_driver(&i801_driver);
1585 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1586 MODULE_DESCRIPTION("I801 SMBus driver");
1587 MODULE_LICENSE("GPL");
1589 module_init(i2c_i801_init);
1590 module_exit(i2c_i801_exit);