2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
68 * Features supported by this driver:
72 * Block process call transaction no
73 * I2C block read transaction yes (doesn't use the block buffer)
75 * Interrupt processing yes
77 * See the file Documentation/i2c/busses/i2c-i801 for details.
80 #include <linux/interrupt.h>
81 #include <linux/module.h>
82 #include <linux/pci.h>
83 #include <linux/kernel.h>
84 #include <linux/stddef.h>
85 #include <linux/delay.h>
86 #include <linux/ioport.h>
87 #include <linux/init.h>
88 #include <linux/i2c.h>
89 #include <linux/acpi.h>
91 #include <linux/dmi.h>
92 #include <linux/slab.h>
93 #include <linux/wait.h>
94 #include <linux/err.h>
95 #include <linux/platform_device.h>
96 #include <linux/platform_data/itco_wdt.h>
97 #include <linux/pm_runtime.h>
99 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
101 #include <linux/gpio.h>
102 #include <linux/i2c-mux-gpio.h>
105 /* I801 SMBus address offsets */
106 #define SMBHSTSTS(p) (0 + (p)->smba)
107 #define SMBHSTCNT(p) (2 + (p)->smba)
108 #define SMBHSTCMD(p) (3 + (p)->smba)
109 #define SMBHSTADD(p) (4 + (p)->smba)
110 #define SMBHSTDAT0(p) (5 + (p)->smba)
111 #define SMBHSTDAT1(p) (6 + (p)->smba)
112 #define SMBBLKDAT(p) (7 + (p)->smba)
113 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
114 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
115 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
117 /* PCI Address Constants */
119 #define SMBPCICTL 0x004
120 #define SMBPCISTS 0x006
121 #define SMBHSTCFG 0x040
122 #define TCOBASE 0x050
125 #define ACPIBASE 0x040
126 #define ACPIBASE_SMI_OFF 0x030
127 #define ACPICTRL 0x044
128 #define ACPICTRL_EN 0x080
130 #define SBREG_BAR 0x10
131 #define SBREG_SMBCTRL 0xc6000c
133 /* Host status bits for SMBPCISTS */
134 #define SMBPCISTS_INTS 0x08
136 /* Control bits for SMBPCICTL */
137 #define SMBPCICTL_INTDIS 0x0400
139 /* Host configuration bits for SMBHSTCFG */
140 #define SMBHSTCFG_HST_EN 1
141 #define SMBHSTCFG_SMB_SMI_EN 2
142 #define SMBHSTCFG_I2C_EN 4
144 /* TCO configuration bits for TCOCTL */
145 #define TCOCTL_EN 0x0100
147 /* Auxiliary control register bits, ICH4+ only */
148 #define SMBAUXCTL_CRC 1
149 #define SMBAUXCTL_E32B 2
152 #define MAX_RETRIES 400
154 /* I801 command constants */
155 #define I801_QUICK 0x00
156 #define I801_BYTE 0x04
157 #define I801_BYTE_DATA 0x08
158 #define I801_WORD_DATA 0x0C
159 #define I801_PROC_CALL 0x10 /* unimplemented */
160 #define I801_BLOCK_DATA 0x14
161 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
163 /* I801 Host Control register bits */
164 #define SMBHSTCNT_INTREN 0x01
165 #define SMBHSTCNT_KILL 0x02
166 #define SMBHSTCNT_LAST_BYTE 0x20
167 #define SMBHSTCNT_START 0x40
168 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
170 /* I801 Hosts Status register bits */
171 #define SMBHSTSTS_BYTE_DONE 0x80
172 #define SMBHSTSTS_INUSE_STS 0x40
173 #define SMBHSTSTS_SMBALERT_STS 0x20
174 #define SMBHSTSTS_FAILED 0x10
175 #define SMBHSTSTS_BUS_ERR 0x08
176 #define SMBHSTSTS_DEV_ERR 0x04
177 #define SMBHSTSTS_INTR 0x02
178 #define SMBHSTSTS_HOST_BUSY 0x01
180 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
183 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
186 /* Older devices have their ID defined in <linux/pci_ids.h> */
187 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
188 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
189 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
191 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
194 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
195 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
196 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
197 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
198 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
199 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
200 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
201 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
202 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
203 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
205 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
206 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
207 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
208 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
209 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
210 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
211 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
213 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
215 struct i801_mux_config {
220 unsigned gpios[2]; /* Relative to gpio_chip->base */
225 struct i2c_adapter adapter;
227 unsigned char original_hstcfg;
228 struct pci_dev *pci_dev;
229 unsigned int features;
232 wait_queue_head_t waitq;
235 /* Command state used by isr for byte-by-byte block transactions */
242 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
244 const struct i801_mux_config *mux_drvdata;
245 struct platform_device *mux_pdev;
247 struct platform_device *tco_pdev;
250 #define FEATURE_SMBUS_PEC (1 << 0)
251 #define FEATURE_BLOCK_BUFFER (1 << 1)
252 #define FEATURE_BLOCK_PROC (1 << 2)
253 #define FEATURE_I2C_BLOCK_READ (1 << 3)
254 #define FEATURE_IRQ (1 << 4)
255 /* Not really a feature, but it's convenient to handle it as such */
256 #define FEATURE_IDF (1 << 15)
257 #define FEATURE_TCO (1 << 16)
259 static const char *i801_feature_names[] = {
262 "Block process call",
267 static unsigned int disable_features;
268 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
269 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
270 "\t\t 0x01 disable SMBus PEC\n"
271 "\t\t 0x02 disable the block buffer\n"
272 "\t\t 0x08 disable the I2C block read functionality\n"
273 "\t\t 0x10 don't use interrupts ");
275 /* Make sure the SMBus host is ready to start transmitting.
276 Return 0 if it is, -EBUSY if it is not. */
277 static int i801_check_pre(struct i801_priv *priv)
281 status = inb_p(SMBHSTSTS(priv));
282 if (status & SMBHSTSTS_HOST_BUSY) {
283 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
287 status &= STATUS_FLAGS;
289 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
291 outb_p(status, SMBHSTSTS(priv));
292 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
294 dev_err(&priv->pci_dev->dev,
295 "Failed clearing status flags (%02x)\n",
305 * Convert the status register to an error code, and clear it.
306 * Note that status only contains the bits we want to clear, not the
307 * actual register value.
309 static int i801_check_post(struct i801_priv *priv, int status)
314 * If the SMBus is still busy, we give up
315 * Note: This timeout condition only happens when using polling
316 * transactions. For interrupt operation, NAK/timeout is indicated by
319 if (unlikely(status < 0)) {
320 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
321 /* try to stop the current command */
322 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
323 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
325 usleep_range(1000, 2000);
326 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
329 /* Check if it worked */
330 status = inb_p(SMBHSTSTS(priv));
331 if ((status & SMBHSTSTS_HOST_BUSY) ||
332 !(status & SMBHSTSTS_FAILED))
333 dev_err(&priv->pci_dev->dev,
334 "Failed terminating the transaction\n");
335 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
339 if (status & SMBHSTSTS_FAILED) {
341 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
343 if (status & SMBHSTSTS_DEV_ERR) {
345 dev_dbg(&priv->pci_dev->dev, "No response\n");
347 if (status & SMBHSTSTS_BUS_ERR) {
349 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
352 /* Clear status flags except BYTE_DONE, to be cleared by caller */
353 outb_p(status, SMBHSTSTS(priv));
358 /* Wait for BUSY being cleared and either INTR or an error flag being set */
359 static int i801_wait_intr(struct i801_priv *priv)
364 /* We will always wait for a fraction of a second! */
366 usleep_range(250, 500);
367 status = inb_p(SMBHSTSTS(priv));
368 } while (((status & SMBHSTSTS_HOST_BUSY) ||
369 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
370 (timeout++ < MAX_RETRIES));
372 if (timeout > MAX_RETRIES) {
373 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
376 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
379 /* Wait for either BYTE_DONE or an error flag being set */
380 static int i801_wait_byte_done(struct i801_priv *priv)
385 /* We will always wait for a fraction of a second! */
387 usleep_range(250, 500);
388 status = inb_p(SMBHSTSTS(priv));
389 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
390 (timeout++ < MAX_RETRIES));
392 if (timeout > MAX_RETRIES) {
393 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
396 return status & STATUS_ERROR_FLAGS;
399 static int i801_transaction(struct i801_priv *priv, int xact)
403 const struct i2c_adapter *adap = &priv->adapter;
405 result = i801_check_pre(priv);
409 if (priv->features & FEATURE_IRQ) {
410 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
412 result = wait_event_timeout(priv->waitq,
413 (status = priv->status),
417 dev_warn(&priv->pci_dev->dev,
418 "Timeout waiting for interrupt!\n");
421 return i801_check_post(priv, status);
424 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
425 * SMBSCMD are passed in xact */
426 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
428 status = i801_wait_intr(priv);
429 return i801_check_post(priv, status);
432 static int i801_block_transaction_by_block(struct i801_priv *priv,
433 union i2c_smbus_data *data,
434 char read_write, int hwpec)
439 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
441 /* Use 32-byte buffer to process this transaction */
442 if (read_write == I2C_SMBUS_WRITE) {
443 len = data->block[0];
444 outb_p(len, SMBHSTDAT0(priv));
445 for (i = 0; i < len; i++)
446 outb_p(data->block[i+1], SMBBLKDAT(priv));
449 status = i801_transaction(priv, I801_BLOCK_DATA |
450 (hwpec ? SMBHSTCNT_PEC_EN : 0));
454 if (read_write == I2C_SMBUS_READ) {
455 len = inb_p(SMBHSTDAT0(priv));
456 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
459 data->block[0] = len;
460 for (i = 0; i < len; i++)
461 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
466 static void i801_isr_byte_done(struct i801_priv *priv)
469 /* For SMBus block reads, length is received with first byte */
470 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
471 (priv->count == 0)) {
472 priv->len = inb_p(SMBHSTDAT0(priv));
473 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
474 dev_err(&priv->pci_dev->dev,
475 "Illegal SMBus block read size %d\n",
478 priv->len = I2C_SMBUS_BLOCK_MAX;
480 dev_dbg(&priv->pci_dev->dev,
481 "SMBus block read size is %d\n",
484 priv->data[-1] = priv->len;
488 if (priv->count < priv->len)
489 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
491 dev_dbg(&priv->pci_dev->dev,
492 "Discarding extra byte on block read\n");
494 /* Set LAST_BYTE for last byte of read transaction */
495 if (priv->count == priv->len - 1)
496 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
498 } else if (priv->count < priv->len - 1) {
499 /* Write next byte, except for IRQ after last byte */
500 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
503 /* Clear BYTE_DONE to continue with next byte */
504 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
508 * There are two kinds of interrupts:
510 * 1) i801 signals transaction completion with one of these interrupts:
512 * DEV_ERR - Invalid command, NAK or communication timeout
513 * BUS_ERR - SMI# transaction collision
514 * FAILED - transaction was canceled due to a KILL request
515 * When any of these occur, update ->status and wake up the waitq.
516 * ->status must be cleared before kicking off the next transaction.
518 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
519 * occurs for each byte of a byte-by-byte to prepare the next byte.
521 static irqreturn_t i801_isr(int irq, void *dev_id)
523 struct i801_priv *priv = dev_id;
527 /* Confirm this is our interrupt */
528 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
529 if (!(pcists & SMBPCISTS_INTS))
532 status = inb_p(SMBHSTSTS(priv));
533 if (status & SMBHSTSTS_BYTE_DONE)
534 i801_isr_byte_done(priv);
537 * Clear irq sources and report transaction result.
538 * ->status must be cleared before the next transaction is started.
540 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
542 outb_p(status, SMBHSTSTS(priv));
543 priv->status |= status;
544 wake_up(&priv->waitq);
551 * For "byte-by-byte" block transactions:
552 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
553 * I2C read uses cmd=I801_I2C_BLOCK_DATA
555 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
556 union i2c_smbus_data *data,
557 char read_write, int command,
564 const struct i2c_adapter *adap = &priv->adapter;
566 result = i801_check_pre(priv);
570 len = data->block[0];
572 if (read_write == I2C_SMBUS_WRITE) {
573 outb_p(len, SMBHSTDAT0(priv));
574 outb_p(data->block[1], SMBBLKDAT(priv));
577 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
578 read_write == I2C_SMBUS_READ)
579 smbcmd = I801_I2C_BLOCK_DATA;
581 smbcmd = I801_BLOCK_DATA;
583 if (priv->features & FEATURE_IRQ) {
584 priv->is_read = (read_write == I2C_SMBUS_READ);
585 if (len == 1 && priv->is_read)
586 smbcmd |= SMBHSTCNT_LAST_BYTE;
587 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
590 priv->data = &data->block[1];
592 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
593 result = wait_event_timeout(priv->waitq,
594 (status = priv->status),
598 dev_warn(&priv->pci_dev->dev,
599 "Timeout waiting for interrupt!\n");
602 return i801_check_post(priv, status);
605 for (i = 1; i <= len; i++) {
606 if (i == len && read_write == I2C_SMBUS_READ)
607 smbcmd |= SMBHSTCNT_LAST_BYTE;
608 outb_p(smbcmd, SMBHSTCNT(priv));
611 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
614 status = i801_wait_byte_done(priv);
618 if (i == 1 && read_write == I2C_SMBUS_READ
619 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
620 len = inb_p(SMBHSTDAT0(priv));
621 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
622 dev_err(&priv->pci_dev->dev,
623 "Illegal SMBus block read size %d\n",
626 while (inb_p(SMBHSTSTS(priv)) &
628 outb_p(SMBHSTSTS_BYTE_DONE,
630 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
633 data->block[0] = len;
636 /* Retrieve/store value in SMBBLKDAT */
637 if (read_write == I2C_SMBUS_READ)
638 data->block[i] = inb_p(SMBBLKDAT(priv));
639 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
640 outb_p(data->block[i+1], SMBBLKDAT(priv));
642 /* signals SMBBLKDAT ready */
643 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
646 status = i801_wait_intr(priv);
648 return i801_check_post(priv, status);
651 static int i801_set_block_buffer_mode(struct i801_priv *priv)
653 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
654 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
659 /* Block transaction function */
660 static int i801_block_transaction(struct i801_priv *priv,
661 union i2c_smbus_data *data, char read_write,
662 int command, int hwpec)
667 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
668 if (read_write == I2C_SMBUS_WRITE) {
669 /* set I2C_EN bit in configuration register */
670 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
671 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
672 hostc | SMBHSTCFG_I2C_EN);
673 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
674 dev_err(&priv->pci_dev->dev,
675 "I2C block read is unsupported!\n");
680 if (read_write == I2C_SMBUS_WRITE
681 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
682 if (data->block[0] < 1)
684 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
685 data->block[0] = I2C_SMBUS_BLOCK_MAX;
687 data->block[0] = 32; /* max for SMBus block reads */
690 /* Experience has shown that the block buffer can only be used for
691 SMBus (not I2C) block transactions, even though the datasheet
692 doesn't mention this limitation. */
693 if ((priv->features & FEATURE_BLOCK_BUFFER)
694 && command != I2C_SMBUS_I2C_BLOCK_DATA
695 && i801_set_block_buffer_mode(priv) == 0)
696 result = i801_block_transaction_by_block(priv, data,
699 result = i801_block_transaction_byte_by_byte(priv, data,
703 if (command == I2C_SMBUS_I2C_BLOCK_DATA
704 && read_write == I2C_SMBUS_WRITE) {
705 /* restore saved configuration register value */
706 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
711 /* Return negative errno on error. */
712 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
713 unsigned short flags, char read_write, u8 command,
714 int size, union i2c_smbus_data *data)
718 int ret = 0, xact = 0;
719 struct i801_priv *priv = i2c_get_adapdata(adap);
721 pm_runtime_get_sync(&priv->pci_dev->dev);
723 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
724 && size != I2C_SMBUS_QUICK
725 && size != I2C_SMBUS_I2C_BLOCK_DATA;
728 case I2C_SMBUS_QUICK:
729 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
734 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
736 if (read_write == I2C_SMBUS_WRITE)
737 outb_p(command, SMBHSTCMD(priv));
740 case I2C_SMBUS_BYTE_DATA:
741 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
743 outb_p(command, SMBHSTCMD(priv));
744 if (read_write == I2C_SMBUS_WRITE)
745 outb_p(data->byte, SMBHSTDAT0(priv));
746 xact = I801_BYTE_DATA;
748 case I2C_SMBUS_WORD_DATA:
749 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
751 outb_p(command, SMBHSTCMD(priv));
752 if (read_write == I2C_SMBUS_WRITE) {
753 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
754 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
756 xact = I801_WORD_DATA;
758 case I2C_SMBUS_BLOCK_DATA:
759 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
761 outb_p(command, SMBHSTCMD(priv));
764 case I2C_SMBUS_I2C_BLOCK_DATA:
765 /* NB: page 240 of ICH5 datasheet shows that the R/#W
766 * bit should be cleared here, even when reading */
767 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
768 if (read_write == I2C_SMBUS_READ) {
769 /* NB: page 240 of ICH5 datasheet also shows
770 * that DATA1 is the cmd field when reading */
771 outb_p(command, SMBHSTDAT1(priv));
773 outb_p(command, SMBHSTCMD(priv));
777 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
783 if (hwpec) /* enable/disable hardware PEC */
784 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
786 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
790 ret = i801_block_transaction(priv, data, read_write, size,
793 ret = i801_transaction(priv, xact);
795 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
796 time, so we forcibly disable it after every transaction. Turn off
797 E32B for the same reason. */
799 outb_p(inb_p(SMBAUXCTL(priv)) &
800 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
806 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
809 switch (xact & 0x7f) {
810 case I801_BYTE: /* Result put in SMBHSTDAT0 */
812 data->byte = inb_p(SMBHSTDAT0(priv));
815 data->word = inb_p(SMBHSTDAT0(priv)) +
816 (inb_p(SMBHSTDAT1(priv)) << 8);
821 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
822 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
827 static u32 i801_func(struct i2c_adapter *adapter)
829 struct i801_priv *priv = i2c_get_adapdata(adapter);
831 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
832 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
833 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
834 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
835 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
836 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
839 static const struct i2c_algorithm smbus_algorithm = {
840 .smbus_xfer = i801_access,
841 .functionality = i801_func,
844 static const struct pci_device_id i801_ids[] = {
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
853 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
854 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
868 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
869 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
870 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
871 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
872 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
873 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
874 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
875 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
876 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
878 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
879 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
880 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
881 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
882 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
883 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
884 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
885 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
889 MODULE_DEVICE_TABLE(pci, i801_ids);
891 #if defined CONFIG_X86 && defined CONFIG_DMI
892 static unsigned char apanel_addr;
894 /* Scan the system ROM for the signature "FJKEYINF" */
895 static __init const void __iomem *bios_signature(const void __iomem *bios)
898 const unsigned char signature[] = "FJKEYINF";
900 for (offset = 0; offset < 0x10000; offset += 0x10) {
901 if (check_signature(bios + offset, signature,
902 sizeof(signature)-1))
903 return bios + offset;
908 static void __init input_apanel_init(void)
911 const void __iomem *p;
913 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
914 p = bios_signature(bios);
916 /* just use the first address */
917 apanel_addr = readb(p + 8 + 3) >> 1;
922 struct dmi_onboard_device_info {
925 unsigned short i2c_addr;
926 const char *i2c_type;
929 static const struct dmi_onboard_device_info dmi_devices[] = {
930 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
931 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
932 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
935 static void dmi_check_onboard_device(u8 type, const char *name,
936 struct i2c_adapter *adap)
939 struct i2c_board_info info;
941 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
942 /* & ~0x80, ignore enabled/disabled bit */
943 if ((type & ~0x80) != dmi_devices[i].type)
945 if (strcasecmp(name, dmi_devices[i].name))
948 memset(&info, 0, sizeof(struct i2c_board_info));
949 info.addr = dmi_devices[i].i2c_addr;
950 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
951 i2c_new_device(adap, &info);
956 /* We use our own function to check for onboard devices instead of
957 dmi_find_device() as some buggy BIOS's have the devices we are interested
958 in marked as disabled */
959 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
966 count = (dm->length - sizeof(struct dmi_header)) / 2;
967 for (i = 0; i < count; i++) {
968 const u8 *d = (char *)(dm + 1) + (i * 2);
969 const char *name = ((char *) dm) + dm->length;
976 while (s > 0 && name[0]) {
977 name += strlen(name) + 1;
980 if (name[0] == 0) /* Bogus string reference */
983 dmi_check_onboard_device(type, name, adap);
987 /* Register optional slaves */
988 static void i801_probe_optional_slaves(struct i801_priv *priv)
990 /* Only register slaves on main SMBus channel */
991 if (priv->features & FEATURE_IDF)
995 struct i2c_board_info info;
997 memset(&info, 0, sizeof(struct i2c_board_info));
998 info.addr = apanel_addr;
999 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1000 i2c_new_device(&priv->adapter, &info);
1003 if (dmi_name_in_vendors("FUJITSU"))
1004 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1007 static void __init input_apanel_init(void) {}
1008 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1009 #endif /* CONFIG_X86 && CONFIG_DMI */
1011 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1013 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1014 .gpio_chip = "gpio_ich",
1015 .values = { 0x02, 0x03 },
1017 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1018 .gpios = { 52, 53 },
1022 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1023 .gpio_chip = "gpio_ich",
1024 .values = { 0x02, 0x03, 0x01 },
1026 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1027 .gpios = { 52, 53 },
1031 static const struct dmi_system_id mux_dmi_table[] = {
1034 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1035 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1037 .driver_data = &i801_mux_config_asus_z8_d12,
1041 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1042 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1044 .driver_data = &i801_mux_config_asus_z8_d12,
1048 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1049 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1051 .driver_data = &i801_mux_config_asus_z8_d12,
1055 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1056 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1058 .driver_data = &i801_mux_config_asus_z8_d12,
1062 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1063 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1065 .driver_data = &i801_mux_config_asus_z8_d12,
1069 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1070 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1072 .driver_data = &i801_mux_config_asus_z8_d12,
1076 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1077 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1079 .driver_data = &i801_mux_config_asus_z8_d18,
1083 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1084 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1086 .driver_data = &i801_mux_config_asus_z8_d18,
1090 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1091 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1093 .driver_data = &i801_mux_config_asus_z8_d12,
1098 /* Setup multiplexing if needed */
1099 static int i801_add_mux(struct i801_priv *priv)
1101 struct device *dev = &priv->adapter.dev;
1102 const struct i801_mux_config *mux_config;
1103 struct i2c_mux_gpio_platform_data gpio_data;
1106 if (!priv->mux_drvdata)
1108 mux_config = priv->mux_drvdata;
1110 /* Prepare the platform data */
1111 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1112 gpio_data.parent = priv->adapter.nr;
1113 gpio_data.values = mux_config->values;
1114 gpio_data.n_values = mux_config->n_values;
1115 gpio_data.classes = mux_config->classes;
1116 gpio_data.gpio_chip = mux_config->gpio_chip;
1117 gpio_data.gpios = mux_config->gpios;
1118 gpio_data.n_gpios = mux_config->n_gpios;
1119 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1121 /* Register the mux device */
1122 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1123 PLATFORM_DEVID_AUTO, &gpio_data,
1124 sizeof(struct i2c_mux_gpio_platform_data));
1125 if (IS_ERR(priv->mux_pdev)) {
1126 err = PTR_ERR(priv->mux_pdev);
1127 priv->mux_pdev = NULL;
1128 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1135 static void i801_del_mux(struct i801_priv *priv)
1138 platform_device_unregister(priv->mux_pdev);
1141 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1143 const struct dmi_system_id *id;
1144 const struct i801_mux_config *mux_config;
1145 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1148 id = dmi_first_match(mux_dmi_table);
1150 /* Remove branch classes from trunk */
1151 mux_config = id->driver_data;
1152 for (i = 0; i < mux_config->n_values; i++)
1153 class &= ~mux_config->classes[i];
1155 /* Remember for later */
1156 priv->mux_drvdata = mux_config;
1162 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1163 static inline void i801_del_mux(struct i801_priv *priv) { }
1165 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1167 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1171 static const struct itco_wdt_platform_data tco_platform_data = {
1172 .name = "Intel PCH",
1176 static DEFINE_SPINLOCK(p2sb_spinlock);
1178 static void i801_add_tco(struct i801_priv *priv)
1180 struct pci_dev *pci_dev = priv->pci_dev;
1181 struct resource tco_res[3], *res;
1182 struct platform_device *pdev;
1184 u32 tco_base, tco_ctl;
1185 u32 base_addr, ctrl_val;
1188 if (!(priv->features & FEATURE_TCO))
1191 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1192 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1193 if (!(tco_ctl & TCOCTL_EN))
1196 memset(tco_res, 0, sizeof(tco_res));
1198 res = &tco_res[ICH_RES_IO_TCO];
1199 res->start = tco_base & ~1;
1200 res->end = res->start + 32 - 1;
1201 res->flags = IORESOURCE_IO;
1204 * Power Management registers.
1206 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1207 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1209 res = &tco_res[ICH_RES_IO_SMI];
1210 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1211 res->end = res->start + 3;
1212 res->flags = IORESOURCE_IO;
1215 * Enable the ACPI I/O space.
1217 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1218 ctrl_val |= ACPICTRL_EN;
1219 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1222 * We must access the NO_REBOOT bit over the Primary to Sideband
1223 * bridge (P2SB). The BIOS prevents the P2SB device from being
1224 * enumerated by the PCI subsystem, so we need to unhide/hide it
1225 * to lookup the P2SB BAR.
1227 spin_lock(&p2sb_spinlock);
1229 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1231 /* Unhide the P2SB device */
1232 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1234 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1235 base64_addr = base_addr & 0xfffffff0;
1237 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1238 base64_addr |= (u64)base_addr << 32;
1240 /* Hide the P2SB device */
1241 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1242 spin_unlock(&p2sb_spinlock);
1244 res = &tco_res[ICH_RES_MEM_OFF];
1245 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1246 res->end = res->start + 3;
1247 res->flags = IORESOURCE_MEM;
1249 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1250 tco_res, 3, &tco_platform_data,
1251 sizeof(tco_platform_data));
1253 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1257 priv->tco_pdev = pdev;
1260 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1264 struct i801_priv *priv;
1266 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1270 i2c_set_adapdata(&priv->adapter, priv);
1271 priv->adapter.owner = THIS_MODULE;
1272 priv->adapter.class = i801_get_adapter_class(priv);
1273 priv->adapter.algo = &smbus_algorithm;
1274 priv->adapter.dev.parent = &dev->dev;
1275 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1276 priv->adapter.retries = 3;
1278 priv->pci_dev = dev;
1279 switch (dev->device) {
1280 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1281 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1282 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1283 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1284 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1285 priv->features |= FEATURE_I2C_BLOCK_READ;
1286 priv->features |= FEATURE_IRQ;
1287 priv->features |= FEATURE_SMBUS_PEC;
1288 priv->features |= FEATURE_BLOCK_BUFFER;
1289 priv->features |= FEATURE_TCO;
1292 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1293 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1294 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1295 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1296 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1297 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1298 priv->features |= FEATURE_IDF;
1301 priv->features |= FEATURE_I2C_BLOCK_READ;
1302 priv->features |= FEATURE_IRQ;
1304 case PCI_DEVICE_ID_INTEL_82801DB_3:
1305 priv->features |= FEATURE_SMBUS_PEC;
1306 priv->features |= FEATURE_BLOCK_BUFFER;
1308 case PCI_DEVICE_ID_INTEL_82801CA_3:
1309 case PCI_DEVICE_ID_INTEL_82801BA_2:
1310 case PCI_DEVICE_ID_INTEL_82801AB_3:
1311 case PCI_DEVICE_ID_INTEL_82801AA_3:
1315 /* Disable features on user request */
1316 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1317 if (priv->features & disable_features & (1 << i))
1318 dev_notice(&dev->dev, "%s disabled by user\n",
1319 i801_feature_names[i]);
1321 priv->features &= ~disable_features;
1323 err = pcim_enable_device(dev);
1325 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1329 pcim_pin_device(dev);
1331 /* Determine the address of the SMBus area */
1332 priv->smba = pci_resource_start(dev, SMBBAR);
1335 "SMBus base address uninitialized, upgrade BIOS\n");
1339 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1344 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1345 dev_driver_string(&dev->dev));
1348 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1350 (unsigned long long)pci_resource_end(dev, SMBBAR));
1354 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1355 priv->original_hstcfg = temp;
1356 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1357 if (!(temp & SMBHSTCFG_HST_EN)) {
1358 dev_info(&dev->dev, "Enabling SMBus device\n");
1359 temp |= SMBHSTCFG_HST_EN;
1361 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1363 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1364 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1365 /* Disable SMBus interrupt feature if SMBus using SMI# */
1366 priv->features &= ~FEATURE_IRQ;
1369 /* Clear special mode bits */
1370 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1371 outb_p(inb_p(SMBAUXCTL(priv)) &
1372 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1374 /* Default timeout in interrupt mode: 200 ms */
1375 priv->adapter.timeout = HZ / 5;
1377 if (priv->features & FEATURE_IRQ) {
1380 /* Complain if an interrupt is already pending */
1381 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1382 if (pcists & SMBPCISTS_INTS)
1383 dev_warn(&dev->dev, "An interrupt is pending!\n");
1385 /* Check if interrupts have been disabled */
1386 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1387 if (pcictl & SMBPCICTL_INTDIS) {
1388 dev_info(&dev->dev, "Interrupts are disabled\n");
1389 priv->features &= ~FEATURE_IRQ;
1393 if (priv->features & FEATURE_IRQ) {
1394 init_waitqueue_head(&priv->waitq);
1396 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1398 dev_driver_string(&dev->dev), priv);
1400 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1402 priv->features &= ~FEATURE_IRQ;
1405 dev_info(&dev->dev, "SMBus using %s\n",
1406 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1410 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1411 "SMBus I801 adapter at %04lx", priv->smba);
1412 err = i2c_add_adapter(&priv->adapter);
1414 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1418 i801_probe_optional_slaves(priv);
1419 /* We ignore errors - multiplexing is optional */
1422 pci_set_drvdata(dev, priv);
1424 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1425 pm_runtime_use_autosuspend(&dev->dev);
1426 pm_runtime_put_autosuspend(&dev->dev);
1427 pm_runtime_allow(&dev->dev);
1432 static void i801_remove(struct pci_dev *dev)
1434 struct i801_priv *priv = pci_get_drvdata(dev);
1436 pm_runtime_forbid(&dev->dev);
1437 pm_runtime_get_noresume(&dev->dev);
1440 i2c_del_adapter(&priv->adapter);
1441 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1443 platform_device_unregister(priv->tco_pdev);
1446 * do not call pci_disable_device(dev) since it can cause hard hangs on
1447 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1452 static int i801_suspend(struct device *dev)
1454 struct pci_dev *pci_dev = to_pci_dev(dev);
1455 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1457 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1461 static int i801_resume(struct device *dev)
1467 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1470 static struct pci_driver i801_driver = {
1471 .name = "i801_smbus",
1472 .id_table = i801_ids,
1473 .probe = i801_probe,
1474 .remove = i801_remove,
1480 static int __init i2c_i801_init(void)
1482 if (dmi_name_in_vendors("FUJITSU"))
1483 input_apanel_init();
1484 return pci_register_driver(&i801_driver);
1487 static void __exit i2c_i801_exit(void)
1489 pci_unregister_driver(&i801_driver);
1492 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1493 MODULE_DESCRIPTION("I801 SMBus driver");
1494 MODULE_LICENSE("GPL");
1496 module_init(i2c_i801_init);
1497 module_exit(i2c_i801_exit);