drivers/i2c/busses/i2c-nvidia-gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nvidia GPU I2C controller Driver
   4  *
   5  * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
   6  * Author: Ajay Gupta <ajayg@nvidia.com>
   7  */
   8 #include <linux/delay.h>
   9 #include <linux/i2c.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm.h>
  15 #include <linux/pm_runtime.h>
  16
  17 #include <asm/unaligned.h>
  18
  19 /* I2C definitions */
  20 #define I2C_MST_CNTL                            0x00
  21 #define I2C_MST_CNTL_GEN_START                  BIT(0)
  22 #define I2C_MST_CNTL_GEN_STOP                   BIT(1)
  23 #define I2C_MST_CNTL_CMD_READ                   (1 << 2)
  24 #define I2C_MST_CNTL_CMD_WRITE                  (2 << 2)
  25 #define I2C_MST_CNTL_BURST_SIZE_SHIFT           6
  26 #define I2C_MST_CNTL_GEN_NACK                   BIT(28)
  27 #define I2C_MST_CNTL_STATUS                     GENMASK(30, 29)
  28 #define I2C_MST_CNTL_STATUS_OKAY                (0 << 29)
  29 #define I2C_MST_CNTL_STATUS_NO_ACK              (1 << 29)
  30 #define I2C_MST_CNTL_STATUS_TIMEOUT             (2 << 29)
  31 #define I2C_MST_CNTL_STATUS_BUS_BUSY            (3 << 29)
  32 #define I2C_MST_CNTL_CYCLE_TRIGGER              BIT(31)
  33
  34 #define I2C_MST_ADDR                            0x04
  35
  36 #define I2C_MST_I2C0_TIMING                             0x08
  37 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ           0x10e
  38 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT             16
  39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX         255
  40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK               BIT(24)
  41
  42 #define I2C_MST_DATA                                    0x0c
  43
  44 #define I2C_MST_HYBRID_PADCTL                           0x20
  45 #define I2C_MST_HYBRID_PADCTL_MODE_I2C                  BIT(0)
  46 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV         BIT(14)
  47 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV         BIT(15)
  48
  49 struct gpu_i2c_dev {
  50         struct device *dev;
  51         void __iomem *regs;
  52         struct i2c_adapter adapter;
  53         struct i2c_board_info *gpu_ccgx_ucsi;
  54 };
  55
  56 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
  57 {
  58         u32 val;
  59
  60         /* enable I2C */
  61         val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
  62         val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
  63                 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
  64                 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
  65         writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
  66
  67         /* enable 100KHZ mode */
  68         val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
  69         val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
  70             << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
  71         val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
  72         writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
  73 }
  74
  75 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
  76 {
  77         unsigned long target = jiffies + msecs_to_jiffies(1000);
  78         u32 val;
  79
  80         do {
  81                 val = readl(i2cd->regs + I2C_MST_CNTL);
  82                 if (!(val & I2C_MST_CNTL_CYCLE_TRIGGER))
  83                         break;
  84                 if ((val & I2C_MST_CNTL_STATUS) !=
  85                                 I2C_MST_CNTL_STATUS_BUS_BUSY)
  86                         break;
  87                 usleep_range(500, 600);
  88         } while (time_is_after_jiffies(target));
  89
  90         if (time_is_before_jiffies(target)) {
  91                 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
  92                 return -ETIMEDOUT;
  93         }
  94
  95         val = readl(i2cd->regs + I2C_MST_CNTL);
  96         switch (val & I2C_MST_CNTL_STATUS) {
  97         case I2C_MST_CNTL_STATUS_OKAY:
  98                 return 0;
  99         case I2C_MST_CNTL_STATUS_NO_ACK:
 100                 return -ENXIO;
 101         case I2C_MST_CNTL_STATUS_TIMEOUT:
 102                 return -ETIMEDOUT;
 103         default:
 104                 return 0;
 105         }
 106 }
 107
 108 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
 109 {
 110         int status;
 111         u32 val;
 112
 113         val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
 114                 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
 115                 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
 116         writel(val, i2cd->regs + I2C_MST_CNTL);
 117
 118         status = gpu_i2c_check_status(i2cd);
 119         if (status < 0)
 120                 return status;
 121
 122         val = readl(i2cd->regs + I2C_MST_DATA);
 123         switch (len) {
 124         case 1:
 125                 data[0] = val;
 126                 break;
 127         case 2:
 128                 put_unaligned_be16(val, data);
 129                 break;
 130         case 3:
 131                 put_unaligned_be16(val >> 8, data);
 132                 data[2] = val;
 133                 break;
 134         case 4:
 135                 put_unaligned_be32(val, data);
 136                 break;
 137         default:
 138                 break;
 139         }
 140         return status;
 141 }
 142
 143 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
 144 {
 145         writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
 146         return gpu_i2c_check_status(i2cd);
 147 }
 148
 149 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
 150 {
 151         writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
 152         return gpu_i2c_check_status(i2cd);
 153 }
 154
 155 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
 156 {
 157         u32 val;
 158
 159         writel(data, i2cd->regs + I2C_MST_DATA);
 160
 161         val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
 162         writel(val, i2cd->regs + I2C_MST_CNTL);
 163
 164         return gpu_i2c_check_status(i2cd);
 165 }
 166
 167 static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
 168                                struct i2c_msg *msgs, int num)
 169 {
 170         struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
 171         int status, status2;
 172         bool send_stop = true;
 173         int i, j;
 174
 175         /*
 176          * The controller supports maximum 4 byte read due to known
 177          * limitation of sending STOP after every read.
 178          */
 179         pm_runtime_get_sync(i2cd->dev);
 180         for (i = 0; i < num; i++) {
 181                 if (msgs[i].flags & I2C_M_RD) {
 182                         /* program client address before starting read */
 183                         writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
 184                         /* gpu_i2c_read has implicit start */
 185                         status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
 186                         if (status < 0)
 187                                 goto exit;
 188                 } else {
 189                         u8 addr = i2c_8bit_addr_from_msg(msgs + i);
 190
 191                         status = gpu_i2c_start(i2cd);
 192                         if (status < 0) {
 193                                 if (i == 0)
 194                                         send_stop = false;
 195                                 goto exit;
 196                         }
 197
 198                         status = gpu_i2c_write(i2cd, addr);
 199                         if (status < 0)
 200                                 goto exit;
 201
 202                         for (j = 0; j < msgs[i].len; j++) {
 203                                 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
 204                                 if (status < 0)
 205                                         goto exit;
 206                         }
 207                 }
 208         }
 209         send_stop = false;
 210         status = gpu_i2c_stop(i2cd);
 211         if (status < 0)
 212                 goto exit;
 213
 214         status = i;
 215 exit:
 216         if (send_stop) {
 217                 status2 = gpu_i2c_stop(i2cd);
 218                 if (status2 < 0)
 219                         dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
 220         }
 221         pm_runtime_mark_last_busy(i2cd->dev);
 222         pm_runtime_put_autosuspend(i2cd->dev);
 223         return status;
 224 }
 225
 226 static const struct i2c_adapter_quirks gpu_i2c_quirks = {
 227         .max_read_len = 4,
 228         .max_comb_2nd_msg_len = 4,
 229         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 230 };
 231
 232 static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
 233 {
 234         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 235 }
 236
 237 static const struct i2c_algorithm gpu_i2c_algorithm = {
 238         .master_xfer    = gpu_i2c_master_xfer,
 239         .functionality  = gpu_i2c_functionality,
 240 };
 241
 242 /*
 243  * This driver is for Nvidia GPU cards with USB Type-C interface.
 244  * We want to identify the cards using vendor ID and class code only
 245  * to avoid dependency of adding product id for any new card which
 246  * requires this driver.
 247  * Currently there is no class code defined for UCSI device over PCI
 248  * so using UNKNOWN class for now and it will be updated when UCSI
 249  * over PCI gets a class code.
 250  * There is no other NVIDIA cards with UNKNOWN class code. Even if the
 251  * driver gets loaded for an undesired card then eventually i2c_read()
 252  * (initiated from UCSI i2c_client) will timeout or UCSI commands will
 253  * timeout.
 254  */
 255 #define PCI_CLASS_SERIAL_UNKNOWN        0x0c80
 256 static const struct pci_device_id gpu_i2c_ids[] = {
 257         { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 258                 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
 259         { }
 260 };
 261 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
 262
 263 static const struct property_entry ccgx_props[] = {
 264         /* Use FW built for NVIDIA (nv) only */
 265         PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
 266         { }
 267 };
 268
 269 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
 270 {
 271         struct i2c_client *ccgx_client;
 272
 273         i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
 274                                            sizeof(*i2cd->gpu_ccgx_ucsi),
 275                                            GFP_KERNEL);
 276         if (!i2cd->gpu_ccgx_ucsi)
 277                 return -ENOMEM;
 278
 279         strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
 280                 sizeof(i2cd->gpu_ccgx_ucsi->type));
 281         i2cd->gpu_ccgx_ucsi->addr = 0x8;
 282         i2cd->gpu_ccgx_ucsi->irq = irq;
 283         i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
 284         ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
 285         if (!ccgx_client)
 286                 return -ENODEV;
 287
 288         return 0;
 289 }
 290
 291 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 292 {
 293         struct gpu_i2c_dev *i2cd;
 294         int status;
 295
 296         i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
 297         if (!i2cd)
 298                 return -ENOMEM;
 299
 300         i2cd->dev = &pdev->dev;
 301         dev_set_drvdata(&pdev->dev, i2cd);
 302
 303         status = pcim_enable_device(pdev);
 304         if (status < 0) {
 305                 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
 306                 return status;
 307         }
 308
 309         pci_set_master(pdev);
 310
 311         i2cd->regs = pcim_iomap(pdev, 0, 0);
 312         if (!i2cd->regs) {
 313                 dev_err(&pdev->dev, "pcim_iomap failed\n");
 314                 return -ENOMEM;
 315         }
 316
 317         status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
 318         if (status < 0) {
 319                 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
 320                 return status;
 321         }
 322
 323         gpu_enable_i2c_bus(i2cd);
 324
 325         i2c_set_adapdata(&i2cd->adapter, i2cd);
 326         i2cd->adapter.owner = THIS_MODULE;
 327         strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
 328                 sizeof(i2cd->adapter.name));
 329         i2cd->adapter.algo = &gpu_i2c_algorithm;
 330         i2cd->adapter.quirks = &gpu_i2c_quirks;
 331         i2cd->adapter.dev.parent = &pdev->dev;
 332         status = i2c_add_adapter(&i2cd->adapter);
 333         if (status < 0)
 334                 goto free_irq_vectors;
 335
 336         status = gpu_populate_client(i2cd, pdev->irq);
 337         if (status < 0) {
 338                 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
 339                 goto del_adapter;
 340         }
 341
 342         pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
 343         pm_runtime_use_autosuspend(&pdev->dev);
 344         pm_runtime_put_autosuspend(&pdev->dev);
 345         pm_runtime_allow(&pdev->dev);
 346
 347         return 0;
 348
 349 del_adapter:
 350         i2c_del_adapter(&i2cd->adapter);
 351 free_irq_vectors:
 352         pci_free_irq_vectors(pdev);
 353         return status;
 354 }
 355
 356 static void gpu_i2c_remove(struct pci_dev *pdev)
 357 {
 358         struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
 359
 360         pm_runtime_get_noresume(i2cd->dev);
 361         i2c_del_adapter(&i2cd->adapter);
 362         pci_free_irq_vectors(pdev);
 363 }
 364
 365 /*
 366  * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work
 367  * correctly. Without it, lspci shows runtime pm status as "D0" for the card.
 368  * Documentation/power/pci.txt also insists for driver to provide this.
 369  */
 370 static __maybe_unused int gpu_i2c_suspend(struct device *dev)
 371 {
 372         return 0;
 373 }
 374
 375 static __maybe_unused int gpu_i2c_resume(struct device *dev)
 376 {
 377         struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
 378
 379         gpu_enable_i2c_bus(i2cd);
 380         return 0;
 381 }
 382
 383 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
 384                             NULL);
 385
 386 static struct pci_driver gpu_i2c_driver = {
 387         .name           = "nvidia-gpu",
 388         .id_table       = gpu_i2c_ids,
 389         .probe          = gpu_i2c_probe,
 390         .remove         = gpu_i2c_remove,
 391         .driver         = {
 392                 .pm     = &gpu_i2c_driver_pm,
 393         },
 394 };
 395
 396 module_pci_driver(gpu_i2c_driver);
 397
 398 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
 399 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
 400 MODULE_LICENSE("GPL v2");