1 // SPDX-License-Identifier: GPL-2.0
3 * Nvidia GPU I2C controller Driver
5 * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
8 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
17 #include <asm/unaligned.h>
20 #define I2C_MST_CNTL 0x00
21 #define I2C_MST_CNTL_GEN_START BIT(0)
22 #define I2C_MST_CNTL_GEN_STOP BIT(1)
23 #define I2C_MST_CNTL_CMD_READ (1 << 2)
24 #define I2C_MST_CNTL_CMD_WRITE (2 << 2)
25 #define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
26 #define I2C_MST_CNTL_GEN_NACK BIT(28)
27 #define I2C_MST_CNTL_STATUS GENMASK(30, 29)
28 #define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
29 #define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
30 #define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
31 #define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
32 #define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
34 #define I2C_MST_ADDR 0x04
36 #define I2C_MST_I2C0_TIMING 0x08
37 #define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
38 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
39 #define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
40 #define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
42 #define I2C_MST_DATA 0x0c
44 #define I2C_MST_HYBRID_PADCTL 0x20
45 #define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
46 #define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
47 #define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
52 struct i2c_adapter adapter;
53 struct i2c_board_info *gpu_ccgx_ucsi;
56 static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
61 val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
62 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
63 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
64 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
65 writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
67 /* enable 100KHZ mode */
68 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
69 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
70 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
71 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
72 writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
75 static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
77 unsigned long target = jiffies + msecs_to_jiffies(1000);
81 val = readl(i2cd->regs + I2C_MST_CNTL);
82 if (!(val & I2C_MST_CNTL_CYCLE_TRIGGER))
84 if ((val & I2C_MST_CNTL_STATUS) !=
85 I2C_MST_CNTL_STATUS_BUS_BUSY)
87 usleep_range(500, 600);
88 } while (time_is_after_jiffies(target));
90 if (time_is_before_jiffies(target)) {
91 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
95 val = readl(i2cd->regs + I2C_MST_CNTL);
96 switch (val & I2C_MST_CNTL_STATUS) {
97 case I2C_MST_CNTL_STATUS_OKAY:
99 case I2C_MST_CNTL_STATUS_NO_ACK:
101 case I2C_MST_CNTL_STATUS_TIMEOUT:
108 static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
113 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
114 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
115 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
116 writel(val, i2cd->regs + I2C_MST_CNTL);
118 status = gpu_i2c_check_status(i2cd);
122 val = readl(i2cd->regs + I2C_MST_DATA);
128 put_unaligned_be16(val, data);
131 put_unaligned_be16(val >> 8, data);
135 put_unaligned_be32(val, data);
143 static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
145 writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
146 return gpu_i2c_check_status(i2cd);
149 static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
151 writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
152 return gpu_i2c_check_status(i2cd);
155 static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
159 writel(data, i2cd->regs + I2C_MST_DATA);
161 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
162 writel(val, i2cd->regs + I2C_MST_CNTL);
164 return gpu_i2c_check_status(i2cd);
167 static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
168 struct i2c_msg *msgs, int num)
170 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
175 * The controller supports maximum 4 byte read due to known
176 * limitation of sending STOP after every read.
178 for (i = 0; i < num; i++) {
179 if (msgs[i].flags & I2C_M_RD) {
180 /* program client address before starting read */
181 writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
182 /* gpu_i2c_read has implicit start */
183 status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
187 u8 addr = i2c_8bit_addr_from_msg(msgs + i);
189 status = gpu_i2c_start(i2cd);
196 status = gpu_i2c_write(i2cd, addr);
200 for (j = 0; j < msgs[i].len; j++) {
201 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
207 status = gpu_i2c_stop(i2cd);
213 status2 = gpu_i2c_stop(i2cd);
215 dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
219 static const struct i2c_adapter_quirks gpu_i2c_quirks = {
221 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
224 static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
226 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
229 static const struct i2c_algorithm gpu_i2c_algorithm = {
230 .master_xfer = gpu_i2c_master_xfer,
231 .functionality = gpu_i2c_functionality,
235 * This driver is for Nvidia GPU cards with USB Type-C interface.
236 * We want to identify the cards using vendor ID and class code only
237 * to avoid dependency of adding product id for any new card which
238 * requires this driver.
239 * Currently there is no class code defined for UCSI device over PCI
240 * so using UNKNOWN class for now and it will be updated when UCSI
241 * over PCI gets a class code.
242 * There is no other NVIDIA cards with UNKNOWN class code. Even if the
243 * driver gets loaded for an undesired card then eventually i2c_read()
244 * (initiated from UCSI i2c_client) will timeout or UCSI commands will
247 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
248 static const struct pci_device_id gpu_i2c_ids[] = {
249 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
250 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
253 MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
255 static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
257 struct i2c_client *ccgx_client;
259 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
260 sizeof(*i2cd->gpu_ccgx_ucsi),
262 if (!i2cd->gpu_ccgx_ucsi)
265 strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
266 sizeof(i2cd->gpu_ccgx_ucsi->type));
267 i2cd->gpu_ccgx_ucsi->addr = 0x8;
268 i2cd->gpu_ccgx_ucsi->irq = irq;
269 ccgx_client = i2c_new_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
276 static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
278 struct gpu_i2c_dev *i2cd;
281 i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
285 i2cd->dev = &pdev->dev;
286 dev_set_drvdata(&pdev->dev, i2cd);
288 status = pcim_enable_device(pdev);
290 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
294 pci_set_master(pdev);
296 i2cd->regs = pcim_iomap(pdev, 0, 0);
298 dev_err(&pdev->dev, "pcim_iomap failed\n");
302 status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
304 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
308 gpu_enable_i2c_bus(i2cd);
310 i2c_set_adapdata(&i2cd->adapter, i2cd);
311 i2cd->adapter.owner = THIS_MODULE;
312 strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
313 sizeof(i2cd->adapter.name));
314 i2cd->adapter.algo = &gpu_i2c_algorithm;
315 i2cd->adapter.quirks = &gpu_i2c_quirks;
316 i2cd->adapter.dev.parent = &pdev->dev;
317 status = i2c_add_adapter(&i2cd->adapter);
319 goto free_irq_vectors;
321 status = gpu_populate_client(i2cd, pdev->irq);
323 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
330 i2c_del_adapter(&i2cd->adapter);
332 pci_free_irq_vectors(pdev);
336 static void gpu_i2c_remove(struct pci_dev *pdev)
338 struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
340 i2c_del_adapter(&i2cd->adapter);
341 pci_free_irq_vectors(pdev);
344 static int gpu_i2c_resume(struct device *dev)
346 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
348 gpu_enable_i2c_bus(i2cd);
352 static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, NULL, gpu_i2c_resume, NULL);
354 static struct pci_driver gpu_i2c_driver = {
355 .name = "nvidia-gpu",
356 .id_table = gpu_i2c_ids,
357 .probe = gpu_i2c_probe,
358 .remove = gpu_i2c_remove,
360 .pm = &gpu_i2c_driver_pm,
364 module_pci_driver(gpu_i2c_driver);
366 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
367 MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
368 MODULE_LICENSE("GPL v2");