drivers/i2c/busses/i2c-qcom-geni.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/clk.h>
   6 #include <linux/dma-mapping.h>
   7 #include <linux/err.h>
   8 #include <linux/i2c.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/qcom-geni-se.h>
  17 #include <linux/spinlock.h>
  18
  19 #define SE_I2C_TX_TRANS_LEN             0x26c
  20 #define SE_I2C_RX_TRANS_LEN             0x270
  21 #define SE_I2C_SCL_COUNTERS             0x278
  22
  23 #define SE_I2C_ERR  (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
  24                         M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
  25 #define SE_I2C_ABORT            BIT(1)
  26
  27 /* M_CMD OP codes for I2C */
  28 #define I2C_WRITE               0x1
  29 #define I2C_READ                0x2
  30 #define I2C_WRITE_READ          0x3
  31 #define I2C_ADDR_ONLY           0x4
  32 #define I2C_BUS_CLEAR           0x6
  33 #define I2C_STOP_ON_BUS         0x7
  34 /* M_CMD params for I2C */
  35 #define PRE_CMD_DELAY           BIT(0)
  36 #define TIMESTAMP_BEFORE        BIT(1)
  37 #define STOP_STRETCH            BIT(2)
  38 #define TIMESTAMP_AFTER         BIT(3)
  39 #define POST_COMMAND_DELAY      BIT(4)
  40 #define IGNORE_ADD_NACK         BIT(6)
  41 #define READ_FINISHED_WITH_ACK  BIT(7)
  42 #define BYPASS_ADDR_PHASE       BIT(8)
  43 #define SLV_ADDR_MSK            GENMASK(15, 9)
  44 #define SLV_ADDR_SHFT           9
  45 /* I2C SCL COUNTER fields */
  46 #define HIGH_COUNTER_MSK        GENMASK(29, 20)
  47 #define HIGH_COUNTER_SHFT       20
  48 #define LOW_COUNTER_MSK         GENMASK(19, 10)
  49 #define LOW_COUNTER_SHFT        10
  50 #define CYCLE_COUNTER_MSK       GENMASK(9, 0)
  51
  52 enum geni_i2c_err_code {
  53         GP_IRQ0,
  54         NACK,
  55         GP_IRQ2,
  56         BUS_PROTO,
  57         ARB_LOST,
  58         GP_IRQ5,
  59         GENI_OVERRUN,
  60         GENI_ILLEGAL_CMD,
  61         GENI_ABORT_DONE,
  62         GENI_TIMEOUT,
  63 };
  64
  65 #define DM_I2C_CB_ERR           ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
  66                                                                         << 5)
  67
  68 #define I2C_AUTO_SUSPEND_DELAY  250
  69 #define KHZ(freq)               (1000 * freq)
  70 #define PACKING_BYTES_PW        4
  71
  72 #define ABORT_TIMEOUT           HZ
  73 #define XFER_TIMEOUT            HZ
  74 #define RST_TIMEOUT             HZ
  75
  76 struct geni_i2c_dev {
  77         struct geni_se se;
  78         u32 tx_wm;
  79         int irq;
  80         int err;
  81         struct i2c_adapter adap;
  82         struct completion done;
  83         struct i2c_msg *cur;
  84         int cur_wr;
  85         int cur_rd;
  86         spinlock_t lock;
  87         u32 clk_freq_out;
  88         const struct geni_i2c_clk_fld *clk_fld;
  89         int suspended;
  90 };
  91
  92 struct geni_i2c_err_log {
  93         int err;
  94         const char *msg;
  95 };
  96
  97 static const struct geni_i2c_err_log gi2c_log[] = {
  98         [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
  99         [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
 100         [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
 101         [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
 102         [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
 103         [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
 104         [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
 105         [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
 106         [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
 107         [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
 108 };
 109
 110 struct geni_i2c_clk_fld {
 111         u32     clk_freq_out;
 112         u8      clk_div;
 113         u8      t_high_cnt;
 114         u8      t_low_cnt;
 115         u8      t_cycle_cnt;
 116 };
 117
 118 /*
 119  * Hardware uses the underlying formula to calculate time periods of
 120  * SCL clock cycle. Firmware uses some additional cycles excluded from the
 121  * below formula and it is confirmed that the time periods are within
 122  * specification limits.
 123  *
 124  * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
 125  * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
 126  * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
 127  * clk_freq_out = t / t_cycle
 128  * source_clock = 19.2 MHz
 129  */
 130 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
 131         {KHZ(100), 7, 10, 11, 26},
 132         {KHZ(400), 2,  5, 12, 24},
 133         {KHZ(1000), 1, 3,  9, 18},
 134 };
 135
 136 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
 137 {
 138         int i;
 139         const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
 140
 141         for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
 142                 if (itr->clk_freq_out == gi2c->clk_freq_out) {
 143                         gi2c->clk_fld = itr;
 144                         return 0;
 145                 }
 146         }
 147         return -EINVAL;
 148 }
 149
 150 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
 151 {
 152         const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
 153         u32 val;
 154
 155         writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
 156
 157         val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
 158         writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
 159
 160         val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
 161         val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
 162         val |= itr->t_cycle_cnt;
 163         writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
 164 }
 165
 166 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
 167 {
 168         u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
 169         u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
 170         u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
 171         u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
 172         u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
 173         u32 rx_st, tx_st;
 174
 175         if (dma) {
 176                 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 177                 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 178         } else {
 179                 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
 180                 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
 181         }
 182         dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
 183                 dma, tx_st, rx_st, m_stat);
 184         dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
 185                 m_cmd, geni_s, geni_ios);
 186 }
 187
 188 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
 189 {
 190         if (!gi2c->err)
 191                 gi2c->err = gi2c_log[err].err;
 192         if (gi2c->cur)
 193                 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
 194                         gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
 195
 196         if (err != NACK && err != GENI_ABORT_DONE) {
 197                 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
 198                 geni_i2c_err_misc(gi2c);
 199         }
 200 }
 201
 202 static irqreturn_t geni_i2c_irq(int irq, void *dev)
 203 {
 204         struct geni_i2c_dev *gi2c = dev;
 205         void __iomem *base = gi2c->se.base;
 206         int j, p;
 207         u32 m_stat;
 208         u32 rx_st;
 209         u32 dm_tx_st;
 210         u32 dm_rx_st;
 211         u32 dma;
 212         u32 val;
 213         struct i2c_msg *cur;
 214         unsigned long flags;
 215
 216         spin_lock_irqsave(&gi2c->lock, flags);
 217         m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
 218         rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
 219         dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
 220         dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
 221         dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
 222         cur = gi2c->cur;
 223
 224         if (!cur ||
 225             m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
 226             dm_rx_st & (DM_I2C_CB_ERR)) {
 227                 if (m_stat & M_GP_IRQ_1_EN)
 228                         geni_i2c_err(gi2c, NACK);
 229                 if (m_stat & M_GP_IRQ_3_EN)
 230                         geni_i2c_err(gi2c, BUS_PROTO);
 231                 if (m_stat & M_GP_IRQ_4_EN)
 232                         geni_i2c_err(gi2c, ARB_LOST);
 233                 if (m_stat & M_CMD_OVERRUN_EN)
 234                         geni_i2c_err(gi2c, GENI_OVERRUN);
 235                 if (m_stat & M_ILLEGAL_CMD_EN)
 236                         geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
 237                 if (m_stat & M_CMD_ABORT_EN)
 238                         geni_i2c_err(gi2c, GENI_ABORT_DONE);
 239                 if (m_stat & M_GP_IRQ_0_EN)
 240                         geni_i2c_err(gi2c, GP_IRQ0);
 241
 242                 /* Disable the TX Watermark interrupt to stop TX */
 243                 if (!dma)
 244                         writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 245         } else if (dma) {
 246                 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
 247                         dm_tx_st, dm_rx_st);
 248         } else if (cur->flags & I2C_M_RD &&
 249                    m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
 250                 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
 251
 252                 for (j = 0; j < rxcnt; j++) {
 253                         p = 0;
 254                         val = readl_relaxed(base + SE_GENI_RX_FIFOn);
 255                         while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
 256                                 cur->buf[gi2c->cur_rd++] = val & 0xff;
 257                                 val >>= 8;
 258                                 p++;
 259                         }
 260                         if (gi2c->cur_rd == cur->len)
 261                                 break;
 262                 }
 263         } else if (!(cur->flags & I2C_M_RD) &&
 264                    m_stat & M_TX_FIFO_WATERMARK_EN) {
 265                 for (j = 0; j < gi2c->tx_wm; j++) {
 266                         u32 temp;
 267
 268                         val = 0;
 269                         p = 0;
 270                         while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
 271                                 temp = cur->buf[gi2c->cur_wr++];
 272                                 val |= temp << (p * 8);
 273                                 p++;
 274                         }
 275                         writel_relaxed(val, base + SE_GENI_TX_FIFOn);
 276                         /* TX Complete, Disable the TX Watermark interrupt */
 277                         if (gi2c->cur_wr == cur->len) {
 278                                 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
 279                                 break;
 280                         }
 281                 }
 282         }
 283
 284         if (m_stat)
 285                 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
 286
 287         if (dma && dm_tx_st)
 288                 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
 289         if (dma && dm_rx_st)
 290                 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
 291
 292         /* if this is err with done-bit not set, handle that through timeout. */
 293         if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
 294             dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
 295             dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
 296                 complete(&gi2c->done);
 297
 298         spin_unlock_irqrestore(&gi2c->lock, flags);
 299
 300         return IRQ_HANDLED;
 301 }
 302
 303 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
 304 {
 305         u32 val;
 306         unsigned long time_left = ABORT_TIMEOUT;
 307         unsigned long flags;
 308
 309         spin_lock_irqsave(&gi2c->lock, flags);
 310         geni_i2c_err(gi2c, GENI_TIMEOUT);
 311         gi2c->cur = NULL;
 312         geni_se_abort_m_cmd(&gi2c->se);
 313         spin_unlock_irqrestore(&gi2c->lock, flags);
 314         do {
 315                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 316                 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
 317         } while (!(val & M_CMD_ABORT_EN) && time_left);
 318
 319         if (!(val & M_CMD_ABORT_EN))
 320                 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
 321 }
 322
 323 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
 324 {
 325         u32 val;
 326         unsigned long time_left = RST_TIMEOUT;
 327
 328         writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
 329         do {
 330                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 331                 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
 332         } while (!(val & RX_RESET_DONE) && time_left);
 333
 334         if (!(val & RX_RESET_DONE))
 335                 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
 336 }
 337
 338 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
 339 {
 340         u32 val;
 341         unsigned long time_left = RST_TIMEOUT;
 342
 343         writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
 344         do {
 345                 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
 346                 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
 347         } while (!(val & TX_RESET_DONE) && time_left);
 348
 349         if (!(val & TX_RESET_DONE))
 350                 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
 351 }
 352
 353 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 354                                 u32 m_param)
 355 {
 356         dma_addr_t rx_dma;
 357         unsigned long time_left;
 358         void *dma_buf = NULL;
 359         struct geni_se *se = &gi2c->se;
 360         size_t len = msg->len;
 361
 362         if (!of_machine_is_compatible("lenovo,yoga-c630"))
 363                 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 364
 365         if (dma_buf)
 366                 geni_se_select_mode(se, GENI_SE_DMA);
 367         else
 368                 geni_se_select_mode(se, GENI_SE_FIFO);
 369
 370         writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
 371         geni_se_setup_m_cmd(se, I2C_READ, m_param);
 372
 373         if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
 374                 geni_se_select_mode(se, GENI_SE_FIFO);
 375                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 376                 dma_buf = NULL;
 377         }
 378
 379         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 380         if (!time_left)
 381                 geni_i2c_abort_xfer(gi2c);
 382
 383         gi2c->cur_rd = 0;
 384         if (dma_buf) {
 385                 if (gi2c->err)
 386                         geni_i2c_rx_fsm_rst(gi2c);
 387                 geni_se_rx_dma_unprep(se, rx_dma, len);
 388                 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
 389         }
 390
 391         return gi2c->err;
 392 }
 393
 394 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
 395                                 u32 m_param)
 396 {
 397         dma_addr_t tx_dma;
 398         unsigned long time_left;
 399         void *dma_buf = NULL;
 400         struct geni_se *se = &gi2c->se;
 401         size_t len = msg->len;
 402
 403         if (!of_machine_is_compatible("lenovo,yoga-c630"))
 404                 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
 405
 406         if (dma_buf)
 407                 geni_se_select_mode(se, GENI_SE_DMA);
 408         else
 409                 geni_se_select_mode(se, GENI_SE_FIFO);
 410
 411         writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
 412         geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
 413
 414         if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
 415                 geni_se_select_mode(se, GENI_SE_FIFO);
 416                 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
 417                 dma_buf = NULL;
 418         }
 419
 420         if (!dma_buf) /* Get FIFO IRQ */
 421                 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
 422
 423         time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
 424         if (!time_left)
 425                 geni_i2c_abort_xfer(gi2c);
 426
 427         gi2c->cur_wr = 0;
 428         if (dma_buf) {
 429                 if (gi2c->err)
 430                         geni_i2c_tx_fsm_rst(gi2c);
 431                 geni_se_tx_dma_unprep(se, tx_dma, len);
 432                 i2c_put_dma_safe_msg_buf(dma_buf, msg, !gi2c->err);
 433         }
 434
 435         return gi2c->err;
 436 }
 437
 438 static int geni_i2c_xfer(struct i2c_adapter *adap,
 439                          struct i2c_msg msgs[],
 440                          int num)
 441 {
 442         struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
 443         int i, ret;
 444
 445         gi2c->err = 0;
 446         reinit_completion(&gi2c->done);
 447         ret = pm_runtime_get_sync(gi2c->se.dev);
 448         if (ret < 0) {
 449                 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
 450                 pm_runtime_put_noidle(gi2c->se.dev);
 451                 /* Set device in suspended since resume failed */
 452                 pm_runtime_set_suspended(gi2c->se.dev);
 453                 return ret;
 454         }
 455
 456         qcom_geni_i2c_conf(gi2c);
 457         for (i = 0; i < num; i++) {
 458                 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
 459
 460                 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
 461
 462                 gi2c->cur = &msgs[i];
 463                 if (msgs[i].flags & I2C_M_RD)
 464                         ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
 465                 else
 466                         ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
 467
 468                 if (ret)
 469                         break;
 470         }
 471         if (ret == 0)
 472                 ret = num;
 473
 474         pm_runtime_mark_last_busy(gi2c->se.dev);
 475         pm_runtime_put_autosuspend(gi2c->se.dev);
 476         gi2c->cur = NULL;
 477         gi2c->err = 0;
 478         return ret;
 479 }
 480
 481 static u32 geni_i2c_func(struct i2c_adapter *adap)
 482 {
 483         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 484 }
 485
 486 static const struct i2c_algorithm geni_i2c_algo = {
 487         .master_xfer    = geni_i2c_xfer,
 488         .functionality  = geni_i2c_func,
 489 };
 490
 491 #ifdef CONFIG_ACPI
 492 static const struct acpi_device_id geni_i2c_acpi_match[] = {
 493         { "QCOM0220"},
 494         { },
 495 };
 496 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
 497 #endif
 498
 499 static int geni_i2c_probe(struct platform_device *pdev)
 500 {
 501         struct geni_i2c_dev *gi2c;
 502         struct resource *res;
 503         u32 proto, tx_depth;
 504         int ret;
 505
 506         gi2c = devm_kzalloc(&pdev->dev, sizeof(*gi2c), GFP_KERNEL);
 507         if (!gi2c)
 508                 return -ENOMEM;
 509
 510         gi2c->se.dev = &pdev->dev;
 511         gi2c->se.wrapper = dev_get_drvdata(pdev->dev.parent);
 512         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 513         gi2c->se.base = devm_ioremap_resource(&pdev->dev, res);
 514         if (IS_ERR(gi2c->se.base))
 515                 return PTR_ERR(gi2c->se.base);
 516
 517         gi2c->se.clk = devm_clk_get(&pdev->dev, "se");
 518         if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(&pdev->dev)) {
 519                 ret = PTR_ERR(gi2c->se.clk);
 520                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
 521                 return ret;
 522         }
 523
 524         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
 525                                                         &gi2c->clk_freq_out);
 526         if (ret) {
 527                 dev_info(&pdev->dev,
 528                         "Bus frequency not specified, default to 100kHz.\n");
 529                 gi2c->clk_freq_out = KHZ(100);
 530         }
 531
 532         if (has_acpi_companion(&pdev->dev))
 533                 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(&pdev->dev));
 534
 535         gi2c->irq = platform_get_irq(pdev, 0);
 536         if (gi2c->irq < 0) {
 537                 dev_err(&pdev->dev, "IRQ error for i2c-geni\n");
 538                 return gi2c->irq;
 539         }
 540
 541         ret = geni_i2c_clk_map_idx(gi2c);
 542         if (ret) {
 543                 dev_err(&pdev->dev, "Invalid clk frequency %d Hz: %d\n",
 544                         gi2c->clk_freq_out, ret);
 545                 return ret;
 546         }
 547
 548         gi2c->adap.algo = &geni_i2c_algo;
 549         init_completion(&gi2c->done);
 550         spin_lock_init(&gi2c->lock);
 551         platform_set_drvdata(pdev, gi2c);
 552         ret = devm_request_irq(&pdev->dev, gi2c->irq, geni_i2c_irq,
 553                                IRQF_TRIGGER_HIGH, "i2c_geni", gi2c);
 554         if (ret) {
 555                 dev_err(&pdev->dev, "Request_irq failed:%d: err:%d\n",
 556                         gi2c->irq, ret);
 557                 return ret;
 558         }
 559         /* Disable the interrupt so that the system can enter low-power mode */
 560         disable_irq(gi2c->irq);
 561         i2c_set_adapdata(&gi2c->adap, gi2c);
 562         gi2c->adap.dev.parent = &pdev->dev;
 563         gi2c->adap.dev.of_node = pdev->dev.of_node;
 564         strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
 565
 566         ret = geni_se_resources_on(&gi2c->se);
 567         if (ret) {
 568                 dev_err(&pdev->dev, "Error turning on resources %d\n", ret);
 569                 return ret;
 570         }
 571         proto = geni_se_read_proto(&gi2c->se);
 572         tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
 573         if (proto != GENI_SE_I2C) {
 574                 dev_err(&pdev->dev, "Invalid proto %d\n", proto);
 575                 geni_se_resources_off(&gi2c->se);
 576                 return -ENXIO;
 577         }
 578         gi2c->tx_wm = tx_depth - 1;
 579         geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
 580         geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
 581                                                         true, true, true);
 582         ret = geni_se_resources_off(&gi2c->se);
 583         if (ret) {
 584                 dev_err(&pdev->dev, "Error turning off resources %d\n", ret);
 585                 return ret;
 586         }
 587
 588         dev_dbg(&pdev->dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
 589
 590         gi2c->suspended = 1;
 591         pm_runtime_set_suspended(gi2c->se.dev);
 592         pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
 593         pm_runtime_use_autosuspend(gi2c->se.dev);
 594         pm_runtime_enable(gi2c->se.dev);
 595
 596         ret = i2c_add_adapter(&gi2c->adap);
 597         if (ret) {
 598                 dev_err(&pdev->dev, "Error adding i2c adapter %d\n", ret);
 599                 pm_runtime_disable(gi2c->se.dev);
 600                 return ret;
 601         }
 602
 603         dev_dbg(&pdev->dev, "Geni-I2C adaptor successfully added\n");
 604
 605         return 0;
 606 }
 607
 608 static int geni_i2c_remove(struct platform_device *pdev)
 609 {
 610         struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
 611
 612         i2c_del_adapter(&gi2c->adap);
 613         pm_runtime_disable(gi2c->se.dev);
 614         return 0;
 615 }
 616
 617 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
 618 {
 619         int ret;
 620         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 621
 622         disable_irq(gi2c->irq);
 623         ret = geni_se_resources_off(&gi2c->se);
 624         if (ret) {
 625                 enable_irq(gi2c->irq);
 626                 return ret;
 627
 628         } else {
 629                 gi2c->suspended = 1;
 630         }
 631
 632         return 0;
 633 }
 634
 635 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
 636 {
 637         int ret;
 638         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 639
 640         ret = geni_se_resources_on(&gi2c->se);
 641         if (ret)
 642                 return ret;
 643
 644         enable_irq(gi2c->irq);
 645         gi2c->suspended = 0;
 646         return 0;
 647 }
 648
 649 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
 650 {
 651         struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
 652
 653         if (!gi2c->suspended) {
 654                 geni_i2c_runtime_suspend(dev);
 655                 pm_runtime_disable(dev);
 656                 pm_runtime_set_suspended(dev);
 657                 pm_runtime_enable(dev);
 658         }
 659         return 0;
 660 }
 661
 662 static const struct dev_pm_ops geni_i2c_pm_ops = {
 663         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, NULL)
 664         SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
 665                                                                         NULL)
 666 };
 667
 668 static const struct of_device_id geni_i2c_dt_match[] = {
 669         { .compatible = "qcom,geni-i2c" },
 670         {}
 671 };
 672 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
 673
 674 static struct platform_driver geni_i2c_driver = {
 675         .probe  = geni_i2c_probe,
 676         .remove = geni_i2c_remove,
 677         .driver = {
 678                 .name = "geni_i2c",
 679                 .pm = &geni_i2c_pm_ops,
 680                 .of_match_table = geni_i2c_dt_match,
 681                 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
 682         },
 683 };
 684
 685 module_platform_driver(geni_i2c_driver);
 686
 687 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
 688 MODULE_LICENSE("GPL v2");